URL
https://opencores.org/ocsvn/phr/phr/trunk
Subversion Repositories phr
Compare Revisions
- This comparison shows the changes necessary to convert path
/phr/trunk/codigo/demos
- from Rev 411 to Rev 412
- ↔ Reverse comparison
Rev 411 → Rev 412
/projects/S3Demo/S3demo_map.xrpt
62,23 → 62,23
<item stringID="MAP_TOTAL_CPU_TIME" value="2 secs "/> |
</section> |
<section stringID="MAP_SLICE_REPORTING"> |
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="157"/> |
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="91"/> |
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="9"/> |
<item dataType="int" stringID="MAP_AVAILABLE_SLICEL" value="896"/> |
<item dataType="int" stringID="MAP_AVAILABLE_SLICEM" value="896"/> |
<item dataType="int" stringID="MAP_FLOPS_PER_SLICE" value="2"/> |
<item dataType="int" stringID="MAP_LUTS_PER_SLICE" value="2"/> |
<item AVAILABLE="896" dataType="int" stringID="MAP_NUM_SLICEM" value="2"/> |
<item AVAILABLE="896" dataType="int" stringID="MAP_NUM_SLICEL" value="2"/> |
<item dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="162"/> |
<item dataType="int" label="Number of occupied Slices" stringID="MAP_AGG_SLICE" value="121"/> |
<item AVAILABLE="896" dataType="int" stringID="MAP_NUM_SLICEM" value="1"/> |
<item AVAILABLE="896" dataType="int" stringID="MAP_NUM_SLICEL" value="1"/> |
<item dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="108"/> |
<item dataType="int" label="Number of occupied Slices" stringID="MAP_AGG_SLICE" value="76"/> |
<item dataType="int" label="Number of Slices containing unrelated logic" stringID="MAP_NUM_SLICE_UNRELATED" value="0"/> |
<item dataType="int" label="Number of route-thrus" stringID="MAP_NUM_LUT_RT" value="62"/> |
<item dataType="int" label="Number of route-thrus" stringID="MAP_NUM_LUT_RT" value="33"/> |
<item dataType="int" stringID="MAP_NUM_DP_RAM" value="0"/> |
<item dataType="int" stringID="MAP_NUM_RAM32" value="0"/> |
<item dataType="int" stringID="MAP_NUM_RAM16" value="0"/> |
<item dataType="int" stringID="MAP_NUM_ROM16" value="0"/> |
<item dataType="int" label="Number used as Shift registers" stringID="MAP_NUM_SHIFT" value="2"/> |
<item dataType="int" label="Number used as Shift registers" stringID="MAP_NUM_SHIFT" value="1"/> |
</section> |
<section stringID="MAP_IOB_REPORTING"> |
<section stringID="MAP_IOB_DATA"> |
85,7 → 85,7
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/> |
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/> |
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/> |
<item AVAILABLE="68" dataType="int" stringID="MAP_AGG_BONDED_IO" value="55"/> |
<item AVAILABLE="68" dataType="int" stringID="MAP_AGG_BONDED_IO" value="38"/> |
<item AVAILABLE="204" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/> |
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/> |
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/> |
102,7 → 102,7
<section stringID="MAP_HARD_IP_REPORTING"> |
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB16" value="0"/> |
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_MULT18X18" value="0"/> |
<item AVAILABLE="24" dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="4"/> |
<item AVAILABLE="24" dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="3"/> |
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_DCM" value="0"/> |
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/> |
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/> |
172,17 → 172,14
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="5"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="blu"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn<0>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="6"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn<0>"/> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn<1>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
189,7 → 186,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="7"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn<1>"/> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn<2>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
196,7 → 193,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="8"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn<2>"/> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn<3>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
203,7 → 200,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="9"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn<3>"/> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="clk_sel1"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
210,7 → 207,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="10"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn_ext<0>"/> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="clk_sel2"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
217,7 → 214,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="11"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn_ext<1>"/> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="clk_sel3"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
224,61 → 221,6
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="12"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn_ext<2>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="13"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn_ext<3>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="14"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="btn_ext<4>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="15"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="grn"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="16"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="hs"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="17"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="kc"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="18"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="kd"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="19"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led<0>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
288,7 → 230,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="20"> |
<row stringID="row" value="13"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led<1>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
298,7 → 240,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="21"> |
<row stringID="row" value="14"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led<2>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
308,7 → 250,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="22"> |
<row stringID="row" value="15"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led<3>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
318,7 → 260,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="23"> |
<row stringID="row" value="16"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led<4>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
328,7 → 270,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="24"> |
<row stringID="row" value="17"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led<5>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
338,7 → 280,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="25"> |
<row stringID="row" value="18"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led<6>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
348,7 → 290,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="26"> |
<row stringID="row" value="19"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led<7>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
358,87 → 300,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="27"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led_ext<0>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="28"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led_ext<1>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="29"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led_ext<2>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="30"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led_ext<3>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="31"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led_ext<4>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="32"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led_ext<5>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="33"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led_ext<6>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="34"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="led_ext<7>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="35"> |
<row stringID="row" value="20"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="mclk"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
445,17 → 307,7
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="36"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="red"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="37"> |
<row stringID="row" value="21"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="rxd"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
462,7 → 314,7
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="38"> |
<row stringID="row" value="22"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="ssg<0>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
472,7 → 324,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="39"> |
<row stringID="row" value="23"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="ssg<1>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
482,7 → 334,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="40"> |
<row stringID="row" value="24"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="ssg<2>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
492,7 → 344,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="41"> |
<row stringID="row" value="25"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="ssg<3>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
502,7 → 354,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="42"> |
<row stringID="row" value="26"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="ssg<4>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
512,7 → 364,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="43"> |
<row stringID="row" value="27"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="ssg<5>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
522,7 → 374,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="44"> |
<row stringID="row" value="28"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="ssg<6>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
532,7 → 384,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="45"> |
<row stringID="row" value="29"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="ssg<7>"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
542,7 → 394,7
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="46"> |
<row stringID="row" value="30"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="swt<0>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
549,7 → 401,7
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="47"> |
<row stringID="row" value="31"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="swt<1>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
556,7 → 408,7
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="48"> |
<row stringID="row" value="32"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="swt<2>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
563,7 → 415,7
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="49"> |
<row stringID="row" value="33"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="swt<3>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
570,7 → 422,7
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="50"> |
<row stringID="row" value="34"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="swt<4>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
577,7 → 429,7
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="51"> |
<row stringID="row" value="35"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="swt<5>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
584,7 → 436,7
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="52"> |
<row stringID="row" value="36"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="swt<6>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
591,7 → 443,7
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="53"> |
<row stringID="row" value="37"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="swt<7>"/> |
<item stringID="Type" value="IBUF"/> |
<item stringID="Direction" value="INPUT"/> |
598,7 → 450,7
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
</row> |
<row stringID="row" value="54"> |
<row stringID="row" value="38"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="txd"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
608,21 → 460,11
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
<row stringID="row" value="55"> |
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="vs"/> |
<item stringID="Type" value="IOB"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/> |
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/> |
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/> |
<item label="IBUF/IFD
Delay" stringID="IBUF_IFD_DELAY" value="0 / 0"/> |
<item label="Suspend" stringID="SUSPEND" value="3STATE"/> |
</row> |
</table> |
</section> |
<section stringID="MAP_RPM_MACROS"> |
<section stringID="MAP_SHAPE_SECTION"> |
<item dataType="int" stringID="MAP_NUM_SHAPE" value="5"/> |
<item dataType="int" stringID="MAP_NUM_SHAPE" value="2"/> |
</section> |
</section> |
<section stringID="MAP_GUIDE_REPORT"/> |
/projects/S3Demo/S3demo.bld
6,7 → 6,8
S3demo.ngd |
|
Reading NGO file |
"/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/S3demo.ngc" ... |
"/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/S3demo.ngc" |
... |
Gathering constraint information from source properties... |
Done. |
|
/projects/S3Demo/S3demo_pad.txt
17,110 → 17,110
|
Pinout by Pin Number: |
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|Pin Number|Signal Name|Pin Usage |Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity| |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|P1 | | |TMS | | | | | | | | | | | | |
|P2 | | |TDI | | | | | | | | | | | | |
|P3 |led<5> |IOB |IO_L01P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P4 |swt<5> |IBUF |IO_L01N_3 |INPUT |LVCMOS25* |3 | | | |IBUF | |LOCATED |NO |NONE | |
|P5 |led<6> |IOB |IO_L02P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P6 |swt<6> |IBUF |IO_L02N_3 |INPUT |LVCMOS25* |3 | | | |IBUF | |LOCATED |NO |NONE | |
|P7 | |DIFFSI_NDT|IP_3/VREF_3 |UNUSED | |3 | | | | | | | | | |
|P8 | | |GND | | | | | | | | | | | | |
|P9 |swt<7> |IBUF |IO_L03P_3/LHCLK0 |INPUT |LVCMOS25* |3 | | | |IBUF | |LOCATED |NO |NONE | |
|P10 | |DIFFSLR |IO_L03N_3/LHCLK1 |UNUSED | |3 | | | | | | | | | |
|P11 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|P12 |vs |IOB |IO_L04P_3/LHCLK2 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P13 |red |IOB |IO_L04N_3/IRDY2/LHCLK3|OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P14 | | |GND | | | | | | | | | | | | |
|P15 |hs |IOB |IO_L05P_3/TRDY2/LHCLK6|OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P16 |grn |IOB |IO_L05N_3/LHCLK7 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P17 | | |VCCINT | | | | | | | |1.2 | | | | |
|P18 | | |GND | | | | | | | | | | | | |
|P19 |kc |IBUF |IO_L06P_3 |INPUT |LVCMOS25* |3 | | | |IBUF | |LOCATED |NO |NONE | |
|P20 |blu |IOB |IO_L06N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P21 |kd |IBUF |IP_3 |INPUT |LVCMOS25* |3 | | | |IBUF | |LOCATED |NO |NONE | |
|P22 | | |VCCAUX | | | | | | | |2.5 | | | | |
|P23 | |DIFFMTB |IO_L01P_2/M1 |UNUSED | |2 | | | | | | | | | |
|P24 | |DIFFMTB |IO_L02P_2/M2 |UNUSED | |2 | | | | | | | | | |
|P25 | |DIFFSTB |IO_L01N_2/M0 |UNUSED | |2 | | | | | | | | | |
|P26 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |
|P27 |led<7> |IOB |IO_L02N_2/CSO_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P28 |ssg<4> |IOB |IO_L03P_2/RDWR_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P29 |led_ext<7> |IOB |IO_L03N_2/VS2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P30 |btn_ext<4> |IBUF |IO_L04P_2/VS1 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P31 |led_ext<6> |IOB |IO_L04N_2/VS0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P32 |led_ext<5> |IOB |IO_L05P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P33 |led_ext<4> |IOB |IO_L05N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P34 |led_ext<3> |IOB |IO_L06P_2/D7 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P35 |led_ext<2> |IOB |IO_L06N_2/D6 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P36 |led_ext<0> |IOB |IO_L07P_2/D5 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P37 |btn_ext<2> |IBUF |IO_L07N_2/D4 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P38 | | |VCCINT | | | | | | | |1.2 | | | | |
|P39 |btn_ext<0> |IBUF |IP_2/VREF_2 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P40 | |DIFFMTB |IO_L08P_2/GCLK14 |UNUSED | |2 | | | | | | | | | |
|P41 | |DIFFSTB |IO_L08N_2/GCLK15 |UNUSED | |2 | | | | | | | | | |
|P42 | | |GND | | | | | | | | | | | | |
|P43 |mclk |IBUF |IO_L09P_2/GCLK0 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P44 | |DIFFSTB |IO_L09N_2/GCLK1 |UNUSED | |2 | | | | | | | | | |
|P45 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |
|P46 |led_ext<1> |IOB |IO_2/MOSI/CSI_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P47 | | |GND | | | | | | | | | | | | |
|P48 | |DIFFMTB |IO_L10P_2/INIT_B |UNUSED | |2 | | | | | | | | | |
|P49 |btn_ext<3> |IBUF |IO_L10N_2/D3 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P50 |btn_ext<1> |IBUF |IO_L11P_2/D2 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P51 | |DIFFMTB |IO_L12P_2/D0/DIN/MISO |UNUSED | |2 | | | | | | | | | |
|P52 |rxd |IBUF |IO_L11N_2/D1 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P53 | |DIFFSTB |IO_L12N_2/CCLK |UNUSED | |2 | | | | | | | | | |
|P54 | | |DONE | | | | | | | | | | | | |
|P55 | | |VCCAUX | | | | | | | |2.5 | | | | |
|P56 |txd |IOB |IO_L01P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P57 |an<1> |IOB |IO_L01N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P58 | | |GND | | | | | | | | | | | | |
|P59 |an<0> |IOB |IO_L02P_1/RHCLK0 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P60 |an<3> |IOB |IO_L02N_1/RHCLK1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P61 |an<2> |IOB |IO_L03P_1/RHCLK2 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P62 |ssg<5> |IOB |IO_L03N_1/TRDY1/RHCLK3|OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P63 | | |GND | | | | | | | | | | | | |
|P64 |ssg<1> |IOB |IO_L04P_1/IRDY1/RHCLK6|OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P65 |ssg<0> |IOB |IO_L04N_1/RHCLK7 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P66 | | |VCCINT | | | | | | | |1.2 | | | | |
|P67 | | |VCCO_1 | | |1 | | | | |2.50 | | | | |
|P68 | |DIFFMI_NDT|IP_1/VREF_1 |UNUSED | |1 | | | | | | | | | |
|P69 | | |GND | | | | | | | | | | | | |
|P70 |ssg<3> |IOB |IO_L05P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P71 |ssg<7> |IOB |IO_L05N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P72 |ssg<2> |IOB |IO_L06P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P73 |ssg<6> |IOB |IO_L06N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P74 | | |GND | | | | | | | | | | | | |
|P75 | | |TDO | | | | | | | | | | | | |
|P76 | | |TCK | | | | | | | | | | | | |
|P77 |btn<0> |IBUF |IO_L01P_0/VREF_0 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P78 |btn<1> |IBUF |IO_L01N_0 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P79 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|P80 | | |GND | | | | | | | | | | | | |
|P81 | | |VCCINT | | | | | | | |1.2 | | | | |
|P82 |btn<2> |IBUF |IP_0/VREF_0 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P83 |btn<3> |IBUF |IO_L02P_0/GCLK4 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P84 |led<0> |IOB |IO_L02N_0/GCLK5 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P85 |swt<0> |IBUF |IO_L03P_0/GCLK6 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P86 |led<1> |IOB |IO_L03N_0/GCLK7 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P87 | | |GND | | | | | | | | | | | | |
|P88 |swt<1> |IBUF |IO_L04P_0/GCLK8 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P89 |led<2> |IOB |IO_L04N_0/GCLK9 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P90 |swt<2> |IBUF |IO_0/GCLK11 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P91 | | |GND | | | | | | | | | | | | |
|P92 | | |VCCAUX | | | | | | | |2.5 | | | | |
|P93 |led<3> |IOB |IO_L05P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P94 |swt<3> |IBUF |IO_L05N_0 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P95 | | |GND | | | | | | | | | | | | |
|P96 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|P97 |swt<4> |IBUF |IP_0 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P98 |led<4> |IOB |IO_L06P_0/VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P99 | |DIFFSTB |IO_L06N_0/PUDC_B |UNUSED | |0 | | | | | | | | | |
|P100 | | |PROG_B | | | | | | | | | | | | |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|Pin Number|Signal Name|Pin Usage |Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|P1 | | |TMS | | | | | | | | | | | | |
|P2 | | |TDI | | | | | | | | | | | | |
|P3 |led<5> |IOB |IO_L01P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P4 |swt<5> |IBUF |IO_L01N_3 |INPUT |LVCMOS25* |3 | | | |IBUF | |LOCATED |NO |NONE | |
|P5 |led<6> |IOB |IO_L02P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P6 |swt<6> |IBUF |IO_L02N_3 |INPUT |LVCMOS25* |3 | | | |IBUF | |LOCATED |NO |NONE | |
|P7 |swt<7> |IBUF |IP_3/VREF_3 |INPUT |LVCMOS25* |3 | | | |IBUF | |LOCATED |NO |NONE | |
|P8 | | |GND | | | | | | | | | | | | |
|P9 |led<7> |IOB |IO_L03P_3/LHCLK0 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P10 | |DIFFSLR |IO_L03N_3/LHCLK1 |UNUSED | |3 | | | | | | | | | |
|P11 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|P12 | |DIFFMLR |IO_L04P_3/LHCLK2 |UNUSED | |3 | | | | | | | | | |
|P13 | |DIFFSLR |IO_L04N_3/IRDY2/LHCLK3|UNUSED | |3 | | | | | | | | | |
|P14 | | |GND | | | | | | | | | | | | |
|P15 | |DIFFMLR |IO_L05P_3/TRDY2/LHCLK6|UNUSED | |3 | | | | | | | | | |
|P16 | |DIFFSLR |IO_L05N_3/LHCLK7 |UNUSED | |3 | | | | | | | | | |
|P17 | | |VCCINT | | | | | | | |1.2 | | | | |
|P18 | | |GND | | | | | | | | | | | | |
|P19 | |DIFFMLR |IO_L06P_3 |UNUSED | |3 | | | | | | | | | |
|P20 | |DIFFSLR |IO_L06N_3 |UNUSED | |3 | | | | | | | | | |
|P21 | |DIFFMI_NDT|IP_3 |UNUSED | |3 | | | | | | | | | |
|P22 | | |VCCAUX | | | | | | | |2.5 | | | | |
|P23 | |DIFFMTB |IO_L01P_2/M1 |UNUSED | |2 | | | | | | | | | |
|P24 | |DIFFMTB |IO_L02P_2/M2 |UNUSED | |2 | | | | | | | | | |
|P25 | |DIFFSTB |IO_L01N_2/M0 |UNUSED | |2 | | | | | | | | | |
|P26 | | |VCCO_2 | | |2 | | | | |any******| | | | |
|P27 | |DIFFSTB |IO_L02N_2/CSO_B |UNUSED | |2 | | | | | | | | | |
|P28 | |DIFFMTB |IO_L03P_2/RDWR_B |UNUSED | |2 | | | | | | | | | |
|P29 | |DIFFSTB |IO_L03N_2/VS2 |UNUSED | |2 | | | | | | | | | |
|P30 | |DIFFMTB |IO_L04P_2/VS1 |UNUSED | |2 | | | | | | | | | |
|P31 | |DIFFSTB |IO_L04N_2/VS0 |UNUSED | |2 | | | | | | | | | |
|P32 | |DIFFMTB |IO_L05P_2 |UNUSED | |2 | | | | | | | | | |
|P33 | |DIFFSTB |IO_L05N_2 |UNUSED | |2 | | | | | | | | | |
|P34 | |DIFFMTB |IO_L06P_2/D7 |UNUSED | |2 | | | | | | | | | |
|P35 | |DIFFSTB |IO_L06N_2/D6 |UNUSED | |2 | | | | | | | | | |
|P36 | |DIFFMTB |IO_L07P_2/D5 |UNUSED | |2 | | | | | | | | | |
|P37 | |DIFFSTB |IO_L07N_2/D4 |UNUSED | |2 | | | | | | | | | |
|P38 | | |VCCINT | | | | | | | |1.2 | | | | |
|P39 | |IBUF |IP_2/VREF_2 |UNUSED | |2 | | | | | | | | | |
|P40 |clk_sel3 |IBUF |IO_L08P_2/GCLK14 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P41 |clk_sel2 |IBUF |IO_L08N_2/GCLK15 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P42 | | |GND | | | | | | | | | | | | |
|P43 |mclk |IBUF |IO_L09P_2/GCLK0 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P44 |clk_sel1 |IBUF |IO_L09N_2/GCLK1 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P45 | | |VCCO_2 | | |2 | | | | |any******| | | | |
|P46 | |DIFFSTB |IO_2/MOSI/CSI_B |UNUSED | |2 | | | | | | | | | |
|P47 | | |GND | | | | | | | | | | | | |
|P48 | |DIFFMTB |IO_L10P_2/INIT_B |UNUSED | |2 | | | | | | | | | |
|P49 | |DIFFSTB |IO_L10N_2/D3 |UNUSED | |2 | | | | | | | | | |
|P50 | |DIFFMTB |IO_L11P_2/D2 |UNUSED | |2 | | | | | | | | | |
|P51 | |DIFFMTB |IO_L12P_2/D0/DIN/MISO |UNUSED | |2 | | | | | | | | | |
|P52 |rxd |IBUF |IO_L11N_2/D1 |INPUT |LVCMOS25* |2 | | | |IBUF | |LOCATED |NO |NONE | |
|P53 | |DIFFSTB |IO_L12N_2/CCLK |UNUSED | |2 | | | | | | | | | |
|P54 | | |DONE | | | | | | | | | | | | |
|P55 | | |VCCAUX | | | | | | | |2.5 | | | | |
|P56 |txd |IOB |IO_L01P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P57 |an<1> |IOB |IO_L01N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P58 | | |GND | | | | | | | | | | | | |
|P59 |an<0> |IOB |IO_L02P_1/RHCLK0 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P60 |an<3> |IOB |IO_L02N_1/RHCLK1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P61 |an<2> |IOB |IO_L03P_1/RHCLK2 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P62 |ssg<5> |IOB |IO_L03N_1/TRDY1/RHCLK3|OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P63 | | |GND | | | | | | | | | | | | |
|P64 |ssg<1> |IOB |IO_L04P_1/IRDY1/RHCLK6|OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P65 |ssg<0> |IOB |IO_L04N_1/RHCLK7 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P66 | | |VCCINT | | | | | | | |1.2 | | | | |
|P67 | | |VCCO_1 | | |1 | | | | |2.50 | | | | |
|P68 |btn<0> |IBUF |IP_1/VREF_1 |INPUT |LVCMOS25* |1 | | | |IBUF | |LOCATED |NO |NONE | |
|P69 | | |GND | | | | | | | | | | | | |
|P70 |ssg<3> |IOB |IO_L05P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P71 |ssg<7> |IOB |IO_L05N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P72 |ssg<2> |IOB |IO_L06P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P73 |ssg<6> |IOB |IO_L06N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P74 | | |GND | | | | | | | | | | | | |
|P75 | | |TDO | | | | | | | | | | | | |
|P76 | | |TCK | | | | | | | | | | | | |
|P77 |ssg<4> |IOB |IO_L01P_0/VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P78 |btn<1> |IBUF |IO_L01N_0 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P79 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|P80 | | |GND | | | | | | | | | | | | |
|P81 | | |VCCINT | | | | | | | |1.2 | | | | |
|P82 |btn<2> |IBUF |IP_0/VREF_0 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P83 |btn<3> |IBUF |IO_L02P_0/GCLK4 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P84 |led<0> |IOB |IO_L02N_0/GCLK5 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P85 |swt<0> |IBUF |IO_L03P_0/GCLK6 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P86 |led<1> |IOB |IO_L03N_0/GCLK7 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P87 | | |GND | | | | | | | | | | | | |
|P88 |swt<1> |IBUF |IO_L04P_0/GCLK8 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P89 |led<2> |IOB |IO_L04N_0/GCLK9 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P90 |swt<2> |IBUF |IO_0/GCLK11 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P91 | | |GND | | | | | | | | | | | | |
|P92 | | |VCCAUX | | | | | | | |2.5 | | | | |
|P93 |led<3> |IOB |IO_L05P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P94 |swt<3> |IBUF |IO_L05N_0 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P95 | | |GND | | | | | | | | | | | | |
|P96 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|P97 |swt<4> |IBUF |IP_0 |INPUT |LVCMOS25* |0 | | | |IBUF | |LOCATED |NO |NONE | |
|P98 |led<4> |IOB |IO_L06P_0/VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | |
|P99 | |DIFFSTB |IO_L06N_0/PUDC_B |UNUSED | |0 | | | | | | | | | |
|P100 | | |PROG_B | | | | | | | | | | | | |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
* Default value. |
** This default Pullup/Pulldown value can be overridden in Bitgen. |
/projects/S3Demo/S3demo_map.map
16,20 → 16,10
Running delay-based LUT packing... |
Running related packing... |
Updating timing models... |
WARNING:PhysDesignRules:367 - The signal <swt<1>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<2>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<3>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<4>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<5>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<6>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<7>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <clk_sel1_IBUF> is incomplete. The |
signal does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <clk_sel2_IBUF> is incomplete. The |
signal does not drive any load pins in the design. |
|
Design Summary |
-------------- |
36,31 → 26,31
|
Design Summary: |
Number of errors: 0 |
Number of warnings: 7 |
Number of warnings: 2 |
Logic Utilization: |
Total Number Slice Registers: 166 out of 3,584 4% |
Number used as Flip Flops: 157 |
Total Number Slice Registers: 100 out of 3,584 2% |
Number used as Flip Flops: 91 |
Number used as Latches: 9 |
Number of 4 input LUTs: 100 out of 3,584 2% |
Number of 4 input LUTs: 75 out of 3,584 2% |
Logic Distribution: |
Number of occupied Slices: 121 out of 1,792 6% |
Number of Slices containing only related logic: 121 out of 121 100% |
Number of Slices containing unrelated logic: 0 out of 121 0% |
Number of occupied Slices: 76 out of 1,792 4% |
Number of Slices containing only related logic: 76 out of 76 100% |
Number of Slices containing unrelated logic: 0 out of 76 0% |
*See NOTES below for an explanation of the effects of unrelated logic. |
Total Number of 4 input LUTs: 162 out of 3,584 4% |
Number used as logic: 98 |
Number used as a route-thru: 62 |
Number used as Shift registers: 2 |
Total Number of 4 input LUTs: 108 out of 3,584 3% |
Number used as logic: 74 |
Number used as a route-thru: 33 |
Number used as Shift registers: 1 |
|
The Slice Logic Distribution report is not meaningful if the design is |
over-mapped for a non-slice resource or if Placement fails. |
|
Number of bonded IOBs: 55 out of 68 80% |
Number of BUFGMUXs: 4 out of 24 16% |
Number of bonded IOBs: 38 out of 68 55% |
Number of BUFGMUXs: 3 out of 24 12% |
|
Average Fanout of Non-Clock Nets: 2.52 |
Average Fanout of Non-Clock Nets: 2.43 |
|
Peak Memory Usage: 161 MB |
Peak Memory Usage: 160 MB |
Total REAL time to MAP completion: 4 secs |
Total CPU time to MAP completion: 2 secs |
|
/projects/S3Demo/S3demo_bitgen.xwbt
1,8 → 1,8
INTSTYLE=ise |
INFILE=/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/S3demo.ncd |
OUTFILE=/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/S3demo.bit |
INFILE=/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/S3demo.ncd |
OUTFILE=/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/S3demo.bit |
FAMILY=Spartan3A and Spartan3AN |
PART=xc3s200a-5vq100 |
WORKINGDIR=/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo |
WORKINGDIR=/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2 |
LICENSE=WebPack |
USER_INFO=0_0_320 |
/projects/S3Demo/S3demo.twr
43,31 → 43,41
|Max Setup to|Max Hold to | | Clock | |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | |
------------+------------+------------+------------------+--------+ |
btn<3> | 1.289(R)| 0.324(R)|mclk_BUFGP | 0.000| |
btn<0> | 1.628(R)| 0.268(R)|mclk_BUFGP | 0.000| |
------------+------------+------------+------------------+--------+ |
|
Clock mclk to Pad |
Clock clk_sel3 to Pad |
------------+------------+------------------+--------+ |
| clk (edge) | | Clock | |
Destination | to PAD |Internal Clock(s) | Phase | |
------------+------------+------------------+--------+ |
an<0> | 8.531(R)|mclk_BUFGP | 0.000| |
an<1> | 9.219(R)|mclk_BUFGP | 0.000| |
ssg<0> | 11.202(R)|mclk_BUFGP | 0.000| |
ssg<1> | 11.110(R)|mclk_BUFGP | 0.000| |
ssg<2> | 10.926(R)|mclk_BUFGP | 0.000| |
ssg<3> | 11.008(R)|mclk_BUFGP | 0.000| |
ssg<4> | 12.286(R)|mclk_BUFGP | 0.000| |
ssg<5> | 11.038(R)|mclk_BUFGP | 0.000| |
ssg<6> | 11.281(R)|mclk_BUFGP | 0.000| |
an<0> | 7.855(R)|clk_sel3_BUFGP | 0.000| |
an<1> | 9.017(R)|clk_sel3_BUFGP | 0.000| |
an<2> | 7.858(R)|clk_sel3_BUFGP | 0.000| |
an<3> | 7.849(R)|clk_sel3_BUFGP | 0.000| |
ssg<0> | 8.678(R)|clk_sel3_BUFGP | 0.000| |
ssg<1> | 8.687(R)|clk_sel3_BUFGP | 0.000| |
ssg<2> | 9.647(R)|clk_sel3_BUFGP | 0.000| |
ssg<3> | 9.505(R)|clk_sel3_BUFGP | 0.000| |
ssg<4> | 9.811(R)|clk_sel3_BUFGP | 0.000| |
ssg<5> | 9.099(R)|clk_sel3_BUFGP | 0.000| |
ssg<6> | 9.768(R)|clk_sel3_BUFGP | 0.000| |
------------+------------+------------------+--------+ |
|
Clock to Setup on destination clock clk_sel3 |
---------------+---------+---------+---------+---------+ |
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
---------------+---------+---------+---------+---------+ |
clk_sel3 | 1.665| | | | |
---------------+---------+---------+---------+---------+ |
|
Clock to Setup on destination clock mclk |
---------------+---------+---------+---------+---------+ |
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
---------------+---------+---------+---------+---------+ |
mclk | 3.894| | | | |
mclk | 3.911| | | | |
---------------+---------+---------+---------+---------+ |
|
Pad to Pad |
74,30 → 84,18
---------------+---------------+---------+ |
Source Pad |Destination Pad| Delay | |
---------------+---------------+---------+ |
btn<0> |an<0> | 7.251| |
btn<0> |ssg<7> | 5.729| |
btn<1> |an<1> | 7.651| |
btn<2> |an<2> | 7.337| |
btn<3> |an<3> | 8.237| |
btn_ext<0> |led_ext<0> | 5.009| |
btn_ext<0> |led_ext<1> | 5.492| |
btn_ext<1> |led_ext<2> | 6.201| |
btn_ext<1> |led_ext<3> | 5.902| |
btn_ext<2> |led_ext<4> | 5.510| |
btn_ext<2> |led_ext<5> | 5.740| |
btn_ext<3> |led_ext<6> | 6.200| |
btn_ext<4> |led_ext<7> | 5.256| |
swt<0> |an<0> | 8.111| |
swt<0> |an<1> | 9.103| |
swt<0> |an<2> | 7.979| |
swt<0> |an<3> | 8.142| |
swt<0> |ssg<0> | 8.932| |
swt<0> |ssg<1> | 9.285| |
swt<0> |ssg<2> | 8.511| |
swt<0> |ssg<3> | 9.010| |
swt<0> |ssg<4> | 9.699| |
swt<0> |ssg<5> | 8.732| |
swt<0> |ssg<6> | 9.283| |
btn<0> |led<4> | 8.204| |
btn<1> |led<5> | 7.608| |
btn<2> |led<6> | 6.966| |
btn<3> |led<7> | 7.685| |
swt<0> |led<0> | 4.993| |
swt<1> |led<1> | 5.003| |
swt<2> |led<2> | 5.037| |
swt<3> |led<3> | 4.991| |
swt<4> |led<4> | 5.931| |
swt<5> |led<5> | 7.085| |
swt<6> |led<6> | 6.185| |
swt<7> |led<7> | 6.719| |
---------------+---------------+---------+ |
|
|
108,7 → 106,7
------------------------- |
Trace Settings |
|
Peak Memory Usage: 101 MB |
Peak Memory Usage: 100 MB |
|
|
|
/projects/S3Demo/S3demo.syr
107,15 → 107,11
========================================================================= |
* HDL Compilation * |
========================================================================= |
Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/RS232RefComp.vhd" in Library work. |
Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/RS232RefComp.vhd" in Library work. |
Architecture behavioral of Entity rs232refcomp is up to date. |
Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/vga_main.vhd" in Library work. |
Architecture behavioral of Entity vgacontroller is up to date. |
Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/kb2vhdl.vhd" in Library work. |
Architecture behavioral of Entity keyboardvhdl is up to date. |
Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/DataCntrl.vhd" in Library work. |
Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/DataCntrl.vhd" in Library work. |
Architecture behavioral of Entity datacntrl is up to date. |
Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/S3demo.vhd" in Library work. |
Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/S3demo.vhd" in Library work. |
Entity <s3demo> compiled. |
ERROR:HDLParsers:164 - "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/S3demo.vhd" Line 102. parse error, unexpected IDENTIFIER |
--> |
/projects/S3Demo/S3demo_pad.csv
25,50 → 25,50
P4,swt<5>,IBUF,IO_L01N_3,INPUT,LVCMOS25*,3,,,,IBUF,,LOCATED,NO,NONE, |
P5,led<6>,IOB,IO_L02P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P6,swt<6>,IBUF,IO_L02N_3,INPUT,LVCMOS25*,3,,,,IBUF,,LOCATED,NO,NONE, |
P7,,DIFFSI_NDT,IP_3/VREF_3,UNUSED,,3,,,,,,,,, |
P7,swt<7>,IBUF,IP_3/VREF_3,INPUT,LVCMOS25*,3,,,,IBUF,,LOCATED,NO,NONE, |
P8,,,GND,,,,,,,,,,,, |
P9,swt<7>,IBUF,IO_L03P_3/LHCLK0,INPUT,LVCMOS25*,3,,,,IBUF,,LOCATED,NO,NONE, |
P9,led<7>,IOB,IO_L03P_3/LHCLK0,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P10,,DIFFSLR,IO_L03N_3/LHCLK1,UNUSED,,3,,,,,,,,, |
P11,,,VCCO_3,,,3,,,,,2.50,,,, |
P12,vs,IOB,IO_L04P_3/LHCLK2,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P13,red,IOB,IO_L04N_3/IRDY2/LHCLK3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P12,,DIFFMLR,IO_L04P_3/LHCLK2,UNUSED,,3,,,,,,,,, |
P13,,DIFFSLR,IO_L04N_3/IRDY2/LHCLK3,UNUSED,,3,,,,,,,,, |
P14,,,GND,,,,,,,,,,,, |
P15,hs,IOB,IO_L05P_3/TRDY2/LHCLK6,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P16,grn,IOB,IO_L05N_3/LHCLK7,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P15,,DIFFMLR,IO_L05P_3/TRDY2/LHCLK6,UNUSED,,3,,,,,,,,, |
P16,,DIFFSLR,IO_L05N_3/LHCLK7,UNUSED,,3,,,,,,,,, |
P17,,,VCCINT,,,,,,,,1.2,,,, |
P18,,,GND,,,,,,,,,,,, |
P19,kc,IBUF,IO_L06P_3,INPUT,LVCMOS25*,3,,,,IBUF,,LOCATED,NO,NONE, |
P20,blu,IOB,IO_L06N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P21,kd,IBUF,IP_3,INPUT,LVCMOS25*,3,,,,IBUF,,LOCATED,NO,NONE, |
P19,,DIFFMLR,IO_L06P_3,UNUSED,,3,,,,,,,,, |
P20,,DIFFSLR,IO_L06N_3,UNUSED,,3,,,,,,,,, |
P21,,DIFFMI_NDT,IP_3,UNUSED,,3,,,,,,,,, |
P22,,,VCCAUX,,,,,,,,2.5,,,, |
P23,,DIFFMTB,IO_L01P_2/M1,UNUSED,,2,,,,,,,,, |
P24,,DIFFMTB,IO_L02P_2/M2,UNUSED,,2,,,,,,,,, |
P25,,DIFFSTB,IO_L01N_2/M0,UNUSED,,2,,,,,,,,, |
P26,,,VCCO_2,,,2,,,,,2.50,,,, |
P27,led<7>,IOB,IO_L02N_2/CSO_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P28,ssg<4>,IOB,IO_L03P_2/RDWR_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P29,led_ext<7>,IOB,IO_L03N_2/VS2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P30,btn_ext<4>,IBUF,IO_L04P_2/VS1,INPUT,LVCMOS25*,2,,,,IBUF,,LOCATED,NO,NONE, |
P31,led_ext<6>,IOB,IO_L04N_2/VS0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P32,led_ext<5>,IOB,IO_L05P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P33,led_ext<4>,IOB,IO_L05N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P34,led_ext<3>,IOB,IO_L06P_2/D7,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P35,led_ext<2>,IOB,IO_L06N_2/D6,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P36,led_ext<0>,IOB,IO_L07P_2/D5,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P37,btn_ext<2>,IBUF,IO_L07N_2/D4,INPUT,LVCMOS25*,2,,,,IBUF,,LOCATED,NO,NONE, |
P26,,,VCCO_2,,,2,,,,,any******,,,, |
P27,,DIFFSTB,IO_L02N_2/CSO_B,UNUSED,,2,,,,,,,,, |
P28,,DIFFMTB,IO_L03P_2/RDWR_B,UNUSED,,2,,,,,,,,, |
P29,,DIFFSTB,IO_L03N_2/VS2,UNUSED,,2,,,,,,,,, |
P30,,DIFFMTB,IO_L04P_2/VS1,UNUSED,,2,,,,,,,,, |
P31,,DIFFSTB,IO_L04N_2/VS0,UNUSED,,2,,,,,,,,, |
P32,,DIFFMTB,IO_L05P_2,UNUSED,,2,,,,,,,,, |
P33,,DIFFSTB,IO_L05N_2,UNUSED,,2,,,,,,,,, |
P34,,DIFFMTB,IO_L06P_2/D7,UNUSED,,2,,,,,,,,, |
P35,,DIFFSTB,IO_L06N_2/D6,UNUSED,,2,,,,,,,,, |
P36,,DIFFMTB,IO_L07P_2/D5,UNUSED,,2,,,,,,,,, |
P37,,DIFFSTB,IO_L07N_2/D4,UNUSED,,2,,,,,,,,, |
P38,,,VCCINT,,,,,,,,1.2,,,, |
P39,btn_ext<0>,IBUF,IP_2/VREF_2,INPUT,LVCMOS25*,2,,,,IBUF,,LOCATED,NO,NONE, |
P40,,DIFFMTB,IO_L08P_2/GCLK14,UNUSED,,2,,,,,,,,, |
P41,,DIFFSTB,IO_L08N_2/GCLK15,UNUSED,,2,,,,,,,,, |
P39,,IBUF,IP_2/VREF_2,UNUSED,,2,,,,,,,,, |
P40,clk_sel3,IBUF,IO_L08P_2/GCLK14,INPUT,LVCMOS25*,2,,,,IBUF,,LOCATED,NO,NONE, |
P41,clk_sel2,IBUF,IO_L08N_2/GCLK15,INPUT,LVCMOS25*,2,,,,IBUF,,LOCATED,NO,NONE, |
P42,,,GND,,,,,,,,,,,, |
P43,mclk,IBUF,IO_L09P_2/GCLK0,INPUT,LVCMOS25*,2,,,,IBUF,,LOCATED,NO,NONE, |
P44,,DIFFSTB,IO_L09N_2/GCLK1,UNUSED,,2,,,,,,,,, |
P45,,,VCCO_2,,,2,,,,,2.50,,,, |
P46,led_ext<1>,IOB,IO_2/MOSI/CSI_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P44,clk_sel1,IBUF,IO_L09N_2/GCLK1,INPUT,LVCMOS25*,2,,,,IBUF,,LOCATED,NO,NONE, |
P45,,,VCCO_2,,,2,,,,,any******,,,, |
P46,,DIFFSTB,IO_2/MOSI/CSI_B,UNUSED,,2,,,,,,,,, |
P47,,,GND,,,,,,,,,,,, |
P48,,DIFFMTB,IO_L10P_2/INIT_B,UNUSED,,2,,,,,,,,, |
P49,btn_ext<3>,IBUF,IO_L10N_2/D3,INPUT,LVCMOS25*,2,,,,IBUF,,LOCATED,NO,NONE, |
P50,btn_ext<1>,IBUF,IO_L11P_2/D2,INPUT,LVCMOS25*,2,,,,IBUF,,LOCATED,NO,NONE, |
P49,,DIFFSTB,IO_L10N_2/D3,UNUSED,,2,,,,,,,,, |
P50,,DIFFMTB,IO_L11P_2/D2,UNUSED,,2,,,,,,,,, |
P51,,DIFFMTB,IO_L12P_2/D0/DIN/MISO,UNUSED,,2,,,,,,,,, |
P52,rxd,IBUF,IO_L11N_2/D1,INPUT,LVCMOS25*,2,,,,IBUF,,LOCATED,NO,NONE, |
P53,,DIFFSTB,IO_L12N_2/CCLK,UNUSED,,2,,,,,,,,, |
86,7 → 86,7
P65,ssg<0>,IOB,IO_L04N_1/RHCLK7,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P66,,,VCCINT,,,,,,,,1.2,,,, |
P67,,,VCCO_1,,,1,,,,,2.50,,,, |
P68,,DIFFMI_NDT,IP_1/VREF_1,UNUSED,,1,,,,,,,,, |
P68,btn<0>,IBUF,IP_1/VREF_1,INPUT,LVCMOS25*,1,,,,IBUF,,LOCATED,NO,NONE, |
P69,,,GND,,,,,,,,,,,, |
P70,ssg<3>,IOB,IO_L05P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P71,ssg<7>,IOB,IO_L05N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
95,7 → 95,7
P74,,,GND,,,,,,,,,,,, |
P75,,,TDO,,,,,,,,,,,, |
P76,,,TCK,,,,,,,,,,,, |
P77,btn<0>,IBUF,IO_L01P_0/VREF_0,INPUT,LVCMOS25*,0,,,,IBUF,,LOCATED,NO,NONE, |
P77,ssg<4>,IOB,IO_L01P_0/VREF_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,LOCATED,NO,NONE, |
P78,btn<1>,IBUF,IO_L01N_0,INPUT,LVCMOS25*,0,,,,IBUF,,LOCATED,NO,NONE, |
P79,,,VCCO_0,,,0,,,,,2.50,,,, |
P80,,,GND,,,,,,,,,,,, |
/projects/S3Demo/webtalk.log
13,4 → 13,4
INFO:WebTalk:8 - WebTalk Install setting is ON. |
INFO:WebTalk:6 - WebTalk User setting is ON. |
|
INFO:WebTalk:5 - /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html |
INFO:WebTalk:5 - /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html |
/projects/S3Demo/S3demo.vhd
42,20 → 42,17
|
entity S3demo is |
Port ( |
mclk : in std_logic; |
btn : in std_logic_vector(3 downto 0); |
btn_ext : in std_logic_vector(4 downto 0); |
mclk : in std_logic; |
clk_sel1: in std_logic; |
clk_sel2: in std_logic; |
clk_sel3: in std_logic; |
btn : in std_logic_vector(3 downto 0); |
swt : in std_logic_vector(7 downto 0); |
led : out std_logic_vector(7 downto 0); |
led_ext : out std_logic_vector(7 downto 0); |
led : out std_logic_vector(7 downto 0); |
an : out std_logic_vector(3 downto 0); |
ssg : out std_logic_vector(7 downto 0); |
hs : out std_logic; |
vs : out std_logic; |
red, grn, blu : out std_logic; |
ssg : out std_logic_vector(7 downto 0); |
txd : out std_logic; |
rxd : in std_logic; |
kd, kc : in std_logic); |
rxd : in std_logic); |
end S3demo; |
|
architecture Behavioral of S3demo is |
63,28 → 60,13
------------------------------------------------------------------------ |
-- Component Declarations |
------------------------------------------------------------------------ |
component vgaController is |
Port ( mclk : in std_logic; |
hs : out std_logic; |
vs : out std_logic; |
red : out std_logic; |
grn : out std_logic; |
blu : out std_logic); |
end component; |
|
component keyboardVhdl is |
Port ( CLK, RST, KD, KC: in std_logic; |
an: out std_logic_vector (3 downto 0); |
sseg: out std_logic_vector (6 downto 0)); |
end component; |
|
|
|
component DataCntrl is |
Port ( |
TXD : out std_logic;-- := '1'; |
RXD : in std_logic;-- := '1'; |
CLK : in std_logic; |
LEDS : out std_logic_vector(7 downto 0);-- := "11111111"; |
LEDS : out std_logic_vector(7 downto 0);-- := "11111111"; |
RST : in std_logic);-- := '0'); |
end component; |
|
93,9 → 75,12
-- Signal Declarations |
------------------------------------------------------------------------ |
|
signal clkdiv : std_logic_vector(23 downto 0); |
signal cntr : std_logic_vector(3 downto 0); |
signal cclk : std_logic; |
signal clkdiv : std_logic_vector(26 downto 0); |
signal clkdiv_sel1 : std_logic_vector(23 downto 0); |
signal cntr : std_logic_vector(3 downto 0); |
signal San_cntr : std_logic_vector(1 downto 0); |
signal cclk : std_logic; |
signal cclk_sel1 : std_logic; |
signal dig : std_logic_vector(6 downto 0); |
signal ssegkb : std_logic_vector(6 downto 0); |
signal ankb : std_logic_vector(3 downto 0); |
105,81 → 90,85
------------------------------------------------------------------------ |
|
begin |
|
vga1: vgaController port map (mclk => mclk, |
hs => hs, |
vs => vs, |
red => red, |
grn => grn, |
blu => blu); |
|
kb1: keyboardVhdl port map( CLK => mclk, |
RST => rst, |
KD => kd, |
KC => kc, |
an => ankb, |
sseg => ssegkb); |
|
RS232Proj: DataCntrl port map( TXD => txd, |
RXD => rxd, |
CLK => mclk, |
LEDS => led,--rxd_out_vector, |
RST => btn(3));-- := '0'); |
|
|
rst <= btn(0); |
|
RS232Proj: DataCntrl port map( TXD => txd, |
RXD => rxd, |
CLK => mclk, |
LEDS => rxd_out_vector, |
RST => rst); |
|
rst <= btn(0); |
|
--led(7 downto 1) <= swt(7 downto 1); |
--led(0) <= swt(0); |
|
dig <= "0111111" when cntr = "0000" else |
"0000110" when cntr = "0001" else |
"1011011" when cntr = "0010" else |
"1001111" when cntr = "0011" else |
"1100110" when cntr = "0100" else |
"1101101" when cntr = "0101" else |
"1111101" when cntr = "0110" else |
"0000111" when cntr = "0111" else |
"1111111" when cntr = "1000" else |
"1101111" when cntr = "1001" else |
"0000000"; |
led(3 downto 0) <= not swt(3 downto 0); |
led(7 downto 4) <= not btn xor swt(7 downto 4); |
|
-- Divide the master clock (50Mhz) down to a lower frequency. |
process (mclk) |
begin |
if mclk = '1' and mclk'Event then |
clkdiv <= clkdiv + 1; |
end if; |
end process; |
|
ssg(6 downto 0) <= not dig when swt(0) = '0' else |
ssegkb; |
an <= btn when swt(0) = '0' else |
ankb; |
ssg(7) <= btn(0); |
cclk <= clkdiv(24); --toma el bit 24 del contador clkdiv para reducir la frecuencia a (50Mhz/2^24) |
|
-- Contado decimal. Utiliza la nueva señal de clock (cclk) a partir de los 50Mhz |
process (cclk) |
begin |
if cclk = '1' and cclk'Event then |
if cntr = "1001" then |
cntr <= "0000"; |
else |
cntr <= cntr + 1; |
end if; |
end if; |
end process; |
|
-- Conversor binario a decimal |
dig <="0111111" when cntr = "0000" else |
"0000110" when cntr = "0001" else |
"1011011" when cntr = "0010" else |
"1001111" when cntr = "0011" else |
"1100110" when cntr = "0100" else |
"1101101" when cntr = "0101" else |
"1111101" when cntr = "0110" else |
"0000111" when cntr = "0111" else |
"1111111" when cntr = "1000" else |
"1101111" when cntr = "1001" else |
"0000000"; |
|
-- Se utiliza el clk_sel3(entrada de clock externa de baja frecuencia) para barrir el display. |
cclk_sel1 <= clk_sel3;--clkdiv_sel1(10); |
|
-- Genero un contador para la secuencia de los transistores |
process (cclk_sel1) |
begin |
if cclk_sel1 = '1' and cclk_sel1'Event then |
San_cntr <= San_cntr + 1; |
end if; |
end process; |
|
-- Se genera el barrido |
an <= "1110" when San_cntr = "00" else |
"1101" when San_cntr = "01" else |
"1011" when San_cntr = "10" else |
"0111" when San_cntr = "11" else |
"1111"; |
|
-- Se muestra el contador decimal en el primer digito, en los demás se muestra un número fijo (1,2,3). |
--ssg(6 downto 0) <= not dig when San_cntr="00" else -- se utiliza el "not" por ser anodo común. |
-- "1111001" when San_cntr="01" else |
-- "0100100" when San_cntr="10" else |
-- "0110000" when San_cntr="11" else |
-- "1111111"; |
|
ssg(6 downto 0) <= not dig when San_cntr="00" else -- se utiliza el "not" por ser anodo común. |
-- "1111001" when San_cntr="01" else |
-- "0100100" when San_cntr="10" else |
-- "0110000" when San_cntr="11" else |
"0000000"; |
|
ssg(7) <= '1'; -- Se apaga el punto del 7seg. |
|
-- Divide the master clock (50Mhz) down to a lower frequency. |
process (mclk) |
begin |
if mclk = '1' and mclk'Event then |
clkdiv <= clkdiv + 1; |
end if; |
end process; |
|
cclk <= clkdiv(23); |
|
process (cclk) |
begin |
if cclk = '1' and cclk'Event then |
if cntr = "1001" then |
cntr <= "0000"; |
else |
cntr <= cntr + 1; |
end if; |
end if; |
|
end process; |
|
led_ext(0) <= not btn_ext(0); |
led_ext(1) <= not btn_ext(0); |
led_ext(2) <= not btn_ext(1); |
led_ext(3) <= not btn_ext(1); |
led_ext(4) <= not btn_ext(2); |
led_ext(5) <= not btn_ext(2); |
led_ext(6) <= not btn_ext(3); |
led_ext(7) <= not btn_ext(4); |
|
end Behavioral; |
|
/projects/S3Demo/S3demo.twx
334,5 → 334,5
|
</twCmdLine><twDesign>S3demo.ncd</twDesign><twDesignPath>S3demo.ncd</twDesignPath><twPCF>S3demo.pcf</twPCF><twPcfPath>S3demo.pcf</twPcfPath><twDevInfo arch="spartan3a" pkg="vq100"><twDevName>xc3s200a</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.41 2010-09-15</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twInfo anchorID="5">INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</twInfo><twInfo anchorID="6">INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="7" twNameLen="15"><twSUH2ClkList anchorID="8" twDestWidth="6" twPhaseWidth="10"><twDest>mclk</twDest><twSUH2Clk ><twSrc>btn<3></twSrc><twSUHTime twInternalClk ="mclk_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">1.289</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="f">0.324</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2OutList anchorID="9" twDestWidth="6" twPhaseWidth="10"><twSrc>mclk</twSrc><twClk2Out twOutPad = "an<0>" twMinTime = "7.036" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "8.531" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="mclk_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "an<1>" twMinTime = "7.587" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "9.219" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="mclk_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ssg<0>" twMinTime = "8.921" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "11.202" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="mclk_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ssg<1>" twMinTime = "8.925" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "11.110" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="mclk_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ssg<2>" twMinTime = "8.778" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "10.926" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="mclk_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ssg<3>" twMinTime = "8.766" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "11.008" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="mclk_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ssg<4>" twMinTime = "9.775" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "12.286" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="mclk_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ssg<5>" twMinTime = "8.790" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "11.038" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="mclk_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ssg<6>" twMinTime = "8.985" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "11.281" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="mclk_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="10" twDestWidth="4"><twDest>mclk</twDest><twClk2SU><twSrc>mclk</twSrc><twRiseRise>3.894</twRiseRise></twClk2SU></twClk2SUList><twPad2PadList anchorID="11" twSrcWidth="10" twDestWidth="10"><twPad2Pad><twSrc>btn<0></twSrc><twDest>an<0></twDest><twDel>7.251</twDel></twPad2Pad><twPad2Pad><twSrc>btn<0></twSrc><twDest>ssg<7></twDest><twDel>5.729</twDel></twPad2Pad><twPad2Pad><twSrc>btn<1></twSrc><twDest>an<1></twDest><twDel>7.651</twDel></twPad2Pad><twPad2Pad><twSrc>btn<2></twSrc><twDest>an<2></twDest><twDel>7.337</twDel></twPad2Pad><twPad2Pad><twSrc>btn<3></twSrc><twDest>an<3></twDest><twDel>8.237</twDel></twPad2Pad><twPad2Pad><twSrc>btn_ext<0></twSrc><twDest>led_ext<0></twDest><twDel>5.009</twDel></twPad2Pad><twPad2Pad><twSrc>btn_ext<0></twSrc><twDest>led_ext<1></twDest><twDel>5.492</twDel></twPad2Pad><twPad2Pad><twSrc>btn_ext<1></twSrc><twDest>led_ext<2></twDest><twDel>6.201</twDel></twPad2Pad><twPad2Pad><twSrc>btn_ext<1></twSrc><twDest>led_ext<3></twDest><twDel>5.902</twDel></twPad2Pad><twPad2Pad><twSrc>btn_ext<2></twSrc><twDest>led_ext<4></twDest><twDel>5.510</twDel></twPad2Pad><twPad2Pad><twSrc>btn_ext<2></twSrc><twDest>led_ext<5></twDest><twDel>5.740</twDel></twPad2Pad><twPad2Pad><twSrc>btn_ext<3></twSrc><twDest>led_ext<6></twDest><twDel>6.200</twDel></twPad2Pad><twPad2Pad><twSrc>btn_ext<4></twSrc><twDest>led_ext<7></twDest><twDel>5.256</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>an<0></twDest><twDel>8.111</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>an<1></twDest><twDel>9.103</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>an<2></twDest><twDel>7.979</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>an<3></twDest><twDel>8.142</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>ssg<0></twDest><twDel>8.932</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>ssg<1></twDest><twDel>9.285</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>ssg<2></twDest><twDel>8.511</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>ssg<3></twDest><twDel>9.010</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>ssg<4></twDest><twDel>9.699</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>ssg<5></twDest><twDel>8.732</twDel></twPad2Pad><twPad2Pad><twSrc>swt<0></twSrc><twDest>ssg<6></twDest><twDel>9.283</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Fri Sep 5 17:08:51 2014 </twTimestamp></twFoot><twClientInfo anchorID="12"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue> |
|
Peak Memory Usage: 101 MB |
Peak Memory Usage: 100 MB |
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport> |
/projects/S3Demo/S3demo.unroutes
5,15 → 5,10
|
All signals are completely routed. |
|
WARNING:ParHelpers:361 - There are 7 loadless signals in this design. This design will cause Bitgen to issue DRC |
WARNING:ParHelpers:361 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC |
warnings. |
|
swt<1>_IBUF |
swt<2>_IBUF |
swt<3>_IBUF |
swt<4>_IBUF |
swt<5>_IBUF |
swt<6>_IBUF |
swt<7>_IBUF |
clk_sel1_IBUF |
clk_sel2_IBUF |
|
|
/projects/S3Demo/_ngo/netlist.lst
1,2 → 1,2
/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/S3demo.ngc 1399424055 |
/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/S3demo.ngc 1418855612 |
OK |
/projects/S3Demo/webtalk_pn.xml
40,7 → 40,7
<property name="PROP_DevSpeed" value="-5" type="design"/> |
<property name="PROP_PreferredLanguage" value="Verilog" type="design"/> |
<property name="FILE_UCF" value="1" type="source"/> |
<property name="FILE_VHDL" value="5" type="source"/> |
<property name="FILE_VHDL" value="3" type="source"/> |
</section> |
</application> |
</document> |
/projects/S3Demo/S3demo.ptwx
329,4 → 329,4
<!ELEMENT twName (#PCDATA)> |
<!ELEMENT twValue (#PCDATA)> |
]> |
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net kb1_KCI</twConstName><twConstData type="SETUP" best="7.382" units="ns" score="0"/><twConstData type="HOLD" slack="0.815" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net mclk_BUFGP</twConstName><twConstData type="SETUP" best="3.894" units="ns" score="0"/><twConstData type="HOLD" slack="1.092" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net RS232Proj_UART_rClk</twConstName><twConstData type="SETUP" best="4.195" units="ns" score="0"/><twConstData type="HOLD" slack="0.789" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net vga1_clkdiv</twConstName><twConstData type="SETUP" best="4.213" units="ns" score="0"/><twConstData type="HOLD" slack="0.924" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net RS232Proj_UART_rClkDiv<3></twConstName><twConstData type="SETUP" best="2.862" units="ns" score="0"/><twConstData type="HOLD" slack="0.995" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clkdiv<23></twConstName><twConstData type="SETUP" best="2.271" units="ns" score="0"/><twConstData type="HOLD" slack="1.167" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net kb1_clkDiv<3></twConstName><twConstData type="SETUP" best="1.173" units="ns" score="0"/><twConstData type="HOLD" slack="0.814" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" best="1.328" units="ns" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="5">0</twUnmetConstCnt><twInfo anchorID="6">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport> |
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net RS232Proj_UART_rClk</twConstName><twConstData type="SETUP" best="3.435" units="ns" score="0"/><twConstData type="HOLD" slack="0.803" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clk_sel3_BUFGP</twConstName><twConstData type="SETUP" best="1.665" units="ns" score="0"/><twConstData type="HOLD" slack="1.183" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net mclk_BUFGP</twConstName><twConstData type="SETUP" best="3.911" units="ns" score="0"/><twConstData type="HOLD" slack="0.957" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net RS232Proj_UART_rClkDiv<3></twConstName><twConstData type="SETUP" best="2.702" units="ns" score="0"/><twConstData type="HOLD" slack="0.805" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clkdiv<24></twConstName><twConstData type="SETUP" best="2.448" units="ns" score="0"/><twConstData type="HOLD" slack="1.255" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="5">0</twUnmetConstCnt><twInfo anchorID="6">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport> |
/projects/S3Demo/DataCntrl.vhd
48,10 → 48,11
-- |
------------------------------------------------------------------------- |
entity DataCntrl is |
Port ( TXD : out std_logic := '1'; |
Port ( |
TXD : out std_logic := '1'; |
RXD : in std_logic := '1'; |
CLK : in std_logic; |
LEDS : out std_logic_vector(7 downto 0) := "11111111"; |
LEDS : out std_logic_vector(7 downto 0) := "11111111"; |
RST : in std_logic := '0'); |
end DataCntrl; |
|
/projects/S3Demo/S3demo.pad
25,50 → 25,50
P4|swt<5>|IBUF|IO_L01N_3|INPUT|LVCMOS25*|3||||IBUF||LOCATED|NO|NONE| |
P5|led<6>|IOB|IO_L02P_3|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P6|swt<6>|IBUF|IO_L02N_3|INPUT|LVCMOS25*|3||||IBUF||LOCATED|NO|NONE| |
P7||DIFFSI_NDT|IP_3/VREF_3|UNUSED||3||||||||| |
P7|swt<7>|IBUF|IP_3/VREF_3|INPUT|LVCMOS25*|3||||IBUF||LOCATED|NO|NONE| |
P8|||GND|||||||||||| |
P9|swt<7>|IBUF|IO_L03P_3/LHCLK0|INPUT|LVCMOS25*|3||||IBUF||LOCATED|NO|NONE| |
P9|led<7>|IOB|IO_L03P_3/LHCLK0|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P10||DIFFSLR|IO_L03N_3/LHCLK1|UNUSED||3||||||||| |
P11|||VCCO_3|||3|||||2.50|||| |
P12|vs|IOB|IO_L04P_3/LHCLK2|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P13|red|IOB|IO_L04N_3/IRDY2/LHCLK3|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P12||DIFFMLR|IO_L04P_3/LHCLK2|UNUSED||3||||||||| |
P13||DIFFSLR|IO_L04N_3/IRDY2/LHCLK3|UNUSED||3||||||||| |
P14|||GND|||||||||||| |
P15|hs|IOB|IO_L05P_3/TRDY2/LHCLK6|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P16|grn|IOB|IO_L05N_3/LHCLK7|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P15||DIFFMLR|IO_L05P_3/TRDY2/LHCLK6|UNUSED||3||||||||| |
P16||DIFFSLR|IO_L05N_3/LHCLK7|UNUSED||3||||||||| |
P17|||VCCINT||||||||1.2|||| |
P18|||GND|||||||||||| |
P19|kc|IBUF|IO_L06P_3|INPUT|LVCMOS25*|3||||IBUF||LOCATED|NO|NONE| |
P20|blu|IOB|IO_L06N_3|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P21|kd|IBUF|IP_3|INPUT|LVCMOS25*|3||||IBUF||LOCATED|NO|NONE| |
P19||DIFFMLR|IO_L06P_3|UNUSED||3||||||||| |
P20||DIFFSLR|IO_L06N_3|UNUSED||3||||||||| |
P21||DIFFMI_NDT|IP_3|UNUSED||3||||||||| |
P22|||VCCAUX||||||||2.5|||| |
P23||DIFFMTB|IO_L01P_2/M1|UNUSED||2||||||||| |
P24||DIFFMTB|IO_L02P_2/M2|UNUSED||2||||||||| |
P25||DIFFSTB|IO_L01N_2/M0|UNUSED||2||||||||| |
P26|||VCCO_2|||2|||||2.50|||| |
P27|led<7>|IOB|IO_L02N_2/CSO_B|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P28|ssg<4>|IOB|IO_L03P_2/RDWR_B|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P29|led_ext<7>|IOB|IO_L03N_2/VS2|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P30|btn_ext<4>|IBUF|IO_L04P_2/VS1|INPUT|LVCMOS25*|2||||IBUF||LOCATED|NO|NONE| |
P31|led_ext<6>|IOB|IO_L04N_2/VS0|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P32|led_ext<5>|IOB|IO_L05P_2|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P33|led_ext<4>|IOB|IO_L05N_2|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P34|led_ext<3>|IOB|IO_L06P_2/D7|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P35|led_ext<2>|IOB|IO_L06N_2/D6|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P36|led_ext<0>|IOB|IO_L07P_2/D5|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P37|btn_ext<2>|IBUF|IO_L07N_2/D4|INPUT|LVCMOS25*|2||||IBUF||LOCATED|NO|NONE| |
P26|||VCCO_2|||2|||||any******|||| |
P27||DIFFSTB|IO_L02N_2/CSO_B|UNUSED||2||||||||| |
P28||DIFFMTB|IO_L03P_2/RDWR_B|UNUSED||2||||||||| |
P29||DIFFSTB|IO_L03N_2/VS2|UNUSED||2||||||||| |
P30||DIFFMTB|IO_L04P_2/VS1|UNUSED||2||||||||| |
P31||DIFFSTB|IO_L04N_2/VS0|UNUSED||2||||||||| |
P32||DIFFMTB|IO_L05P_2|UNUSED||2||||||||| |
P33||DIFFSTB|IO_L05N_2|UNUSED||2||||||||| |
P34||DIFFMTB|IO_L06P_2/D7|UNUSED||2||||||||| |
P35||DIFFSTB|IO_L06N_2/D6|UNUSED||2||||||||| |
P36||DIFFMTB|IO_L07P_2/D5|UNUSED||2||||||||| |
P37||DIFFSTB|IO_L07N_2/D4|UNUSED||2||||||||| |
P38|||VCCINT||||||||1.2|||| |
P39|btn_ext<0>|IBUF|IP_2/VREF_2|INPUT|LVCMOS25*|2||||IBUF||LOCATED|NO|NONE| |
P40||DIFFMTB|IO_L08P_2/GCLK14|UNUSED||2||||||||| |
P41||DIFFSTB|IO_L08N_2/GCLK15|UNUSED||2||||||||| |
P39||IBUF|IP_2/VREF_2|UNUSED||2||||||||| |
P40|clk_sel3|IBUF|IO_L08P_2/GCLK14|INPUT|LVCMOS25*|2||||IBUF||LOCATED|NO|NONE| |
P41|clk_sel2|IBUF|IO_L08N_2/GCLK15|INPUT|LVCMOS25*|2||||IBUF||LOCATED|NO|NONE| |
P42|||GND|||||||||||| |
P43|mclk|IBUF|IO_L09P_2/GCLK0|INPUT|LVCMOS25*|2||||IBUF||LOCATED|NO|NONE| |
P44||DIFFSTB|IO_L09N_2/GCLK1|UNUSED||2||||||||| |
P45|||VCCO_2|||2|||||2.50|||| |
P46|led_ext<1>|IOB|IO_2/MOSI/CSI_B|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P44|clk_sel1|IBUF|IO_L09N_2/GCLK1|INPUT|LVCMOS25*|2||||IBUF||LOCATED|NO|NONE| |
P45|||VCCO_2|||2|||||any******|||| |
P46||DIFFSTB|IO_2/MOSI/CSI_B|UNUSED||2||||||||| |
P47|||GND|||||||||||| |
P48||DIFFMTB|IO_L10P_2/INIT_B|UNUSED||2||||||||| |
P49|btn_ext<3>|IBUF|IO_L10N_2/D3|INPUT|LVCMOS25*|2||||IBUF||LOCATED|NO|NONE| |
P50|btn_ext<1>|IBUF|IO_L11P_2/D2|INPUT|LVCMOS25*|2||||IBUF||LOCATED|NO|NONE| |
P49||DIFFSTB|IO_L10N_2/D3|UNUSED||2||||||||| |
P50||DIFFMTB|IO_L11P_2/D2|UNUSED||2||||||||| |
P51||DIFFMTB|IO_L12P_2/D0/DIN/MISO|UNUSED||2||||||||| |
P52|rxd|IBUF|IO_L11N_2/D1|INPUT|LVCMOS25*|2||||IBUF||LOCATED|NO|NONE| |
P53||DIFFSTB|IO_L12N_2/CCLK|UNUSED||2||||||||| |
86,7 → 86,7
P65|ssg<0>|IOB|IO_L04N_1/RHCLK7|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P66|||VCCINT||||||||1.2|||| |
P67|||VCCO_1|||1|||||2.50|||| |
P68||DIFFMI_NDT|IP_1/VREF_1|UNUSED||1||||||||| |
P68|btn<0>|IBUF|IP_1/VREF_1|INPUT|LVCMOS25*|1||||IBUF||LOCATED|NO|NONE| |
P69|||GND|||||||||||| |
P70|ssg<3>|IOB|IO_L05P_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P71|ssg<7>|IOB|IO_L05N_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE| |
95,7 → 95,7
P74|||GND|||||||||||| |
P75|||TDO|||||||||||| |
P76|||TCK|||||||||||| |
P77|btn<0>|IBUF|IO_L01P_0/VREF_0|INPUT|LVCMOS25*|0||||IBUF||LOCATED|NO|NONE| |
P77|ssg<4>|IOB|IO_L01P_0/VREF_0|OUTPUT|LVCMOS25*|0|12|SLOW|NONE**|||LOCATED|NO|NONE| |
P78|btn<1>|IBUF|IO_L01N_0|INPUT|LVCMOS25*|0||||IBUF||LOCATED|NO|NONE| |
P79|||VCCO_0|||0|||||2.50|||| |
P80|||GND|||||||||||| |
/projects/S3Demo/S3demo.ucf
9,11 → 9,8
NET "btn<0>" LOC = "P77" ;# PHRBoard |
NET "btn<1>" LOC = "P78" ;# PHRBoard |
NET "btn<2>" LOC = "P82" ;# PHRBoard |
NET "btn<3>" LOC = "P83" ;# PHRBoard |
NET "grn" LOC = "P16 " ;# PHRBoard | CON-MOD (hembra) | Pin 4 | |
NET "hs" LOC = "P15" ;# PHRBoard | CON-MOD (hembra) | Pin 5 | |
NET "kc" LOC = "P19" ;# PHRBoard | CON-MOD (hembra) | Pin 3 | |
NET "kd" LOC = "P21" ;# PHRBoard | CON-MOD (hembra) | Pin 1 | |
NET "btn<3>" LOC = "P83" ;# PHRBoard |
|
NET "led<0>" LOC = "P84" ;# PHRBoard |
NET "led<1>" LOC = "P86" ;# PHRBoard |
NET "led<2>" LOC = "P89" ;# PHRBoard |
21,17 → 18,19
NET "led<4>" LOC = "P98" ;# PHRBoard |
NET "led<5>" LOC = "P3 " ;# PHRBoard |
NET "led<6>" LOC = "P5 " ;# PHRBoard |
NET "led<7>" LOC = "P27" ;# PHRBoard |
NET "led<7>" LOC = "P9" ;# PHRBoard |
|
NET "mclk" LOC = "P43" ;# PHRBoard |
NET "red" LOC = "P13" ;# PHRBoard | CON-MOD (hembra) | Pin 6 | |
NET "ssg<0>" LOC = "P65" ;# PHRBoard |
NET "ssg<1>" LOC = "P64" ;# PHRBoard |
NET "ssg<2>" LOC = "P72" ;# PHRBoard |
NET "ssg<3>" LOC = "P70" ;# PHRBoard |
NET "ssg<4>" LOC = "P28" ;# PHRBoard |
NET "ssg<5>" LOC = "P62" ;# PHRBoard |
NET "ssg<6>" LOC = "P73" ;# PHRBoard |
NET "ssg<7>" LOC = "P71" ;# PHRBoard |
|
NET "ssg<0>" LOC = "P65" ;# PHRBoard a |
NET "ssg<1>" LOC = "P64" ;# PHRBoard b |
NET "ssg<2>" LOC = "P72" ;# PHRBoard c |
NET "ssg<3>" LOC = "P70" ;# PHRBoard d |
NET "ssg<4>" LOC = "P77" ;# PHRBoard e |
NET "ssg<5>" LOC = "P62" ;# PHRBoard f |
NET "ssg<6>" LOC = "P73" ;# PHRBoard g |
NET "ssg<7>" LOC = "P71" ;# PHRBoard dot |
|
NET "swt<0>" LOC = "P85" ;# PHRBoard |
NET "swt<1>" LOC = "P88" ;# PHRBoard |
NET "swt<2>" LOC = "P90" ;# PHRBoard |
39,8 → 38,7
NET "swt<4>" LOC = "P97" ;# PHRBoard |
NET "swt<5>" LOC = "P4 " ;# PHRBoard |
NET "swt<6>" LOC = "P6 " ;# PHRBoard |
NET "swt<7>" LOC = "P9 " ;# PHRBoard |
NET "vs" LOC = "P12" ;# PHRBoard | CON-MOD (hembra) | Pin 7 | |
NET "swt<7>" LOC = "P7 " ;# PHRBoard |
|
#PACE: Start of PACE Area Constraints |
|
48,23 → 46,10
|
#PACE: End of Constraints generated by PACE |
|
# PHRBoard NET "clk_div_1" LOC = "P44"; |
# PHRBoard NET "clk_div_2" LOC = "P41"; |
# PHRBoard NET "clk_div_3" LOC = "P40"; |
NET "clk_sel1" LOC = "P44"; |
NET "clk_sel2" LOC = "P41"; |
NET "clk_sel3" LOC = "P40"; |
|
NET "rxd" LOC = "P52"; |
NET "txd" LOC = "P56"; |
NET "btn_ext<0>" LOC = "P39" ;# PHRBoard | CON-IO (macho) | Pin 1 | |
NET "btn_ext<1>" LOC = "P50" ;# PHRBoard | CON-IO (macho) | Pin 2 | |
NET "btn_ext<2>" LOC = "P37" ;# PHRBoard | CON-IO (macho) | Pin 3 | |
NET "btn_ext<3>" LOC = "P49" ;# PHRBoard | CON-IO (macho) | Pin 4 | |
|
NET "led_ext<0>" LOC = "P36" ;# PHRBoard | CON-IO (macho) | Pin 5 | |
NET "led_ext<1>" LOC = "P46" ;# PHRBoard | CON-IO (macho) | Pin 6 | |
NET "led_ext<2>" LOC = "P35" ;# PHRBoard | CON-IO (macho) | Pin 7 | |
NET "led_ext<3>" LOC = "P34" ;# PHRBoard | CON-IO (macho) | Pin 8 | |
NET "led_ext<4>" LOC = "P33" ;# PHRBoard | CON-IO (macho) | Pin 9 | |
NET "led_ext<5>" LOC = "P32" ;# PHRBoard | CON-IO (macho) | Pin 10 | |
NET "led_ext<6>" LOC = "P31" ;# PHRBoard | CON-IO (macho) | Pin 11 | |
NET "led_ext<7>" LOC = "P29" ;# PHRBoard | CON-IO (macho) | Pin 12 | |
NET "btn_ext<4>" LOC = "P30" ;# PHRBoard | CON-IO (macho) | Pin 13 | |
|
|
/projects/S3Demo/S3demo_summary.html
44,7 → 44,7
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/S3demo_envsettings.html'> |
<A HREF_DISABLED='/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/S3demo_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
/projects/S3Demo/S3demo.par
24,26 → 24,26
|
Design Summary Report: |
|
Number of External IOBs 55 out of 68 80% |
Number of External IOBs 38 out of 68 55% |
|
Number of External Input IOBs 21 |
Number of External Input IOBs 17 |
|
Number of External Input IBUFs 21 |
Number of LOCed External Input IBUFs 21 out of 21 100% |
Number of External Input IBUFs 17 |
Number of LOCed External Input IBUFs 17 out of 17 100% |
|
|
Number of External Output IOBs 34 |
Number of External Output IOBs 21 |
|
Number of External Output IOBs 34 |
Number of LOCed External Output IOBs 34 out of 34 100% |
Number of External Output IOBs 21 |
Number of LOCed External Output IOBs 21 out of 21 100% |
|
|
Number of External Bidir IOBs 0 |
|
|
Number of BUFGMUXs 4 out of 24 16% |
Number of Slices 121 out of 1792 6% |
Number of SLICEMs 2 out of 896 1% |
Number of BUFGMUXs 3 out of 24 12% |
Number of Slices 76 out of 1792 4% |
Number of SLICEMs 1 out of 896 1% |
|
|
|
55,13 → 55,8
Starting initial Timing Analysis. REAL time: 2 secs |
Finished initial Timing Analysis. REAL time: 2 secs |
|
WARNING:Par:288 - The signal swt<1>_IBUF has no load. PAR will not attempt to route this signal. |
WARNING:Par:288 - The signal swt<2>_IBUF has no load. PAR will not attempt to route this signal. |
WARNING:Par:288 - The signal swt<3>_IBUF has no load. PAR will not attempt to route this signal. |
WARNING:Par:288 - The signal swt<4>_IBUF has no load. PAR will not attempt to route this signal. |
WARNING:Par:288 - The signal swt<5>_IBUF has no load. PAR will not attempt to route this signal. |
WARNING:Par:288 - The signal swt<6>_IBUF has no load. PAR will not attempt to route this signal. |
WARNING:Par:288 - The signal swt<7>_IBUF has no load. PAR will not attempt to route this signal. |
WARNING:Par:288 - The signal clk_sel1_IBUF has no load. PAR will not attempt to route this signal. |
WARNING:Par:288 - The signal clk_sel2_IBUF has no load. PAR will not attempt to route this signal. |
|
Starting Placer |
Total REAL time at the beginning of Placer: 2 secs |
136,16 → 131,14
Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 13 secs |
|
Phase 12 : 0 unrouted; (Par is working to improve performance) REAL time: 13 secs |
WARNING:Route:455 - CLK Net:RS232Proj_UART_stbeCur_FSM_FFd1 may have excessive skew because |
1 CLK pins and 3 NON_CLK pins failed to route using a CLK template. |
WARNING:Route:455 - CLK Net:clkdiv<24> may have excessive skew because |
2 CLK pins and 1 NON_CLK pins failed to route using a CLK template. |
WARNING:Route:455 - CLK Net:RS232Proj_UART_rClkDiv<3> may have excessive skew because |
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. |
WARNING:Route:455 - CLK Net:RS232Proj_UART_stbeCur_FSM_FFd1 may have excessive skew because |
1 CLK pins and 3 NON_CLK pins failed to route using a CLK template. |
WARNING:Route:455 - CLK Net:RS232Proj_stCur<0> may have excessive skew because |
0 CLK pins and 5 NON_CLK pins failed to route using a CLK template. |
WARNING:Route:455 - CLK Net:clkdiv<23> may have excessive skew because |
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. |
WARNING:Route:455 - CLK Net:kb1_clkDiv<3> may have excessive skew because |
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. |
|
Total REAL time to Router completion: 13 secs |
Total CPU time to Router completion: 12 secs |
166,25 → 159,21
+---------------------+--------------+------+------+------------+-------------+ |
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| |
+---------------------+--------------+------+------+------------+-------------+ |
| kb1_KCI | BUFGMUX_X2Y11| No | 16 | 0.033 | 0.908 | |
| RS232Proj_UART_rClk | BUFGMUX_X1Y10| No | 18 | 0.040 | 0.913 | |
+---------------------+--------------+------+------+------------+-------------+ |
| mclk_BUFGP | BUFGMUX_X2Y1| No | 28 | 0.056 | 0.929 | |
| clk_sel3_BUFGP | BUFGMUX_X1Y1| No | 2 | 0.000 | 0.904 | |
+---------------------+--------------+------+------+------------+-------------+ |
| RS232Proj_UART_rClk | BUFGMUX_X1Y0| No | 18 | 0.025 | 0.908 | |
| mclk_BUFGP | BUFGMUX_X2Y1| No | 21 | 0.062 | 0.938 | |
+---------------------+--------------+------+------+------------+-------------+ |
| vga1_clkdiv | BUFGMUX_X1Y10| No | 11 | 0.025 | 0.915 | |
+---------------------+--------------+------+------+------------+-------------+ |
|RS232Proj_UART_rClkD | | | | | | |
| iv<3> | Local| | 11 | 0.043 | 1.394 | |
| iv<3> | Local| | 11 | 0.050 | 1.714 | |
+---------------------+--------------+------+------+------------+-------------+ |
| RS232Proj_stCur<0> | Local| | 9 | 0.093 | 1.844 | |
+---------------------+--------------+------+------+------------+-------------+ |
|RS232Proj_UART_stbeC | | | | | | |
| ur_FSM_FFd1 | Local| | 4 | 0.000 | 1.032 | |
| ur_FSM_FFd1 | Local| | 4 | 0.000 | 1.018 | |
+---------------------+--------------+------+------+------------+-------------+ |
| clkdiv<23> | Local| | 3 | 0.000 | 1.393 | |
| RS232Proj_stCur<0> | Local| | 9 | 0.041 | 1.613 | |
+---------------------+--------------+------+------+------------+-------------+ |
| kb1_clkDiv<3> | Local| | 4 | 0.004 | 1.800 | |
| clkdiv<24> | Local| | 3 | 0.000 | 1.046 | |
+---------------------+--------------+------+------+------------+-------------+ |
|
* Net Skew is the difference between the minimum and maximum routing |
201,28 → 190,21
Constraint | Check | Worst Case | Best Case | Timing | Timing |
| | Slack | Achievable | Errors | Score |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net kb1 | SETUP | N/A| 7.382ns| N/A| 0 |
_KCI | HOLD | 0.815ns| | 0| 0 |
Autotimespec constraint for clock net RS2 | SETUP | N/A| 3.435ns| N/A| 0 |
32Proj_UART_rClk | HOLD | 0.803ns| | 0| 0 |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net mcl | SETUP | N/A| 3.894ns| N/A| 0 |
k_BUFGP | HOLD | 1.092ns| | 0| 0 |
Autotimespec constraint for clock net clk | SETUP | N/A| 1.665ns| N/A| 0 |
_sel3_BUFGP | HOLD | 1.183ns| | 0| 0 |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net RS2 | SETUP | N/A| 4.195ns| N/A| 0 |
32Proj_UART_rClk | HOLD | 0.789ns| | 0| 0 |
Autotimespec constraint for clock net mcl | SETUP | N/A| 3.911ns| N/A| 0 |
k_BUFGP | HOLD | 0.957ns| | 0| 0 |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net vga | SETUP | N/A| 4.213ns| N/A| 0 |
1_clkdiv | HOLD | 0.924ns| | 0| 0 |
Autotimespec constraint for clock net RS2 | SETUP | N/A| 2.702ns| N/A| 0 |
32Proj_UART_rClkDiv<3> | HOLD | 0.805ns| | 0| 0 |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net RS2 | SETUP | N/A| 2.862ns| N/A| 0 |
32Proj_UART_rClkDiv<3> | HOLD | 0.995ns| | 0| 0 |
Autotimespec constraint for clock net clk | SETUP | N/A| 2.448ns| N/A| 0 |
div<24> | HOLD | 1.255ns| | 0| 0 |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net clk | SETUP | N/A| 2.271ns| N/A| 0 |
div<23> | HOLD | 1.167ns| | 0| 0 |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net kb1 | SETUP | N/A| 1.173ns| N/A| 0 |
_clkDiv<3> | HOLD | 0.814ns| | 0| 0 |
| MINPERIOD | N/A| 1.328ns| N/A| 0 |
---------------------------------------------------------------------------------------------------------- |
|
|
All constraints were met. |
237,7 → 219,7
|
All signals are completely routed. |
|
WARNING:Par:283 - There are 7 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. |
WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. |
|
Total REAL time to PAR completion: 13 secs |
Total CPU time to PAR completion: 12 secs |
248,7 → 230,7
Routing: Completed - No errors found. |
|
Number of error messages: 0 |
Number of warning messages: 14 |
Number of warning messages: 8 |
Number of info messages: 1 |
|
Writing design to file S3demo.ncd |
/projects/S3Demo/xst/work/hdpdeps.ref
1,4 → 1,4
V3 22 |
V3 25 |
FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/DataCntrl.vhd 2014/05/05.13:58:13 M.70d |
EN work/DataCntrl 1416615908 \ |
FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/DataCntrl.vhd \ |
/projects/S3Demo/xst/work/sub00/vhpl05.vho
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/projects/S3Demo/S3demo_map.mrp
14,31 → 14,31
Design Summary |
-------------- |
Number of errors: 0 |
Number of warnings: 7 |
Number of warnings: 2 |
Logic Utilization: |
Total Number Slice Registers: 166 out of 3,584 4% |
Number used as Flip Flops: 157 |
Total Number Slice Registers: 100 out of 3,584 2% |
Number used as Flip Flops: 91 |
Number used as Latches: 9 |
Number of 4 input LUTs: 100 out of 3,584 2% |
Number of 4 input LUTs: 75 out of 3,584 2% |
Logic Distribution: |
Number of occupied Slices: 121 out of 1,792 6% |
Number of Slices containing only related logic: 121 out of 121 100% |
Number of Slices containing unrelated logic: 0 out of 121 0% |
Number of occupied Slices: 76 out of 1,792 4% |
Number of Slices containing only related logic: 76 out of 76 100% |
Number of Slices containing unrelated logic: 0 out of 76 0% |
*See NOTES below for an explanation of the effects of unrelated logic. |
Total Number of 4 input LUTs: 162 out of 3,584 4% |
Number used as logic: 98 |
Number used as a route-thru: 62 |
Number used as Shift registers: 2 |
Total Number of 4 input LUTs: 108 out of 3,584 3% |
Number used as logic: 74 |
Number used as a route-thru: 33 |
Number used as Shift registers: 1 |
|
The Slice Logic Distribution report is not meaningful if the design is |
over-mapped for a non-slice resource or if Placement fails. |
|
Number of bonded IOBs: 55 out of 68 80% |
Number of BUFGMUXs: 4 out of 24 16% |
Number of bonded IOBs: 38 out of 68 55% |
Number of BUFGMUXs: 3 out of 24 12% |
|
Average Fanout of Non-Clock Nets: 2.52 |
Average Fanout of Non-Clock Nets: 2.43 |
|
Peak Memory Usage: 161 MB |
Peak Memory Usage: 160 MB |
Total REAL time to MAP completion: 4 secs |
Total CPU time to MAP completion: 2 secs |
|
81,31 → 81,17
|
Section 2 - Warnings |
-------------------- |
WARNING:PhysDesignRules:367 - The signal <swt<1>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<2>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<3>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<4>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<5>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<6>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<7>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <clk_sel1_IBUF> is incomplete. The |
signal does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <clk_sel2_IBUF> is incomplete. The |
signal does not drive any load pins in the design. |
|
Section 3 - Informational |
------------------------- |
INFO:LIT:243 - Logical network swt<7>_IBUF has no load. |
INFO:LIT:395 - The above info message is repeated 6 more times for the following |
INFO:LIT:243 - Logical network clk_sel1_IBUF has no load. |
INFO:LIT:395 - The above info message is repeated 1 more times for the following |
(max. 5 shown): |
swt<6>_IBUF, |
swt<5>_IBUF, |
swt<4>_IBUF, |
swt<3>_IBUF, |
swt<2>_IBUF |
clk_sel2_IBUF |
To see the details of these info messages, please use the -detail switch. |
INFO:MapLib:562 - No environment variables are currently set. |
INFO:LIT:244 - All of the single ended outputs in this design are using slew |
114,7 → 100,7
|
Section 4 - Removed Logic Summary |
--------------------------------- |
3 block(s) optimized away |
2 block(s) optimized away |
|
Section 5 - Removed Logic |
------------------------- |
138,20 → 124,13
| an<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| an<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| an<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| blu | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| btn<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| btn<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| btn<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| btn<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| btn_ext<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| btn_ext<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| btn_ext<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| btn_ext<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| btn_ext<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| grn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| hs | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| kc | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| kd | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| clk_sel1 | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| clk_sel2 | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| clk_sel3 | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| led<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
160,16 → 139,7
| led<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led_ext<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led_ext<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led_ext<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led_ext<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led_ext<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led_ext<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led_ext<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| led_ext<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| mclk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| red | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| rxd | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| ssg<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| ssg<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
188,7 → 158,6
| swt<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| swt<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | |
| txd | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
| vs | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
Section 7 - RPMs |
/projects/S3Demo/S3demo.xise
15,14 → 15,6
<version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="vga_main.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="kb2vhdl.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="S3demo.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
30,11 → 22,11
<file xil_pn:name="S3demo.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="DataCntrl.vhd" xil_pn:type="FILE_VHDL"> |
<file xil_pn:name="RS232RefComp.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="RS232RefComp.vhd" xil_pn:type="FILE_VHDL"> |
<file xil_pn:name="DataCntrl.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
/projects/S3Demo/S3demo.drc
5,19 → 5,9
|
drc -z S3demo.ncd S3demo.pcf |
|
WARNING:PhysDesignRules:367 - The signal <swt<1>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<2>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<3>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<4>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<5>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<6>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<7>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
DRC detected 0 errors and 7 warnings. Please see the previously displayed |
WARNING:PhysDesignRules:367 - The signal <clk_sel1_IBUF> is incomplete. The |
signal does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <clk_sel2_IBUF> is incomplete. The |
signal does not drive any load pins in the design. |
DRC detected 0 errors and 2 warnings. Please see the previously displayed |
individual error or warning messages for more details. |
/projects/S3Demo/iseconfig/S3demo.projectmgr
8,6 → 8,8
<ClosedNodes> |
<ClosedNodesVersion>2</ClosedNodesVersion> |
<ClosedNode>/DataCntrl - Behavioral |home|lguanuco|opencores|phr|trunk|codigo|demos|projects|S3Demo|DataCntrl.vhd</ClosedNode> |
<ClosedNode>/S3demo - Behavioral |home|lguanuco|opencores|phr|trunk|codigo|demos|projects|S3Demo2|S3demo.vhd/RS232Proj - DataCntrl - Behavioral</ClosedNode> |
<ClosedNode>/S3demo - Behavioral |home|lguanuco|opencores|phr|trunk|codigo|demos|projects|S3Demo|S3demo.vhd</ClosedNode> |
<ClosedNode>/S3demo - Behavioral |home|lguanuco|opencores|phr|trunk|codigo|demos|projects|S3Demo|S3demo.vhd/RS232Proj - DataCntrl - Behavioral</ClosedNode> |
</ClosedNodes> |
<SelectedItems> |
28,13 → 30,13
<ClosedNode>User Constraints</ClosedNode> |
</ClosedNodes> |
<SelectedItems> |
<SelectedItem></SelectedItem> |
<SelectedItem>Generate Programming File</SelectedItem> |
</SelectedItems> |
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> |
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000186000000010000000100000000000000000000000064ffffffff000000810000000000000001000001860000000100000000</ViewHeaderState> |
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem></CurrentItem> |
<CurrentItem>Generate Programming File</CurrentItem> |
</ItemView> |
<ItemView guiview="File" > |
<ClosedNodes> |
43,7 → 45,7
<SelectedItems/> |
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> |
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000039f000000040101000100000000000000000000000064ffffffff000000810000000000000004000000750000000100000000000000d00000000100000000000000840000000100000000000001d60000000100000000</ViewHeaderState> |
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000665000000040101000100000000000000000000000064ffffffff0000008100000000000000040000033b0000000100000000000000d00000000100000000000000840000000100000000000001d60000000100000000</ViewHeaderState> |
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem>/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/DataCntrl.vhd</CurrentItem> |
</ItemView> |
/projects/S3Demo/iseconfig/S3demo.xreport
4,8 → 4,8
<DateModified>2014-12-05T20:30:33</DateModified> |
<ModuleName>S3demo</ModuleName> |
<SummaryTimeStamp>2014-05-05T16:04:41</SummaryTimeStamp> |
<SavedFilePath>/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/iseconfig/S3demo.xreport</SavedFilePath> |
<ImplementationReportsDirectory>/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/</ImplementationReportsDirectory> |
<SavedFilePath>/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/iseconfig/S3demo.xreport</SavedFilePath> |
<ImplementationReportsDirectory>/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/</ImplementationReportsDirectory> |
<DateInitialized>2014-05-02T14:32:11</DateInitialized> |
<EnableMessageFiltering>false</EnableMessageFiltering> |
</header> |
/projects/S3Demo/S3demo.gise
22,6 → 22,7
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="S3demo.xise"/> |
|
<files xmlns="http://www.xilinx.com/XMLSchema"> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name=".lso"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="S3demo.bgn" xil_pn:subbranch="FPGAConfiguration"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="S3demo.bit" xil_pn:subbranch="FPGAConfiguration"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="S3demo.bld"/> |
84,11 → 85,11
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1399072765" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3716619188453653280" xil_pn:start_ts="1399072765"> |
<transform xil_pn:end_ts="1418849453" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3716619188453653280" xil_pn:start_ts="1418849453"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1399072765" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="3846051257213414380" xil_pn:start_ts="1399072765"> |
<transform xil_pn:end_ts="1418849453" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="3846051257213414380" xil_pn:start_ts="1418849453"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
96,7 → 97,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1399072765" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3970552786519378616" xil_pn:start_ts="1399072765"> |
<transform xil_pn:end_ts="1418849453" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3970552786519378616" xil_pn:start_ts="1418849453"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
104,7 → 105,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1399072765" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7533788573620134838" xil_pn:start_ts="1399072765"> |
<transform xil_pn:end_ts="1418849453" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7533788573620134838" xil_pn:start_ts="1418849453"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
111,6 → 112,7
<transform xil_pn:end_ts="1416615902" xil_pn:in_ck="-7977162588153681233" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-1348612597204470803" xil_pn:start_ts="1416615898"> |
<status xil_pn:value="FailedRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name=".lso"/> |
<outfile xil_pn:name="S3demo.lso"/> |
<outfile xil_pn:name="S3demo.ngc"/> |
<outfile xil_pn:name="S3demo.ngr"/> |
/projects/S3Demo/S3demo.prj
1,5 → 1,3
vhdl work "RS232RefComp.vhd" |
vhdl work "vga_main.vhd" |
vhdl work "kb2vhdl.vhd" |
vhdl work "DataCntrl.vhd" |
vhdl work "S3demo.vhd" |
/projects/S3Demo/S3demo_par.xrpt
70,48 → 70,47
<column label="Net Skew(ns)" stringID="NET_SKEW"/> |
<column label="Max Delay(ns)" stringID="MAX_DELAY"/> |
<row stringID="row" value="1"> |
<item label="Clock Net" stringID="CLOCK_NET" value="kb1_KCI"/> |
<item label="Clock Net" stringID="CLOCK_NET" value="RS232Proj_UART_rClk"/> |
<item label="Routed" stringID="ROUTED" value="ROUTED"/> |
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y11"/> |
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X1Y10"/> |
<item label="Locked" stringID="LOCKED" value="No"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="16.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.033000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.908000"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="18.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.040000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.913000"/> |
</row> |
<row stringID="row" value="2"> |
<item label="Clock Net" stringID="CLOCK_NET" value="mclk_BUFGP"/> |
<item label="Clock Net" stringID="CLOCK_NET" value="clk_sel3_BUFGP"/> |
<item label="Routed" stringID="ROUTED" value="ROUTED"/> |
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y1"/> |
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X1Y1"/> |
<item label="Locked" stringID="LOCKED" value="No"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="28.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.056000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.929000"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="2.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.904000"/> |
</row> |
<row stringID="row" value="3"> |
<item label="Clock Net" stringID="CLOCK_NET" value="RS232Proj_UART_rClk"/> |
<item label="Clock Net" stringID="CLOCK_NET" value="mclk_BUFGP"/> |
<item label="Routed" stringID="ROUTED" value="ROUTED"/> |
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X1Y0"/> |
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y1"/> |
<item label="Locked" stringID="LOCKED" value="No"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="18.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.025000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.908000"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="21.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.062000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.938000"/> |
</row> |
<row stringID="row" value="4"> |
<item label="Clock Net" stringID="CLOCK_NET" value="vga1_clkdiv"/> |
<item label="Clock Net" stringID="CLOCK_NET" value="RS232Proj_UART_rClkDiv<3>"/> |
<item label="Routed" stringID="ROUTED" value="ROUTED"/> |
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X1Y10"/> |
<item label="Locked" stringID="LOCKED" value="No"/> |
<item label="Resource" stringID="RESOURCE" value="Local"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="11.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.025000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.915000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.050000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.714000"/> |
</row> |
<row stringID="row" value="5"> |
<item label="Clock Net" stringID="CLOCK_NET" value="RS232Proj_UART_rClkDiv<3>"/> |
<item label="Clock Net" stringID="CLOCK_NET" value="RS232Proj_UART_stbeCur_FSM_FFd1"/> |
<item label="Routed" stringID="ROUTED" value="ROUTED"/> |
<item label="Resource" stringID="RESOURCE" value="Local"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="11.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.043000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.394000"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="4.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.018000"/> |
</row> |
<row stringID="row" value="6"> |
<item label="Clock Net" stringID="CLOCK_NET" value="RS232Proj_stCur<0>"/> |
118,33 → 117,17
<item label="Routed" stringID="ROUTED" value="ROUTED"/> |
<item label="Resource" stringID="RESOURCE" value="Local"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="9.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.093000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.844000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.041000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.613000"/> |
</row> |
<row stringID="row" value="7"> |
<item label="Clock Net" stringID="CLOCK_NET" value="RS232Proj_UART_stbeCur_FSM_FFd1"/> |
<item label="Clock Net" stringID="CLOCK_NET" value="clkdiv<24>"/> |
<item label="Routed" stringID="ROUTED" value="ROUTED"/> |
<item label="Resource" stringID="RESOURCE" value="Local"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="4.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.032000"/> |
</row> |
<row stringID="row" value="8"> |
<item label="Clock Net" stringID="CLOCK_NET" value="clkdiv<23>"/> |
<item label="Routed" stringID="ROUTED" value="ROUTED"/> |
<item label="Resource" stringID="RESOURCE" value="Local"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="3.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.393000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.046000"/> |
</row> |
<row stringID="row" value="9"> |
<item label="Clock Net" stringID="CLOCK_NET" value="kb1_clkDiv<3>"/> |
<item label="Routed" stringID="ROUTED" value="ROUTED"/> |
<item label="Resource" stringID="RESOURCE" value="Local"/> |
<item dataType="float" label="Fanout" stringID="FANOUT" value="4.000000"/> |
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.004000"/> |
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.800000"/> |
</row> |
</table> |
</section> |
<section stringID="PAR_PAD_PIN_REPORT"> |
230,10 → 213,16
</row> |
<row stringID="row" value="7"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P7"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSI_NDT"/> |
<item label="Signal
Name" stringID="Signal_Name" value="swt<7>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP_3/VREF_3"/> |
<item stringID="Direction" value="UNUSED"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="8"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P8"/> |
241,13 → 230,15
</row> |
<row stringID="row" value="9"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P9"/> |
<item label="Signal
Name" stringID="Signal_Name" value="swt<7>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Signal
Name" stringID="Signal_Name" value="led<7>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03P_3/LHCLK0"/> |
<item stringID="Direction" value="INPUT"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
267,33 → 258,17
</row> |
<row stringID="row" value="12"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P12"/> |
<item label="Signal
Name" stringID="Signal_Name" value="vs"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMLR"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L04P_3/LHCLK2"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="13"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P13"/> |
<item label="Signal
Name" stringID="Signal_Name" value="red"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSLR"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L04N_3/IRDY2/LHCLK3"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="14"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P14"/> |
301,33 → 276,17
</row> |
<row stringID="row" value="15"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P15"/> |
<item label="Signal
Name" stringID="Signal_Name" value="hs"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMLR"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L05P_3/TRDY2/LHCLK6"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="16"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P16"/> |
<item label="Signal
Name" stringID="Signal_Name" value="grn"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSLR"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L05N_3/LHCLK7"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="17"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P17"/> |
340,44 → 299,24
</row> |
<row stringID="row" value="19"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P19"/> |
<item label="Signal
Name" stringID="Signal_Name" value="kc"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMLR"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06P_3"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="20"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P20"/> |
<item label="Signal
Name" stringID="Signal_Name" value="blu"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSLR"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06N_3"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="21"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P21"/> |
<item label="Signal
Name" stringID="Signal_Name" value="kd"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMI_NDT"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP_3"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="22"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P22"/> |
409,168 → 348,84
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P26"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Voltage" stringID="Voltage" value="2.50"/> |
<item label="Voltage" stringID="Voltage" value="any******"/> |
</row> |
<row stringID="row" value="27"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P27"/> |
<item label="Signal
Name" stringID="Signal_Name" value="led<7>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L02N_2/CSO_B"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="28"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P28"/> |
<item label="Signal
Name" stringID="Signal_Name" value="ssg<4>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03P_2/RDWR_B"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="29"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P29"/> |
<item label="Signal
Name" stringID="Signal_Name" value="led_ext<7>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03N_2/VS2"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="30"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P30"/> |
<item label="Signal
Name" stringID="Signal_Name" value="btn_ext<4>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L04P_2/VS1"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="31"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P31"/> |
<item label="Signal
Name" stringID="Signal_Name" value="led_ext<6>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L04N_2/VS0"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="32"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P32"/> |
<item label="Signal
Name" stringID="Signal_Name" value="led_ext<5>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L05P_2"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="33"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P33"/> |
<item label="Signal
Name" stringID="Signal_Name" value="led_ext<4>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L05N_2"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="34"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P34"/> |
<item label="Signal
Name" stringID="Signal_Name" value="led_ext<3>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06P_2/D7"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="35"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P35"/> |
<item label="Signal
Name" stringID="Signal_Name" value="led_ext<2>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06N_2/D6"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="36"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P36"/> |
<item label="Signal
Name" stringID="Signal_Name" value="led_ext<0>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L07P_2/D5"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="37"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P37"/> |
<item label="Signal
Name" stringID="Signal_Name" value="btn_ext<2>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L07N_2/D4"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="38"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P38"/> |
579,9 → 434,16
</row> |
<row stringID="row" value="39"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P39"/> |
<item label="Signal
Name" stringID="Signal_Name" value="btn_ext<0>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP_2/VREF_2"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
</row> |
<row stringID="row" value="40"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P40"/> |
<item label="Signal
Name" stringID="Signal_Name" value="clk_sel3"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L08P_2/GCLK14"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
590,19 → 452,18
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="40"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P40"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L08P_2/GCLK14"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
</row> |
<row stringID="row" value="41"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P41"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSTB"/> |
<item label="Signal
Name" stringID="Signal_Name" value="clk_sel2"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L08N_2/GCLK15"/> |
<item stringID="Direction" value="UNUSED"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="42"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P42"/> |
623,31 → 484,29
</row> |
<row stringID="row" value="44"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P44"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSTB"/> |
<item label="Signal
Name" stringID="Signal_Name" value="clk_sel1"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L09N_2/GCLK1"/> |
<item stringID="Direction" value="UNUSED"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="45"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P45"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Voltage" stringID="Voltage" value="2.50"/> |
<item label="Voltage" stringID="Voltage" value="any******"/> |
</row> |
<row stringID="row" value="46"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P46"/> |
<item label="Signal
Name" stringID="Signal_Name" value="led_ext<1>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_2/MOSI/CSI_B"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="47"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P47"/> |
662,29 → 521,17
</row> |
<row stringID="row" value="49"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P49"/> |
<item label="Signal
Name" stringID="Signal_Name" value="btn_ext<3>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L10N_2/D3"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="50"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P50"/> |
<item label="Signal
Name" stringID="Signal_Name" value="btn_ext<1>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMTB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L11P_2/D2"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item stringID="Direction" value="UNUSED"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="51"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P51"/> |
863,10 → 710,16
</row> |
<row stringID="row" value="68"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P68"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFMI_NDT"/> |
<item label="Signal
Name" stringID="Signal_Name" value="btn<0>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP_1/VREF_1"/> |
<item stringID="Direction" value="UNUSED"/> |
<item stringID="Direction" value="INPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
</row> |
<row stringID="row" value="69"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P69"/> |
946,13 → 799,15
</row> |
<row stringID="row" value="77"> |
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P77"/> |
<item label="Signal
Name" stringID="Signal_Name" value="btn<0>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/> |
<item label="Signal
Name" stringID="Signal_Name" value="ssg<4>"/> |
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/> |
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L01P_0/VREF_0"/> |
<item stringID="Direction" value="INPUT"/> |
<item stringID="Direction" value="OUTPUT"/> |
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/> |
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/> |
<item label="IOB
Delay" stringID="IOB_Delay" value="IBUF"/> |
<item label="Drive
(mA)" stringID="Drive" value="12"/> |
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/> |
<item label="Termination" stringID="Termination" value="NONE**"/> |
<item label="Constraint" stringID="Constraint" value="LOCATED"/> |
<item label="IO
Register" stringID="IO_Register" value="NO"/> |
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/> |
1195,7 → 1050,7
<section stringID="PAR_UNROUTES_REPORT"> |
<item dataType="int" stringID="PAR_UNROUTED_NETS" value="0"/> |
<item dataType="int" stringID="PAR_TOTAL_SOURCELESS_NETS" value="0"/> |
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="7"/> |
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="2"/> |
</section> |
</task> |
</application> |
/projects/S3Demo/S3demo_ngdbuild.xrpt
54,69 → 54,60
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/> |
</section> |
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY"> |
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="3"/> |
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="40"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="4"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="9"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDC_1" value="21"/> |
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="2"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="29"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="27"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="40"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="14"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="29"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="4"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDRS" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="13"/> |
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="15"/> |
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="11"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LDE_1" value="8"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LD_1" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="61"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="15"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT2_L" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="26"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="32"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="20"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="23"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT3_D" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="46"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_D" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="2"/> |
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="61"/> |
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="10"/> |
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="34"/> |
<item dataType="int" stringID="NGDBUILD_NUM_SRL16_1" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT3_L" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="26"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="32"/> |
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="3"/> |
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="21"/> |
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="66"/> |
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="34"/> |
</section> |
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY"> |
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="4"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="40"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="4"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="9"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDC_1" value="21"/> |
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="3"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="29"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="27"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="40"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="14"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="29"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="4"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FDRS" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="20"/> |
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="15"/> |
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="15"/> |
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/> |
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="11"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LDE_1" value="8"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LD_1" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="61"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="15"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT2_L" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="26"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="32"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="20"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="23"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT3_D" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="46"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_D" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="2"/> |
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="61"/> |
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="10"/> |
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="34"/> |
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="2"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT3_L" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="26"/> |
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="32"/> |
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="3"/> |
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="21"/> |
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/> |
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="66"/> |
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="34"/> |
</section> |
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY"> |
<section stringID="NGDBUILD_CORE_INSTANCES"/> |
/projects/S3Demo/S3demo.bgn
114,21 → 114,11
|
|
Running DRC. |
WARNING:PhysDesignRules:367 - The signal <swt<1>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<2>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<3>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<4>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<5>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<6>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <swt<7>_IBUF> is incomplete. The signal |
does not drive any load pins in the design. |
DRC detected 0 errors and 7 warnings. Please see the previously displayed |
WARNING:PhysDesignRules:367 - The signal <clk_sel1_IBUF> is incomplete. The |
signal does not drive any load pins in the design. |
WARNING:PhysDesignRules:367 - The signal <clk_sel2_IBUF> is incomplete. The |
signal does not drive any load pins in the design. |
DRC detected 0 errors and 2 warnings. Please see the previously displayed |
individual error or warning messages for more details. |
Creating bit map... |
Saving bit stream in "S3demo.bit". |
/projects/S3Demo/_xmsgs/par.xmsgs
8,58 → 8,39
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". |
</msg> |
|
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">swt<1>_IBUF</arg> has no load. PAR will not attempt to route this signal. |
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">clk_sel1_IBUF</arg> has no load. PAR will not attempt to route this signal. |
</msg> |
|
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">swt<2>_IBUF</arg> has no load. PAR will not attempt to route this signal. |
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">clk_sel2_IBUF</arg> has no load. PAR will not attempt to route this signal. |
</msg> |
|
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">swt<3>_IBUF</arg> has no load. PAR will not attempt to route this signal. |
</msg> |
|
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">swt<4>_IBUF</arg> has no load. PAR will not attempt to route this signal. |
</msg> |
|
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">swt<5>_IBUF</arg> has no load. PAR will not attempt to route this signal. |
</msg> |
|
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">swt<6>_IBUF</arg> has no load. PAR will not attempt to route this signal. |
</msg> |
|
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">swt<7>_IBUF</arg> has no load. PAR will not attempt to route this signal. |
</msg> |
|
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg> |
|
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg> |
|
<msg type="warning" file="Route" num="455" delta="old" >CLK Net:<arg fmt="%s" index="1">RS232Proj_UART_rClkDiv<3></arg> may have excessive skew because |
<arg fmt="%d" index="2">0</arg> CLK pins and <arg fmt="%d" index="3">1</arg> NON_CLK pins failed to route using a CLK template. |
</msg> |
|
<msg type="warning" file="Route" num="455" delta="old" >CLK Net:<arg fmt="%s" index="1">RS232Proj_UART_stbeCur_FSM_FFd1</arg> may have excessive skew because |
<arg fmt="%d" index="2">1</arg> CLK pins and <arg fmt="%d" index="3">3</arg> NON_CLK pins failed to route using a CLK template. |
</msg> |
|
<msg type="warning" file="Route" num="455" delta="old" >CLK Net:<arg fmt="%s" index="1">RS232Proj_stCur<0></arg> may have excessive skew because |
<arg fmt="%d" index="2">0</arg> CLK pins and <arg fmt="%d" index="3">5</arg> NON_CLK pins failed to route using a CLK template. |
<msg type="warning" file="Route" num="455" delta="new" >CLK Net:<arg fmt="%s" index="1">clkdiv<24></arg> may have excessive skew because |
<arg fmt="%d" index="2">2</arg> CLK pins and <arg fmt="%d" index="3">1</arg> NON_CLK pins failed to route using a CLK template. |
</msg> |
|
<msg type="warning" file="Route" num="455" delta="old" >CLK Net:<arg fmt="%s" index="1">clkdiv<23></arg> may have excessive skew because |
<msg type="warning" file="Route" num="455" delta="old" >CLK Net:<arg fmt="%s" index="1">RS232Proj_UART_rClkDiv<3></arg> may have excessive skew because |
<arg fmt="%d" index="2">0</arg> CLK pins and <arg fmt="%d" index="3">1</arg> NON_CLK pins failed to route using a CLK template. |
</msg> |
|
<msg type="warning" file="Route" num="455" delta="old" >CLK Net:<arg fmt="%s" index="1">kb1_clkDiv<3></arg> may have excessive skew because |
<arg fmt="%d" index="2">0</arg> CLK pins and <arg fmt="%d" index="3">1</arg> NON_CLK pins failed to route using a CLK template. |
<msg type="warning" file="Route" num="455" delta="new" >CLK Net:<arg fmt="%s" index="1">RS232Proj_stCur<0></arg> may have excessive skew because |
<arg fmt="%d" index="2">0</arg> CLK pins and <arg fmt="%d" index="3">5</arg> NON_CLK pins failed to route using a CLK template. |
</msg> |
|
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg> |
|
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">7</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings. |
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">2</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings. |
|
</msg> |
|
<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">7</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings. |
<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">2</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings. |
|
</msg> |
|
/projects/S3Demo/_xmsgs/bitgen.xmsgs
5,26 → 5,11
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<1>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">clk_sel1_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<2>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">clk_sel2_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<3>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<4>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<5>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<6>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<7>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
</messages> |
|
/projects/S3Demo/_xmsgs/pn_parser.xmsgs
8,13 → 8,13
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/DataCntrl.vhd" into library work</arg> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/DataCntrl.vhd" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/RS232RefComp.vhd" into library work</arg> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/RS232RefComp.vhd" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/S3demo.vhd" into library work</arg> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo2/S3demo.vhd" into library work</arg> |
</msg> |
|
<msg type="error" file="ProjectMgmt" num="806" >"<arg fmt="%s" index="1">/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/S3Demo/S3demo.vhd</arg>" Line <arg fmt="%d" index="2">102</arg>. <arg fmt="%s" index="3">Syntax error near "z".</arg> |
/projects/S3Demo/_xmsgs/map.xmsgs
5,15 → 5,11
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">swt<7>_IBUF</arg> has no load. |
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">clk_sel1_IBUF</arg> has no load. |
</msg> |
|
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">6</arg> more times for the following (max. 5 shown): |
<arg fmt="%s" index="3">swt<6>_IBUF, |
swt<5>_IBUF, |
swt<4>_IBUF, |
swt<3>_IBUF, |
swt<2>_IBUF</arg> |
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">1</arg> more times for the following (max. 5 shown): |
<arg fmt="%s" index="3">clk_sel2_IBUF</arg> |
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch. |
</msg> |
|
23,26 → 19,11
<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<1>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">clk_sel1_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<2>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">clk_sel2_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<3>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<4>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<5>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<6>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">swt<7>_IBUF</arg>> is incomplete. The signal does not drive any load pins in the design. |
</msg> |
|
</messages> |
|
/projects/S3Demo/S3demo.pcf
3,15 → 3,11
//! ************************************************************************** |
|
SCHEMATIC START; |
COMP "blu" LOCATE = SITE "P20" LEVEL 1; |
COMP "grn" LOCATE = SITE "P16" LEVEL 1; |
COMP "red" LOCATE = SITE "P13" LEVEL 1; |
COMP "rxd" LOCATE = SITE "P52" LEVEL 1; |
COMP "txd" LOCATE = SITE "P56" LEVEL 1; |
COMP "an<0>" LOCATE = SITE "P59" LEVEL 1; |
COMP "an<1>" LOCATE = SITE "P57" LEVEL 1; |
COMP "an<2>" LOCATE = SITE "P61" LEVEL 1; |
COMP "an<3>" LOCATE = SITE "P60" LEVEL 1; |
COMP "btn<3>" LOCATE = SITE "P83" LEVEL 1; |
COMP "led<4>" LOCATE = SITE "P98" LEVEL 1; |
COMP "led<5>" LOCATE = SITE "P3" LEVEL 1; |
COMP "led<6>" LOCATE = SITE "P5" LEVEL 1; |
COMP "led<7>" LOCATE = SITE "P9" LEVEL 1; |
COMP "swt<0>" LOCATE = SITE "P85" LEVEL 1; |
COMP "swt<1>" LOCATE = SITE "P88" LEVEL 1; |
COMP "swt<2>" LOCATE = SITE "P90" LEVEL 1; |
19,45 → 15,31
COMP "swt<4>" LOCATE = SITE "P97" LEVEL 1; |
COMP "swt<5>" LOCATE = SITE "P4" LEVEL 1; |
COMP "swt<6>" LOCATE = SITE "P6" LEVEL 1; |
COMP "swt<7>" LOCATE = SITE "P9" LEVEL 1; |
NET "mclk_BUFGP/IBUFG" BEL "mclk_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT; |
COMP "led<0>" LOCATE = SITE "P84" LEVEL 1; |
COMP "btn<0>" LOCATE = SITE "P77" LEVEL 1; |
COMP "led<1>" LOCATE = SITE "P86" LEVEL 1; |
COMP "btn<1>" LOCATE = SITE "P78" LEVEL 1; |
COMP "led<2>" LOCATE = SITE "P89" LEVEL 1; |
COMP "btn<2>" LOCATE = SITE "P82" LEVEL 1; |
COMP "led<3>" LOCATE = SITE "P93" LEVEL 1; |
COMP "btn<3>" LOCATE = SITE "P83" LEVEL 1; |
COMP "led<4>" LOCATE = SITE "P98" LEVEL 1; |
COMP "led<5>" LOCATE = SITE "P3" LEVEL 1; |
COMP "led<6>" LOCATE = SITE "P5" LEVEL 1; |
COMP "led<7>" LOCATE = SITE "P27" LEVEL 1; |
COMP "kc" LOCATE = SITE "P19" LEVEL 1; |
COMP "kd" LOCATE = SITE "P21" LEVEL 1; |
COMP "hs" LOCATE = SITE "P15" LEVEL 1; |
COMP "vs" LOCATE = SITE "P12" LEVEL 1; |
COMP "led_ext<0>" LOCATE = SITE "P36" LEVEL 1; |
COMP "btn_ext<0>" LOCATE = SITE "P39" LEVEL 1; |
COMP "led_ext<1>" LOCATE = SITE "P46" LEVEL 1; |
COMP "btn_ext<1>" LOCATE = SITE "P50" LEVEL 1; |
COMP "led_ext<2>" LOCATE = SITE "P35" LEVEL 1; |
COMP "btn_ext<2>" LOCATE = SITE "P37" LEVEL 1; |
COMP "led_ext<3>" LOCATE = SITE "P34" LEVEL 1; |
COMP "btn_ext<3>" LOCATE = SITE "P49" LEVEL 1; |
COMP "led_ext<4>" LOCATE = SITE "P33" LEVEL 1; |
COMP "btn_ext<4>" LOCATE = SITE "P30" LEVEL 1; |
COMP "led_ext<5>" LOCATE = SITE "P32" LEVEL 1; |
COMP "led_ext<6>" LOCATE = SITE "P31" LEVEL 1; |
COMP "led_ext<7>" LOCATE = SITE "P29" LEVEL 1; |
COMP "swt<7>" LOCATE = SITE "P7" LEVEL 1; |
COMP "clk_sel1" LOCATE = SITE "P44" LEVEL 1; |
COMP "clk_sel2" LOCATE = SITE "P41" LEVEL 1; |
COMP "clk_sel3" LOCATE = SITE "P40" LEVEL 1; |
COMP "ssg<0>" LOCATE = SITE "P65" LEVEL 1; |
COMP "mclk" LOCATE = SITE "P43" LEVEL 1; |
COMP "ssg<0>" LOCATE = SITE "P65" LEVEL 1; |
COMP "ssg<1>" LOCATE = SITE "P64" LEVEL 1; |
COMP "ssg<2>" LOCATE = SITE "P72" LEVEL 1; |
COMP "ssg<3>" LOCATE = SITE "P70" LEVEL 1; |
COMP "ssg<4>" LOCATE = SITE "P28" LEVEL 1; |
COMP "ssg<4>" LOCATE = SITE "P77" LEVEL 1; |
COMP "ssg<5>" LOCATE = SITE "P62" LEVEL 1; |
COMP "ssg<6>" LOCATE = SITE "P73" LEVEL 1; |
COMP "rxd" LOCATE = SITE "P52" LEVEL 1; |
COMP "ssg<7>" LOCATE = SITE "P71" LEVEL 1; |
COMP "txd" LOCATE = SITE "P56" LEVEL 1; |
COMP "an<0>" LOCATE = SITE "P59" LEVEL 1; |
COMP "an<1>" LOCATE = SITE "P57" LEVEL 1; |
COMP "an<2>" LOCATE = SITE "P61" LEVEL 1; |
COMP "led<0>" LOCATE = SITE "P84" LEVEL 1; |
COMP "btn<0>" LOCATE = SITE "P68" LEVEL 1; |
COMP "an<3>" LOCATE = SITE "P60" LEVEL 1; |
COMP "led<1>" LOCATE = SITE "P86" LEVEL 1; |
COMP "btn<1>" LOCATE = SITE "P78" LEVEL 1; |
COMP "led<2>" LOCATE = SITE "P89" LEVEL 1; |
COMP "btn<2>" LOCATE = SITE "P82" LEVEL 1; |
COMP "led<3>" LOCATE = SITE "P93" LEVEL 1; |
SCHEMATIC END; |
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