compiled -No errors in compilation -Analysis of file <"main.prj"> succeeded. - - -========================================================================= -* Design Hierarchy Analysis * -========================================================================= -Analyzing hierarchy for module

in library . - -Analyzing hierarchy for module in library with parameters. - HACTIVE = "1001111111" - HBACK = "0000101111" - HFRONT = "0000001111" - HSYNC = "0001011111" - VACTIVE = "111011111" - VBACK = "000011100" - VFRONT = "000001001" - VSYNC = "000000001" - - -========================================================================= -* HDL Analysis * -========================================================================= -Analyzing top module

. -Module

is correct for synthesis. - -Analyzing module in library . - HACTIVE = 10'b1001111111 - HBACK = 10'b0000101111 - HFRONT = 10'b0000001111 - HSYNC = 10'b0001011111 - VACTIVE = 9'b111011111 - VBACK = 9'b000011100 - VFRONT = 9'b000001001 - VSYNC = 9'b000000001 -Module is correct for synthesis. - - -========================================================================= -* HDL Synthesis * -========================================================================= - -Performing bidirectional port resolution... - -Synthesizing Unit . - Related source file is "vga.v". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 13-bit register for signal . - Found 10-bit adder for signal created at line 71. - Found 12-bit register for signal . - Found 9-bit adder for signal created at line 92. - Summary: - inferred 28 D-type flip-flop(s). - inferred 2 Adder/Subtractor(s). -Unit synthesized. - - -Synthesizing Unit

. - Related source file is "main.v". -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:643 - "main.v" line 107: The result of a 18x10-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. -WARNING:Xst:643 - "main.v" line 108: The result of a 18x9-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. -WARNING:Xst:643 - "main.v" line 122: The result of a 18x10-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. -WARNING:Xst:643 - "main.v" line 123: The result of a 18x9-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. -WARNING:Xst:643 - "main.v" line 125: The result of a 18x9-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. -WARNING:Xst:643 - "main.v" line 137: The result of a 18x10-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. -WARNING:Xst:643 - "main.v" line 138: The result of a 18x9-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit xor2 for signal created at line 169. - Found 1-bit register for signal . - Found 18-bit up accumulator for signal . - Found 18-bit down accumulator for signal . - Found 1-bit xor2 for signal created at line 168. - Found 18-bit up accumulator for signal . - Found 18-bit down accumulator for signal . - Found 18-bit register for signal . - Found 18-bit adder for signal created at line 142. - Found 18-bit adder for signal created at line 137. - Found 18-bit adder for signal created at line 147. - Found 18x10-bit multiplier for signal created at line 137. - Found 18-bit register for signal . - Found 18-bit register for signal . - Found 18-bit adder for signal created at line 148. - Found 18x9-bit multiplier for signal created at line 138. - Found 18-bit subtractor for signal created at line 143. - Found 18-bit register for signal . - Found 1-bit xor2 for signal created at line 167. - Found 18-bit up accumulator for signal . - Found 18-bit down accumulator for signal . - Found 18-bit register for signal . - Found 18-bit adder for signal created at line 127. - Found 18-bit adder for signal created at line 122. - Found 18-bit adder for signal created at line 132. - Found 18x10-bit multiplier for signal created at line 122. - Found 18-bit register for signal . - Found 18-bit register for signal . - Found 18-bit adder for signal created at line 133. - Found 18x9-bit multiplier for signal created at line 123. - Found 18-bit subtractor for signal created at line 128. - Found 18-bit register for signal . - Found 18x9-bit multiplier for signal created at line 125. - Found 18-bit register for signal . - Found 18-bit adder for signal created at line 112. - Found 18-bit adder for signal created at line 107. - Found 18-bit adder for signal created at line 117. - Found 18x10-bit multiplier for signal created at line 107. - Found 18-bit register for signal . - Found 18-bit register for signal . - Found 18-bit adder for signal created at line 118. - Found 18x9-bit multiplier for signal created at line 108. - Found 18-bit subtractor for signal created at line 113. - Found 18-bit register for signal . - Summary: - inferred 6 Accumulator(s). - inferred 222 D-type flip-flop(s). - inferred 15 Adder/Subtractor(s). - inferred 7 Multiplier(s). -Unit

synthesized. - - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# Multipliers : 7 - 18x10-bit multiplier : 3 - 18x9-bit multiplier : 4 -# Adders/Subtractors : 17 - 10-bit adder : 1 - 18-bit adder : 12 - 18-bit subtractor : 3 - 9-bit adder : 1 -# Accumulators : 6 - 18-bit down accumulator : 3 - 18-bit up accumulator : 3 -# Registers : 23 - 1-bit register : 9 - 12-bit register : 1 - 13-bit register : 1 - 18-bit register : 12 -# Xors : 3 - 1-bit xor2 : 3 - -========================================================================= - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - - -Synthesizing (advanced) Unit

. -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit

synthesized (advanced). - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# Multipliers : 7 - 18x10-bit multiplier : 3 - 18x9-bit multiplier : 4 -# Adders/Subtractors : 17 - 10-bit adder : 1 - 18-bit adder : 12 - 18-bit subtractor : 3 - 9-bit adder : 1 -# Accumulators : 12 - 18-bit down accumulator : 3 - 18-bit down loadable accumulator : 3 - 18-bit up accumulator : 3 - 18-bit up loadable accumulator : 3 -# Registers : 142 - Flip-Flops : 142 -# Xors : 3 - 1-bit xor2 : 3 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= - -Optimizing unit

... - -Optimizing unit ... - -Mapping all equations... -Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block main, actual ratio is 27. - -Final Macro Processing ... - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 358 - Flip-Flops : 358 - -========================================================================= - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Final Report * -========================================================================= -Final Results -RTL Top Level Output File Name : main.ngr -Top Level Output File Name : main -Output Format : NGC -Optimization Goal : Speed -Keep Hierarchy : No - -Design Statistics -# IOs : 10 - -Cell Usage : -# BELS : 1998 -# GND : 1 -# INV : 55 -# LUT1 : 20 -# LUT2 : 439 -# LUT3 : 312 -# LUT4 : 106 -# MULT_AND : 51 -# MUXCY : 476 -# MUXF5 : 32 -# VCC : 1 -# XORCY : 505 -# FlipFlops/Latches : 358 -# FD : 3 -# FDE : 216 -# FDR : 5 -# FDRE : 99 -# FDRSE : 1 -# FDSE : 34 -# Clock Buffers : 1 -# BUFGP : 1 -# IO Buffers : 9 -# IBUF : 4 -# OBUF : 5 -# MULTs : 7 -# MULT18X18SIO : 7 -========================================================================= - -Device utilization summary: ---------------------------- - -Selected Device : 3s200avq100-4 - - Number of Slices: 489 out of 1792 27% - Number of Slice Flip Flops: 358 out of 3584 9% - Number of 4 input LUTs: 932 out of 3584 26% - Number of IOs: 10 - Number of bonded IOBs: 10 out of 68 14% - Number of MULT18X18SIOs: 7 out of 16 43% - Number of GCLKs: 1 out of 24 4% - ---------------------------- -Partition Resource Summary: ---------------------------- - - No Partitions were found in this design. - ---------------------------- - - -========================================================================= -TIMING REPORT - -NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. - FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT - GENERATED AFTER PLACE-and-ROUTE. - -Clock Information: ------------------- ------------------------------------+------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | ------------------------------------+------------------------+-------+ -Clk | BUFGP | 358 | ------------------------------------+------------------------+-------+ - -Asynchronous Control Signals Information: ----------------------------------------- -No asynchronous control signals found in this design - -Timing Summary: ---------------- -Speed Grade: -4 - - Minimum period: 13.701ns (Maximum Frequency: 72.987MHz) - Minimum input arrival time before clock: 4.225ns - Maximum output required time after clock: 5.531ns - Maximum combinational path delay: No path found - -Timing Detail: --------------- -All values displayed in nanoseconds (ns) - -========================================================================= -Timing constraint: Default period analysis for Clock 'Clk' - Clock period: 13.701ns (frequency: 72.987MHz) - Total number of paths / destination ports: 42816 / 712 -------------------------------------------------------------------------- -Delay: 13.701ns (Levels of Logic = 23) - Source: RDX_0 (FF) - Destination: RX1_17 (FF) - Source Clock: Clk rising - Destination Clock: Clk rising - - Data Path: RDX_0 to RX1_17 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDRE:C->Q 5 0.591 0.776 RDX_0 (RDX_0) - LUT1:I0->O 1 0.648 0.000 Madd_RX0_addsub0000_cy<0>_rt (Madd_RX0_addsub0000_cy<0>_rt) - MUXCY:S->O 1 0.632 0.000 Madd_RX0_addsub0000_cy<0> (Madd_RX0_addsub0000_cy<0>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<1> (Madd_RX0_addsub0000_cy<1>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<2> (Madd_RX0_addsub0000_cy<2>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<3> (Madd_RX0_addsub0000_cy<3>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<4> (Madd_RX0_addsub0000_cy<4>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<5> (Madd_RX0_addsub0000_cy<5>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<6> (Madd_RX0_addsub0000_cy<6>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<7> (Madd_RX0_addsub0000_cy<7>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<8> (Madd_RX0_addsub0000_cy<8>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<9> (Madd_RX0_addsub0000_cy<9>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<10> (Madd_RX0_addsub0000_cy<10>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<11> (Madd_RX0_addsub0000_cy<11>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<12> (Madd_RX0_addsub0000_cy<12>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<13> (Madd_RX0_addsub0000_cy<13>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<14> (Madd_RX0_addsub0000_cy<14>) - MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<15> (Madd_RX0_addsub0000_cy<15>) - XORCY:CI->O 1 0.844 0.420 Madd_RX0_addsub0000_xor<16> (RX0_addsub0000<16>) - MULT18X18SIO:A16->P16 2 4.860 0.479 Mmult_RX0_mult0001 (RX0_mult0001<16>) - LUT3:I2->O 1 0.648 0.452 RX0_mult0001<16>1 (RX0_mult0001<16>1) - LUT3:I2->O 1 0.648 0.000 Maccum_RX1_lut<16> (Maccum_RX1_lut<16>) - MUXCY:S->O 0 0.632 0.000 Maccum_RX1_cy<16> (Maccum_RX1_cy<16>) - XORCY:CI->O 1 0.844 0.000 Maccum_RX1_xor<17> (Result<17>6) - FDE:D 0.252 RX1_17 - ---------------------------------------- - Total 13.701ns (11.574ns logic, 2.127ns route) - (84.5% logic, 15.5% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk' - Total number of paths / destination ports: 265 / 247 -------------------------------------------------------------------------- -Offset: 4.225ns (Levels of Logic = 2) - Source: SW2 (PAD) - Destination: do_DY (FF) - Destination Clock: Clk rising - - Data Path: SW2 to do_DY - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 2 0.849 0.590 SW2_IBUF (SW2_IBUF) - LUT3:I0->O 55 0.648 1.269 Rot1 (Rot) - FDRSE:S 0.869 do_DY - ---------------------------------------- - Total 4.225ns (2.366ns logic, 1.859ns route) - (56.0% logic, 44.0% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk' - Total number of paths / destination ports: 5 / 5 -------------------------------------------------------------------------- -Offset: 5.531ns (Levels of Logic = 1) - Source: VSync (FF) - Destination: VSync (PAD) - Source Clock: Clk rising - - Data Path: VSync to VSync - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FD:C->Q 1 0.591 0.420 VSync (VSync_OBUF) - OBUF:I->O 4.520 VSync_OBUF (VSync) - ---------------------------------------- - Total 5.531ns (5.111ns logic, 0.420ns route) - (92.4% logic, 7.6% route) - -========================================================================= - - -Total REAL time to Xst completion: 9.00 secs -Total CPU time to Xst completion: 8.90 secs - ---> - - -Total memory usage is 163528 kilobytes - -Number of errors : 0 ( 0 filtered) -Number of warnings : 16 ( 0 filtered) -Number of infos : 0 ( 0 filtered) - Index: VGAdemo/main_summary.xml =================================================================== --- VGAdemo/main_summary.xml (revision 429) +++ VGAdemo/main_summary.xml (nonexistent) @@ -1,10 +0,0 @@ - - - - - -