URL
https://opencores.org/ocsvn/phr/phr/trunk
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- This comparison shows the changes necessary to convert path
/phr/trunk/codigo/demos
- from Rev 429 to Rev 430
- ↔ Reverse comparison
Rev 429 → Rev 430
/VGAdemo/VGAdemo.gise
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/VGAdemo/main.ngr
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/VGAdemo/webtalk.log
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/VGAdemo/main_map.mrp
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/VGAdemo/main.lso
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/VGAdemo/main_par.xrpt
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/VGAdemo/main_map.ncd
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\ No newline at end of file
/VGAdemo/main.bld
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/VGAdemo/webtalk_impact.xml
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/VGAdemo/main.ptwx
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/VGAdemo/main_pad.txt
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/VGAdemo/main.cmd_log
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/VGAdemo/main.v
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/VGAdemo/VGAdemoPHR.prm
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/VGAdemo/usage_statistics_webtalk.html
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/VGAdemo/main.drc
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/VGAdemo/main_map.map
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/VGAdemo/xlnx_auto_0_xdb/cst.xbcd
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VGAdemo/xlnx_auto_0_xdb/cst.xbcd
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Index: VGAdemo/main.twr
===================================================================
--- VGAdemo/main.twr (revision 429)
+++ VGAdemo/main.twr (nonexistent)
@@ -1,83 +0,0 @@
---------------------------------------------------------------------------------
-Release 12.3 Trace (lin)
-Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
-
-/opt/Xilinx/12.3/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 4 -n 3
--fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf main.ucf
-
-Design file: main.ncd
-Physical constraint file: main.pcf
-Device,package,speed: xc3s200a,vq100,-4 (PRODUCTION 1.41 2010-09-15)
-Report level: verbose report
-
-Environment Variable Effect
--------------------- ------
-NONE No environment variables were set
---------------------------------------------------------------------------------
-
-INFO:Timing:2698 - No timing constraints found, doing default enumeration.
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
- option. All paths that are not constrained will be reported in the
- unconstrained paths section(s) of the report.
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
- a 50 Ohm transmission line loading model. For the details of this model,
- and for more information on accounting for different loading conditions,
- please see the device datasheet.
-INFO:Timing:3390 - This architecture does not support a default System Jitter
- value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
- Uncertainty calculation.
-INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
- 'Phase Error' calculations, these terms will be zero in the Clock
- Uncertainty calculation. Please make appropriate modification to
- SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
- Error.
-
-
-
-Data Sheet report:
------------------
-All values displayed in nanoseconds (ns)
-
-Setup/Hold to clock Clk
-------------+------------+------------+------------------+--------+
- |Max Setup to|Max Hold to | | Clock |
-Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
-------------+------------+------------+------------------+--------+
-Reset | 3.618(R)| -0.526(R)|Clk_BUFGP | 0.000|
-SW0 | 3.708(R)| -0.054(R)|Clk_BUFGP | 0.000|
-SW1 | 3.208(R)| -0.220(R)|Clk_BUFGP | 0.000|
-SW2 | 5.900(R)| -0.703(R)|Clk_BUFGP | 0.000|
-------------+------------+------------+------------------+--------+
-
-Clock Clk to Pad
-------------+------------+------------------+--------+
- | clk (edge) | | Clock |
-Destination | to PAD |Internal Clock(s) | Phase |
-------------+------------+------------------+--------+
-B | 9.133(R)|Clk_BUFGP | 0.000|
-G | 8.397(R)|Clk_BUFGP | 0.000|
-HSync | 7.717(R)|Clk_BUFGP | 0.000|
-R | 7.827(R)|Clk_BUFGP | 0.000|
-VSync | 7.967(R)|Clk_BUFGP | 0.000|
-------------+------------+------------------+--------+
-
-Clock to Setup on destination clock Clk
----------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-Clk | 13.525| | | |
----------------+---------+---------+---------+---------+
-
-
-Analysis completed Wed May 7 22:40:15 2014
---------------------------------------------------------------------------------
-
-Trace Settings:
--------------------------
-Trace Settings
-
-Peak Memory Usage: 107 MB
-
-
-
Index: VGAdemo/main_bitgen.xwbt
===================================================================
--- VGAdemo/main_bitgen.xwbt (revision 429)
+++ VGAdemo/main_bitgen.xwbt (nonexistent)
@@ -1,8 +0,0 @@
-INTSTYLE=ise
-INFILE=/home/lguanuco/opencores/phr/trunk/codigo/demos/VGAdemo/main.ncd
-OUTFILE=/home/lguanuco/opencores/phr/trunk/codigo/demos/VGAdemo/main.bit
-FAMILY=Spartan3A and Spartan3AN
-PART=xc3s200a-4vq100
-WORKINGDIR=/home/lguanuco/opencores/phr/trunk/codigo/demos/VGAdemo
-LICENSE=WebPack
-USER_INFO=0_0_320
Index: VGAdemo/main.syr
===================================================================
--- VGAdemo/main.syr (revision 429)
+++ VGAdemo/main.syr (nonexistent)
@@ -1,538 +0,0 @@
-Release 12.3 - xst M.70d (lin)
-Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--->
-Parameter TMPDIR set to xst/projnav.tmp
-
-
-Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.04 secs
-
--->
-Parameter xsthdpdir set to xst
-
-
-Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.04 secs
-
--->
-Reading design: main.prj
-
-TABLE OF CONTENTS
- 1) Synthesis Options Summary
- 2) HDL Compilation
- 3) Design Hierarchy Analysis
- 4) HDL Analysis
- 5) HDL Synthesis
- 5.1) HDL Synthesis Report
- 6) Advanced HDL Synthesis
- 6.1) Advanced HDL Synthesis Report
- 7) Low Level Synthesis
- 8) Partition Report
- 9) Final Report
- 9.1) Device utilization summary
- 9.2) Partition Resource Summary
- 9.3) TIMING REPORT
-
-
-=========================================================================
-* Synthesis Options Summary *
-=========================================================================
----- Source Parameters
-Input File Name : "main.prj"
-Input Format : mixed
-Ignore Synthesis Constraint File : NO
-
----- Target Parameters
-Output File Name : "main"
-Output Format : NGC
-Target Device : xc3s200a-4-vq100
-
----- Source Options
-Top Module Name : main
-Automatic FSM Extraction : YES
-FSM Encoding Algorithm : Auto
-Safe Implementation : No
-FSM Style : LUT
-RAM Extraction : Yes
-RAM Style : Auto
-ROM Extraction : Yes
-Mux Style : Auto
-Decoder Extraction : YES
-Priority Encoder Extraction : Yes
-Shift Register Extraction : YES
-Logical Shifter Extraction : YES
-XOR Collapsing : YES
-ROM Style : Auto
-Mux Extraction : Yes
-Resource Sharing : YES
-Asynchronous To Synchronous : NO
-Multiplier Style : Auto
-Automatic Register Balancing : No
-
----- Target Options
-Add IO Buffers : YES
-Global Maximum Fanout : 500
-Add Generic Clock Buffer(BUFG) : 24
-Register Duplication : YES
-Slice Packing : YES
-Optimize Instantiated Primitives : NO
-Use Clock Enable : Yes
-Use Synchronous Set : Yes
-Use Synchronous Reset : Yes
-Pack IO Registers into IOBs : Auto
-Equivalent register Removal : YES
-
----- General Options
-Optimization Goal : Speed
-Optimization Effort : 1
-Keep Hierarchy : No
-Netlist Hierarchy : As_Optimized
-RTL Output : Yes
-Global Optimization : AllClockNets
-Read Cores : YES
-Write Timing Constraints : NO
-Cross Clock Analysis : NO
-Hierarchy Separator : /
-Bus Delimiter : <>
-Case Specifier : Maintain
-Slice Utilization Ratio : 100
-BRAM Utilization Ratio : 100
-Verilog 2001 : YES
-Auto BRAM Packing : NO
-Slice Utilization Ratio Delta : 5
-
-=========================================================================
-
-
-=========================================================================
-* HDL Compilation *
-=========================================================================
-Compiling verilog file "vga.v" in library work
-Compiling verilog file "main.v" in library work
-Module compiled
-Module compiled
-No errors in compilation
-Analysis of file <"main.prj"> succeeded.
-
-
-=========================================================================
-* Design Hierarchy Analysis *
-=========================================================================
-Analyzing hierarchy for module in library .
-
-Analyzing hierarchy for module in library with parameters.
- HACTIVE = "1001111111"
- HBACK = "0000101111"
- HFRONT = "0000001111"
- HSYNC = "0001011111"
- VACTIVE = "111011111"
- VBACK = "000011100"
- VFRONT = "000001001"
- VSYNC = "000000001"
-
-
-=========================================================================
-* HDL Analysis *
-=========================================================================
-Analyzing top module .
-Module is correct for synthesis.
-
-Analyzing module in library .
- HACTIVE = 10'b1001111111
- HBACK = 10'b0000101111
- HFRONT = 10'b0000001111
- HSYNC = 10'b0001011111
- VACTIVE = 9'b111011111
- VBACK = 9'b000011100
- VFRONT = 9'b000001001
- VSYNC = 9'b000000001
-Module is correct for synthesis.
-
-
-=========================================================================
-* HDL Synthesis *
-=========================================================================
-
-Performing bidirectional port resolution...
-
-Synthesizing Unit .
- Related source file is "vga.v".
- Found 1-bit register for signal .
- Found 1-bit register for signal .
- Found 1-bit register for signal .
- Found 13-bit register for signal .
- Found 10-bit adder for signal created at line 71.
- Found 12-bit register for signal .
- Found 9-bit adder for signal created at line 92.
- Summary:
- inferred 28 D-type flip-flop(s).
- inferred 2 Adder/Subtractor(s).
-Unit synthesized.
-
-
-Synthesizing Unit .
- Related source file is "main.v".
-WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:643 - "main.v" line 107: The result of a 18x10-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
-WARNING:Xst:643 - "main.v" line 108: The result of a 18x9-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
-WARNING:Xst:643 - "main.v" line 122: The result of a 18x10-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
-WARNING:Xst:643 - "main.v" line 123: The result of a 18x9-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
-WARNING:Xst:643 - "main.v" line 125: The result of a 18x9-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
-WARNING:Xst:643 - "main.v" line 137: The result of a 18x10-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
-WARNING:Xst:643 - "main.v" line 138: The result of a 18x9-bit multiplication is partially used. Only the 18 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
- Found 1-bit register for signal .
- Found 1-bit register for signal .
- Found 1-bit register for signal .
- Found 1-bit register for signal .
- Found 1-bit register for signal .
- Found 1-bit xor2 for signal created at line 169.
- Found 1-bit register for signal .
- Found 18-bit up accumulator for signal .
- Found 18-bit down accumulator for signal .
- Found 1-bit xor2 for signal created at line 168.
- Found 18-bit up accumulator for signal .
- Found 18-bit down accumulator for signal .
- Found 18-bit register for signal .
- Found 18-bit adder for signal created at line 142.
- Found 18-bit adder for signal created at line 137.
- Found 18-bit adder for signal created at line 147.
- Found 18x10-bit multiplier for signal created at line 137.
- Found 18-bit register for signal .
- Found 18-bit register for signal .
- Found 18-bit adder for signal created at line 148.
- Found 18x9-bit multiplier for signal created at line 138.
- Found 18-bit subtractor for signal created at line 143.
- Found 18-bit register for signal .
- Found 1-bit xor2 for signal created at line 167.
- Found 18-bit up accumulator for signal .
- Found 18-bit down accumulator for signal .
- Found 18-bit register for signal .
- Found 18-bit adder for signal created at line 127.
- Found 18-bit adder for signal created at line 122.
- Found 18-bit adder for signal created at line 132.
- Found 18x10-bit multiplier for signal created at line 122.
- Found 18-bit register for signal .
- Found 18-bit register for signal .
- Found 18-bit adder for signal created at line 133.
- Found 18x9-bit multiplier for signal created at line 123.
- Found 18-bit subtractor for signal created at line 128.
- Found 18-bit register for signal .
- Found 18x9-bit multiplier for signal created at line 125.
- Found 18-bit register for signal .
- Found 18-bit adder for signal created at line 112.
- Found 18-bit adder for signal created at line 107.
- Found 18-bit adder for signal created at line 117.
- Found 18x10-bit multiplier for signal created at line 107.
- Found 18-bit register for signal .
- Found 18-bit register for signal .
- Found 18-bit adder for signal created at line 118.
- Found 18x9-bit multiplier for signal created at line 108.
- Found 18-bit subtractor for signal created at line 113.
- Found 18-bit register for signal .
- Summary:
- inferred 6 Accumulator(s).
- inferred 222 D-type flip-flop(s).
- inferred 15 Adder/Subtractor(s).
- inferred 7 Multiplier(s).
-Unit synthesized.
-
-
-=========================================================================
-HDL Synthesis Report
-
-Macro Statistics
-# Multipliers : 7
- 18x10-bit multiplier : 3
- 18x9-bit multiplier : 4
-# Adders/Subtractors : 17
- 10-bit adder : 1
- 18-bit adder : 12
- 18-bit subtractor : 3
- 9-bit adder : 1
-# Accumulators : 6
- 18-bit down accumulator : 3
- 18-bit up accumulator : 3
-# Registers : 23
- 1-bit register : 9
- 12-bit register : 1
- 13-bit register : 1
- 18-bit register : 12
-# Xors : 3
- 1-bit xor2 : 3
-
-=========================================================================
-
-=========================================================================
-* Advanced HDL Synthesis *
-=========================================================================
-
-
-Synthesizing (advanced) Unit .
-The following registers are absorbed into accumulator : 1 register on signal .
-The following registers are absorbed into accumulator : 1 register on signal .
-The following registers are absorbed into accumulator : 1 register on signal .
-The following registers are absorbed into accumulator : 1 register on signal .
-The following registers are absorbed into accumulator : 1 register on signal .
-The following registers are absorbed into accumulator : 1 register on signal .
-Unit synthesized (advanced).
-
-=========================================================================
-Advanced HDL Synthesis Report
-
-Macro Statistics
-# Multipliers : 7
- 18x10-bit multiplier : 3
- 18x9-bit multiplier : 4
-# Adders/Subtractors : 17
- 10-bit adder : 1
- 18-bit adder : 12
- 18-bit subtractor : 3
- 9-bit adder : 1
-# Accumulators : 12
- 18-bit down accumulator : 3
- 18-bit down loadable accumulator : 3
- 18-bit up accumulator : 3
- 18-bit up loadable accumulator : 3
-# Registers : 142
- Flip-Flops : 142
-# Xors : 3
- 1-bit xor2 : 3
-
-=========================================================================
-
-=========================================================================
-* Low Level Synthesis *
-=========================================================================
-
-Optimizing unit ...
-
-Optimizing unit ...
-
-Mapping all equations...
-Building and optimizing final netlist ...
-Found area constraint ratio of 100 (+ 5) on block main, actual ratio is 27.
-
-Final Macro Processing ...
-
-=========================================================================
-Final Register Report
-
-Macro Statistics
-# Registers : 358
- Flip-Flops : 358
-
-=========================================================================
-
-=========================================================================
-* Partition Report *
-=========================================================================
-
-Partition Implementation Status
--------------------------------
-
- No Partitions were found in this design.
-
--------------------------------
-
-=========================================================================
-* Final Report *
-=========================================================================
-Final Results
-RTL Top Level Output File Name : main.ngr
-Top Level Output File Name : main
-Output Format : NGC
-Optimization Goal : Speed
-Keep Hierarchy : No
-
-Design Statistics
-# IOs : 10
-
-Cell Usage :
-# BELS : 1998
-# GND : 1
-# INV : 55
-# LUT1 : 20
-# LUT2 : 439
-# LUT3 : 312
-# LUT4 : 106
-# MULT_AND : 51
-# MUXCY : 476
-# MUXF5 : 32
-# VCC : 1
-# XORCY : 505
-# FlipFlops/Latches : 358
-# FD : 3
-# FDE : 216
-# FDR : 5
-# FDRE : 99
-# FDRSE : 1
-# FDSE : 34
-# Clock Buffers : 1
-# BUFGP : 1
-# IO Buffers : 9
-# IBUF : 4
-# OBUF : 5
-# MULTs : 7
-# MULT18X18SIO : 7
-=========================================================================
-
-Device utilization summary:
----------------------------
-
-Selected Device : 3s200avq100-4
-
- Number of Slices: 489 out of 1792 27%
- Number of Slice Flip Flops: 358 out of 3584 9%
- Number of 4 input LUTs: 932 out of 3584 26%
- Number of IOs: 10
- Number of bonded IOBs: 10 out of 68 14%
- Number of MULT18X18SIOs: 7 out of 16 43%
- Number of GCLKs: 1 out of 24 4%
-
----------------------------
-Partition Resource Summary:
----------------------------
-
- No Partitions were found in this design.
-
----------------------------
-
-
-=========================================================================
-TIMING REPORT
-
-NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
- FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
- GENERATED AFTER PLACE-and-ROUTE.
-
-Clock Information:
-------------------
------------------------------------+------------------------+-------+
-Clock Signal | Clock buffer(FF name) | Load |
------------------------------------+------------------------+-------+
-Clk | BUFGP | 358 |
------------------------------------+------------------------+-------+
-
-Asynchronous Control Signals Information:
-----------------------------------------
-No asynchronous control signals found in this design
-
-Timing Summary:
----------------
-Speed Grade: -4
-
- Minimum period: 13.701ns (Maximum Frequency: 72.987MHz)
- Minimum input arrival time before clock: 4.225ns
- Maximum output required time after clock: 5.531ns
- Maximum combinational path delay: No path found
-
-Timing Detail:
---------------
-All values displayed in nanoseconds (ns)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'Clk'
- Clock period: 13.701ns (frequency: 72.987MHz)
- Total number of paths / destination ports: 42816 / 712
--------------------------------------------------------------------------
-Delay: 13.701ns (Levels of Logic = 23)
- Source: RDX_0 (FF)
- Destination: RX1_17 (FF)
- Source Clock: Clk rising
- Destination Clock: Clk rising
-
- Data Path: RDX_0 to RX1_17
- Gate Net
- Cell:in->out fanout Delay Delay Logical Name (Net Name)
- ---------------------------------------- ------------
- FDRE:C->Q 5 0.591 0.776 RDX_0 (RDX_0)
- LUT1:I0->O 1 0.648 0.000 Madd_RX0_addsub0000_cy<0>_rt (Madd_RX0_addsub0000_cy<0>_rt)
- MUXCY:S->O 1 0.632 0.000 Madd_RX0_addsub0000_cy<0> (Madd_RX0_addsub0000_cy<0>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<1> (Madd_RX0_addsub0000_cy<1>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<2> (Madd_RX0_addsub0000_cy<2>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<3> (Madd_RX0_addsub0000_cy<3>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<4> (Madd_RX0_addsub0000_cy<4>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<5> (Madd_RX0_addsub0000_cy<5>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<6> (Madd_RX0_addsub0000_cy<6>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<7> (Madd_RX0_addsub0000_cy<7>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<8> (Madd_RX0_addsub0000_cy<8>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<9> (Madd_RX0_addsub0000_cy<9>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<10> (Madd_RX0_addsub0000_cy<10>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<11> (Madd_RX0_addsub0000_cy<11>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<12> (Madd_RX0_addsub0000_cy<12>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<13> (Madd_RX0_addsub0000_cy<13>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<14> (Madd_RX0_addsub0000_cy<14>)
- MUXCY:CI->O 1 0.065 0.000 Madd_RX0_addsub0000_cy<15> (Madd_RX0_addsub0000_cy<15>)
- XORCY:CI->O 1 0.844 0.420 Madd_RX0_addsub0000_xor<16> (RX0_addsub0000<16>)
- MULT18X18SIO:A16->P16 2 4.860 0.479 Mmult_RX0_mult0001 (RX0_mult0001<16>)
- LUT3:I2->O 1 0.648 0.452 RX0_mult0001<16>1 (RX0_mult0001<16>1)
- LUT3:I2->O 1 0.648 0.000 Maccum_RX1_lut<16> (Maccum_RX1_lut<16>)
- MUXCY:S->O 0 0.632 0.000 Maccum_RX1_cy<16> (Maccum_RX1_cy<16>)
- XORCY:CI->O 1 0.844 0.000 Maccum_RX1_xor<17> (Result<17>6)
- FDE:D 0.252 RX1_17
- ----------------------------------------
- Total 13.701ns (11.574ns logic, 2.127ns route)
- (84.5% logic, 15.5% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
- Total number of paths / destination ports: 265 / 247
--------------------------------------------------------------------------
-Offset: 4.225ns (Levels of Logic = 2)
- Source: SW2 (PAD)
- Destination: do_DY (FF)
- Destination Clock: Clk rising
-
- Data Path: SW2 to do_DY
- Gate Net
- Cell:in->out fanout Delay Delay Logical Name (Net Name)
- ---------------------------------------- ------------
- IBUF:I->O 2 0.849 0.590 SW2_IBUF (SW2_IBUF)
- LUT3:I0->O 55 0.648 1.269 Rot1 (Rot)
- FDRSE:S 0.869 do_DY
- ----------------------------------------
- Total 4.225ns (2.366ns logic, 1.859ns route)
- (56.0% logic, 44.0% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
- Total number of paths / destination ports: 5 / 5
--------------------------------------------------------------------------
-Offset: 5.531ns (Levels of Logic = 1)
- Source: VSync (FF)
- Destination: VSync (PAD)
- Source Clock: Clk rising
-
- Data Path: VSync to VSync
- Gate Net
- Cell:in->out fanout Delay Delay Logical Name (Net Name)
- ---------------------------------------- ------------
- FD:C->Q 1 0.591 0.420 VSync (VSync_OBUF)
- OBUF:I->O 4.520 VSync_OBUF (VSync)
- ----------------------------------------
- Total 5.531ns (5.111ns logic, 0.420ns route)
- (92.4% logic, 7.6% route)
-
-=========================================================================
-
-
-Total REAL time to Xst completion: 9.00 secs
-Total CPU time to Xst completion: 8.90 secs
-
--->
-
-
-Total memory usage is 163528 kilobytes
-
-Number of errors : 0 ( 0 filtered)
-Number of warnings : 16 ( 0 filtered)
-Number of infos : 0 ( 0 filtered)
-
Index: VGAdemo/main_summary.xml
===================================================================
--- VGAdemo/main_summary.xml (revision 429)
+++ VGAdemo/main_summary.xml (nonexistent)
@@ -1,10 +0,0 @@
-
-
-
-
-
-
Index: VGAdemo/main.xst
===================================================================
--- VGAdemo/main.xst (revision 429)
+++ VGAdemo/main.xst (nonexistent)
@@ -1,56 +0,0 @@
-set -tmpdir "xst/projnav.tmp"
-set -xsthdpdir "xst"
-run
--ifn main.prj
--ifmt mixed
--ofn main
--ofmt NGC
--p xc3s200a-4-vq100
--top main
--opt_mode Speed
--opt_level 1
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--verilog2001 YES
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--mux_style Auto
--decoder_extract YES
--priority_extract Yes
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--rom_style Auto
--auto_bram_packing NO
--mux_extract Yes
--resource_sharing YES
--async_to_sync NO
--mult_style Auto
--iobuf YES
--max_fanout 500
--bufg 24
--register_duplication YES
--register_balancing No
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Yes
--use_sync_set Yes
--use_sync_reset Yes
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
Index: VGAdemo/main_map.ngm
===================================================================
--- VGAdemo/main_map.ngm (revision 429)
+++ VGAdemo/main_map.ngm (nonexistent)
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$02:2~6<9?1/^hxfshmm>%7):=;%>#:/$038 Wcqazcdb7.>.40# 4=7<2:;<<:401210>670980<5:409DE5>7538:?7<>?05924G6338:M<95>10;24>7?2@D[YY4N<0594;773821EC^ZT;@?52<76890=54FNQWW>GENF5;<6=0>5:3;>JSSX\^1NNAZT=34>586929=6B[[PTV9T952294o7>}=01cuu467%=;08?5;739604=1<2<8:N<46B3837=00;1>789>04I671:;1?<063H80M=<4A018E4643H;:?6O>229B56587L?:3:C226=F9>80M?<4A208E140M1>15:C?55823H6:=3;4A=31:0=F489596O315<6?D:6=7?0M1?9>69B841=87?0M1?8>59B84833H69295N<2<7?D:36=1J080;;@>5:1=F4>4?7L27>59B8<833HKJ4h5NDE]DHJDFDVZBB>5NDS18EKB33HXNK85NSXL@5>D23K$[MI<4B108F453:@266=E9:90N<:<;C367>D6>:1I=:<4B308F64D;994>7O2>1?78F9756<1I0<=15:@?51823K6:93;4B=35:2=E48=1<3;4B=34:1=E484?7O2=>59A86833K6?295M<4<7?G:16=1I0:0;;C>;:1=E40497OL<;C@21>DE9VL>7OL>_F68FFOI=2HHEC>:;CAJJ4085MCHL01>DDAG>>7OMFN478FFOI><1IOD@85:@@MK>23KIBB494BBKM858?3KIBB1??>99AGLH;98437OMFN=31:==EK@D7=>07;CAJJ973611IOD@314<;?GENF5;=2l5MCHL?52<7611IOD@316<4?GENF5;5;6LLIO>1:2=EK@D7?394BBKM81803KIBB1;17:@@MK:16>1IOD@37?58FFOI414<7OMFN=;=1>DDG\^=7OM@UU25?GEH]];<7OM@UU333>DDG\^:=:5MCNWW571569AGJSS9?=0NNAZT055?GEH]]8=7OM@UU15?GEH]]>=7OM@UU75?GEH]]<=7OM@UU55?GEH]]2=7OM@UU;;?GEH]]6;245MCNWW846912HHCXZ310<:?GEH]]6:>374BBMVP974601IOB[[<06==>DDG\^7=806;CALQQ:6>7h0NNAZT=34>58>3KIDYY2>7?:8FFIR\5;546LLOTV?6;>DDG\^7:364BBMVP91902HHCXZ38?:8FFIR\53586LJ1568FC@A<2HYIJ=4BTD7?GSAO<1IYKI_119AQLJCW]KYKHZNRBJ;?GSTW@DMC:5M_HLSQQ0EN=2I@NXH<;BNH7>EKZ01HC@CFTUGG<>EHFZ^JBY?>;BMMWQGI\V^YM^FLAO58GWCF\LN87Nbd9:AooZDRNNZn7Nbd_CWECU)E]OM:h6Mck^@VBBV(J\LLSD>Pmtz\w`jX{`mm7Nbd_CWECU)NJ\LL=6J=;EK5?AOUMJ^n7I\L_RW@G@UTN\F>7IV30?48@]:687<0HU2>1?48@]:6:7<0HU2>3?48@]:6<7<0HU2>5?48@]:6>7<0HU2>7?78@]:66<1OT1<15:F[86823MR783;4DY>6:0=CP5<596JW<6<6?A^;07?0HU26>59G\Z633MRT=85KX^331>B_W8;>7IVP1378@]Y6;<1OTR?;5:F[[4323MRT=;;4DY]231=CPV8?7IVP359G\Z233MRT995KX^47?A^X?=1OTR6;;EZ\=d=CPVddx=>?1c9G\Zhh|9:;=<;4DX>3:3=CQ5;;2;5KY=32:3=CQ5;92;5KY=30:3=CQ5;?2;5KY=36:3=CQ5;=2;5KY=34:0=CQ5;596JV<3<6?A_;;7?0HT2;>49G]939=2NR0;0:;E[?3;3B^W9>0HTQ>5:FZ[4623MST=<;4DX]260=CQV;896JV_066?A_X90HTQ>649G]Z70<2NRS?:4DX]00>B^W=>0HTQ:4:FZ[32:2O?=<5JXQCM@@BXJJNTJDBJ159F\UGILLNTOB@\TSCJJQU692OS\L@KEE]JW@YAAEOn7Ha_1325ZOI^V:i7Ha_13\idhck2OzbR>>_lcm`4d1N}cQ?3048AthX8==0I|`P0535?@wiW9?<7Ha_172e>CvfV:Tal`kb:GrjZ6Xehdo=n5Jqo]244Yjigno7Ha_022[hgil8i0I|`P110\idhcl2OzbR??2^obja703L{eS<><8:GrjZ77;8=0I|`P116;?@wiW8:?=:5Jqo]240>b:GrjZ77Wdkehn5Jqo]24Zkffm;<7Ha_033<>CvfV;:<13]nekb6?2OzbR?>399FukY69:;<7Ha_037<>CvfV;:8<94Epl\543?3L{eSCvfV;:;55Jqo]2527e3L{eSCvfV;:S`oad0a8AthX9;;Tal`kd:GrjZ759Vgjbi?l;Dsm[445Wdkehi5Jqo]267Yjign:;6K~n^317==BygU:>>?8;Dsm[44302OzbR?=4058AthX9;?37Ha_0065g=BygU:>Rcnnea8AthX9;Ufmcj>c:GrjZ749Vgjbij4Epl\567Xehdo=n5Jqo]277Yjigno7Ha_011[hgil8=0I|`P121;?@wiW898=:5Jqo]271>:>7:GrjZ74=11N}cQ>343a?@wiW89Tal`kc:GrjZ74Wdkeh43]nekb6?2OzbR?;399FukY6<:;<7Ha_067<>CvfV;?8<94Epl\513?3L{eS<::1c9FukY653]nekbc3L{eS<;=_lcm`411N}cQ>55:8AthX9<>:;6K~n^361==BygU:98?m;Dsm[43Xehdoo6K~n^36[hgil8i0I|`P173\idhcl2OzbR?91^obja7d3L{eS<8=_lcm`a=BygU::?Qbaof23>CvfV;=?55Jqo]226703L{eS<8;8:GrjZ71<8=0I|`P177;?@wiW8<>=o5Jqo]22Zkffmi0I|`P17]nekb6j2OzbR?7_lcm`f=BygU:4Rcnne3a?@wiW83Tal`kc:GrjZ7>WdkehCvfV8:S`oad0`8AthX:;Ufmcjl;Dsm[74Xehdo=;5Jqo]172=BygU9?<84Epl\6119?9;Dsm[7303L{eS?;>a:GrjZ4Xehdon6K~n^0\idhc9k1N}cQ<1^objaeCvfV99S`oadb9FukY4:Vgjbi?9;Dsm[6503L{eS>=>6:GrjZ53?2OzbR=;179FukY4=>1N}cQ<50c8AthX;Vgjbil4Epl\7Zkffm;i7Ha_53\idhck2OzbR:>_lcm`4d1N}cQ;3048AthX<==0I|`P4535?@wiW=?<7Ha_572e>CvfV>Tal`kb:GrjZ2Xehdo=o5Jqo]65Zkffmi0I|`P50]nekb6j2OzbR;=_lcm`f=BygU>>Rcnne35?@wiW<9<7Ha_4122>CvfV??;6K~n^7753=BygU>9:5Jqo]614gCvfV2OzbR9;7:GrjZ139?1N}cQ8569FukY0=8k0I|`P7^objad6Wdkehb:GrjZ?5Wdkehn5Jqo]:6Zkffm;=7Ha_814?@wiW09::6K~n^;73>CvfV3?=;5Jqo]:12=BygU29@UINUHCCHFG`9EVDAXKF_EX55IRNO\QF@63N?0K#^ND39DF6=@J8?0KO?PF49DF4Y@>2MOT1>17:EG\9776>1LHU2>1?58CA^;9;4<7JJW<01=3>ACP5;?2:5HDY>21;12MOT1?16:EG\949>2MOT1=16:EG\929>2MOT1;16:EG\909>2MOT1916:EG\9>9>2MOT1715:EG\Z623NNSS<84GEZ\55084GEZ\5101LHT2>3?58CA_;9=4<7JJV<07=3>ACQ5;=2:5HDX>23;0ACQV;::6IKY^312>ACQV;8:6IKY^372>ACQV;>:6IKY^352>ACQV;<96IKY^06?BB^W:?0KIWP449D@\Y2=2MOUR8:;FFZ[236IJNDPBP@B'XFY_!J=?3:EM@0=@ZF_[:6IW0=2=3>A_85;;2:5HX1>25;169D\5:6=7=0KU>317<4?B^748=5:6IW0=3=2>A_8585:6IW0=1=2>A_85>5:6IW0=7=2>A_85<5:6IW0=5=2>A_8525:6IW0=;=1>A_8V:>7JV?_048C]6X99<0KU>P1048C]6X9;<0KU>P1248C]6X9=<0KU>P1448C]6X9?<0KU>P1678C]6X:<1LT=Q<5:E[4Z223NR;S8;4GY2\20=@P9U<96IW0^:6?B^7W0o0KU>Paef3456;87l0KU>Paef3456;994m7JV?_`fg456748;5j6IW0^cg`56785;92k5HX1]b`a67896:?3h4GY2\eab789:7=90i;FZ3[dbc89:;0<;1f:E[4Zgcl9:;<1?9>g9D\5Yflm:;<=2>7?g8C]6Ximn;<=>31?g8C]6Ximn;<=>32?g8C]6Ximn;<=>33?g8C]6Ximn;<=>34?g8C]6Ximn;<=>35?g8C]6Ximn;<=>36?g8C]6Ximn;<=>37?g8C]6Ximn;<=>38?g8C]6Ximn;<=>39?32?B^7Whnoxl?012?4;753NR;Sljkst`3456;994:>6IW0^cg`vse89:;01139D\5Yflmy~n=>?0=31:442:E[4Zgclzi<=>?<07=57=@P9Ujhi}zb12349716880KU>Paefpqg67896:;3?>;FZ3[dbc{|h;<=>31?32?B^7Whnoxl?012?6;763NR;Sljkst`3456;;7;:7JV?_`fgwpd789:783?>;FZ3[dbc{|h;<=>35?32?B^7Whnoxl?012?2;763NR;Sljkst`3456;?7;:7JV?_`fgwpd789:743?>;FZ3[dbc{|h;<=>39?32?B^7Whnoxl?013?4;753NR;Sljkst`3457;994:>6IW0^cg`vse89::01139D\5Yflmy~n=>?1=31:442:E[4Zgclzi<=>><07=57=@P9Ujhi}zb12359716880KU>Paefpqg67886:;3?>;FZ3[dbc{|h;<=?31?32?B^7Whnoxl?013?6;763NR;Sljkst`3457;;7;:7JV?_`fgwpd789;783?>;FZ3[dbc{|h;<=?35?32?B^7Whnoxl?013?2;763NR;Sljkst`3457;?7;:7JV?_`fgwpd789;743?>;FZ3[dbc{|h;<=?39?d8C]6Xe|f<=>><1<24>A_8Vg~`y>?00>3:4773NR;S`{ct123597768;0KU>Pmtnw456648:5=<>4GY2\ipjs89::01109D\5Yj}e~;<=?310<255=@P9Ufyaz?013?578692MS;FZ3[hsk|9:;=1?<>033?B^7Wdgx=>?1=37:47Pmtnw456648?5=<5HX1]nqir789;7=80>119D\5Yj}e~;<=?317<25>A_8Vg~`y>?00>22;7682MSPmtnw4566484:<6IW0^ovhq67886:20:E[4Zkrd}:;<<2=>0d8C]6Xe|f<=>><2<24>A_8Vg~`y>?00>0:4`Pmtnw45664<4:<6IW0^ovhq67886>20:E[4Zkrd}:;<<29>0d8C]6Xe|f<=>><6<24>A_8Vg~`y>?00>4:4`Pmtnw4566404:<6IW0^ovhq6788622?<02=56=@P9Ufyu>?01>24;YT_9l0KU>Pmtz3456;984:?6IW0^ov|56785;:2R]X0g9D\5Yj}q:;<=2>2?30?B^7Wds<=>?<00=[VQ7n2MSPmtz3456;9:4T_Z>i;FZ3[hs89:;0<:1129D\5Yj}q:;<=2>4?]PS5`A_8Vg~t=>?0=34:456IW0^ov|56785;5S^Y?e:E[4Zkrp9:;<1<1139D\5Yj}q:;<=2=>^QT4`=@P9Ufyu>?01>0:44Pmtz3456;<7;97JV?_lw{45674=4T_Z>j;FZ3[hs89:;080>2:E[4Zkrp9:;<1;1_RU3a>A_8Vg~t=>?0=4=57=@P9Ufyu>?01>5:ZUP8l1LT=Qbuy2345:06880KU>Pmtz3456;?7UX[=k4GY2\ip~789:743?=;FZ3[hs89:;050PSV2f?B^7Wds<=>?<8<26>A_8Vg~t=>?0=;=[VQ7>2MS=1>17:E[59776>1LT<2>1?58C]7;9;4<7JV><01=3>A_95;?2:5HX0>21;12MS=1?16:E[5949>2MS=1=16:E[5929>2MS=1;16:E[5909>2MS=1916:E[59>9>2MS=1715:E[5Z623NR:S<84GY3\55084GY3\51017:EZ49766>1LU=2>2?58C\6;9:4<7JW?<06=3>A^85;>2:5HY1>22;1;5HY1]273=@Q9U:8;5HY1]213=@Q9U::;5HY1]230=@Q9U996IV0^16?B_7W=?0KT>P549D]5Y1=2MR008C\6Ximnxyo>?01>24;753NS;Sljkst`3456;984:>6IV0^cg`vse89:;0<<1139D]5Yflmy~n=>?0=30:442:EZ4Zgclzi<=>?<04=57=@Q9Ujhi}zb123497068;0KT>Paefpqg67896:24GX2\eabt}k:;<=2=>038C\6Ximnxyo>?01>0:47Paefpqg67896>24GX2\eabt}k:;<=29>038C\6Ximnxyo>?01>4:47Paefpqg6789622k5HY1]nqir789;7<3??;F[3[hsk|9:;=1>11028C\6Xe|f<=>><02=55=@Q9Ufyaz?013?548682MR4GX2\ipjs89::0<:1119D]5Yj}e~;<=?314<24>A^8Vg~`y>?00>22;773NS;S`{ct12359706o1LU=Qbumv3457;97l0KT>Pmtnw45664;4m7JW?_lwop5679595j6IV0^ovhq67886?2k5HY1]nqir789;793h4GX2\ipjs89::0;0i;F[3[hsk|9:;=191f:EZ4Zkrd}:;<<27>g9D]5Yj}e~;<=?39?g8C\6Xe|r;<=>30?d8C\6Xe|r;<=>30?325>A^8Vg~t=>?0=2=[c3a3NS;S`{w012384699:1LU=Qbuy2345:687UX[=h4GX2\ip~789:7=<0>3:EZ4Zkrp9:;<1?>>^QT4c=@Q9Ufyu>?01>26;743NS;S`{w01238449WZ];j6IV0^ov|56785;82<=4GX2\ip~789:7=>0PSV2e?B_7Wds<=>?<06=56=@Q9Ufyu>?01>20;YT_9l0KT>Pmtz3456;9<4:?6IV0^ov|56785;>2R]X0g9D]5Yj}q:;<=2>6?30?B_7Wds<=>?<04=[VQ7n2MRPmtz3456;9>4T_Z>j;F[3[hs89:;0<0i;F[3[hs89:;0<0>109D]5Yj}q:;<=2>>^d6a>A^8Vg~t=>?0=0=b>A^8Vg~t=>?0=0=5471:EZ4Zkrp9:;<1:1_g7f?B_7Wds<=>?<4?<4<254=@Q9Ufyu>?01>6:Z`2m2MRPmtz3456;>7Um9h5HY1]nq}67896<2k5HY1]nq}67896<2>;F[3[hs89:;0:0Pf4g8C\6Xe|r;<=>38?31?B_7Wds<=>?<9<\WR6b3NS;S`{w01238<86:2MRg9D]5Yt}k:;<=2>5?d8C\6X{|h;<=>317?<05=a>A^8Vy~n=>?0=3=a>A^8Vy~n=>?0=0=a>A^8Vy~n=>?0=1=a>A^8Vy~n=>?0=6=a>A^8Vy~n=>?0=7=a>A^8Vy~n=>?0=4=a>A^8Vy~n=>?0=5=a>A^8Vy~n=>?0=:=a>A^8Vy~n=>?0=;=2>A^95:5;6IV1=33:2=@Q86:=394GX3?57803NS:0<=17:EZ59736>1LU<2>5?58C\7;9?4<7JW><05=2>A^95;5:6IV1=0=2>A^9595:6IV1=6=2>A^95?5:6IV1=4=2>A^95=5:6IV1=:=2>A^953596IV1^26?B_6W8<0KT?P1148C\7X98<0KT?P1348C\7X9:<0KT?P1548C\7X9<<0KT?P1748C\7X9>?0KT?P249D]4Y4=2MR=R::;F[2[03A^9V2>7JW>_848CZIE]O30KRoad1234d=@Whdo<=>?149KW|hd12BXucm!P@Fb?MU~fjUDNXH>;H08M543@DBX^ZNTD18MKP?3@D]I_ZJDd9JJZH@LVKEHRLLD79JKFIJX?1BCYW_E59JTDB53EC<7AGMR@PZ6>JH>2FDMIKK3:NLG2=KGNCHMA=4LTV7?ISS9=1GYY<;;MWW71=K]]>>7@ 80e58I+17lVFi7@O_EYRBJACC>2GJ\]KKa:OBTZKHL\FNh6CNP^VJI@USIDZi7@O__WGQWLII901F@RIJNDPBP@BXXFY_!J\NNHVFg>KRD];3T<6\IN:8IPJSWHDO?6CZX49NQ]E^=2G^TK;i;Lc`gpkXLQUhu1>1119NefereVNSSnw311<24>KfkjfSIVPcx>25;773DkhoxcPDY]`}97568:0Almlul]G\Ze~4895==5BabaviZB_Wjs7=90>0:ObgfsjWMRTot2>5?33?Hgdk|gTHUQly=35:c=Jiji~aRJW_b{?5;`038Ided}dUOTRbzt=33:47038Ided}dUOTRbzt=37:47028Ided}dUOTRbzt=3=55=Jiji~aRJW_mww878682Gjon{b_EZ\hpr;;7;;7@olcto\@]Yk}}6?2<>4M`a`qhYCPVf~x1;1119NefereVNSSa{{<7<24>KfkjfSIVPltv?3;773DkhoxcPDY]oqq:?68:0Almlul]G\Zjr|535==5BabaviZB_Wqey0=0>1:ObgfsjWMRTtb|311<25>KfkjfSIVPxnp?548692Gjon{b_EZ\|jt;9;4:=6Cncbwn[A^Xpfx7=>0>1:ObgfsjWMRTtb|315<25>KfkjfSIVPxnp?508692Gjon{b_EZ\|jt;9?4:=6Cncbwn[A^Xpfx7=:0>0:ObgfsjWMRTtb|31?33?Hgdk|gTHUQwos>1:46028Ided}dUOTRv`r=5=55=Jiji~aRJW_ymq8=8682Gjon{b_EZ\|jt;17l0Almlul]G]Ze~494:<6Cncbwn[A_Xkp6:<3??;Lc`gpkXLPUhu1?>>028Ided}dUOURmv<00=55=Jiji~aRJV_b{?568682Gjon{b_E[\g|:6<7;;7@olcto\@\Ydq5;>2<>4M`a`qhYCQVir0<81f:ObgfsjWMSTot2>>g9NefereVNRSnw32?d8Ided}dUOURmv<2KfkjfSIWPcx>6:c=Jiji~aRJV_b{?2;`9n2Gjon{b_E[\g|:>68:0Almlul]G]Zjr|5:5=<5BabaviZB^We0<>1109NefereVNRSa{{<03=54=Jiji~aRJV_mww8449981Fmnmzm^FZ[iss4895=<5BabaviZB^We0<:1109NefereVNRSa{{<07=54=Jiji~aRJV_mww8409981Fmnmzm^FZ[iss48=5==5BabaviZB^We0<0>0:ObgfsjWMST`xz32?33?Hgdk|gTHTQcuu>0:46028Ided}dUOURbzt=:=55=Jiji~aRJV_mww8<8682Gjon{b_E[\|jt;87;:7@olcto\@\Yg{6:<3?>;Lc`gpkXLPUsc2>1?32?Hgdk|gTHTQwos>26;763DkhoxcPDX]{kw:6;7;:7@olcto\@\Yg{6:83?>;Lc`gpkXLPUsc2>5?32?Hgdk|gTHTQwos>22;763DkhoxcPDX]{kw:6?7;;7@olcto\@\Yg{6:2<>4M`a`qhYCQVrd~1<1119NefereVNRSua}<2<24>KfkjfSIWPxnp?0;773DkhoxcPDX]{kw:268:0Almlul]G]Z~hz5<5==5BabaviZB^Wqey0:0>0:ObgfsjWMSTtb|38?33?Hgdk|gTHTQwos>::465=<5BabaviZACPVir0<;1109NefereVMOTRmv<04=55=Jiji~aRIKX^az848682Gjon{b_FF[[f;:7;;7@olcto\CA^Xkp682<>4M`a`qhY@LQUhu1:1119NefereVMOTRmv<4<24>KfkjfSJJW_b{?2;773DkhoxcPGEZ\g|:068:0Almlul]D@]Ydq525==5BabaviZACPVir040>1:ObgfsjWNNSSa{{<1<26>KfkjfSJJW_mww84699;1Fmnmzm^EG\Zjr|5;:2<<4M`a`qhY@LQUgyy2>2?31?Hgdk|gTKIVPltv?5686:2Gjon{b_FF[[iss48>5=?5BabaviZACPVf~x1?:>008Ided}dULHUQcuu>22;753DkhoxcPGEZ\hpr;9>4:=6Cncbwn[BB_We0<0>1:ObgfsjWNNSSa{{<3<25>KfkjfSJJW_mww868692Gjon{b_FF[[iss4=4:=6Cncbwn[BB_We080>1:ObgfsjWNNSSa{{<7<25>KfkjfSJJW_mww828692Gjon{b_FF[[iss414:=6Cncbwn[BB_We040>1:ObgfsjWNNSSua}<1<26>KfkjfSJJW_ymq84699;1Fmnmzm^EG\Z~hz5;:2<<4M`a`qhY@LQUsc2>2?31?Hgdk|gTKIVPxnp?5686:2Gjon{b_FF[[}iu48>5=?5BabaviZACPVrd~1?:>008Ided}dULHUQwos>22;753DkhoxcPGEZ\|jt;9>4:=6Cncbwn[BB_Wqey0<0>1:ObgfsjWNNSSua}<3<25>KfkjfSJJW_ymq868692Gjon{b_FF[[}iu4=4:=6Cncbwn[BB_Wqey080>1:ObgfsjWNNSSua}<7<25>KfkjfSJJW_ymq828692Gjon{b_FF[[}iu414:=6Cncbwn[BB_Wqey040>0:ObgfsjWNNRSnw30?32?Hgdk|gTKIWPcx>24;763DkhoxcPGE[\g|:697;:7@olcto\CA_Xkp6:>3?>;Lc`gpkXOMSTot2>3?32?Hgdk|gTKIWPcx>20;763DkhoxcPGE[\g|:6=7;:7@olcto\CA_Xkp6::3??;Lc`gpkXOMSTot2>>028Ided}dULHTQly=0=55=Jiji~aRIKY^az868682Gjon{b_FFZ[f;<7;;7@olcto\CA_Xkp6>2<>4M`a`qhY@LPUhu181119NefereVMOURmv<6<24>KfkjfSJJV_b{?<;773DkhoxcPGE[\g|:>68;0Almlul]D@\Yk}}6;2<<4M`a`qhY@LPUgyy2>0?31?Hgdk|gTKIWPltv?5486:2Gjon{b_FFZ[iss4885=?5BabaviZACQVf~x1?<>008Ided}dULHTQcuu>20;753DkhoxcPGE[\hpr;9<4:>6Cncbwn[BB^We0<81139NefereVMOURbzt=34:47038Ided}dULHTQcuu>7:47038Ided}dULHTQcuu>;:4768;0Almlul]D@\Yg{6;2<<4M`a`qhY@LPUsc2>0?31?Hgdk|gTKIWPxnp?5486:2Gjon{b_FFZ[}iu4885=?5BabaviZACQVrd~1?<>008Ided}dULHTQwos>20;753DkhoxcPGE[\|jt;9<4:>6Cncbwn[BB^Wqey0<81139NefereVMOURv`r=34:47038Ided}dULHTQwos>7:47038Ided}dULHTQwos>;:4768:0Almlul]D\4Ydq5:5=<5BabaviZA_9Vir0<>1109NefereVMS=Rmv<03=54=Jiji~aRIW1^az8449981Fmnmzm^E[5Ze~4895=<5BabaviZA_9Vir0<:1109NefereVMS=Rmv<07=54=Jiji~aRIW1^az8409991Fmnmzm^E[5Ze~484:<6Cncbwn[B^6Wjs7>3??;Lc`gpkXOQ;Tot2<>028Ided}dULT7;;7@olcto\C]7Xkp6<2<>4M`a`qhY@P8Uhu161119NefereVMS=Rmv<8<25>KfkjfSJV>_mww8586:2Gjon{b_FZ2[iss48:5=?5BabaviZA_9Vf~x1?>>008Ided}dULT26;753DkhoxcPGY3\hpr;9:4:>6Cncbwn[B^6We0<:1139NefereVMS=Rbzt=36:447;97@olcto\C]7Xd|~7=:0>1:ObgfsjWNR:Sa{{<0<25>KfkjfSJV>_mww878692Gjon{b_FZ2[iss4:4:=6Cncbwn[B^6We090>1:ObgfsjWNR:Sa{{<4<25>KfkjfSJV>_mww838692Gjon{b_FZ2[iss4>4:=6Cncbwn[B^6We050>1:ObgfsjWNR:Sa{{<8<25>KfkjfSJV>_ymq8586:2Gjon{b_FZ2[}iu48:5=?5BabaviZA_9Vrd~1?>>008Ided}dULT26;753DkhoxcPGY3\|jt;9:4:>6Cncbwn[B^6Wqey0<:1139NefereVMS=Rv`r=36:447;97@olcto\C]7Xpfx7=:0>1:ObgfsjWNR:Sua}<0<25>KfkjfSJV>_ymq878692Gjon{b_FZ2[}iu4:4:=6Cncbwn[B^6Wqey090>1:ObgfsjWNR:Sua}<4<25>KfkjfSJV>_ymq838692Gjon{b_FZ2[}iu4>4:=6Cncbwn[B^6Wqey050>1:ObgfsjWNR:Sua}<8<24>KfkjfSJW>_b{?4;763DkhoxcPGX3\g|:687;:7@olcto\C\7Xkp6:=3?>;Lc`gpkXOP;Tot2>2?32?Hgdk|gTKT?Pcx>27;763DkhoxcPGX3\g|:6<7;:7@olcto\C\7Xkp6:93?>;Lc`gpkXOP;Tot2>6?33?Hgdk|gTKT?Pcx>2:46028Ided}dULU008Ided}dULU24;713DkhoxcPGX3\hpr;994T_Z>>2:ObgfsjWNS:Sa{{<03=53=Jiji~aRIV1^nvp9766VY\<<<4M`a`qhY@Q8Ugyy2>2?35?Hgdk|gTKT?Pltv?578X[^::>6Cncbwn[B_6We0<=1179NefereVMR=Rbzt=30:ZUP8880Almlul]D]4Yk}}6:83?9;Lc`gpkXOP;T`xz315<\WR66:2Gjon{b_F[2[iss48?5=;5BabaviZA^9Vf~x1?:>^QT4447;=7@olcto\C\7Xd|~7=;0PSV226>KfkjfSJW>_mww84199?1Fmnmzm^EZ5Zjr|5;<2R]X0038Ided}dULU2:43078Ided}dULU1:ZUP88;0Almlul]D]4Yk}}682<;4M`a`qhY@Q8Ugyy2<>^QT4476:43078Ided}dULU5:ZUP88;0Almlul]D]4Yk}}6<2<;4M`a`qhY@Q8Ugyy28>^QT447::436VY\<4M`a`qhY@Q8Usc2?>008Ided}dULU24;753DkhoxcPGX3\|jt;984:>6Cncbwn[B_6Wqey0<<1139NefereVMR=Rv`r=30:442:ObgfsjWNS:Sua}<04=57=Jiji~aRIV1^zlv97068;0Almlul]D]4Yg{6:24M`a`qhY@Q8Usc2=>038Ided}dULU0:4724M`a`qhY@Q8Usc29>038Ided}dULU4:474M`a`qhYULQUhu1>1109NefereVXOTRmv<02=54=Jiji~aR\KX^az8479981Fmnmzm^PG\Ze~4885=<5BabaviZTCPVir0<=1109NefereVXOTRmv<06=54=Jiji~aR\KX^az8439981Fmnmzm^PG\Ze~48<5==5BabaviZTCPVir0<0>0:ObgfsjW[NSSnw32?33?Hgdk|gT^IVPcx>0:46028Ided}dUYHUQly=:=55=Jiji~aR\KX^az8<8692Gjon{b_SF[[iss494:>6Cncbwn[WB_We0<>1139NefereVXOTRbzt=32:440>2:ObgfsjW[NSSa{{<06=57=Jiji~aR\KX^nvp9726880Almlul]Q@]Yk}}6::3?=;Lc`gpkXZMRT`xz316<25>KfkjfS_JW_mww848692Gjon{b_SF[[iss4;4:=6Cncbwn[WB_We0>0>1:ObgfsjW[NSSa{{<5<25>KfkjfS_JW_mww808692Gjon{b_SF[[iss4?4:=6Cncbwn[WB_We0:0>1:ObgfsjW[NSSa{{<9<25>KfkjfS_JW_mww8<8692Gjon{b_SF[[}iu494:>6Cncbwn[WB_Wqey0<>1139NefereVXOTRv`r=32:440>2:ObgfsjW[NSSua}<06=57=Jiji~aR\KX^zlv9726880Almlul]Q@]Yg{6::3?=;Lc`gpkXZMRTtb|316<25>KfkjfS_JW_ymq848692Gjon{b_SF[[}iu4;4:=6Cncbwn[WB_Wqey0>0>1:ObgfsjW[NSSua}<5<25>KfkjfS_JW_ymq808692Gjon{b_SF[[}iu4?4:=6Cncbwn[WB_Wqey0:0>1:ObgfsjW[NSSua}<9<25>KfkjfS_JW_ymq8<8682Gjon{b_SFZ[f;87;:7@olcto\VA_Xkp6:<3?>;Lc`gpkXZMSTot2>1?32?Hgdk|gT^IWPcx>26;763DkhoxcPRE[\g|:6;7;:7@olcto\VA_Xkp6:83?>;Lc`gpkXZMSTot2>5?32?Hgdk|gT^IWPcx>22;773DkhoxcPRE[\g|:668:0Almlul]Q@\Ydq585==5BabaviZTCQVir0>0>0:ObgfsjW[NRSnw34?33?Hgdk|gT^IWPcx>6:464:<6Cncbwn[WB^Wjs743??;Lc`gpkXZMSTot26>038Ided}dUYHTQcuu>3:442:ObgfsjW[NRSa{{<00=57=Jiji~aR\KY^nvp9746880Almlul]Q@\Yk}}6:83?=;Lc`gpkXZMST`xz314<26>KfkjfS_JV_mww84099;1Fmnmzm^PG]Zjr|5;<24M`a`qhYULPUgyy2>>038Ided}dUYHTQcuu>1:47038Ided}dUYHTQcuu>5:47038Ided}dUYHTQwos>3:442:ObgfsjW[NRSua}<00=57=Jiji~aR\KY^zlv9746880Almlul]Q@\Yg{6:83?=;Lc`gpkXZMSTtb|314<26>KfkjfS_JV_ymq84099;1Fmnmzm^PG]Z~hz5;<24M`a`qhYULPUsc2>>038Ided}dUYHTQwos>1:47038Ided}dUYHTQwos>5:47028Ided}dUYTKfkjfS_V>_b{?6;773DkhoxcPRY3\g|:468:0Almlul]Q\4Ydq5>5==5BabaviZT_9Vir080>0:ObgfsjW[R:Snw36?33?Hgdk|gT^U?Pcx>4:469991Fmnmzm^P[5Ze~404:=6Cncbwn[W^6We0=0>2:ObgfsjW[R:Sa{{<02=57=Jiji~aR\W1^nvp9766880Almlul]Q\4Yk}}6:>3?=;Lc`gpkXZQ;T`xz312<26>KfkjfS_V>_mww84299;1Fmnmzm^P[5Zjr|5;>2<<4M`a`qhYUP8Ugyy2>6?31?Hgdk|gT^U?Pltv?528692Gjon{b_SZ2[iss484:=6Cncbwn[W^6We0?0>1:ObgfsjW[R:Sa{{<2<25>KfkjfS_V>_mww818692Gjon{b_SZ2[iss4<4:=6Cncbwn[W^6We0;0>1:ObgfsjW[R:Sa{{<6<25>KfkjfS_V>_mww8=8692Gjon{b_SZ2[iss404:=6Cncbwn[W^6Wqey0=0>2:ObgfsjW[R:Sua}<02=57=Jiji~aR\W1^zlv9766880Almlul]Q\4Yg{6:>3?=;Lc`gpkXZQ;Ttb|312<26>KfkjfS_V>_ymq84299;1Fmnmzm^P[5Z~hz5;>2<<4M`a`qhYUP8Usc2>6?31?Hgdk|gT^U?Pxnp?528692Gjon{b_SZ2[}iu484:=6Cncbwn[W^6Wqey0?0>1:ObgfsjW[R:Sua}<2<25>KfkjfS_V>_ymq818692Gjon{b_SZ2[}iu4<4:=6Cncbwn[W^6Wqey0;0>1:ObgfsjW[R:Sua}<6<25>KfkjfS_V>_ymq8=8692Gjon{b_SZ2[}iu404:<6Cncbwn[W_6Wjs7<3?>;Lc`gpkXZP;Tot2>0?32?Hgdk|gT^T?Pcx>25;763DkhoxcPRX3\g|:6:7;:7@olcto\V\7Xkp6:?3?>;Lc`gpkXZP;Tot2>4?32?Hgdk|gT^T?Pcx>21;763DkhoxcPRX3\g|:6>7;;7@olcto\V\7Xkp6:2<>4M`a`qhYUQ8Uhu1<1119NefereVXR=Rmv<2<24>KfkjfS_W>_b{?0;773DkhoxcPRX3\g|:268:0Almlul]Q]4Ydq5<5==5BabaviZT^9Vir0:0>0:ObgfsjW[S:Snw38?33?Hgdk|gT^T?Pcx>::47>^QT444KfkjfS_W>_mww84599?1Fmnmzm^PZ5Zjr|5;82R]X0008Ided}dUYU20;713DkhoxcPRX3\hpr;9=4T_Z>>2:ObgfsjW[S:Sa{{<07=53=Jiji~aR\V1^nvp9726VY\<<<4M`a`qhYUQ8Ugyy2>6?35?Hgdk|gT^T?Pltv?538X[^::>6Cncbwn[W_6We0<91179NefereVXR=Rbzt=34:ZUP88;0Almlul]Q]4Yk}}6:2<;4M`a`qhYUQ8Ugyy2>>^QT4470:43078Ided}dUYU7:ZUP88;0Almlul]Q]4Yk}}6>2<;4M`a`qhYUQ8Ugyy2:>^QT4474:43078Ided}dUYU;:ZUP88;0Almlul]Q]4Yk}}622<;4M`a`qhYUQ8Ugyy26>^QT447KfkjfS_W>_ymq84499;1Fmnmzm^PZ5Z~hz5;82<<4M`a`qhYUQ8Usc2>4?31?Hgdk|gT^T?Pxnp?5086:2Gjon{b_S[2[}iu48<5=?5BabaviZT^9Vrd~1?8>038Ided}dUYU2:47038Ided}dUYU6:47038Ided}dUYU::c=Jiji~aRV>_b{?4;773DkhoxcPX0]`}97768:0Almlul][5Ze~48;5==5BabaviZ^6Wjs7=?0>0:ObgfsjWQ;Tot2>3?33?Hgdk|gTTg9NefereVR:Snw37?d8Ided}dUS=Rmv<9_mww858692Gjon{b_Y3\hpr;994:=6Cncbwn[]7Xd|~7=<0>1:ObgfsjWQ;T`xz313<25>KfkjfSU?Pltv?568692Gjon{b_Y3\hpr;9=4:=6Cncbwn[]7Xd|~7=80>1:ObgfsjWQ;T`xz317<25>KfkjfSU?Pltv?528682Gjon{b_Y3\hpr;97;;7@olcto\\4Yk}}692<>4M`a`qhY_9Vf~x1=1119NefereVR:Sa{{<5<24>KfkjfSU?Pltv?1;773DkhoxcPX0]oqq:168:0Almlul][5Zjr|5=5==5BabaviZ^6We050>0:ObgfsjWQ;T`xz39?33?Hgdk|gTT3:47038Ided}dUS=Rv`r=30:4724M`a`qhY_9Vrd~1?9>038Ided}dUS=Rv`r=34:46028Ided}dUS=Rv`r=7=55=Jiji~aRV>_ymq838682Gjon{b_Y3\|jt;?7;;7@olcto\\4Yg{632<>4M`a`qhY_9Vrd~171f:ObgfsjWP;Tot2?>028Ided}dUR=Rmv<02=55=Jiji~aRW>_b{?548682Gjon{b_X3\g|:6:7;;7@olcto\]4Ydq5;82<>4M`a`qhY^9Vir0<:1119NefereVS:Snw314<24>KfkjfST?Pcx>22;`0:ObgfsjWP;T`xz30?32?Hgdk|gTU24;723DkhoxcPY0]oqq:687UX[=?>;Lc`gpkXQ8Ugyy2>1?36?Hgdk|gTU25;YT_9;:7@olcto\]4Yk}}6:>3?:;Lc`gpkXQ8Ugyy2>2?]PS5763DkhoxcPY0]oqq:6;7;>7@olcto\]4Yk}}6:?3Q\W132?Hgdk|gTU20;723DkhoxcPY0]oqq:6<7UX[=?>;Lc`gpkXQ8Ugyy2>5?36?Hgdk|gTU21;YT_9;:7@olcto\]4Yk}}6::3?:;Lc`gpkXQ8Ugyy2>6?]PS5763DkhoxcPY0]oqq:6?7;>7@olcto\]4Yk}}6:;3Q\W133?Hgdk|gTU2:424:ObgfsjWP;T`xz32?]PS5773DkhoxcPY0]oqq:468>0Almlul]Z5Zjr|595S^Y?119NefereVS:Sa{{<5<20>KfkjfST?Pltv?0;YT_9;;7@olcto\]4Yk}}6>2<:4M`a`qhY^9Vf~x1;1_RU355=Jiji~aRW>_mww8386<2Gjon{b_X3\hpr;>7UX[=??;Lc`gpkXQ8Ugyy28>068Ided}dUR=Rbzt=5=[VQ7991Fmnmzm^[2[iss414:86Cncbwn[\7Xd|~743Q\W133?Hgdk|gTU::421:ObgfsjWP;Ttb|311<25>KfkjfST?Pxnp?548692Gjon{b_X3\|jt;9;4:=6Cncbwn[\7Xpfx7=>0>1:ObgfsjWP;Ttb|315<25>KfkjfST?Pxnp?508692Gjon{b_X3\|jt;9?4:=6Cncbwn[\7Xpfx7=:0>0:ObgfsjWP;Ttb|31?33?Hgdk|gTU1:46028Ided}dUR=Rv`r=5=55=Jiji~aRW>_ymq8=8682Gjon{b_X3\|jt;17;=7@okd^E[4Zgcl9:;KflmULT=Qnde2345Ydq5;;2<94M`fg[B^7Whno<=>?_b{?5486?2GjhiQHX1]b`a6789Uhu1?=>058IdbcWNR;Sljk0123[f;9:4:;6Cnde]D\5Yflm:;<=Qly=37:417:Ob`aY@P9Ujhi>?01]`}97168<0Aljk_FZ3[dbc89:;Snw31?35?HgclVMSPaef3456Xkp6?2<84M`fg[B^7Whno<=>?_b{?1;713DkohRIW0^cg`5678Vir0;0>6:Ob`aY@P9Ujhi>?01]`}9199?1FmijPGY2\eab789:Tot27>048IdbcWNR;Sljk0123[f;17;<7@okd^E[4Zgcl9:;Paef3456Xd|~7==0>8:Ob`aY@P9Ujhi>?01]oqq:697;37@okd^E[4Zgcl9:;21;7?3DkohRIW0^cg`5678Vf~x1?9>0:8IdbcWNR;Sljk0123[iss48=5=:5Baef\C]6Ximn;<=>Pltv?5;703DkohRIW0^cg`5678Vf~x1<1169NeabXOQ:Tmij?012\hpr;;7;<7@okd^E[4Zgcl9:;Paef3456Xd|~793?8;Lcg`ZA_8Vkoh=>?0^nvp9099>1FmijPGY2\eab789:T`xz37?34?HgclVMSPltv?=;703DkohRIW0^cg`5678Vrd~1>1199NeabXOQ:Tmij?012\|jt;994:46Cnde]D\5Yflm:;<=Qwos>25;7?3DkohRIW0^cg`5678Vrd~1?=>0:8IdbcWNR;Sljk0123[}iu4895=55Baef\C]6Ximn;<=>Pxnp?518602GjhiQHX1]b`a6789Usc2>5?3;?HgclVMS?_ymq84199>1FmijPGY2\eab789:Ttb|31?34?HgclVMS