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Rev 358 → Rev 371
/implementaciones/vga/vgacontroller.vhd
0,0 → 1,241
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
|
use work.vgapack.all; |
|
|
entity vgacontroller is |
Port ( clock : in STD_LOGIC; -- 50MHz clock |
reset : in STD_LOGIC; |
hsync : out STD_LOGIC; |
vsync : out STD_LOGIC; |
red : out STD_LOGIC; |
green : out STD_LOGIC; |
blue : out STD_LOGIC); |
end vgacontroller; |
|
architecture Behavioral of vgacontroller is |
|
signal clock_enable : std_logic; |
signal hclock_enable : std_logic; |
-- signal vclock_enable : std_logic; |
signal hsync_enable : std_logic; |
signal hsync_sig : std_logic; |
signal hsync_enable2 : std_logic; |
signal vsync_enable : std_logic; |
signal hvsync_enable : std_logic; |
|
signal colors_enable : std_logic; |
-- signal v_clock_enable : std_logic; |
-- signal hcounter : integer; |
-- signal vcounter : integer; |
|
begin |
|
divideBy2_proc : process(clock, reset) |
variable ce : std_logic := '0'; |
begin |
if reset='1' then |
ce := '0'; |
elsif falling_edge(clock) then |
ce := not ce; |
end if; |
clock_enable <= ce; |
end process; |
|
----VSYNC |
--------------------------------xxxxxxxxxxxx-------- |
vsync_ena_proc : process(clock, reset) |
variable contador : integer := 0; |
variable vse : std_logic := '0'; |
begin |
if reset='1' then |
contador := 0; |
elsif rising_edge(clock) then |
if clock_enable = '0' then |
case contador is |
when 0 => vse := '1'; |
when (b+c+d+e)*p => vse := '1'; |
when (b+c+d+e)*(p+q+r+s)-1 => vse := '0'; contador := -1; |
when others => vse := '0'; |
end case; |
contador := contador + 1; |
end if; |
end if; |
vsync_enable <= vse; |
end process; |
|
|
vsync_proc : process(clock, vsync_enable, reset) |
variable vs : std_logic := '1'; |
begin |
if reset='1' then |
vs := '1'; |
elsif rising_edge(clock) then |
if clock_enable = '1' and vsync_enable = '1' then |
vs := not vs; |
end if; |
end if; |
vsync <= vs; |
end process; |
|
|
-------HSYNC |
--------------------------------xxxxxxxxxxxx-------- |
|
hvsync_ena_proc : process(clock, reset) |
variable contador : integer := 0; |
variable vse : std_logic := '0'; |
begin |
if reset='1' then |
contador := 0; |
elsif rising_edge(clock) then |
if clock_enable = '0' then |
case contador is |
--when 0 => vse := '1'; |
when (b+c+d+e)*(p+q)-1 => vse := '1'; |
when (b+c+d+e)*(p+q+r)-1 => vse := '1'; |
when (b+c+d+e)*(p+q+r+s)-1 => vse := '0'; contador := -1; |
when others => vse := '0'; |
end case; |
contador := contador + 1; |
end if; |
end if; |
hvsync_enable <= vse; |
end process; |
|
|
hvsync_proc : process(clock, reset) |
variable vs : std_logic := '0'; |
begin |
if reset='1' then |
vs := '1'; |
elsif rising_edge(clock) then |
if clock_enable = '1' and hvsync_enable = '1' then |
vs := not vs; |
end if; |
end if; |
hsync_enable2 <= vs; |
end process; |
|
|
hsync_ena_proc : process(clock, reset) |
variable contador : integer := 0; |
variable hse : std_logic := '0'; |
begin |
if reset='1' then |
contador := 0; |
elsif rising_edge(clock) then |
if clock_enable = '0' then |
case contador is |
when 0 => hse := '1'; |
when b => hse := '1'; |
when b+c+d+e-1 => hse := '0'; contador := -1; |
when others => hse := '0'; |
end case; |
contador := contador + 1; |
end if; |
end if; |
hsync_enable <= hse ; |
end process; |
|
|
hsync_proc : process(clock, reset) |
variable hs : std_logic := '1'; |
begin |
if reset='1' then |
hs := '1'; |
elsif rising_edge(clock) then |
if hsync_enable = '1' and clock_enable = '1' then |
hs := not hs; |
end if; |
end if; |
hsync_sig <= hs ; |
end process; |
|
|
------COLORS |
----------------------------------- |
colors_ena_proc : process(clock, reset) |
variable contador : integer := 0; |
variable hse : std_logic := '0'; |
begin |
if reset='1' then |
contador := 0; |
elsif rising_edge(clock) then |
if clock_enable = '0' then |
case contador is |
when b+c => hse := '1'; |
when b+c+d => hse := '1'; |
when b+c+d+e-1 => hse := '0'; contador := -1; |
when others => hse := '0'; |
end case; |
contador := contador + 1; |
end if; |
end if; |
colors_enable <= hse ; |
end process; |
|
|
colors_proc : process(clock, reset) |
variable hs : std_logic := '0'; |
begin |
if reset='1' then |
hs := '1'; |
elsif rising_edge(clock) then |
if colors_enable = '1' and clock_enable = '1' then |
hs := not hs; |
end if; |
end if; |
blue <= hs and hsync_enable2; |
end process; |
|
|
-- |
-- |
-- |
--hclock_ena_proc : process(clock, reset) |
-- variable contador : integer := 0; |
-- variable hce : std_logic := '0'; |
--begin |
-- if reset='1' then |
-- contador := 0; |
-- elsif falling_edge(clock) then |
-- case contador is |
-- when 0 => hce := '1'; |
-- when b+c+d+e-1 => hce := '0'; contador := -1; |
-- when others => hce := '0'; |
-- end case; |
-- contador := contador + 1; |
-- end if; |
-- hclock_enable <= hce; |
--end process; |
|
|
--hclock_proc : process(clock, hsync_enable, reset) |
-- variable hs : std_logic := '1'; |
--begin |
-- if reset='1' then |
-- hs := '1'; |
-- elsif rising_edge(clock) then |
-- if hsync_enable = '1' then |
-- hs := not hs; |
-- end if; |
-- end if; |
-- hsync <= hs; |
--end process; |
|
|
|
|
hsync <= hsync_sig or not hsync_enable2; |
-- vsync <= '0'; |
red <= clock_enable; |
green <= hsync_sig; |
--blue <= hsync_enable2; |
|
|
end Behavioral; |
|
/implementaciones/vga/vga_tb.vhd
0,0 → 1,73
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
|
use work.vgapack.all; |
|
ENTITY vga_tb IS |
END vga_tb; |
|
ARCHITECTURE behavior OF vga_tb IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT vga |
PORT( |
ck_50M : IN std_logic; |
-- vgaFrame : IN display; |
reset : in std_logic; |
hsync : OUT std_logic; |
vsync : OUT std_logic; |
red : OUT std_logic; |
green : OUT std_logic; |
blue : OUT std_logic |
); |
END COMPONENT; |
|
|
--Inputs |
signal ck_50M : std_logic := '0'; |
signal reset : std_logic := '1'; |
-- signal vgaFrame : display; |
|
--Outputs |
signal hsync : std_logic; |
signal vsync : std_logic; |
signal red : std_logic; |
signal green : std_logic; |
signal blue : std_logic; |
|
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: vga PORT MAP ( |
ck_50M => ck_50M, |
-- vgaFrame => vgaFrame, |
reset => reset, |
hsync => hsync, |
vsync => vsync, |
red => red, |
green => green, |
blue => blue |
); |
|
-- Clock process definitions |
ck_50M_process :process |
begin |
ck_50M <= '0'; |
wait for 10 ns; |
ck_50M <= '1'; |
wait for 10 ns; |
end process; |
|
-- filas: for i in 0 to row_num-1 generate |
-- begin |
-- columnas: for j in 0 to col_num-1 generate |
-- begin |
-- vgaFrame(i,j) <= '1'; |
-- end generate; |
-- end generate; |
|
END; |
/implementaciones/vga/vgacontroller_tb.vhd
0,0 → 1,79
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
use work.vgapack.all; |
|
|
ENTITY vgacontroller_tb IS |
END vgacontroller_tb; |
|
ARCHITECTURE behavior OF vgacontroller_tb IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT vgacontroller |
PORT( |
clock : IN std_logic; |
reset : IN std_logic; |
hsync : OUT std_logic; |
vsync : OUT std_logic; |
red : OUT std_logic; |
green : OUT std_logic; |
blue : OUT std_logic |
); |
END COMPONENT; |
|
|
--Inputs |
signal clock : std_logic := '0'; |
signal reset : std_logic := '0'; |
|
--Outputs |
signal hsync : std_logic; |
signal vsync : std_logic; |
signal red : std_logic; |
signal green : std_logic; |
signal blue : std_logic; |
|
-- Clock period definitions |
constant clock_period : time := 20 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: vgacontroller PORT MAP ( |
clock => clock, |
reset => reset, |
hsync => hsync, |
vsync => vsync, |
red => red, |
green => green, |
blue => blue |
); |
|
-- Clock process definitions |
clock_process :process |
begin |
clock <= '0'; |
wait for clock_period/2; |
clock <= '1'; |
wait for clock_period/2; |
end process; |
|
|
-- -- Stimulus process |
-- stim_proc: process |
-- begin |
-- -- hold reset state for 100 ns. |
-- reset <= '0'; |
-- wait for 10 ns; |
-- reset <= '1'; |
---- wait for clock_period*10; |
---- |
---- -- insert stimulus here |
---- |
---- wait; |
-- end process; |
|
END; |
/implementaciones/vga/stem.vhd
0,0 → 1,44
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use work.vgapack.all; |
|
entity stem is |
Port ( enable : in STD_LOGIC; |
jaja : out std_logic; |
display : out lr_display); |
end stem; |
|
architecture Behavioral of stem is |
|
type vector is array (0 to 3) of unsigned (2 downto 0); |
signal secuencia : vector := ("001","010","011","100"); |
begin |
|
|
process (secuencia) |
begin |
|
for c in 0 to lr_col_num-1 loop |
for r in 0 to lr_row_num-1 loop |
if secuencia(c) > r then |
display (lr_row_num-1-r,c) <= '1'; |
else |
display (lr_row_num-1-r,c) <= '0'; |
end if; |
end loop; |
end loop; |
|
|
-- if secuencia(1) > 3 then |
-- jaja <= '1'; |
-- else |
-- jaja <= '0'; |
-- end if; |
|
|
end process; |
|
end Behavioral; |
|
/implementaciones/vga/vgaframe.vhd
0,0 → 1,112
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
|
use work.vgapack.all; |
|
|
entity vgaframe is |
generic ( |
BN : integer := 6 |
); |
Port ( enable : in STD_LOGIC; |
vgaFrame : out display |
); |
end vgaframe; |
|
architecture Behavioral of vgaframe is |
|
signal little_display : lr_display; |
|
-- type seq_type is array (0 to 7) of unsigned (BN-1 downto 0); |
-- signal seq : seq_type := ("000000","001000","010000","011000","100000","101000","110000","111000"); |
-- |
-- signal test : unsigned(BN-1 downto 0); |
begin |
-- |
-- test <= not to_unsigned(2,BN) ; |
-- |
-- process (little_display, seq) |
-- begin |
-- |
-- for j in 0 to col_num/x_step-1 loop |
-- for i in 0 to row_num/y_step-1 loop |
-- if ((not to_unsigned(i,BN)) < seq (j)) then |
-- little_display (i,j) <= '1'; |
-- else |
-- little_display (i,j) <= '0'; |
-- end if; |
-- end loop; |
-- end loop; |
-- |
-- end process; |
|
process (little_display) |
begin |
|
for i in 0 to lr_row_num-1 loop |
for j in 0 to lr_col_num-1 loop |
if (i = 1 and j = 2) or |
(i = 1 and j = 3) or |
(i = 1 and j = 5) or |
(i = 1 and j = 7) or |
(i = 1 and j = 9) or |
(i = 1 and j = 10) or |
(i = 1 and j = 14) or |
(i = 1 and j = 17) or |
(i = 1 and j = 18) or |
(i = 2 and j = 1) or |
(i = 2 and j = 5) or |
(i = 2 and j = 7) or |
(i = 2 and j = 9) or |
(i = 2 and j = 11) or |
(i = 2 and j = 13) or |
(i = 2 and j = 15) or |
(i = 2 and j = 17) or |
(i = 2 and j = 19) or |
(i = 3 and j = 1) or |
(i = 3 and j = 5) or |
(i = 3 and j = 7) or |
(i = 3 and j = 9) or |
(i = 3 and j = 11) or |
(i = 3 and j = 13) or |
(i = 3 and j = 14) or |
(i = 3 and j = 15) or |
(i = 3 and j = 17) or |
(i = 3 and j = 18) or |
(i = 4 and j = 2) or |
(i = 4 and j = 3) or |
(i = 4 and j = 6) or |
(i = 4 and j = 9) or |
(i = 4 and j = 10) or |
(i = 4 and j = 13) or |
(i = 4 and j = 15) or |
(i = 4 and j = 17) or |
(i = 4 and j = 19) then |
little_display (i,j) <= '1'; |
else |
little_display (i,j) <= '0'; |
end if; |
end loop; |
end loop; |
|
end process; |
|
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algo1: for i in 0 to lr_row_num-1 generate |
begin |
algo2 : for j in 0 to lr_col_num-1 generate |
begin |
algo3 : for r in i*x_step to (i+1)*x_step-1 generate |
begin |
algo4 : for c in j*y_step to (j+1)*y_step-1 generate |
begin |
vgaFrame (r,c) <= little_display (i,j); |
end generate; |
end generate; |
end generate; |
end generate; |
|
end Behavioral; |
|
/implementaciones/vga/vgapack.vhd
0,0 → 1,36
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.ALL; |
|
package vgapack is |
|
constant col_num : integer := 640; --640 |
constant row_num : integer := 480; --480 |
|
--type display is array (0 to row_num-1, 0 to col_num-1) of STD_LOGIC; |
|
constant b : integer := 95; -- 95 |
constant c : integer := 45; -- 45 |
constant d : integer := col_num; |
constant e : integer := 20; -- 20 |
|
constant p : integer := 2; -- 2 |
constant q : integer := 32; -- 32 |
constant r : integer := row_num; |
constant s : integer := 14; --14 |
|
|
-- low resolution display |
|
constant x_step : integer := 128; -- POTENCIA DE 2 !!! |
constant y_step : integer := 32; -- POTENCIA DE 2 !!! |
|
constant lr_row_num : integer := row_num/y_step; |
constant lr_col_num : integer := col_num/x_step; |
|
type lr_display is array (0 to lr_row_num-1, 0 to lr_col_num-1) of STD_LOGIC; |
|
|
end vgapack; |
|
/implementaciones/vga/vga.vhd
0,0 → 1,123
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
|
use work.vgapack.all; |
|
|
entity vga is |
Port ( |
ck_50M : in STD_LOGIC; |
reset : in STD_LOGIC; |
hsync : out STD_LOGIC; |
vsync : out STD_LOGIC; |
red : out STD_LOGIC; |
green : out STD_LOGIC; |
blue : out STD_LOGIC); |
end vga; |
|
architecture Behavioral of vga is |
|
signal r_lr_frame : lr_display := (('1','0','0','1','1'),('1','1','0','0','0'),('1','0','0','1','1'),('1','1','0','0','0'),('1','0','0','1','1'),('1','1','0','0','0'),('1','0','0','1','1'),('1','1','0','0','0'),('1','0','0','1','1'),('1','1','0','0','0'),('1','0','0','1','1'),('1','1','0','0','0'),('1','0','0','1','1'),('1','1','0','0','0'),('1','0','0','1','1')); |
signal g_lr_frame : lr_display := (('0','1','0','1','1'),('1','0','1','0','0'),('0','1','0','1','1'),('1','0','1','0','0'),('0','1','0','1','1'),('1','0','1','0','0'),('0','1','0','1','1'),('1','0','1','0','0'),('0','1','0','1','1'),('1','0','1','0','0'),('0','1','0','1','1'),('1','0','1','0','0'),('0','1','0','1','1'),('1','0','1','0','0'),('0','1','0','1','1')); |
signal b_lr_frame : lr_display := (('0','0','1','1','1'),('0','1','1','0','0'),('0','0','1','1','1'),('0','1','1','0','0'),('0','0','1','1','1'),('0','1','1','0','0'),('0','0','1','1','1'),('0','1','1','0','0'),('0','0','1','1','1'),('0','1','1','0','0'),('0','0','1','1','1'),('0','1','1','0','0'),('0','0','1','1','1'),('0','1','1','0','0'),('0','0','1','1','1')); |
|
begin |
|
-- purpose: vga |
-- type : sequential |
-- inputs : ck_50M, reset |
-- outputs: |
vga_gen: process (ck_50M, reset) |
|
variable hsync_var : std_logic := '1'; |
variable vsync_var : std_logic := '1'; |
variable red_var : std_logic := '0'; |
variable green_var : std_logic := '0'; |
variable blue_var : std_logic := '0'; |
|
variable icounter : integer := 0; |
|
variable hcounter : integer := 0; |
variable vcounter : integer := 0; |
|
variable rcounter : integer := 0; |
variable ccounter : integer := 0; |
|
begin -- process vga_gen |
if reset = '0' then -- asynchronous reset (active low) |
|
hsync_var := '1'; |
vsync_var := '1'; |
red_var := '0'; |
green_var := '0'; |
blue_var := '0'; |
|
icounter := 0; |
|
hcounter := 0; |
vcounter := 0; |
|
ccounter := 0; |
rcounter := 0; |
|
elsif ck_50M'event and ck_50M = '1' then -- rising clock edge |
|
icounter := icounter + 1; |
|
if icounter >= 2 then |
icounter := 0; |
hcounter := hcounter + 1; |
end if; |
|
if hcounter >= b+c+d+e then |
hcounter := 0; |
vcounter := vcounter + 1; |
end if; |
|
ccounter := hcounter - b - c; |
|
if vcounter >= p+q+r+s then |
vcounter := 0; |
end if; |
|
rcounter := vcounter - p - q; |
|
if vcounter < p then |
vsync_var := '0'; |
else |
vsync_var := '1'; |
end if; |
|
|
if vcounter >= p+q and vcounter < p+q+r and hcounter < b then |
hsync_var := '0'; |
else |
hsync_var := '1'; |
end if; |
|
|
if ccounter >= 0 and ccounter < col_num and rcounter >= 0 and rcounter < row_num then |
red_var := r_lr_frame (rcounter/y_step,ccounter/x_step); |
green_var := g_lr_frame (rcounter/y_step,ccounter/x_step); |
blue_var := b_lr_frame (rcounter/y_step,ccounter/x_step); |
else |
red_var := '0'; |
green_var := '0'; |
blue_var := '0'; |
end if; |
|
end if; |
|
hsync <= hsync_var; |
vsync <= vsync_var; |
red <= red_var; |
green <= green_var; |
blue <= blue_var; |
|
end process vga_gen; |
|
|
end Behavioral; |
|