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  • This comparison shows the changes necessary to convert path 
    /phr/trunk/codigo
    from Rev 390 to Rev 392
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Rev 390 → Rev 392

/implementaciones/adc/pmod2nexys2/displayPmod.vhd
5,17 → 5,19
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
 
entity displayPmod is
generic(
NB_ADC : integer := 12;
PROM : integer := 16);
NB_ADC : integer := 12;
PROM : integer := 64;
NB_DISP : integer := 16);
Port (
clock : in STD_LOGIC;
--slow_clock : in STD_LOGIC;
reset : in STD_LOGIC;
-- convert_button : in std_logic;
sel_data : in std_logic;
pmod_sdata1 : in std_logic;
pmod_sdata2 : in std_logic;
48,19 → 50,19
PORT(
clock : IN std_logic;
reset : IN std_logic;
data : IN std_logic_vector(15 downto 0);
data : IN std_logic_vector((NB_DISP-1) downto 0);
segments : OUT std_logic_vector(6 downto 0);
char_sel : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
signal data1 : std_logic_vector (15 downto 0) := (others => '0');
signal data2 : std_logic_vector (15 downto 0) := (others => '0');
signal data1 : std_logic_vector ((NB_ADC+PROM)-1 downto 0) := (others => '0');
signal Sdata1prom : std_logic_vector ((NB_DISP)-1 downto 0) := (others => '0');
signal Sdatafinal : std_logic_vector ((NB_DISP)-1 downto 0) := (others => '0');
signal data2 : std_logic_vector (NB_DISP downto 0) := (others => '0');
signal done : std_logic;
signal Sstart_conv : std_logic_vector (9 downto 0) := (others => '0');
signal Sslow_clock : std_logic := '0';
signal Sacum : std_logic_vector ((NB_ADC+PROM)-1 downto 0):=(others=>'0');
signal Sready2prom : std_logic;
begin
 
71,44 → 73,39
SDATA2 => pmod_sdata2,
SCLK => pmod_sclk,
nCS => pmod_ncs,
DATA1 => data1 (11 downto 0),
DATA2 => data2 (11 downto 0),
--START => convert_button,
START => Sstart_conv(9),
DATA1 => data1 ((NB_ADC-1) downto 0),
DATA2 => data2 ((NB_ADC-1) downto 0),
START => done,
DONE => done
);
process(clock)
begin
if(falling_edge(clock)) then
Sstart_conv <= Sstart_conv(8 downto 0) & done;
end if;
end process;
data1((NB_ADC+PROM)-1 downto NB_ADC) <= (others => '0');
data1(15 downto 12) <= "0000";
process(clock)
variable Vcountsamp : integer := 0;
variable Vcountsamp : integer := 0;
variable acum : std_logic_vector ((NB_ADC+PROM)-1 downto 0):=(others=>'0');
begin
if(reset = '1') then
Sacum <= (others => '0');
Vcountsamp := 0;
elsif (falling_edge(clock)) then
Sacum <= Sacum + data1;
if(reset = '1') then
Vcountsamp := 0;
Sacum <= (others => '0');
elsif (rising_edge(clock)) then
if(done = '1') then
Vcountsamp := Vcountsamp + 1;
if (Sacum > PROM) then
Sready2prom <= '1';
else
Sready2prom <= '0';
acum := acum + data1;
if (Vcountsamp > PROM) then
Sdata1prom <= ((NB_DISP-NB_ADC-1) downto 0 => '0')& acum((NB_ADC+PROM-1) downto PROM);
Vcountsamp := 0;
acum := (others=>'0');
end if;
end if;
end if;
end process;
process(clock)
variable cuenta: integer:=0;
begin
if (falling_edge(clock)) then
if (cuenta<1000) then
if (rising_edge(clock)) then
if (cuenta<5000) then
cuenta:=cuenta + 1;
else
Sslow_clock <=not Sslow_clock;
116,12 → 113,13
end if;
end if;
end process;
Sdatafinal <= Sdata1prom when sel_data = '1' else
data1(NB_DISP-1 downto 0);
 
Inst_sevseg_display: sevseg_display PORT MAP(
clock => Sslow_clock,
reset => reset,
data => data1,
--data => "0000000000011111",
data => Sdatafinal,
segments => display_seg (6 downto 0),
char_sel => display_char (3 downto 0)
);
/implementaciones/adc/pmod2nexys2/pines.ucf
1,5 → 1,6
net "clock" loc="B8"; # 50 MHz clock
net "reset" loc="B18"; # Button 1
net "sel_data" loc="G18";
 
net "pmod_sdata1" loc="M18"; # change
net "pmod_sdata2" loc="N18"; # change

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