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Rev 395 → Rev 396
/implementaciones/fft/pkg/pipelined_fft_64/trunk/BENCH/sin_tst_rom.v
0,0 → 1,65
///////////////////////////////////////////////////////////////////// |
//// //// |
//// ROM with 64 samples of sine waves at the frequencies 0/1 //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
`timescale 1 ns / 1 ps |
module Wave_ROM64 ( ADDR ,DATA ); |
output [15:0] DATA ; |
input [5:0] ADDR ; |
reg [15:0] sine[0:63]; |
initial begin |
sine[0]=16'h0000; sine[1]=16'h0C8B; sine[2]=16'h18F8; sine[3]=16'h2527; |
sine[4]=16'h30FB; sine[5]=16'h3C56; sine[6]=16'h471C; sine[7]=16'h5133; |
sine[8]=16'h5A82; sine[9]=16'h62F1; sine[10]=16'h6A6D; sine[11]=16'h70E2; |
sine[12]=16'h7641; sine[13]=16'h7A7C; sine[14]=16'h7D8A; sine[15]=16'h7F62; |
sine[16]=16'h7FFF; sine[17]=16'h7F62; sine[18]=16'h7D8A; sine[19]=16'h7A7C; |
sine[20]=16'h7641; sine[21]=16'h70E2; sine[22]=16'h6A6D; sine[23]=16'h62F1; |
sine[24]=16'h5A82; sine[25]=16'h5133; sine[26]=16'h471C; sine[27]=16'h3C56; |
sine[28]=16'h30FB; sine[29]=16'h2527; sine[30]=16'h18F8; sine[31]=16'h0C8B; |
sine[32]=16'h0000; sine[33]=16'hF375; sine[34]=16'hE708; sine[35]=16'hDAD9; |
sine[36]=16'hCF05; sine[37]=16'hC3AA; sine[38]=16'hB8E4; sine[39]=16'hAECD; |
sine[40]=16'hA57E; sine[41]=16'h9D0F; sine[42]=16'h9593; sine[43]=16'h8F1E; |
sine[44]=16'h89BF; sine[45]=16'h8584; sine[46]=16'h8276; sine[47]=16'h809E; |
sine[48]=16'h8001; sine[49]=16'h809E; sine[50]=16'h8276; sine[51]=16'h8584; |
sine[52]=16'h89BF; sine[53]=16'h8F1E; sine[54]=16'h9593; sine[55]=16'h9D0F; |
sine[56]=16'hA57E; sine[57]=16'hAECD; sine[58]=16'hB8E4; sine[59]=16'hC3AA; |
sine[60]=16'hCF05; sine[61]=16'hDAD9; sine[62]=16'hE708; sine[63]=16'hF375; |
end |
|
assign DATA=sine[ADDR]; |
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/BENCH/sinerom64_gen.pl
0,0 → 1,138
#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
# |
# Copyright(c) 2007 by Unicore Systems. All rights reserved |
# |
# DESIGN : UNFFT64_core |
# FILENAME : sinerom64_gen.pl |
# CREATED : 1.11:2007 |
# MODIFIED : |
# VERSION : 1.0 |
# |
# AUTHORS: Anatolij Sergiyenko. |
# HISTORY : |
#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
# DESCRIPTION : Test generating PERL file1 |
# FUNCTION: Generating sine wave ROM |
# with $n samples which consists of 4 sine wave sum |
#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
|
$aw=6; ## - address bit width |
$n = 64; ### - period length |
$n0 = 0; ### - init address |
$f1 = 1; ## - first frequency |
$f2 = 3; ## -second frequency |
$f3 = 5; ## - 3-d frequency |
$f4 = 7; ## -4-th frequency |
$Pi = 3.14159265358 ; |
|
|
|
|
print OutFile "//^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n"; |
print OutFile "// ROM with ".$n." samples of the sine waves at the frequencies = ".$f1." and ".$f2 ."\n"; |
print OutFile "//^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n"; |
print OutFile " `timescale 1 ns / 1 ps \n"; |
print OutFile "module Wave_ROM64 ( ADDR ,DATA_RE,DATA_IM,DATA_REF ); \n"; |
print OutFile " output [15:0] DATA_RE,DATA_IM,DATA_REF ; \n"; |
print OutFile " input [".($aw-1).":0] ADDR ; \n"; |
# # Cosine table generation |
print OutFile " reg [15:0] cosi[0:".($n-1)."]; \n"; |
print OutFile " initial begin \n"; |
for $j(0..$n/4-1){ |
$cos_row=0; |
for $i(0..3){ |
# $CosArr=(16383*cos(2*$Pi*$f1*(($n0+$i+$j*4)/$n)) |
# +16383*cos(2*$Pi*$f2*(($n0+$i+$j*4)/$n))); |
$CosArr=(8191*cos(2*$Pi*$f1*(($n0+$i+$j*4)/$n)) |
+8191*cos(2*$Pi*$f2*(($n0+$i+$j*4)/$n)) |
+8191*cos(2*$Pi*$f3*(($n0+$i+$j*4)/$n)) |
+8191*cos(2*$Pi*$f4*(($n0+$i+$j*4)/$n))); |
$sinv= To_Hex4(int ($CosArr)); |
|
print OutFile " cosi[".($n0+$i+$j*4)."]=16'h".$sinv.";"; |
} |
print OutFile "\n"; |
} |
print OutFile " end \n\n"; |
print "\n"; |
# # Sine table generation |
print OutFile " reg [15:0] sine[0:".($n-1)."]; \n"; |
print OutFile " initial begin \n"; |
for $j(0..$n/4-1){ |
$sin_row=0; |
for $i(0..3){ |
# $SinArr=(16383*sin(2*$Pi*$f1*(($n0+$i+$j*4)/$n)) |
# +16383*sin(2*$Pi*$f2*(($n0+$i+$j*4)/$n))); |
$SinArr=(8191*sin(2*$Pi*$f1*(($n0+$i+$j*4)/$n)) |
+8191*sin(2*$Pi*$f2*(($n0+$i+$j*4)/$n)) |
+8191*sin(2*$Pi*$f3*(($n0+$i+$j*4)/$n)) |
+8191*sin(2*$Pi*$f4*(($n0+$i+$j*4)/$n))); |
|
|
$sinv= To_Hex4(int ($SinArr)); |
|
print OutFile " sine[".($n0+$i+$j*4)."]=16'h".$sinv.";"; |
} |
print OutFile "\n"; |
} |
print "\n"; |
print OutFile " end \n\n"; |
|
##Reference table generation |
print OutFile " reg [15:0] deltas[0:".($n-1)."]; \n"; |
print OutFile " initial begin \n"; |
for $j(0..$n/4-1){ |
for $i(0..3){ |
print OutFile " deltas[".($n0+$i+$j*4)."]=16'h0000;"; |
} |
print OutFile "\n"; |
} |
##print OutFile " deltas[".$f1."]=16'h3fff; deltas[".$f2."]=16'h3fff;\n"; |
print OutFile " deltas[".$f1."]=16'h7ffc; deltas[".$f2."]=16'h7ffc; deltas[".$f3."]=16'h7ffc; deltas[".$f4."]=16'h7ffc;\n"; |
print OutFile " end \n\n"; |
|
print OutFile " assign DATA_RE=cosi[ADDR]; \n"; |
print OutFile " assign DATA_IM=sine[ADDR]; \n"; |
print OutFile " assign DATA_REF=deltas[ADDR]; \n"; |
print OutFile "endmodule \n"; |
|
close(OutFile); |
|
|
sub To_Hex2{ |
my(%Hexnumbers)= (0,0,1,1,2,2,3,3, |
4,4,5,5,6,6,7,7, |
8,8,9,9,10,'A',11,'B', |
12,'C',13,'D',14,'E',15,'F'); |
|
$_[0]=($_[0]>=0) ? $_[0] : 256+$_[0]; |
my($h21)=$_[0] % 16; |
my($h22)=int($_[0] / 16); |
return $Hexnumbers{$h22}.$Hexnumbers{$h21}; |
}; |
|
sub To_Hex4{ |
my(%Hexnumbers)= (0,0,1,1,2,2,3,3, |
4,4,5,5,6,6,7,7, |
8,8,9,9,10,'A',11,'B', |
12,'C',13,'D',14,'E',15,'F'); |
|
$_[0]=($_[0]>=0) ? $_[0] : 65536+$_[0]; |
my($h21)=$_[0] % 16; |
my($r21)=int($_[0] / 16); |
my($h22)=$r21 % 16; |
my($r22)=int($r21 / 16); |
my($h23)=$r22 % 16; |
my($h24)=int($r22 / 16); |
return $Hexnumbers{$h24}.$Hexnumbers{$h23}.$Hexnumbers{$h22}.$Hexnumbers{$h21}; |
##return $_[0]; |
}; |
|
open (File, "Wave_ROM64.v") || die "Cannot open r"; |
while ($line = <File>) |
{ |
print $line; # Ready file output to the screen |
} |
|
|
close(File); |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/BENCH/USFFT64_2B_TB.v
0,0 → 1,158
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Testbench for the UNFFT64_core - FFT 64 processor //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// FUNCTION:a set of 4 sine waves is inputted to the FFT processor, |
// the results are compared with the expected waves, |
// the square root mean error is calculated (without a root) |
// FILES: USFFT64_2B_TB.v - this file, contains |
// USFFT64_2B.v - unit under test |
// sin_tst_rom.v - rom with the test waveform, generating by |
// sinerom64_gen.pl |
// PROPERTIES: 1) the calculated error after ca. 4us modeling |
// is outputted to the console as the note: |
// rms error is 1 lsb |
// 2)if the error is 0,1,2 then the test is OK |
// 3) the customer can exchange the test selecting the |
// different frequencies and generating the wave ROM by |
// the script sinerom64_gen.pl |
// 4) the proper operation can be checked by investigation |
// of the core output waveforms |
///////////////////////////////////////////////////////////////////// |
`include "FFT64_CONFIG.inc" |
|
`timescale 1ns / 1ps |
module USFFT64_2B_tb; |
//Parameters declaration: |
//defparam UUT.nb = 12; |
`USFFT64paramnb |
|
//Internal signals declarations: |
reg CLK; |
reg RST; |
reg ED; |
reg START; |
reg [3:0]SHIFT; |
wire [nb-1:0]DR; |
wire [nb-1:0]DI; |
wire RDY; |
wire OVF1; |
wire OVF2; |
wire [5:0]ADDR; |
wire signed [nb+2:0]DOR; |
wire signed [nb+2:0]DOI; |
|
initial |
begin |
CLK = 1'b0; |
forever #5 CLK = ~CLK; |
end |
initial |
begin |
SHIFT = 4'b0000; |
ED = 1'b1; |
RST = 1'b0; |
START = 1'b0; |
#13 RST =1'b1; |
#43 RST =1'b0; |
#53 START =1'b1; |
#12 START =1'b0; |
end |
|
reg [5:0] ct64; |
always @(posedge CLK or posedge START) begin |
if (START) ct64 = 6'b000000; |
else ct64 = ct64 + 'd1; |
end |
|
wire [15:0] DATA_RE,DATA_IM,DATA_0; |
Wave_ROM64 UG( .ADDR(ct64) , |
.DATA_RE(DATA_RE), .DATA_IM(DATA_IM), .DATA_REF(DATA_0) );// |
|
assign DR=DATA_RE[15:15-nb+1]; |
assign DI=DATA_IM[15:15-nb+1]; |
|
// Unit Under Test |
USFFT64_2B UUT ( |
.CLK(CLK), |
.RST(RST), |
.ED(ED), |
.START(START), |
.SHIFT(SHIFT), |
.DR(DR), |
.DI(DI), |
.RDY(RDY), |
.OVF1(OVF1), |
.OVF2(OVF2), |
.ADDR(ADDR), |
.DOR(DOR), |
.DOI(DOI)); |
|
wire [5:0] addrr; |
`ifdef USFFT64paramifft |
assign addrr= (64-ADDR); //the result order if IFFT |
`else |
assign addrr= ADDR; |
`endif |
|
|
wire signed [15:0] DATA_R0,DATA_I0,DATA_REF; |
Wave_ROM64 UR( .ADDR(addrr) , |
.DATA_RE(DATA_R0), .DATA_IM(DATA_I0), .DATA_REF(DATA_REF) );// |
|
wire signed [18:15-nb+1] DREF=2*DATA_REF[15:15-nb+1]; |
|
integer sqra; |
integer ctres; |
reg f; |
initial f=0; |
always@(posedge CLK) begin |
if (f) |
ctres=ctres+1; |
if (RST || RDY) begin |
if (RDY) f=1; |
sqra=0; |
ctres=0; end |
else if (ctres<64) begin |
#2 sqra = sqra +(DREF-DOR)*(DREF-DOR); |
#2 sqra = sqra +(DOI)*(DOI); end |
else if (ctres==64) |
$display("rms error is ", (sqra/128), " lsb"); |
end |
|
|
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/RTL/WROM64.v
0,0 → 1,205
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Twiddle factor ROM for 64-point FFT //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// Design_Version : 1.0 |
// File name : WROM64.v |
// File Revision : |
// Last modification : Sun Sep 30 20:11:56 2007 |
///////////////////////////////////////////////////////////////////// |
// FUNCTION: 1-port synchronous RAM |
// FILES: RAM64.v -single ported synchronous RAM |
// PROPERTIES: |
//1) Has 64 complex coefficients which form a table 8x8, |
//and stay in the needed order, as they are addressed |
//by the simple counter |
//2) 16-bit values are stored. When shorter bit width is set |
//then rounding is not used |
//3) for FFT and IFFT depending on paramifft |
///////////////////////////////////////////////////////////////////// |
|
`timescale 1ps / 1ps |
`include "FFT64_CONFIG.inc" |
|
module WROM64 ( WI ,WR ,ADDR ); |
`USFFT64paramnw |
|
input [5:0] ADDR ; |
wire [5:0] ADDR ; |
|
output [nw-1:0] WI ; |
wire [nw-1:0] WI ; |
output [nw-1:0] WR ; |
wire [nw-1:0] WR ; |
|
parameter signed [15:0] c0 = 16'h7fff; |
parameter signed [15:0] s0 = 16'h0000; |
parameter signed [15:0] c1 = 16'h7f62; |
parameter signed [15:0] s1 = 16'h0c8c; |
parameter signed [15:0] c2 = 16'h7d8a; |
parameter signed [15:0] s2 = 16'h18f9 ; |
parameter signed [15:0] c3 = 16'h7a7d; |
parameter signed [15:0] s3 = 16'h2528; |
parameter signed [15:0] c4 = 16'h7642; |
parameter signed [15:0] s4 = 16'h30fc; |
parameter signed [15:0] c5 = 16'h70e3; |
parameter signed [15:0] s5 = 16'h3c57; |
parameter signed [15:0] c6 = 16'h6a6e; |
parameter signed [15:0] s6 = 16'h471d ; |
parameter signed [15:0] c7 = 16'h62f2; |
parameter signed [15:0] s7 = 16'h5134; |
parameter signed [15:0] c8 = 16'h5a82; |
|
parameter[31:0] w0= {c0,-s0}; |
parameter[31:0] w1= {c1,-s1}; |
parameter[31:0] w2= {c2,-s2}; |
parameter[31:0] w3= {c3,-s3}; |
parameter[31:0] w4= {c4,-s4}; |
parameter[31:0] w5= {c5,-s5}; |
parameter[31:0] w6= {c6,-s6}; |
parameter[31:0] w7= {c7,-s7}; |
parameter[31:0] w8= {c8,-c8}; |
parameter[31:0] w9= {s7,-c7}; |
parameter[31:0] w10= {s6,-c6}; |
parameter[31:0] w12= {s4,-c4}; |
parameter[31:0] w14= {s2,-c2}; |
parameter[31:0] w15= {s1,-c1}; |
parameter[31:0] w16= {s0,-c0}; |
parameter[31:0] w18= {-s2, -c2}; |
parameter[31:0] w20= {-s4, -c4}; |
parameter[31:0] w21= {-s5, -c5}; |
parameter[31:0] w24= {-c8, -c8}; |
parameter[31:0] w25= {-c7, -s7}; |
parameter[31:0] w28= {-c4, -s4}; |
parameter[31:0] w30= {-c2, -s2}; |
parameter[31:0] w35= {-c3, s3}; |
parameter[31:0] w36= {-c4, s4}; |
parameter[31:0] w42= {-s6, c6}; |
parameter[31:0] w49= {s1, c1}; |
|
reg [31:0] wf [0:63] ; |
integer i; |
|
always@(ADDR) begin |
//(w0, w0, w0, w0, w0, w0, w0, w0, 0..7 // twiddle factors for FFT |
// w0, w1, w2, w3, w4, w5, w6, w7, 8..15 |
// w0, w2, w4, w6, w8, w10,w12,w14, 16..23 |
// w0, w3, w6, w9, w12,w15,w18,w21, 24..31 |
// w0, w4, w8, w12,w16,w20,w24,w28, 32..47 |
// w0, w5, w10,w15,w20,w25,w30,w35, |
// w0, w6, w12,w18,w24,w30,w36,w42, |
// w0, w7, w14,w21,w28,w35,w42,w49); |
for( i =0; i<8; i=i+1) wf[i] =w0; |
for( i =8; i<63; i=i+8) wf[i] =w0; |
wf[9] =w1 ; wf[10] =w2 ; wf[11] =w3 ;wf[12] =w4 ; |
wf[13] =w5 ;wf[14] =w6 ; wf[15] =w7 ; |
wf[17] =w2 ;wf[18] =w4 ; wf[19] =w6 ;wf[20] =w8 ; |
wf[21] =w10 ;wf[22] =w12 ;wf[23] =w14; |
wf[25] =w3 ;wf[26] =w6 ; wf[27] =w9 ;wf[28] =w12 ; |
wf[29] =w15 ;wf[30] =w18 ;wf[31] =w21; |
wf[33] =w4 ;wf[34] =w8 ; wf[35] =w12 ;wf[36] =w16 ; |
wf[37] =w20 ;wf[38] =w24 ;wf[39] =w28; |
wf[41] =w5 ;wf[42] =w10 ; wf[43] =w15 ;wf[44] =w20 ; |
wf[45] =w25 ;wf[46] =w30 ;wf[47] =w35; |
wf[49] =w6 ;wf[50] =w12 ; wf[51] =w18 ;wf[52] =w24 ; |
wf[53] =w30 ;wf[54] =w36 ;wf[55] =w42; |
wf[57] =w7 ;wf[58] =w14 ; wf[59] =w21 ;wf[60] =w28 ; |
wf[61] =w35 ;wf[62] =w42 ;wf[63] =w49; |
end |
|
parameter[31:0] wi0= {c0,s0}; |
parameter[31:0] wi1= {c1,s1}; |
parameter[31:0] wi2= {c2,s2}; |
parameter[31:0] wi3= {c3,s3}; |
parameter[31:0] wi4= {c4,s4}; |
parameter[31:0] wi5= {c5,s5}; |
parameter[31:0] wi6= {c6,s6}; |
parameter[31:0] wi7= {c7,s7}; |
parameter[31:0] wi8= {c8,c8}; |
parameter[31:0] wi9= {s7,c7}; |
parameter[31:0] wi10= {s6,c6}; |
parameter[31:0] wi12= {s4,c4}; |
parameter[31:0] wi14= {s2,c2}; |
parameter[31:0] wi15= {s1,c1}; |
parameter[31:0] wi16= {s0,c0}; |
parameter[31:0] wi18= {-s2, c2}; |
parameter[31:0] wi20= {-s4, c4}; |
parameter[31:0] wi21= {-s5, c5}; |
parameter[31:0] wi24= {-c8, c8}; |
parameter[31:0] wi25= {-c7, s7}; |
parameter[31:0] wi28= {-c4, s4}; |
parameter[31:0] wi30= {-c2, s2}; |
parameter[31:0] wi35= {-c3, -s3}; |
parameter[31:0] wi36= {-c4, -s4}; |
parameter[31:0] wi42= {-s6, -c6}; |
parameter[31:0] wi49= {s1, -c1}; |
|
reg [31:0] wb [0:63] ; |
always@(ADDR) begin |
//initial begin #10; |
//(w0, w0, w0, w0, w0, w0, w0, w0, // twiddle factors for IFFT |
for( i =0; i<8; i=i+1) wb[i] =wi0; |
for( i =8; i<63; i=i+8) wb[i] =wi0; |
wb[9] =wi1 ; wb[10] =wi2 ; wb[11] =wi3 ;wb[12] =wi4 ; |
wb[13] =wi5 ;wb[14] =wi6 ; wb[15] =wi7 ; |
wb[17] =wi2 ;wb[18] =wi4 ; wb[19] =wi6 ;wb[20] =wi8 ; |
wb[21] =wi10 ;wb[22] =wi12 ;wb[23] =wi14; |
wb[25] =wi3 ;wb[26] =wi6 ; wb[27] =wi9 ;wb[28] =wi12 ; |
wb[29] =wi15 ;wb[30] =wi18 ;wb[31] =wi21; |
wb[33] =wi4 ;wb[34] =wi8 ; wb[35] =wi12 ;wb[36] =wi16 ; |
wb[37] =wi20 ;wb[38] =wi24 ;wb[39] =wi28; |
wb[41] =wi5 ;wb[42] =wi10 ; wb[43] =wi15 ;wb[44] =wi20 ; |
wb[45] =wi25 ;wb[46] =wi30 ;wb[47] =wi35; |
wb[49] =wi6 ;wb[50] =wi12 ; wb[51] =wi18 ;wb[52] =wi24 ; |
wb[53] =wi30 ;wb[54] =wi36 ;wb[55] =wi42; |
wb[57] =wi7 ;wb[58] =wi14 ; wb[59] =wi21 ;wb[60] =wi28 ; |
wb[61] =wi35 ;wb[62] =wi42 ;wb[63] =wi49; |
end |
|
wire[31:0] reim; |
|
`ifdef USFFT64paramifft |
assign reim = wb[ADDR]; |
`else |
assign reim = wf[ADDR]; |
`endif |
|
assign WR =reim[31:32-nw]; |
assign WI=reim[15 :16-nw]; |
|
|
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/RTL/cnorm.v
0,0 → 1,115
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Normalization unit //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// Design_Version : 1.0 |
// File name : CNORM.v |
// File Revision : |
// Last modification : Sun Sep 30 20:11:56 2007 |
///////////////////////////////////////////////////////////////////// |
// FUNCTION: shifting left up to 3 bits |
// PROPERTIES: 1)shifting left up to 3 bits controlled by |
// the 2-bit code SHIFT |
// 2)Is registered |
// 3)Overflow detector detects the overflow event |
// by the given shift condition. The detector is |
// zeroed by the START signal |
// 4)RDY is the START signal delayed to a single |
// clock cycle |
///////////////////////////////////////////////////////////////////// |
`timescale 1 ns / 1 ps |
`include "FFT64_CONFIG.inc" |
|
module CNORM ( CLK ,ED ,START ,DR ,DI ,SHIFT ,OVF ,RDY ,DOR ,DOI ); |
`USFFT64paramnb |
|
output OVF ; |
reg OVF ; |
output RDY ; |
reg RDY ; |
output [nb+1:0] DOR ; |
wire [nb+1:0] DOR ; |
output [nb+1:0] DOI ; |
wire [nb+1:0] DOI ; |
|
input CLK ; |
wire CLK ; |
input ED ; |
wire ED ; |
input START ; |
wire START ; |
input [nb+2:0] DR ; |
wire [nb+2:0] DR ; |
input [nb+2:0] DI ; |
wire [nb+2:0] DI ; |
input [1:0] SHIFT ; |
wire [1:0] SHIFT ; |
|
wire[nb+2:0] diri,diii; |
assign diri = DR << SHIFT; |
assign diii = DI << SHIFT; |
|
reg [nb+2:0] dir,dii; |
always @( posedge CLK ) begin |
if (ED) begin |
dir<=diri[nb+2:1]; |
dii<=diii[nb+2:1]; |
end |
end |
|
|
always @( posedge CLK ) begin |
if (ED) begin |
RDY<=START; |
if (START) |
OVF<=0; |
else |
case (SHIFT) |
2'b01 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1]); |
2'b10 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1]) || |
(DR[nb+2] != DR[nb]) || (DI[nb+2] != DI[nb]); |
2'b11 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1])|| |
(DR[nb+2] != DR[nb]) || (DI[nb+2] != DI[nb]) || |
(DR[nb+2] != DR[nb+1]) || (DI[nb-1] != DI[nb-1]); |
endcase |
end |
end |
|
assign DOR= dir; |
assign DOI= dii; |
|
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/RTL/mpu707.v
0,0 → 1,90
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Multiplier by 0.7071 //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// Design_Version : 1.0 |
// File name : MPU707.v |
// File Revision : |
// Last modification : Sun Sep 30 20:11:56 2007 |
///////////////////////////////////////////////////////////////////// |
// FUNCTION: Constant multiplier |
// PROPERTIES:1)Is based on shifts right and add |
// 2)for short input bit width 0.7071 is approximated as |
// 10110101 then rounding is not used |
// 3)for long input bit width 0.7071 is approximated as |
// 10110101000000101 |
// 4)hardware is 3 or 4 adders |
///////////////////////////////////////////////////////////////////// |
`include "FFT64_CONFIG.inc" |
|
module MPU707 ( CLK ,DO ,DI ,EI ); |
`USFFT64paramnb |
|
input CLK ; |
wire CLK ; |
input [nb+1:0] DI ; |
wire signed [nb+1:0] DI ; |
input EI ; |
wire EI ; |
|
output [nb+1:0] DO ; |
reg [nb+1:0] DO ; |
|
reg signed [nb+5 :0] dx5; |
reg signed [nb+2 : 0] dt; |
wire signed [nb+6 : 0] dx5p; |
wire signed [nb+6 : 0] dot; |
|
always @(posedge CLK) |
begin |
if (EI) begin |
dx5<=DI+(DI <<2); //multiply by 5 |
dt<=DI; |
DO<=dot >>>4; |
end |
end |
|
`ifdef USFFT64bitwidth_0707_high |
assign dot= (dx5p+(dt>>>4)+(dx5>>>12)); // multiply by 10110101000000101 |
`else |
assign dot= (dx5p+(dt>>>4) ) ; // multiply by 10110101 |
`endif |
|
assign dx5p=(dx5<<1)+(dx5>>>2); // multiply by 101101 |
|
|
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/RTL/fft64_config.inc
0,0 → 1,66
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Parameter file //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// Design_Version : 1.0 |
// File name : fft64_config.inc |
// File Revision : |
// Last modification : Sun Sep 30 20:11:56 2007 |
///////////////////////////////////////////////////////////////////// |
|
`timescale 10 ps / 1ps |
|
//input data bit width |
`define USFFT64paramnb parameter nb=16; |
|
//2-nd stage data bit width |
`define USFFT64paramnb2 parameter nb2=nb+2; |
|
//twiddle factor bit width |
`define USFFT64paramnw parameter nw=15; |
|
//when is absent then FFT, when is present then IFFT |
//`define USFFT64paramifft ; |
|
//buffer number 2 or 3 |
`define USFFT64parambuffers3 |
|
// buffer type: 1 ports in RAMS else -2 ports RAMS |
//`define USFFT64bufferports1 |
|
//Coeficient 0.707 bit width is increased |
`define USFFT64bitwidth_0707_high |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/RTL/usfft64_2b.v
0,0 → 1,180
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Top level of the high speed FFT core //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// Design_Version : 1.0 |
// File name : |
// File Revision : |
// Last modification : Sun Sep 30 20:11:56 2007 |
///////////////////////////////////////////////////////////////////// |
// FUNCTION: Structural model of the high speed 64-complex point FFT |
// PROPERTIES: |
//1.Fully pipelined, 1 complex data in, 1 complex result out each |
//clock cycle |
//2. Input data, output data, coefficient widths are adjustable |
//in range 8..16 |
//3. Normalization stages trigger the data overflow and shift |
//data right to prevent the overflow |
//4. Core can contain 2 or 3 data buffers. In the configuration of |
//2 buffers the results are in the shuffled order but provided with |
//the proper address. |
//5. The core operation can be slowed down by the control |
//of the ED input |
//6. The reset RST is synchronous |
///////////////////////////////////////////////////////////////////// |
|
`timescale 1 ns / 1 ps |
`include "FFT64_CONFIG.inc" |
|
module USFFT64_2B ( CLK ,RST ,ED ,START ,SHIFT ,DR ,DI ,RDY ,OVF1 ,OVF2 ,ADDR ,DOR ,DOI ); |
`USFFT64paramnb //nb is the data bit width |
|
output RDY ; // in the next cycle after RDY=1 the 0-th result is present |
wire RDY ; |
output OVF1 ; // 1 signals that an overflow occured in the 1-st stage |
wire OVF1 ; |
output OVF2 ; // 1 signals that an overflow occured in the 2-nd stage |
wire OVF2 ; |
output [5:0] ADDR ; //result data address/number |
wire [5:0] ADDR ; |
output [nb+2:0] DOR ;//Real part of the output data, |
wire [nb+2:0] DOR ; // the bit width is nb+3, can be decreased when instantiating the core |
output [nb+2:0] DOI ;//Imaginary part of the output data |
wire [nb+2:0] DOI ; |
|
input CLK ; //Clock signal is less than 320 MHz for the Xilinx Virtex5 FPGA |
wire CLK ; |
input RST ; //Reset signal, is the synchronous one with respect to CLK |
wire RST ; |
input ED ; //=1 enables the operation (eneabling CLK) |
wire ED ; |
input START ; // its falling edge starts the transform or the serie of transforms |
wire START ; // and resets the overflow detectors |
input [3:0] SHIFT ; // bits 1,0 -shift left code in the 1-st stage |
wire [3:0] SHIFT ; // bits 3,2 -shift left code in the 2-nd stage |
input [nb-1:0] DR ; // Real part of the input data, 0-th data goes just after |
wire [nb-1:0] DR ; // the START signal or after 63-th data of the previous transform |
input [nb-1:0] DI ; //Imaginary part of the input data |
wire [nb-1:0] DI ; |
|
wire [nb-1:0] dr1,di1; |
wire [nb+1:0] dr3,di3,dr4,di4, dr5,di5 ; |
wire [nb+2:0] dr2,di2; |
wire [nb+4:0] dr6,di6; |
wire [nb+2:0] dr7,di7,dr8,di8; |
wire rdy1,rdy2,rdy3,rdy4,rdy5,rdy6,rdy7,rdy8; |
reg [5:0] addri ; |
// input buffer =8-bit inversion ordering |
BUFRAM64C1 #(nb) U_BUF1(.CLK(CLK), .RST(RST), .ED(ED), .START(START), |
.DR(DR), .DI(DI), .RDY(rdy1), .DOR(dr1), .DOI(di1)); |
|
//1-st stage of FFT |
FFT8 #(nb) U_FFT1(.CLK(CLK), .RST(RST), .ED(ED), |
.START(rdy1),.DIR(dr1),.DII(di1), |
.RDY(rdy2), .DOR(dr2),. DOI(di2)); |
|
wire [1:0] shiftl= SHIFT[1:0]; |
CNORM #(nb) U_NORM1( .CLK(CLK), .ED(ED), //1-st normalization unit |
.START(rdy2), // overflow detector reset |
.DR(dr2), .DI(di2), |
.SHIFT(shiftl), //shift left bit number |
.OVF(OVF1), |
.RDY(rdy3), |
.DOR(dr3),.DOI(di3)); |
|
// rotator to the angles proportional to PI/32 |
ROTATOR64 U_MPU (.CLK(CLK),.RST(RST),.ED(ED), |
.START(rdy3),. DR(dr3),.DI(di3), |
.RDY(rdy4), .DOR(dr4), .DOI(di4)); |
|
BUFRAM64C1 #(nb+2) U_BUF2(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering |
.START(rdy4),. DR(dr4),.DI(di4), |
.RDY(rdy5), .DOR(dr5), .DOI(di5)); |
|
//2-nd stage of FFT |
FFT8 #(nb+2) U_FFT2(.CLK(CLK), .RST(RST), .ED(ED), |
.START(rdy5),. DIR(dr5),.DII(di5), |
.RDY(rdy6), .DOR(dr6), .DOI(di6)); |
|
wire [1:0] shifth= SHIFT[3:2]; |
//2-nd normalization unit |
CNORM #(nb+2) U_NORM2 ( .CLK(CLK), .ED(ED), |
.START(rdy6), // overflow detector reset |
.DR(dr6), .DI(di6), |
.SHIFT(shifth), //shift left bit number |
.OVF(OVF2), |
.RDY(rdy7), |
.DOR(dr7), .DOI(di7)); |
|
|
BUFRAM64C1 #(nb+3) Ubuf3(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering |
.START(rdy7),. DR(dr7),.DI(di7), |
.RDY(rdy8), .DOR(dr8), .DOI(di8)); |
|
|
|
|
`ifdef USFFT64parambuffers3 // 3-data buffer configuratiion |
always @(posedge CLK) begin //POINTER to the result samples |
if (RST) |
addri<=6'b000000; |
else if (rdy8==1 ) |
addri<=6'b000000; |
else if (ED) |
addri<=addri+1; |
end |
|
assign ADDR= addri ; |
assign DOR=dr8; |
assign DOI=di8; |
assign RDY=rdy8; |
|
`else |
always @(posedge CLK) begin //POINTER to the result samples |
if (RST) |
addri<=6'b000000; |
else if (rdy7) |
addri<=6'b000000; |
else if (ED) |
addri<=addri+1; |
end |
assign ADDR= {addri[2:0] , addri[5:3]} ; |
assign DOR= dr7; |
assign DOI= di7; |
assign RDY= rdy7; |
`endif |
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/RTL/ram2x64c_1.v
0,0 → 1,141
///////////////////////////////////////////////////////////////////// |
//// //// |
//// 2-port RAM //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// Design_Version : 1.0 |
// File name : RAM2x64C_1.v |
// File Revision : |
// Last modification : Sun Sep 30 20:11:56 2007 |
///////////////////////////////////////////////////////////////////// |
// FUNCTION: 2-port RAM with 1 port to write and 1 port to read |
// FILES: RAM2x64C_1.v - dual ported synchronous RAM, contains: |
// RAM64.v -single ported synchronous RAM |
// PROPERTIES: 1)Has the volume of 2x64 complex data |
// 2)Contains 4 single port RAMs for real and |
// imaginary parts of data in the 2-fold volume |
// Two halves of RAM are switched on and off in the |
// write mode by the signal ODD |
// 3)RAM is synchronous one, the read datum is |
// outputted in 2 cycles after the address setting |
// 4)Can be substituted to any 2-port synchronous |
// RAM for example, to one RAMB16_S36_S36 in XilinxFPGAs |
///////////////////////////////////////////////////////////////////// |
|
`timescale 1 ns / 1 ps |
`include "FFT64_CONFIG.inc" |
|
module RAM2x64C_1 ( CLK ,ED ,WE ,ODD ,ADDRW ,ADDRR ,DR ,DI ,DOR ,DOI ); |
`USFFT64paramnb |
|
|
output [nb-1:0] DOR ; |
wire [nb-1:0] DOR ; |
output [nb-1:0] DOI ; |
wire [nb-1:0] DOI ; |
input CLK ; |
wire CLK ; |
input ED ; |
wire ED ; |
input WE ; //write enable |
wire WE ; |
input ODD ; // RAM part switshing |
wire ODD ; |
input [5:0] ADDRW ; |
wire [5:0] ADDRW ; |
input [5:0] ADDRR ; |
wire [5:0] ADDRR ; |
input [nb-1:0] DR ; |
wire [nb-1:0] DR ; |
input [nb-1:0] DI ; |
wire [nb-1:0] DI ; |
|
reg oddd,odd2; |
always @( posedge CLK) begin //switch which reswiches the RAM parts |
if (ED) begin |
oddd<=ODD; |
odd2<=oddd; |
end |
end |
`ifdef USFFT64bufferports1 |
//One-port RAMs are used |
wire we0,we1; |
wire [nb-1:0] dor0,dor1,doi0,doi1; |
wire [5:0] addr0,addr1; |
|
|
|
assign addr0 =ODD? ADDRW: ADDRR; //MUXA0 |
assign addr1 = ~ODD? ADDRW:ADDRR; // MUXA1 |
assign we0 =ODD? WE: 0; // MUXW0: |
assign we1 =~ODD? WE: 0; // MUXW1: |
|
//1-st half - write when odd=1 read when odd=0 |
RAM64 #(nb) URAM0(.CLK(CLK),.ED(ED),.WE(we0), .ADDR(addr0),.DI(DR),.DO(dor0)); // |
RAM64 #(nb) URAM1(.CLK(CLK),.ED(ED),.WE(we0), .ADDR(addr0),.DI(DI),.DO(doi0)); |
|
//2-d half |
RAM64 #(nb) URAM2(.CLK(CLK),.ED(ED),.WE(we1), .ADDR(addr1),.DI(DR),.DO(dor1));// |
RAM64 #(nb) URAM3(.CLK(CLK),.ED(ED),.WE(we1), .ADDR(addr1),.DI(DI),.DO(doi1)); |
|
assign DOR=~odd2? dor0 : dor1; // MUXDR: |
assign DOI=~odd2? doi0 : doi1; // MUXDI: |
|
`else |
//Two-port RAM is used |
wire [6:0] addrr2 = {ODD,ADDRR}; |
wire [6:0] addrw2 = {~ODD,ADDRW}; |
wire [2*nb-1:0] di= {DR,DI} ; |
wire [2*nb-1:0] doi; |
|
reg [2*nb-1:0] ram [127:0]; |
reg [6:0] read_addra; |
always @(posedge CLK) begin |
if (ED) |
begin |
if (WE) |
ram[addrw2] <= di; |
read_addra <= addrr2; |
end |
end |
assign doi = ram[read_addra]; |
|
assign DOR=doi[2*nb-1:nb]; // Real read data |
assign DOI=doi[nb-1:0]; // Imaginary read data |
|
|
`endif |
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/RTL/fft8.v
0,0 → 1,352
///////////////////////////////////////////////////////////////////// |
//// //// |
//// 8-point FFT, First stage of FFT 64 processor //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// Design_Version : 1.0 |
// File name : FFT8.v |
// File Revision : |
// Last modification : Sun Sep 30 20:11:56 2007 |
///////////////////////////////////////////////////////////////////// |
// FUNCTION: 8-point FFT |
// FILES: FFT8.v - 1-st stage, contains |
// MPU707.v - multiplier to the factor 0.707. |
// PROPERTIES:1) Fully pipelined |
// 2) Each clock cycle complex datum is entered |
// and complex result is outputted |
// 3) Has 8-clock cycle period starting with the START |
// impulse and continuing forever |
// 4) rounding is not used |
// 5)Algorithm is from the book "H.J.Nussbaumer FFT and |
// convolution algorithms". |
// 6)IFFT is performed by substituting the output result |
// order to the reversed one |
// (by exchanging - to + and + to -) |
///////////////////////////////////////////////////////////////////// |
//Algorithm: |
// procedure FFT8( |
// D: in MEMOC8; -- input array |
// DO:out MEMOC8) -- output ARRAY |
// is |
// variable t1,t2,t3,t4,t5,t6,t7,t8,m0,m1,m2,m3,m4,m5,m6,m7: complex; |
// variable s1,s2,s3,s4: complex; |
// begin |
// t1:=D(0) + D(4); |
// m3:=D(0) - D(4); |
// t2:=D(6) + D(2); |
// m6:=CBASE_j*(D(6)-D(2)); |
// t3:=D(1) + D(5); |
// t4:=D(1) - D(5); |
// t5:=D(3) + D(7); |
// t6:=D(3) - D(7); |
// t8:=t5 + t3; |
// m5:=CBASE_j*(t5-t3); |
// t7:=t1 + t2; |
// m2:=t1 - t2; |
// m0:=t7 + t8; |
// m1:=t7 - t8; |
// m4:=SQRT(0.5)*(t4 - t6); |
// m7:=-CBASE_j*SQRT(0.5)*(t4 + t6); |
// s1:=m3 + m4; |
// s2:=m3 - m4; |
// s3:=m6 + m7; |
// s4:=m6 - m7; |
// DO(0):=m0; |
// DO(4):=m1; |
// DO(1):=s1 + s3; |
// DO(7):=s1 - s3; |
// DO(2):=m2 + m5; |
// DO(6):=m2 - m5; |
// DO(5):=s2 + s4; |
// DO(3):=s2 - s4; |
// end procedure; |
///////////////////////////////////////////////////////////////////// |
`timescale 1ps / 1ps |
`include "FFT64_CONFIG.inc" |
|
module FFT8 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY ); |
`USFFT64paramnb |
|
input ED ; |
wire ED ; |
input RST ; |
wire RST ; |
input CLK ; |
wire CLK ; |
input [nb-1:0] DII ; |
wire [nb-1:0] DII ; |
input START ; |
wire START ; |
input [nb-1:0] DIR ; |
wire [nb-1:0] DIR ; |
|
output [nb+2:0] DOI ; |
wire [nb+2:0] DOI ; |
output [nb+2:0] DOR ; |
wire [nb+2:0] DOR ; |
output RDY ; |
reg RDY ; |
|
reg [2:0] ct; //main phase counter |
reg [3:0] ctd; //delay counter |
|
always @( posedge CLK) begin //Control counter |
// |
if (RST) begin |
ct<=0; |
ctd<=15; |
RDY<=0; end |
else if (START) begin |
ct<=0; |
ctd<=0; |
RDY<=0; end |
else if (ED) begin |
RDY<=0; |
ct<=ct+1; |
if (ctd !=4'b1111) |
ctd<=ctd+1; |
if (ctd==12 ) |
RDY<=1; |
end |
|
end |
|
reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,di,d1i,d2i,d3i,d4i; |
always @(posedge CLK) // input register file |
begin |
if (ED) begin |
dr<=DIR; |
d1r<=dr; |
d2r<=d1r; |
d3r<=d2r; |
d4r<=d3r; |
di<=DII; |
d1i<=di; |
d2i<=d1i; |
d3i<=d2i; |
d4i<=d3i; |
end |
end |
|
reg signed [nb:0] s1r,s2r,s1d1r,s1d2r,s1d3r,s2d1r,s2d2r,s2d3r; |
reg signed [nb:0] s1i,s2i,s1d1i,s1d2i,s1d3i,s2d1i,s2d2i,s2d3i; |
always @(posedge CLK) begin // S1,S2 =t1-t6,m3 and delayed |
if (ED && ((ct==5) || (ct==6) || (ct==7) || (ct==0))) begin |
s1r<=d4r + dr ; |
s1i<=d4i + di ; |
s2r<=d4r - dr ; |
s2i<= d4i - di; |
end |
if (ED) begin |
s1d1r<=s1r; |
s1d2r<=s1d1r; |
s1d1i<=s1i; |
s1d2i<=s1d1i; |
if (ct==0 || ct==1) begin //## note for vhdl |
s1d3r<=s1d2r; |
s1d3i<=s1d2i; |
end |
if (ct==6 || ct==7 || ct==0) begin |
s2d1r<=s2r; |
s2d2r<=s2d1r; |
s2d1i<=s2i; |
s2d2i<=s2d1i; |
end |
if (ct==0) begin |
s2d3r<=s2d2r; |
s2d3i<=s2d2i; |
end |
end |
end |
|
|
reg signed [nb+1:0] s3r,s4r,s3d1r,s3d2r,s3d3r; |
reg signed [nb+1:0] s3i,s4i,s3d1i,s3d2i,s3d3i; |
always @(posedge CLK) begin //ALU S3: |
if (ED) |
case (ct) |
0: begin s3r<= s1d2r+s1r; //t7 |
s3i<= s1d2i+ s1i ;end |
1: begin s3r<= s1d3r - s1d1r; //m2 |
s3i<= s1d3i - s1d1i; end |
2: begin s3r<= s1d3r +s1r; //t8 |
s3i<= s1d3i+ s1i ; end |
3: begin s3r<= s1d3r - s1r; // |
s3i<= s1d3i - s1i ; end |
endcase |
|
if (ED) begin |
if (ct==1 || ct==2 || ct==3) begin |
s3d1r<=s3r; //t8 |
s3d1i<=s3i; |
end |
if ( ct==2 || ct==3) begin |
s3d2r<=s3d1r; //m2 |
s3d3r<=s3d2r; //t7 |
s3d2i<=s3d1i; |
s3d3i<=s3d2i; |
end |
end |
end |
|
always @ (posedge CLK) begin // S4 |
if (ED) begin |
if (ct==1) begin |
s4r<= s2d2r + s2r; |
s4i<= s2d2i + s2i; end |
else if (ct==2) begin |
s4r<=s2d2r - s2r; |
s4i<= s2d2i - s2i; |
end |
end |
end |
|
assign em = ((ct==2 || ct==3 || ct==4)&& ED); |
|
wire signed [nb+1:0] m4m7r,m4m7i; |
MPU707 #(nb) UMR( .CLK(CLK),.EI(em),.DI(s4r),.DO(m4m7r)); // UMR |
MPU707 #(nb) UMI( .CLK(CLK),.EI(em),.DI(s4i), .DO(m4m7i)); // UMR |
|
reg signed [nb+1:0] sjr,sji, m6r,m6i; |
always @ (posedge CLK) begin //multiply by J |
if (ED) begin |
case (ct) |
3: begin sjr<= s2d1i; //m6 |
sji<=0 - s2d1r; end |
4: begin sjr<= m4m7i; //m7 |
sji<=0 - m4m7r;end |
6: begin sjr<= s3i; //m5 |
sji<=0 - s3r; end |
endcase |
if (ct==4) begin |
m6r<=sjr; //m6 |
m6i<=sji; |
end |
end |
end |
|
reg signed [nb+2:0] s5r,s5d1r,s5d2r,q1r; |
reg signed [nb+2:0] s5i,s5d1i,s5d2i,q1i; |
always @ (posedge CLK) // S5: |
if (ED) |
case (ct) |
5: begin q1r<=s2d3r +m4m7r ; // S1 |
q1i<=s2d3i +m4m7i ; |
s5r<=m6r + sjr; |
s5i<=m6i + sji; end |
6: begin s5r<=m6r - sjr; |
s5i<=m6i - sji; |
s5d1r<=s5r; |
s5d1i<=s5i; end |
7: begin s5r<=s2d3r - m4m7r; |
s5i<=s2d3i - m4m7i; |
s5d1r<=s5r; |
s5d1i<=s5i; |
s5d2r<=s5d1r; |
s5d2i<=s5d1i; |
end |
endcase |
|
reg signed [nb+3:0] s6r,s6i ; |
`ifdef paramifft |
always @ (posedge CLK) begin // S6-- result adder |
if (ED) |
case (ct) |
5: begin s6r<=s3d3r +s3d1r ; // -- D0 |
s6i<=s3d3i +s3d1i ;end //-- D0 |
6: begin |
s6r<=q1r - s5r ; |
s6i<=q1i - s5i ; end |
7: begin |
s6r<=s3d2r - sjr ; |
s6i<=s3d2i - sji ; end |
0: begin |
s6r<=s5r + s5d1r ; |
s6i<= s5i +s5d1i ; end |
1:begin s6r<=s3d3r - s3d1r ; //-- D4 |
s6i<=s3d3i - s3d1i ; end |
2: begin |
s6r<= s5r - s5d1r ; // D5 |
s6i<= s5i - s5d1i ; end |
3: begin // D6 |
s6r<=s3d3r + sjr ; |
s6i<=s3d3i + sji ; |
end |
4: begin // D0 |
s6r<= q1r + s5d2r ; |
s6i<= q1i + s5d2i ; |
end |
endcase |
end |
|
`else |
always @ (posedge CLK) begin // S6-- result adder |
if (ED) |
case (ct) |
5: begin s6r<=s3d3r +s3d1r ; // -- D0 |
s6i<=s3d3i +s3d1i ;end //-- D0 |
6: begin |
s6r<=q1r + s5r ; //-- D1 |
s6i<=q1i + s5i ; end |
7: begin |
s6r<=s3d2r +sjr ; //-- D2 |
s6i<=s3d2i +sji ; end |
0: begin |
s6r<=s5r - s5d1r ; // -- D3 |
s6i<= s5i - s5d1i ;end |
|
1:begin s6r<=s3d3r - s3d1r ; //-- D4 |
s6i<=s3d3i - s3d1i ; end |
2: begin |
s6r<=s5r + s5d1r ; //-- D5 |
s6i<=s5i + s5d1i ; end |
|
3: begin |
s6r<= s3d3r - sjr ; // D6 |
s6i<=s3d3i - sji ; end |
|
4: begin |
s6r<= q1r - s5d2r ; // D0 |
s6i<= q1i - s5d2i ; end |
|
endcase |
end |
`endif |
|
assign #1 DOR=s6r[nb+2:0]; |
assign #1 DOI= s6i[nb+2:0]; |
|
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/RTL/ram64.v
0,0 → 1,81
///////////////////////////////////////////////////////////////////// |
//// //// |
//// 1-port synchronous RAM //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// Design_Version : 1.0 |
// File name : RAM64.v |
// File Revision : |
// Last modification : Sun Sep 30 20:11:56 2007 |
///////////////////////////////////////////////////////////////////// |
// FUNCTION: 1-port synchronous RAM |
// FILES: RAM64.v -single ported synchronous RAM |
// PROPERTIES: 1) Has the volume of 64 data |
// 2) RAM is synchronous one, the read datum is outputted |
// in 2 cycles after the address setting |
// 3) Can be substituted to any 2-port synchronous RAM |
///////////////////////////////////////////////////////////////////// |
|
`timescale 1 ns / 1 ps |
`include "FFT64_CONFIG.inc" |
|
module RAM64 ( CLK, ED,WE ,ADDR ,DI ,DO ); |
`USFFT64paramnb |
|
output [nb-1:0] DO ; |
reg [nb-1:0] DO ; |
input CLK ; |
wire CLK ; |
input ED; |
input WE ; |
wire WE ; |
input [5:0] ADDR ; |
wire [5:0] ADDR ; |
input [nb-1:0] DI ; |
wire [nb-1:0] DI ; |
reg [nb-1:0] mem [63:0]; |
reg [5:0] addrrd; |
|
always @(posedge CLK) begin |
if (ED) begin |
if (WE) mem[ADDR] <= DI; |
addrrd <= ADDR; //storing the address |
DO <= mem[addrrd]; // registering the read datum |
end |
end |
|
|
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/RTL/rotator64_v.v
0,0 → 1,130
///////////////////////////////////////////////////////////////////// |
//// //// |
//// rotating unit, stays between 2 stages of FFT pipeline //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// Design_Version : 1.0 |
// File name : |
// File Revision : |
// Last modification : Sun Sep 30 20:11:56 2007 |
///////////////////////////////////////////////////////////////////// |
// FUNCTION: complex multiplication to the twiddle factors proper to the 64 point FFT |
// PROPERTIES: 1) Has 64-clock cycle period starting with the START impulse and continuing forever |
// 2) rounding is not used |
///////////////////////////////////////////////////////////////////// |
|
`timescale 1ps / 1ps |
`include "FFT64_CONFIG.inc" |
|
module ROTATOR64 (CLK ,RST,ED,START, DR,DI, DOR, DOI,RDY ); |
`USFFT64paramnb |
`USFFT64paramnw |
|
input RST ; |
wire RST ; |
input CLK ; |
wire CLK ; |
input ED ; //operation enable |
input [nb+1:0] DI; //Imaginary part of data |
wire [nb+1:0] DI ; |
input [nb+1:0] DR ; //Real part of data |
input START ; //1-st Data is entered after this impulse |
wire START ; |
|
output [nb+1:0] DOI ; //Imaginary part of data |
wire [nb+1:0] DOI ; |
output [nb+1:0] DOR ; //Real part of data |
wire [nb+1:0] DOR ; |
output RDY ; //repeats START impulse following the output data |
reg RDY ; |
|
|
reg [5:0] addrw; |
reg sd1,sd2; |
always @( posedge CLK) //address counter for twiddle factors |
begin |
if (RST) begin |
addrw<=0; |
sd1<=0; |
sd2<=0; |
end |
else if (START && ED) begin |
addrw[5:0]<=0; |
sd1<=START; |
sd2<=0; |
end |
else if (ED) begin |
addrw<=addrw+1; |
sd1<=START; |
sd2<=sd1; |
RDY<=sd2; |
end |
end |
|
wire signed [nw-1:0] wr,wi; //twiddle factor coefficients |
//twiddle factor ROM |
WROM64 UROM( .ADDR(addrw), .WR(wr),.WI(wi) ); |
|
|
reg signed [nb+1 : 0] drd,did; |
reg signed [nw-1 : 0] wrd,wid; |
wire signed [nw+nb+1 : 0] drri,drii,diri,diii; |
reg signed [nb+2:0] drr,dri,dir,dii,dwr,dwi; |
|
assign drri=drd*wrd; |
assign diri=did*wrd; |
assign drii=drd*wid; |
assign diii=did*wid; |
|
always @(posedge CLK) //complex multiplier |
begin |
if (ED) begin |
drd<=DR; |
did<=DI; |
wrd<=wr; |
wid<=wi; |
drr<=drri[nw+nb+1 :nw-1]; //msbs of multiplications are stored |
dri<=drii[nw+nb+1 : nw-1]; |
dir<=diri[nw+nb+1 : nw-1]; |
dii<=diii[nw+nb+1 : nw-1]; |
dwr<=drr - dii; |
dwi<=dri + dir; |
end |
end |
assign DOR=dwr[nb+2:1]; |
assign DOI=dwi[nb+2 :1]; |
|
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/RTL/bufram64c1.v
0,0 → 1,117
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Storage Buffer //// |
//// //// |
//// Authors: Anatoliy Sergienko, Volodya Lepeha //// |
//// Company: Unicore Systems http://unicore.co.ua //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2006-2010 Unicore Systems LTD //// |
//// www.unicore.co.ua //// |
//// o.uzenkov@unicore.co.ua //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED "AS IS" //// |
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// |
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// |
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// |
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// |
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// |
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// |
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// |
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// |
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// |
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// |
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// |
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// |
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
// Design_Version : 1.0 |
// File name : BUFRAM64C1.v |
// File Revision : |
// Last modification : Sun Sep 30 20:11:56 2007 |
///////////////////////////////////////////////////////////////////// |
// FUNCTION: FIFO - buffer with direct input order and 8-th inverse |
// output order |
// FILES: BUFRAM64C1.v - 1-st,2-nd,3-d data buffer, contains: |
// RAM2x64C_1.v - dual ported synchronous RAM, contains: |
// RAM64.v -single ported synchronous RAM |
// PROPERTIES: 1)Has the volume of 2x64 complex data |
// 2)Contains 2- port RAM and address counter |
// 3)Has 64-clock cycle period starting with the START |
// impulse and continuing forever |
// 4)Signal RDY precedes the 1-st correct datum output |
// from the buffer |
///////////////////////////////////////////////////////////////////// |
`timescale 1 ns / 1 ps |
`include "FFT64_CONFIG.inc" |
|
module BUFRAM64C1 ( CLK ,RST ,ED ,START ,DR ,DI ,RDY ,DOR ,DOI ); |
`USFFT64paramnb |
output RDY ; |
reg RDY ; |
output [nb-1:0] DOR ; |
wire [nb-1:0] DOR ; |
output [nb-1:0] DOI ; |
wire [nb-1:0] DOI ; |
|
input CLK ; |
wire CLK ; |
input RST ; |
wire RST ; |
input ED ; |
wire ED ; |
input START ; |
wire START ; |
input [nb-1:0] DR ; |
wire [nb-1:0] DR ; |
input [nb-1:0] DI ; |
wire [nb-1:0] DI ; |
|
wire odd, we; |
wire [5:0] addrw,addrr; |
reg [6:0] addr; |
reg [7:0] ct2; //counter for the RDY signal |
|
always @(posedge CLK) // CTADDR |
begin |
if (RST) begin |
addr<=6'b000000; |
ct2<= 7'b1000001; |
RDY<=1'b0; end |
else if (START) begin |
addr<=6'b000000; |
ct2<= 6'b000000; |
RDY<=1'b0;end |
else if (ED) begin |
RDY<=1'b0; |
addr<=addr+1; |
if (ct2!=65) |
ct2<=ct2+1; |
if (ct2==64) |
RDY<=1'b1; |
end |
end |
|
|
assign addrw= addr[5:0]; |
assign odd=addr[6]; // signal which switches the 2 parts of the buffer |
assign addrr={addr[2 : 0], addr[5 : 3]}; // 8-th inverse output address |
assign we = ED; |
|
RAM2x64C_1 #(nb) URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd), |
.ADDRW(addrw), .ADDRR(addrr), |
.DR(DR),.DI(DI), |
.DOR(DOR), .DOI(DOI)); |
|
endmodule |
/implementaciones/fft/pkg/pipelined_fft_64/trunk/DOC/fft64_um.pdf
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implementaciones/fft/pkg/pipelined_fft_64/trunk/DOC/fft64_um.pdf
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Index: implementaciones/fft/pkg/cfft/trunk/imp/cfft1024X12.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/imp/cfft1024X12.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/imp/cfft1024X12.vhd (revision 396)
@@ -0,0 +1,130 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : cfft1024X12
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : cfft1024X12.vhd
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description :This is a sample implementation of cfft
+--
+-- radix 4 1024 point FFT input 12 bit Output 14 bit with
+-- limit and overfall processing internal
+--
+-- The gain is 0.0287 for FFT and 29.4 for IFFT
+--
+-- The output is 4-based reversed ordered, it means
+-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
+--
+--
+---------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+--
+-- port :
+-- clk : main clk -- I have test 90M with Xilinx virtex600E
+-- rst : globe reset -- '1' for reset
+-- start : start fft -- one clock '1' before data input
+-- invert : '0' for fft and '1' for ifft, it is sampled when start is '1'
+-- Iin,Qin : data input-- following start immediately, input data
+-- -- power should not be too big
+-- inputbusy : if it change to '0' then next fft is enable
+-- outdataen : when it is '1', the valid data is output
+-- Iout,Qout : fft data output when outdataen is '1'
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 31 2002
+-- Modifier : ZHAO Ming
+-- Desccription : initial release
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.0
+-- Date : Nov 19 2002
+-- Modifier : ZHAO Ming
+-- Desccription : add output data position indication
+--
+--
+---------------------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity cfft1024X12 is
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ invert : in std_logic;
+ Iin : in STD_LOGIC_VECTOR(11 downto 0);
+ Qin : in STD_LOGIC_VECTOR(11 downto 0);
+ inputbusy : out STD_LOGIC;
+ outdataen : out STD_LOGIC;
+ Iout : out STD_LOGIC_VECTOR(13 downto 0);
+ Qout : out STD_LOGIC_VECTOR(13 downto 0);
+ OutPosition : out STD_LOGIC_VECTOR( 9 downto 0 )
+ );
+end cfft1024X12;
+
+
+architecture imp of cfft1024X12 is
+
+component cfft
+ generic (
+ WIDTH : Natural;
+ POINT : Natural;
+ STAGE : Natural -- STAGE=log4(POINT)
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ invert : in std_logic;
+ Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ inputbusy : out STD_LOGIC;
+ outdataen : out STD_LOGIC;
+ Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
+ Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
+ OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )
+ );
+end component;
+
+begin
+
+aCfft:cfft
+generic map (
+ WIDTH=>12,
+ POINT=>1024,
+ STAGE=>5
+)
+port map (
+ clk=>clk,
+ rst=>rst,
+ start=>start,
+ invert=>invert,
+ Iin=>Iin,
+ Qin=>Qin,
+ inputbusy=>inputbusy,
+ outdataen=>outdataen,
+ Iout=>Iout,
+ Qout=>Qout,
+ OutPosition=>OutPosition
+
+);
+
+
+end imp;
Index: implementaciones/fft/pkg/cfft/trunk/cfft.doc
===================================================================
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Index: implementaciones/fft/pkg/cfft/trunk/cfft.doc
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/cfft.doc (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/cfft.doc (revision 396)
implementaciones/fft/pkg/cfft/trunk/cfft.doc
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: implementaciones/fft/pkg/cfft/trunk/src/rofactor.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/src/rofactor.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/src/rofactor.vhd (revision 396)
@@ -0,0 +1,119 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : rofactor
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : rofactor.vhd
+-- Generated : Thu Oct 3 00:12:16 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Generate FFT rotation factor
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.0
+-- Date : Oct 18 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_signed.all;
+
+entity rofactor is
+ generic (
+ POINT : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ invert : in std_logic;
+-- step : in STD_LOGIC_VECTOR(2 downto 0);
+ angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
+ );
+end rofactor;
+
+
+architecture rofactor of rofactor is
+signal counter : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
+signal inc,iinc,phase : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
+signal mask : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
+begin
+angle<=phase;
+
+count:process( clk,rst )
+begin
+ if rst='1' then
+ counter<=( others=>'0' );
+ inc<=( others=>'0' );
+ mask<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ if start='1' then
+ counter<=( others=>'0' );
+ mask<=( others=>'0' );
+-- state<="000";
+ if invert='1' then
+ inc<=CONV_STD_LOGIC_VECTOR(1,STAGE*2);
+ else
+ inc<=CONV_STD_LOGIC_VECTOR(-1,STAGE*2);
+ end if;
+ else
+ counter<=unsigned(counter)+1;
+ if signed(counter)=-1 then
+ inc<=inc(STAGE*2-3 downto 0 )&"00";
+ mask<="11"&mask( STAGE*2-1 downto 2 );
+-- if state/="100" then
+-- state<=state+1;
+-- end if;
+ end if;
+ end if;
+ end if;
+end process count;
+
+output : process( clk, rst )
+begin
+ if rst='1' then
+ phase<=( others=>'0' );
+ iinc<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ if start='1' then
+ iinc<=( others=>'0' );
+ phase<=( others=>'0' );
+ else
+ if unsigned(counter( 1 downto 0 ))=3 then
+ phase<=( others=>'0' );
+ else
+ phase<=unsigned(phase)+unsigned(iinc);
+ end if;
+ if signed(counter or mask)=-1 then
+ iinc<=(others=>'0');
+ elsif unsigned(counter( 1 downto 0 ))=3 then
+ iinc<=unsigned(iinc)+unsigned(inc);
+ end if;
+ end if;
+ end if;
+end process output;
+end rofactor;
Index: implementaciones/fft/pkg/cfft/trunk/src/cfft.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/src/cfft.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/src/cfft.vhd (revision 396)
@@ -0,0 +1,348 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : cfft
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : cfft.vhd
+-- Generated : Thu Oct 3 03:03:58 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : radix 4 1024 point FFT input 12 bit Output 14 bit with
+-- limit and overfall processing internal
+--
+-- The gain is 0.0287 for FFT and 29.4 for IFFT
+--
+-- The output is 4-based reversed ordered, it means
+-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
+--
+--
+---------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+--
+-- port :
+-- clk : main clk -- I have test 90M with Xilinx virtex600E
+-- rst : globe reset -- '1' for reset
+-- start : start fft -- one clock '1' before data input
+-- invert : '0' for fft and '1' for ifft, it is sampled when start is '1'
+-- Iin,Qin : data input-- following start immediately, input data
+-- -- power should not be too big
+-- inputbusy : if it change to '0' then next fft is enable
+-- outdataen : when it is '1', the valid data is output
+-- Iout,Qout : fft data output when outdataen is '1'
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.0
+-- Date : Oct 18 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Point configurable
+-- FFT Gain IFFT GAIN
+-- 256 0.0698 17.9
+-- 1024 0.0287 29.4
+-- 4096 0.0118 48.2742
+--
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 3
+-- Version : 1.3.0
+-- Date : Nov 19 2002
+-- Modifier : ZHAO Ming
+-- Desccription : add output data position indication
+--
+--
+---------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+entity cfft is
+ generic (
+ WIDTH : Natural;
+ POINT : Natural;
+ STAGE : Natural -- STAGE=log4(POINT)
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ invert : in std_logic;
+ Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ inputbusy : out STD_LOGIC;
+ outdataen : out STD_LOGIC;
+ Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
+ Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
+ OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )
+ );
+end cfft;
+
+
+architecture cfft of cfft is
+
+component address
+ generic (
+ WIDTH : Natural;
+ POINT : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ Iin : in std_logic_vector( WIDTH-1 downto 0 );
+ Qin : in std_logic_vector( WIDTH-1 downto 0 );
+ fftI : in std_logic_vector( WIDTH-1 downto 0 );
+ fftQ : in std_logic_vector( WIDTH-1 downto 0 );
+ wdataI : out std_logic_vector( WIDTH-1 downto 0 );
+ wdataQ : out std_logic_vector( WIDTH-1 downto 0 );
+ raddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
+ waddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
+ wen : out std_logic;
+ factorstart : out STD_LOGIC;
+ cfft4start : out STD_LOGIC;
+ outdataen : out std_logic;
+ inputbusy : out std_logic;
+ OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )
+ );
+end component;
+
+component blockdram
+generic(
+ depth: integer;
+ Dwidth: integer;
+ Awidth: integer
+);
+port(
+ addra: IN std_logic_VECTOR(Awidth-1 downto 0);
+ clka: IN std_logic;
+ addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
+ clkb: IN std_logic;
+ dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
+ wea: IN std_logic;
+ dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
+end component;
+
+component cfft4
+ generic (
+ WIDTH : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ invert : in std_logic;
+ I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
+ Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
+ );
+end component;
+
+component div4limit
+ generic (
+ WIDTH : Natural
+ );
+ port(
+ clk : in std_logic;
+ D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
+ Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+ );
+end component;
+
+component mulfactor
+ generic (
+ WIDTH : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ angle : in signed(2*STAGE-1 downto 0);
+ I : in signed(WIDTH+1 downto 0);
+ Q : in signed(WIDTH+1 downto 0);
+ Iout : out signed(WIDTH+3 downto 0);
+ Qout : out signed(WIDTH+3 downto 0)
+ );
+end component;
+
+component rofactor
+ generic (
+ POINT : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ invert : in std_logic;
+ angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
+ );
+end component;
+signal wea,cfft4start,factorstart:std_logic:='0';
+signal wdataI,wdataQ,fftI,fftQ,Iramout,Qramout:std_logic_vector(WIDTH-1 downto 0):=(others=>'0');
+signal waddr,raddr:std_logic_vector( 2*STAGE-1 downto 0):=(others=>'0');
+signal Icfft4out,Qcfft4out:std_logic_vector( WIDTH+1 downto 0):=(others=>'0');
+signal angle:std_logic_vector( 2*STAGE-1 downto 0 ):=( others=>'0');
+signal Imulout,Qmulout:signed( WIDTH+3 downto 0):=(others=>'0');
+signal inv_reg:std_logic:='0';
+
+begin
+
+Aaddress:address
+generic map (
+ WIDTH=>WIDTH,
+ POINT=>POINT,
+ STAGE=>STAGE
+)
+port map (
+ clk=>clk,
+ rst=>rst,
+ start=>start,
+ Iin=>Iin,
+ Qin=>Qin,
+ fftI=>fftI,
+ fftQ=>fftQ,
+ wdataI=>wdataI,
+ wdataQ=>wdataQ,
+ raddr=>raddr,
+ waddr=>waddr,
+ wen=>wea,
+ factorstart=>factorstart,
+ cfft4start=>cfft4start,
+ outdataen=>outdataen,
+ inputbusy=>inputbusy,
+ OutPosition=>OutPosition
+ );
+
+Iram:blockdram
+generic map (
+ depth=>POINT,
+ Dwidth=>WIDTH,
+ Awidth=>2*STAGE
+)
+port map (
+ addra=>waddr,
+ clka=>clk,
+ addrb=>raddr,
+ clkb=>clk,
+ dia=>wdataI,
+ wea=>wea,
+ dob=>Iramout
+);
+
+Qram:blockdram
+generic map (
+ depth=>POINT,
+ Dwidth=>WIDTH,
+ Awidth=>2*STAGE
+)
+port map (
+ addra=>waddr,
+ clka=>clk,
+ addrb=>raddr,
+ clkb=>clk,
+ dia=>wdataQ,
+ wea=>wea,
+ dob=>Qramout
+);
+
+acfft4:cfft4
+generic map (
+ WIDTH=>WIDTH
+)
+port map (
+ clk=>clk,
+ rst=>rst,
+ start=>cfft4start,
+ invert=>inv_reg,
+ I=>Iramout,
+ Q=>Qramout,
+ Iout=>Icfft4out,
+ Qout=>Qcfft4out
+ );
+
+Iout<=Icfft4out;
+Qout<=Qcfft4out;
+
+Ilimit:div4limit
+generic map (
+ WIDTH=>WIDTH
+)
+port map (
+ clk=>clk,
+ D=>std_logic_vector(Imulout),
+ Q=>fftI
+ );
+Qlimit:div4limit
+generic map (
+ WIDTH=>WIDTH
+)
+port map (
+ clk=>clk,
+ D=>std_logic_vector(Qmulout),
+ Q=>fftQ
+ );
+
+amulfactor:mulfactor
+generic map (
+ WIDTH=>WIDTH,
+ STAGE=>STAGE
+)
+port map (
+ clk=>clk,
+ rst=>rst,
+ angle=>signed(angle),
+ I=>signed(Icfft4out),
+ Q=>signed(Qcfft4out),
+ Iout=>Imulout,
+ Qout=>Qmulout
+ );
+
+arofactor:rofactor
+generic map (
+ POINT=>POINT,
+ STAGE=>STAGE
+)
+port map (
+ clk=>clk,
+ rst=>rst,
+ start=>factorstart,
+ invert=>inv_reg,
+ angle=>angle
+ );
+
+process( clk, rst )
+begin
+ if rst='1' then
+ inv_reg<='0';
+ elsif clk'event and clk='1' then
+ if start='1' then
+ inv_reg<=invert;
+ end if;
+ end if;
+end process;
+
+
+
+end cfft;
Index: implementaciones/fft/pkg/cfft/trunk/src/p2r_CordicPipe.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/src/p2r_CordicPipe.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/src/p2r_CordicPipe.vhd (revision 396)
@@ -0,0 +1,170 @@
+--
+-- file: p2r_CordicPipe.vhd
+-- author: Richard Herveille
+-- rev. 1.0 initial release
+--
+
+--
+-- This file is come from WWW.OPENCORES.ORG
+
+---------------------------------------------------------------------------------------------------
+--
+-- Title : p2r_CordicPipe
+-- Design : cfft
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : p2r_CordicPipe.vhd
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Cordic arith pilepline
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity p2r_CordicPipe is
+ generic(
+ WIDTH : natural := 16;
+ PIPEID : natural := 1
+ );
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+
+ Xi : in signed(WIDTH -1 downto 0);
+ Yi : in signed(WIDTH -1 downto 0);
+ Zi : in signed(19 downto 0);
+
+ Xo : out signed(WIDTH -1 downto 0);
+ Yo : out signed(WIDTH -1 downto 0);
+ Zo : out signed(19 downto 0)
+ );
+end entity p2r_CordicPipe;
+
+architecture dataflow of p2r_CordicPipe is
+
+ --
+ -- functions
+ --
+
+ -- Function CATAN (constante arc-tangent).
+ -- This is a lookup table containing pre-calculated arc-tangents.
+ -- 'n' is the number of the pipe, returned is a 20bit arc-tangent value.
+ -- The numbers are calculated as follows: Z(n) = atan(1/2^n)
+ -- examples:
+ -- 20bit values => 2^20 = 2pi(rad)
+ -- 1(rad) = 2^20/2pi = 166886.053....
+ -- n:0, atan(1/1) = 0.7853...(rad)
+ -- 0.7853... * 166886.053... = 131072(dec) = 20000(hex)
+ -- n:1, atan(1/2) = 0.4636...(rad)
+ -- 0.4636... * 166886.053... = 77376.32(dec) = 12E40(hex)
+ -- n:2, atan(1/4) = 0.2449...(rad)
+ -- 0.2449... * 166886.053... = 40883.52(dec) = 9FB3(hex)
+ -- n:3, atan(1/8) = 0.1243...(rad)
+ -- 0.1243... * 166886.053... = 20753.11(dec) = 5111(hex)
+ --
+ function CATAN(n :natural) return integer is
+ variable result :integer;
+ begin
+ case n is
+ when 0 => result := 16#020000#;
+ when 1 => result := 16#012E40#;
+ when 2 => result := 16#09FB4#;
+ when 3 => result := 16#05111#;
+ when 4 => result := 16#028B1#;
+ when 5 => result := 16#0145D#;
+ when 6 => result := 16#0A2F#;
+ when 7 => result := 16#0518#;
+ when 8 => result := 16#028C#;
+ when 9 => result := 16#0146#;
+ when 10 => result := 16#0A3#;
+ when 11 => result := 16#051#;
+ when 12 => result := 16#029#;
+ when 13 => result := 16#014#;
+ when 14 => result := 16#0A#;
+ when 15 => result := 16#05#;
+ when 16 => result := 16#03#;
+ when 17 => result := 16#01#;
+ when others => result := 16#0#;
+ end case;
+ return result;
+ end CATAN;
+
+ -- function Delta is actually an arithmatic shift right
+ -- This strange construction is needed for compatibility with Xilinx WebPack
+ function Delta(Arg : signed; Cnt : natural) return signed is
+ variable tmp : signed(Arg'range);
+ constant lo : integer := Arg'high -cnt +1;
+ begin
+ for n in Arg'high downto lo loop
+ tmp(n) := Arg(Arg'high);
+ end loop;
+ for n in Arg'high -cnt downto 0 loop
+ tmp(n) := Arg(n +cnt);
+ end loop;
+ return tmp;
+ end function Delta;
+
+ function AddSub(dataa, datab : in signed; add_sub : in std_logic) return signed is
+ begin
+ if (add_sub = '1') then
+ return dataa + datab;
+ else
+ return dataa - datab;
+ end if;
+ end;
+
+ --
+ -- ARCHITECTURE BODY
+ --
+ signal dX, Xresult : signed(WIDTH -1 downto 0);
+ signal dY, Yresult : signed(WIDTH -1 downto 0);
+ signal atan, Zresult : signed(19 downto 0);
+
+ signal Zneg, Zpos : std_logic;
+
+begin
+
+ dX <= Delta(Xi, PIPEID);
+ dY <= Delta(Yi, PIPEID);
+ atan <= conv_signed( catan(PIPEID), 20);
+
+ -- generate adder structures
+ Zneg <= Zi(19);
+ Zpos <= not Zi(19);
+
+ -- xadd
+ Xresult <= AddSub(Xi, dY, Zneg);
+
+ -- yadd
+ Yresult <= AddSub(Yi, dX, Zpos);
+
+ -- zadd
+ Zresult <= AddSub(Zi, atan, Zneg);
+
+ gen_regs: process(clk)
+ begin
+ if(clk'event and clk='1') then
+ if (ena = '1') then
+ Xo <= Xresult;
+ Yo <= Yresult;
+ Zo <= Zresult;
+ end if;
+ end if;
+ end process;
+
+end architecture dataflow;
Index: implementaciones/fft/pkg/cfft/trunk/src/div4limit.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/src/div4limit.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/src/div4limit.vhd (revision 396)
@@ -0,0 +1,63 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : div4limit
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : div4limit.vhd
+-- Generated : Tue Jul 16 10:39:17 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Div 4 Limit to 12 bit
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity div4limit is
+ generic (
+ WIDTH : Natural
+ );
+ port(
+ clk : in std_logic;
+ D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
+ Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+ );
+end div4limit;
+
+architecture div4limit of div4limit is
+begin
+
+process( clk )
+variable Temp_D:std_logic_vector( WIDTH+1 downto 0 );
+begin
+ if clk'event and clk='1' then
+ Temp_D:=D( WIDTH+3 downto 2 )+D(1);
+ if Temp_D(WIDTH+1)='1' and Temp_D(WIDTH downto WIDTH-1)/="11" then
+ Temp_D(WIDTH+1 downto WIDTH-1):="111";
+ Temp_D(WIDTH-2 downto 1):=( others=>'0' );
+ Temp_D(0):='1';
+ elsif Temp_D(WIDTH+1)='0' and Temp_D(WIDTH downto WIDTH-1)/="00" then
+ Temp_D(WIDTH+1 downto WIDTH-1):="000";
+ Temp_D(WIDTH-2 downto 0):=( others=>'1' );
+ end if;
+ Q<=Temp_D(WIDTH-1 downto 0 );
+ end if;
+end process;
+
+end div4limit;
Index: implementaciones/fft/pkg/cfft/trunk/src/address.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/src/address.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/src/address.vhd (revision 396)
@@ -0,0 +1,326 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : address
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : address.vhd
+-- Generated : Thu Oct 3 01:44:47 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Generate RAM read write address and start finish control signal
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.0
+-- Date : Oct 18 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 1
+-- Revision Number : 2
+-- Version : 1.2.1
+-- Date : Oct 19 2002
+-- Modifier : ZHAO Ming
+-- Desccription : modified fuction counter2address for syn
+-- add rmask1,rmask2,wmask1,wmask2 signal
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 3
+-- Version : 1.3.0
+-- Date : Nov 19 2002
+-- Modifier : ZHAO Ming
+-- Desccription : add output data position indication
+--
+--
+---------------------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_signed.all;
+
+entity address is
+ generic (
+ WIDTH : Natural;
+ POINT : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ Iin : in std_logic_vector( WIDTH-1 downto 0 );
+ Qin : in std_logic_vector( WIDTH-1 downto 0 );
+ fftI : in std_logic_vector( WIDTH-1 downto 0 );
+ fftQ : in std_logic_vector( WIDTH-1 downto 0 );
+ wdataI : out std_logic_vector( WIDTH-1 downto 0 );
+ wdataQ : out std_logic_vector( WIDTH-1 downto 0 );
+ raddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);
+ waddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);
+ wen : out std_logic;
+ factorstart : out STD_LOGIC;
+ cfft4start : out STD_LOGIC;
+ outdataen : out std_logic;
+ inputbusy : out std_logic;
+ OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )
+ );
+end address;
+
+
+architecture address of address is
+
+
+-- function counter2addr(counter : std_logic_vector; state:std_logic_vector) return std_logic_vector is
+-- variable result :std_logic_vector(counter'range);
+-- variable istate : Natural;
+-- begin
+-- istate:=CONV_INTEGER(unsigned(state));
+-- if istate=0 then
+-- result := counter( 1 downto 0 )&counter( counter'high downto 2 );
+-- elsif istate=(counter'high-1)/2 then
+-- result := counter;
+-- elsif istate<(counter'high-1)/2 then
+-- result := counter( counter'high downto counter'high-istate*2+1 )&counter( 1 downto 0 )&counter( counter'high-istate*2 downto 2 );
+-- else
+-- result := counter;
+-- end if;
+-- return result;
+-- end counter2addr;
+
+ function counter2addr(
+ counter : std_logic_vector;
+ mask1:std_logic_vector;
+ mask2:std_logic_vector
+ ) return std_logic_vector is
+ variable result :std_logic_vector(counter'range);
+ begin
+ for n in mask1'range loop
+ if mask1(n)='1' then
+ result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
+ elsif mask2(n)='1' and n/=STAGE-1 then
+ result( 2*n+1 downto 2*n ):=counter( 2*n+3 downto 2*n+2 );
+ else
+ result( 2*n+1 downto 2*n ):=counter( 2*n+1 downto 2*n );
+ end if;
+ end loop;
+ return result;
+ end counter2addr;
+
+ function outcounter2addr(
+ counter : std_logic_vector
+ ) return std_logic_vector is
+ variable result :std_logic_vector(counter'range);
+ begin
+ for n in 0 to STAGE-1 loop
+ result( 2*n+1 downto 2*n ):=counter( counter'high-2*n downto counter'high-2*n-1 );
+ end loop;
+ return result;
+ end outcounter2addr;
+
+signal rstate,wstate,state:std_logic_vector( 3 downto 0 );
+signal rmask1,rmask2,wmask1,wmask2:std_logic_vector( STAGE-1 downto 0 );
+signal counter,wcounter,rcounter:std_logic_vector( STAGE*2-1 downto 0 );
+signal outcounter:std_logic_vector( STAGE*2 downto 0 );
+
+constant FFTDELAY:integer:=12+2*STAGE;
+constant FACTORDELAY:integer:=6;
+constant OUTDELAY:integer:=7;
+
+
+
+begin
+outdataen<=outcounter(STAGE*2);
+OutPosition<=outcounter2addr( outcounter( STAGE*2-1 downto 0 ));
+count:process( clk, rst )
+begin
+ if rst='1' then
+ counter<=( others=>'0' );
+ state<=CONV_STD_LOGIC_VECTOR( STAGE+1,4);
+ elsif clk'event and clk='1' then
+ if start='1' then
+ counter<=( others=>'0' );
+ state<=(others=>'0');
+ elsif unsigned(state)/=STAGE+1 then
+ counter<=unsigned(counter)+1;
+ if signed(counter)=-1 then
+ state<=unsigned(state)+1;
+ end if;
+ end if;
+ end if;
+end process count;
+
+readaddr:process( clk,rst )
+begin
+ if rst='1' then
+ raddr<=( others=>'0' );
+ rcounter<=( others=>'0' );
+ rstate<=( others=>'0' );
+ rmask1<=( others=>'0' );
+ rmask2<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ if unsigned(state)=0 and signed(counter)=-1 then
+ rmask1(STAGE-1)<='1';
+ rmask1(STAGE-2 downto 0)<=(others=>'0');
+ rmask2(STAGE-1)<='0';
+ rmask2(STAGE-2 downto 0)<=(others=>'1');
+ elsif signed(counter)=-1 then
+ rmask1<='0'&rmask1( STAGE-1 downto 1 );
+ rmask2<='0'&rmask2( STAGE-1 downto 1 );
+ end if;
+ if unsigned(state)/=STAGE+1 and signed(counter)=-1 then
+ rcounter<=( others=>'0' );
+ rstate<=state;
+ else
+ rcounter<=unsigned(rcounter)+1;
+ end if;
+ raddr<=counter2addr( rcounter, rmask1, rmask2 );
+-- modified for point configurable
+-- case rstate is
+-- when "000" =>
+-- raddr<=rcounter( 1 downto 0 )&rcounter( 9 downto 2);
+-- when "001" =>
+-- raddr<=rcounter( 9 downto 8 )&rcounter( 1 downto 0 )&rcounter( 7 downto 2);
+-- when "010" =>
+-- raddr<=rcounter( 9 downto 6 )&rcounter( 1 downto 0 )&rcounter( 5 downto 2);
+-- when "011" =>
+-- raddr<=rcounter( 9 downto 4 )&rcounter( 1 downto 0 )&rcounter( 3 downto 2);
+-- when "100" =>
+-- raddr<=rcounter( 9 downto 2 )&rcounter( 1 downto 0 );
+-- when others =>
+-- raddr<=( others=> '0' );
+-- end case;
+ end if;
+end process readaddr;
+
+writeaddr:process( clk,rst )
+begin
+ if rst='1' then
+ waddr<=( others=>'0' );
+ wcounter<=( others=>'0' );
+ wstate<=( others=>'0' );
+ wmask1<=( others=>'0' );
+ wmask2<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ if unsigned(state)=0 then
+ waddr<=counter;
+ else
+ if UNSIGNED(rstate)=0 and unsigned(rcounter)=FFTDELAY-1 then
+ wmask1(STAGE-1)<='1';
+ wmask1(STAGE-2 downto 0)<=(others=>'0');
+ wmask2(STAGE-1)<='0';
+ wmask2(STAGE-2 downto 0)<=(others=>'1');
+ elsif unsigned(rcounter)=FFTDELAY-1 then
+ wmask1<='0'&wmask1( STAGE-1 downto 1 );
+ wmask2<='0'&wmask2( STAGE-1 downto 1 );
+ end if;
+ if UNSIGNED(rstate)'0' );
+ wstate<=rstate;
+ else
+ wcounter<=unsigned(wcounter)+1;
+ end if;
+ waddr<=counter2addr( wcounter, wmask1, wmask2 );
+-- modified for point configurable
+-- case wstate is
+-- when "000" =>
+-- waddr<=wcounter( 1 downto 0 )&wcounter( 9 downto 2);
+-- when "001" =>
+-- waddr<=wcounter( 9 downto 8 )&wcounter( 1 downto 0 )&wcounter( 7 downto 2);
+-- when "010" =>
+-- waddr<=wcounter( 9 downto 6 )&wcounter( 1 downto 0 )&wcounter( 5 downto 2);
+-- when "011" =>
+-- waddr<=wcounter( 9 downto 4 )&wcounter( 1 downto 0 )&wcounter( 3 downto 2);
+-- when others =>
+-- waddr<=( others=> '0' );
+-- end case;
+ end if;
+ end if;
+end process writeaddr;
+
+writeen : process( clk, rst )
+begin
+ if rst='1' then
+ wen<='0';
+ elsif clk'event and clk='1' then
+ if unsigned(state)=0 then
+ wen<='1';
+ elsif unsigned(state)=1 and unsigned(counter)=0 then
+ wen<='0';
+ elsif unsigned(rstate)=0 and unsigned(rcounter)=FFTDELAY then
+ wen<='1';
+ elsif unsigned(rstate)=STAGE-1 and unsigned(rcounter)=FFTDELAY then
+ wen<='0';
+ end if;
+ end if;
+end process writeen;
+
+otherstart : process( clk, rst )
+begin
+ if rst='1' then
+ factorstart<='0';
+ cfft4start<='0';
+ outcounter<=(others=>'0');
+ inputbusy<='0';
+ elsif clk'event and clk='1' then
+ if start='1' then
+ inputbusy<='1';
+ elsif unsigned(state)=STAGE and unsigned(counter)=FFTDELAY then
+ inputbusy<='0';
+ end if;
+ if unsigned(state)=1 and unsigned(counter)=0 then
+ cfft4start<='1';
+ else
+ cfft4start<='0';
+ end if;
+ if unsigned(rstate)=0 and unsigned(rcounter)=FACTORDELAY then
+ factorstart<='1';
+ else
+ factorstart<='0';
+ end if;
+ if unsigned(state)=STAGE and unsigned(rcounter)=OUTDELAY then
+ outcounter<=CONV_STD_LOGIC_VECTOR(POINT,2*STAGE+1);
+ elsif outcounter(STAGE*2)='1' then
+ outcounter<=unsigned(outcounter)+1;
+ end if;
+ end if;
+end process otherstart;
+
+datasel : process( clk,rst )
+begin
+ if rst='1' then
+ wdataI<=( others=>'0' );
+ wdataQ<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ if unsigned(state)=0 then
+ wdataI<=Iin;
+ wdataQ<=Qin;
+ else
+ wdataI<=fftI;
+ wdataQ<=fftQ;
+ end if;
+ end if;
+end process datasel;
+
+end address;
Index: implementaciones/fft/pkg/cfft/trunk/src/p2r_cordic.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/src/p2r_cordic.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/src/p2r_cordic.vhd (revision 396)
@@ -0,0 +1,131 @@
+--
+-- VHDL implementation of cordic algorithm
+--
+-- File: p2r_cordic.vhd
+-- author: Richard Herveille
+-- rev. 1.0 initial release
+--
+
+--
+--
+-- This file is come from www.opencores.org
+--
+-- It has been modified by zhaom to enable 20 bit phase input
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Title : p2r_cordic
+-- Design : cfft
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : p2r_cordic.vhd
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Cordic arith pilepline
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity p2r_cordic is
+ generic(
+ PIPELINE : integer := 15;
+ WIDTH : integer := 16);
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+
+ Xi : in signed(WIDTH -1 downto 0);
+ Yi : in signed(WIDTH -1 downto 0) := (others => '0');
+ Zi : in signed(19 downto 0);
+
+ Xo : out signed(WIDTH -1 downto 0);
+ Yo : out signed(WIDTH -1 downto 0)
+ );
+end entity p2r_Cordic;
+
+
+architecture dataflow of p2r_cordic is
+
+ --
+ -- TYPE defenitions
+ --
+ type XYVector is array(PIPELINE downto 0) of signed(WIDTH -1 downto 0);
+ type ZVector is array(PIPELINE downto 0) of signed(19 downto 0);
+
+ --
+ -- COMPONENT declarations
+ --
+ component p2r_CordicPipe
+ generic(
+ WIDTH : natural := 16;
+ PIPEID : natural := 1
+ );
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+
+ Xi : in signed(WIDTH -1 downto 0);
+ Yi : in signed(WIDTH -1 downto 0);
+ Zi : in signed(19 downto 0);
+
+ Xo : out signed(WIDTH -1 downto 0);
+ Yo : out signed(WIDTH -1 downto 0);
+ Zo : out signed(19 downto 0)
+ );
+ end component p2r_CordicPipe;
+
+ --
+ -- SIGNALS
+ --
+ signal X, Y : XYVector;
+ signal Z : ZVector;
+
+ --
+ -- ACHITECTURE BODY
+ --
+begin
+ -- fill first nodes
+
+ -- fill X
+ X(0) <= Xi;
+
+ -- fill Y
+ Y(0) <= Yi;
+
+ -- fill Z
+ Z(0)(19 downto 0) <= Zi; -- modified by zhaom
+ --Z(0)(3 downto 0) <= (others => '0'); -- modified by zhaom
+
+ --
+ -- generate pipeline
+ --
+ gen_pipe:
+ for n in 1 to PIPELINE generate
+ Pipe: p2r_CordicPipe
+ generic map(WIDTH => WIDTH, PIPEID => n -1)
+ port map ( clk, ena, X(n-1), Y(n-1), Z(n-1), X(n), Y(n), Z(n) );
+ end generate gen_pipe;
+
+ --
+ -- assign outputs
+ --
+ Xo <= X(PIPELINE);
+ Yo <= Y(PIPELINE);
+end dataflow;
+
+
Index: implementaciones/fft/pkg/cfft/trunk/src/cfft4.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/src/cfft4.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/src/cfft4.vhd (revision 396)
@@ -0,0 +1,128 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : cfft4
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : cfft4.vhd
+-- Generated : Wed Oct 2 15:49:06 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : 4 point fft
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_SIGNED.all;
+
+
+entity cfft4 is
+ generic (
+ WIDTH : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ invert : in std_logic;
+ I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
+ Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
+ );
+end cfft4;
+
+
+architecture cfft4 of cfft4 is
+type RegAtype is array (3 downto 0) of std_logic_vector(WIDTH-1 downto 0);
+type RegBtype is array (3 downto 0) of std_logic_vector(WIDTH downto 0);
+
+signal counter : std_logic_vector( 1 downto 0 ):="00";
+signal RegAI,RegAQ : RegAtype;
+signal RegBI,RegBQ : RegBtype;
+begin
+
+
+count:process( clk,rst )
+begin
+ if rst='1' then
+ counter<="00";
+ elsif clk'event and clk='1' then
+ if start='1' then
+ counter<="00";
+ else
+ counter<=counter+1;
+ end if;
+ end if;
+end process count;
+
+
+-------------------------------------------------------------------------
+--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)--
+--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
+--2 rA(2)<=A2 B1<=rB(1)+rB(3)--
+--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)--
+-------------------------------------------------------------------------
+calculate:process( clk )
+begin
+ if clk'event and clk='1' then
+ case counter is
+--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)--
+ when "00" =>
+ RegAI(0)<=I;
+ RegAQ(0)<=Q;
+ RegBI(1)<=SXT(RegAI(0),WIDTH+1)-SXT(RegAI(2),WIDTH+1);
+ RegBQ(1)<=SXT(RegAQ(0),WIDTH+1)-SXT(RegAQ(2),WIDTH+1);
+ RegBI(2)<=SXT(RegAI(1),WIDTH+1)+SXT(RegAI(3),WIDTH+1);
+ RegBQ(2)<=SXT(RegAQ(1),WIDTH+1)+SXT(RegAQ(3),WIDTH+1);
+ Iout<=SXT(RegBI(1),WIDTH+2)-SXT(RegBI(3),WIDTH+2);
+ Qout<=SXT(RegBQ(1),WIDTH+2)-SXT(RegBQ(3),WIDTH+2);
+--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
+ when "01" =>
+ RegAI(1)<=I;
+ RegAQ(1)<=Q;
+ if invert='0' then
+ -- for fft *(-j)
+ RegBI(3)<=SXT(RegAQ(1),WIDTH+1)-SXT(RegAQ(3),WIDTH+1);
+ RegBQ(3)<=SXT(RegAI(3),WIDTH+1)-SXT(RegAI(1),WIDTH+1);
+ else
+ -- for fft *(j)
+ RegBI(3)<=SXT(RegAQ(3),WIDTH+1)-SXT(RegAQ(1),WIDTH+1);
+ RegBQ(3)<=SXT(RegAI(1),WIDTH+1)-SXT(RegAI(3),WIDTH+1);
+ end if;
+ Iout<=SXT(RegBI(0),WIDTH+2)+SXT(RegBI(2),WIDTH+2);
+ Qout<=SXT(RegBQ(0),WIDTH+2)+SXT(RegBQ(2),WIDTH+2);
+--2 rA(2)<=A2 B1<=rB(1)+rB(3)--
+ when "10" =>
+ RegAI(2)<=I;
+ RegAQ(2)<=Q;
+ Iout<=SXT(RegBI(1),WIDTH+2)+SXT(RegBI(3),WIDTH+2);
+ Qout<=SXT(RegBQ(1),WIDTH+2)+SXT(RegBQ(3),WIDTH+2);
+--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)--
+ when "11" =>
+ RegAI(3)<=I;
+ RegAQ(3)<=Q;
+ RegBI(0)<=SXT(RegAI(0),WIDTH+1)+SXT(RegAI(2),WIDTH+1);
+ RegBQ(0)<=SXT(RegAQ(0),WIDTH+1)+SXT(RegAQ(2),WIDTH+1);
+ Iout<=SXT(RegBI(0),WIDTH+2)-SXT(RegBI(2),WIDTH+2);
+ Qout<=SXT(RegBQ(0),WIDTH+2)-SXT(RegBQ(2),WIDTH+2);
+ when others => null;
+ end case;
+ end if;
+end process calculate;
+end cfft4;
Index: implementaciones/fft/pkg/cfft/trunk/src/mulfactor.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/src/mulfactor.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/src/mulfactor.vhd (revision 396)
@@ -0,0 +1,126 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : mulfactor
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : mulfactor.vhd
+-- Generated : Thu Oct 3 00:37:40 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : 360 degee complex rotation
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.1
+-- Date : Oct 18 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Point configurable
+--
+---------------------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_SIGNED.all;
+
+entity mulfactor is
+ generic (
+ WIDTH : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ angle : in signed(2*STAGE-1 downto 0);
+ I : in signed(WIDTH+1 downto 0);
+ Q : in signed(WIDTH+1 downto 0);
+ Iout : out signed(WIDTH+3 downto 0);
+ Qout : out signed(WIDTH+3 downto 0)
+ );
+end mulfactor;
+
+
+architecture mulfactor of mulfactor is
+signal phase : signed( 2*STAGE-3 downto 0 );
+signal Xi,Yi : signed( WIDTH+1 downto 0 );
+component sc_corproc
+ generic(
+ WIDTH : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+ Xin : in signed(WIDTH+1 downto 0);
+ Yin : in signed(WIDTH+1 downto 0);
+ Ain : in signed(2*STAGE-3 downto 0 );
+
+ sin : out signed(WIDTH+3 downto 0);
+ cos : out signed(WIDTH+3 downto 0));
+end component;
+
+begin
+
+ u1: sc_corproc
+ generic map(
+ WIDTH=>WIDTH,
+ STAGE=>STAGE
+ )
+ port map (
+ clk=>clk,
+ ena=>'1',
+ Xin=>Xi,
+ Yin=>Yi,
+ Ain=>phase,
+
+ sin=>Qout,
+ cos=>Iout
+ );
+
+process( clk, rst )
+variable temp : std_logic_vector( 1 downto 0 );
+begin
+ if rst='1' then
+ phase<=( others=>'0' );
+ Xi<=( others=>'0' );
+ Yi<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ phase<=angle( 2*STAGE-3 downto 0 );
+ temp:=std_logic_vector(angle( 2*STAGE-1 downto 2*STAGE-2 ));
+ case temp is
+ when "00" =>
+ Xi<=I;
+ Yi<=Q;
+ when "01" =>
+ Xi<=0-Q;
+ Yi<=I;
+ when "10" =>
+ Xi<=0-I;
+ Yi<=0-Q;
+ when "11" =>
+ Xi<=Q;
+ Yi<=0-I;
+ when others=>
+ null;
+ end case;
+ end if;
+end process;
+
+end mulfactor;
Index: implementaciones/fft/pkg/cfft/trunk/src/sc_corproc.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/src/sc_corproc.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/src/sc_corproc.vhd (revision 396)
@@ -0,0 +1,100 @@
+--
+-- This file is come from www.opencores.org
+--
+-- It has been modified by ZHAO Ming for 20 bit complex rotation
+--
+
+---------------------------------------------------------------------------------------------------
+--
+-- Title : sc_corproc
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : sc_corproc.vhd
+-- Generated : Tue Jul 16 10:39:17 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : complex rotation
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.0
+-- Date : Oct 18 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_signed.all;
+
+entity sc_corproc is
+ generic (
+ WIDTH : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+ Xin : in signed(WIDTH+1 downto 0);
+ Yin : in signed(WIDTH+1 downto 0);
+ Ain : in signed(2*STAGE-3 downto 0 );
+
+ sin : out signed(WIDTH+3 downto 0);
+ cos : out signed(WIDTH+3 downto 0)
+ );
+end entity sc_corproc;
+
+architecture dataflow of sc_corproc is
+ constant PipeLength : natural := 2*STAGE+2;
+
+ component p2r_cordic is
+ generic(
+ PIPELINE : integer := 15;
+ WIDTH : integer := 16);
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+
+ Xi : in signed(WIDTH -1 downto 0);
+ Yi : in signed(WIDTH -1 downto 0) := (others => '0');
+ Zi : in signed(19 downto 0);
+
+ Xo : out signed(WIDTH -1 downto 0);
+ Yo : out signed(WIDTH -1 downto 0)
+ );
+ end component p2r_cordic;
+signal phase:signed( 19 downto 0 );
+signal Xi,Yi:signed( WIDTH+7 downto 0 );
+signal Xo,Yo:signed( WIDTH+7 downto 0 );
+signal zeros:signed( 19-STAGE*2 downto 0 );
+begin
+ Xi<= Xin(WIDTH+1)&Xin&"00000";
+ Yi<= Yin(WIDTH+1)&Yin&"00000";
+ zeros<=(others=>'0');
+ phase<="00"&Ain&zeros;
+ cos<=Xo(WIDTH+7)&Xo( WIDTH+7 downto 5 );
+ sin<=Yo(WIDTH+7)&Yo( WIDTH+7 downto 5 );
+
+ u1: p2r_cordic
+ generic map(PIPELINE => PipeLength, WIDTH => WIDTH+8)
+ port map(clk => clk, ena => ena, Xi => Xi, Yi=>Yi,Zi => phase, Xo => Xo, Yo => Yo);
+end architecture dataflow;
Index: implementaciones/fft/pkg/cfft/trunk/src/blockdram.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/src/blockdram.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/src/blockdram.vhd (revision 396)
@@ -0,0 +1,68 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : blockram
+-- Design : cfft
+-- Author : MENG Lin
+-- email :
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : blockram.vhd
+-- Generated : unknown
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Dual port ram
+--
+---------------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library synplify;
+use synplify.attributes.all;
+
+entity blockdram is
+generic(
+ depth: integer;
+ Dwidth: integer;
+ Awidth: integer
+);
+port(
+ addra: IN std_logic_VECTOR(Awidth-1 downto 0);
+ clka: IN std_logic;
+ addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
+ clkb: IN std_logic;
+ dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
+ wea: IN std_logic;
+ dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
+end blockdram;
+
+architecture arch_blockdram of blockdram is
+
+type ram_memtype is array (depth-1 downto 0) of std_logic_vector
+ (Dwidth-1 downto 0);
+signal mem : ram_memtype := (others => (others => '0'));
+attribute syn_ramstyle of mem : signal is "block_ram";
+
+signal addrb_reg: std_logic_vector(Awidth-1 downto 0);
+
+begin
+ wr: process( clka )
+ begin
+ if rising_edge(clka) then
+ if wea = '1' then
+ mem(conv_integer(addra)) <= dia;
+ end if;
+ end if;
+ end process wr;
+
+ rd: process( clkb )
+ begin
+ if rising_edge(clkb) then
+ addrb_reg <= addrb;
+ end if;
+ end process rd;
+ dob <= mem(conv_integer(addrb_reg));
+end arch_blockdram;
+
Index: implementaciones/fft/pkg/cfft/trunk/sim/tb_cfft1024x12_read_from_file.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/sim/tb_cfft1024x12_read_from_file.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/sim/tb_cfft1024x12_read_from_file.vhd (revision 396)
@@ -0,0 +1,90 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use std.textio.all;
+use IEEE.std_logic_textio.all;
+
+entity tb_cfft1024x12 is
+
+end tb_cfft1024x12;
+
+architecture tb of tb_cfft1024x12 is
+
+component cfft1024X12
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ invert : in std_logic;
+ Iin : in STD_LOGIC_VECTOR(11 downto 0);
+ Qin : in STD_LOGIC_VECTOR(11 downto 0);
+ inputbusy : out STD_LOGIC;
+ outdataen : out STD_LOGIC;
+ Iout : out STD_LOGIC_VECTOR(13 downto 0);
+ Qout : out STD_LOGIC_VECTOR(13 downto 0);
+ OutPosition : out STD_LOGIC_VECTOR( 9 downto 0 )
+ );
+end component;
+
+signal clk : STD_LOGIC;
+signal rst : STD_LOGIC;
+signal start : STD_LOGIC;
+signal invert : std_logic;
+signal Iin : STD_LOGIC_VECTOR(11 downto 0);
+signal Qin : STD_LOGIC_VECTOR(11 downto 0);
+signal inputbusy : STD_LOGIC;
+signal outdataen : STD_LOGIC;
+signal Iout : STD_LOGIC_VECTOR(13 downto 0);
+signal Qout : STD_LOGIC_VECTOR(13 downto 0);
+signal output_position:std_logic_vector(9 downto 0 );
+constant clkprd : time:=10 ns;
+
+begin
+f: cfft1024x12 port map(clk=>clk,
+ rst =>rst,
+ start=> start,
+ invert=>invert,
+ Iin=>Iin,
+ Qin=>Qin,
+ inputbusy=>inputbusy,
+ outdataen=>outdataen,
+ Iout=>Iout,
+ Qout=>Qout,
+ OutPosition=>output_position);
+
+clockgen: process
+begin
+ clk <= '1';
+ wait for clkprd/2;
+ clk <= '0';
+ wait for clkprd/2;
+end process;
+
+fileread: process
+file FileIn1 : text is in "bindata"; -- bindata is a file containing 1-1024
+in binary.
+variable LineIn1 : line;
+variable InputTmp1 :std_logic_vector(11 downto 0);
+begin
+ rst<='1';
+ wait until clk'EVENT and clk='1';
+ rst<='0';
+ wait until clk'EVENT and clk='1';
+ invert<='0';
+ start<='1';
+ wait until clk'EVENT and clk='1';
+ start<='0';
+
+ while not( endfile( FileIn1)) loop
+ readline( FileIn1, LineIn1);
+ read(LineIn1, InputTmp1);
+ Iin<=InputTmp1;
+ Qin<="000000000000";
+ wait until clk'EVENT and clk='1';
+ end loop;
+
+ wait until outdataen'EVENT and outdataen='1';
+ wait for 15000 ns;
+end process;
+
+end tb;
Index: implementaciones/fft/pkg/cfft/trunk/sim/tb_cfft1024x12.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/sim/tb_cfft1024x12.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/sim/tb_cfft1024x12.vhd (revision 396)
@@ -0,0 +1,165 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : test bench
+-- Design : cfft
+-- Author : henning larsen
+-- email :
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : tb_cfft1024x12.vhd
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description :
+--
+-- Simple "testbench" for cfft1024x12. It is realy just an excitation of inputs
+-- The output has to be evaluated manually. run for 125 us with current settings.
+-- Input is a dual sinsoid with constant amplitudes, and a DC value.
+-- Input is real valued only. A calculation of the power spectrum, and a frequency bin
+-- counter is included, but no reordering of output sequence is performed.
+-- Frequencies are easy to select such that a minimum of spill into side bins is obtained.
+-- Beware of the posibilty of saturation in the output. For single sinsoide,the saturation limit
+-- is 2^14/29.4=557 units of input amplitude.
+--
+-- henning larsen
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Nov 21 2002
+-- Modifier : ZHAO Ming
+-- Desccription : init release
+-- compare output position
+--
+---------------------------------------------------------------------------------------------------
+
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.math_real.all;
+USE ieee.std_logic_signed.all;
+
+ENTITY cfft1024x12_tester1 IS
+END cfft1024x12_tester1 ;
+ARCHITECTURE tester OF cfft1024x12_tester1 IS
+ -- Component Declarations
+ COMPONENT cfft1024X12
+ PORT (
+ clk : IN STD_LOGIC ;
+ rst : IN STD_LOGIC ;
+ start : IN STD_LOGIC ;
+ invert : IN std_logic ;
+ Iin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+ Qin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+ inputbusy : OUT STD_LOGIC ;
+ outdataen : OUT STD_LOGIC ;
+ Iout : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ Qout : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ OutPosition : out STD_LOGIC_VECTOR( 9 downto 0 )
+ );
+ END COMPONENT;
+
+ constant Tck_half : time:=10 ns;
+ constant Tckhalf : real:=10.0e-9;-- real value eqv of time, there is some conversion function
+ -- for this but could not find/remember.
+ constant ampl1 : real:=100.0;-- max amplitude is roughly 550=2^14/29.4 to avoid sturation in output
+ constant ampl2 : real:=200.0; -- .. but see intro comments
+ constant f1 : real := 100.0/TckHalf/2.0/1024.0;-- bin number =100
+ constant f2 : real := 33.0/TckHalf/2.0/1024.0;-- bin number =33
+ constant dc : real:=100.0;--bin number=0
+
+ signal c1,c2,cout: real;
+ signal clock : std_logic:='0';
+ signal reset : std_logic:='0';
+ signal start : std_logic:='0';
+ signal invert : std_logic ;
+ signal Iin : STD_LOGIC_VECTOR (11 DOWNTO 0);
+ signal Qin : STD_LOGIC_VECTOR (11 DOWNTO 0);
+ signal inputbusy : STD_LOGIC:='0' ;
+ signal outdataen : STD_LOGIC:='0' ;
+ signal Iout : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ signal Qout : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ signal amp : real; -- power spectrum
+ signal bitRev : STD_LOGIC_VECTOR (9 DOWNTO 0);-- bin counter
+ signal OutPosition : STD_LOGIC_VECTOR( 9 downto 0 );
+
+BEGIN
+ -- Instance port mappings.
+ I0 : cfft1024X12
+ PORT MAP (
+ clk => clock,
+ rst => reset,
+ start => start,
+ invert => invert,
+ Iin => Iin,
+ Qin => Qin,
+ inputbusy => inputbusy,
+ outdataen => outdataen,
+ Iout => Iout,
+ Qout => Qout,
+ OutPosition => OutPosition
+ );
+
+----------------------------------------------------------------------------
+--
+-- control signals ,setup
+clock <= not clock after Tck_half;
+reset <= '1', '0' after 2*Tck_half;
+start <= '0', '1' after 3*Tck_half, '0' after 5*Tck_half;-- only one FFT is done
+invert <= '0';-- FFT
+
+----------------------------------------------------------------------------
+--
+sin_gen: process(clock, reset)
+ variable tid : real;
+ variable TM : real :=0.0 ;
+ begin
+ if Reset = '1' then
+ c1 <= 0.0;
+ c2 <= 0.0;
+ Iin<="000000000000" ;
+ Qin<="000000000000" ;
+ TM := 0.0;
+ tid := TM;
+ else
+ if clock'event and clock = '1' then
+ TM := TM + Tckhalf*2.0;
+ tid := TM;
+ c1 <= (ampl1 * sin(2.0*math_pi*f1*tid));
+ c2 <= (ampl2 * sin(2.0*math_pi*f2*tid));
+ cout <= c1+c2+dc;
+ Iin <= conv_std_logic_vector(integer(cout),Iin'length);
+ Qin <="000000000000" ;
+ end if;
+ end if;
+ end process sin_gen;
+----------------------------------------------------------------------------
+--
+--Output power spectrum, normalized with the gain of 29.4
+amp <= sqrt(real(CONV_integer(Iout)) * real(CONV_integer(Iout))
+ + real(CONV_integer(Qout)) * real(CONV_integer(Qout)))/29.4;
+----------------------------------------------------------------------------
+--
+-- radix 4 bit reversed counter
+radix4cnt: process (clock)
+variable cntr: std_logic_vector ( 9 downto 0);
+begin
+ if rising_edge(clock) then
+ if outdataen='1' then
+ cntr:=unsigned(cntr)+1;
+ else
+ cntr:=(others => '0');
+ end if;
+ for k in 1 to ((10) / 2) loop
+ bitRev(2*k-2)<= cntr(10-2*k);
+ bitRev(2*k-1)<= cntr(10-(-1+2*k));
+ end loop;
+ end if;
+end process radix4cnt;
+
+END tester;
Index: implementaciones/fft/pkg/cfft/trunk/cfft.vsd
===================================================================
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Index: implementaciones/fft/pkg/cfft/trunk/cfft.vsd
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/cfft.vsd (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/cfft.vsd (revision 396)
implementaciones/fft/pkg/cfft/trunk/cfft.vsd
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: implementaciones/fft/pkg/cfft/trunk/cfft_e.pdf
===================================================================
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Index: implementaciones/fft/pkg/cfft/trunk/cfft_e.pdf
===================================================================
--- implementaciones/fft/pkg/cfft/trunk/cfft_e.pdf (nonexistent)
+++ implementaciones/fft/pkg/cfft/trunk/cfft_e.pdf (revision 396)
implementaciones/fft/pkg/cfft/trunk/cfft_e.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: implementaciones/fft/pkg/cfft/tags/arelease/imp/cfft1024X12.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/imp/cfft1024X12.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/imp/cfft1024X12.vhd (revision 396)
@@ -0,0 +1,116 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : cfft1024X12
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : cfft1024X12.vhd
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description :This is a sample implementation of cfft
+--
+-- radix 4 1024 point FFT input 12 bit Output 14 bit with
+-- limit and overfall processing internal
+--
+-- The gain is 0.0287 for FFT and 29.4 for IFFT
+--
+-- The output is 4-based reversed ordered, it means
+-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
+--
+--
+---------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+--
+-- port :
+-- clk : main clk -- I have test 90M with Xilinx virtex600E
+-- rst : globe reset -- '1' for reset
+-- start : start fft -- one clock '1' before data input
+-- inv : '0' for fft and '1' for ifft, it is sampled when start is '1'
+-- Iin,Qin : data input-- following start immediately, input data
+-- -- power should not be too big
+-- inputbusy : if it change to '0' then next fft is enable
+-- outdataen : when it is '1', the valid data is output
+-- Iout,Qout : fft data output when outdataen is '1'
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 31 2002
+-- Modifier : ZHAO Ming
+-- Desccription : initial release
+--
+---------------------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity cfft1024X12 is
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ inv : in std_logic;
+ Iin : in STD_LOGIC_VECTOR(11 downto 0);
+ Qin : in STD_LOGIC_VECTOR(11 downto 0);
+ inputbusy : out STD_LOGIC;
+ outdataen : out STD_LOGIC;
+ Iout : out STD_LOGIC_VECTOR(13 downto 0);
+ Qout : out STD_LOGIC_VECTOR(13 downto 0)
+ );
+end cfft1024X12;
+
+
+architecture imp of cfft1024X12 is
+
+component cfft
+ generic (
+ WIDTH : Natural;
+ POINT : Natural;
+ STAGE : Natural -- STAGE=log4(POINT)
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ inv : in std_logic;
+ Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ inputbusy : out STD_LOGIC;
+ outdataen : out STD_LOGIC;
+ Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
+ Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
+ );
+end component;
+
+begin
+
+aCfft:cfft
+generic map (
+ WIDTH=>12,
+ POINT=>1024,
+ STAGE=>5
+)
+port map (
+ clk=>clk,
+ rst=>rst,
+ start=>start,
+ inv=>inv,
+ Iin=>Iin,
+ Qin=>Qin,
+ inputbusy=>inputbusy,
+ outdataen=>outdataen,
+ Iout=>Iout,
+ Qout=>Qout
+);
+
+
+end imp;
Index: implementaciones/fft/pkg/cfft/tags/arelease/cfft.doc
===================================================================
Cannot display: file marked as a binary type.
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Index: implementaciones/fft/pkg/cfft/tags/arelease/cfft.doc
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/cfft.doc (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/cfft.doc (revision 396)
implementaciones/fft/pkg/cfft/tags/arelease/cfft.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: implementaciones/fft/pkg/cfft/tags/arelease/src/rofactor.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/src/rofactor.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/src/rofactor.vhd (revision 396)
@@ -0,0 +1,119 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : rofactor
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : rofactor.vhd
+-- Generated : Thu Oct 3 00:12:16 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Generate FFT rotation factor
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.0
+-- Date : Oct 18 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_signed.all;
+
+entity rofactor is
+ generic (
+ POINT : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ inv : in std_logic;
+-- step : in STD_LOGIC_VECTOR(2 downto 0);
+ angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
+ );
+end rofactor;
+
+
+architecture rofactor of rofactor is
+signal counter : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
+signal inc,iinc,phase : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
+signal mask : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
+begin
+angle<=phase;
+
+count:process( clk,rst )
+begin
+ if rst='1' then
+ counter<=( others=>'0' );
+ inc<=( others=>'0' );
+ mask<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ if start='1' then
+ counter<=( others=>'0' );
+ mask<=( others=>'0' );
+-- state<="000";
+ if inv='1' then
+ inc<=CONV_STD_LOGIC_VECTOR(1,STAGE*2);
+ else
+ inc<=CONV_STD_LOGIC_VECTOR(-1,STAGE*2);
+ end if;
+ else
+ counter<=unsigned(counter)+1;
+ if signed(counter)=-1 then
+ inc<=inc(STAGE*2-3 downto 0 )&"00";
+ mask<="11"&mask( STAGE*2-1 downto 2 );
+-- if state/="100" then
+-- state<=state+1;
+-- end if;
+ end if;
+ end if;
+ end if;
+end process count;
+
+output : process( clk, rst )
+begin
+ if rst='1' then
+ phase<=( others=>'0' );
+ iinc<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ if start='1' then
+ iinc<=( others=>'0' );
+ phase<=( others=>'0' );
+ else
+ if unsigned(counter( 1 downto 0 ))=3 then
+ phase<=( others=>'0' );
+ else
+ phase<=unsigned(phase)+unsigned(iinc);
+ end if;
+ if signed(counter or mask)=-1 then
+ iinc<=(others=>'0');
+ elsif unsigned(counter( 1 downto 0 ))=3 then
+ iinc<=unsigned(iinc)+unsigned(inc);
+ end if;
+ end if;
+ end if;
+end process output;
+end rofactor;
Index: implementaciones/fft/pkg/cfft/tags/arelease/src/cfft.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/src/cfft.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/src/cfft.vhd (revision 396)
@@ -0,0 +1,335 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : cfft
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : cfft.vhd
+-- Generated : Thu Oct 3 03:03:58 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : 4-based 1024 point FFT input 12 bit Output 14 bit with
+-- limit and overfall processing internal
+--
+-- The gain is 0.0287 for FFT and 29.4 for IFFT
+--
+-- The output is 4-based reversed ordered, it means
+-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
+--
+--
+---------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+--
+-- port :
+-- clk : main clk -- I have test 90M with Xilinx virtex600E
+-- rst : globe reset -- '1' for reset
+-- start : start fft -- one clock '1' before data input
+-- inv : '0' for fft and '1' for ifft, it is sampled when start is '1'
+-- Iin,Qin : data input-- following start immediately, input data
+-- -- power should not be too big
+-- inputbusy : if it change to '0' then next fft is enable
+-- outdataen : when it is '1', the valid data is output
+-- Iout,Qout : fft data output when outdataen is '1'
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.0
+-- Date : Oct 18 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Point configurable
+-- FFT Gain IFFT GAIN
+-- 256 0.0698 17.9
+-- 1024 0.0287 29.4
+-- 4096 0.0118 48.2742
+--
+--
+---------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+entity cfft is
+ generic (
+ WIDTH : Natural;
+ POINT : Natural;
+ STAGE : Natural -- STAGE=log4(POINT)
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ inv : in std_logic;
+ Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ inputbusy : out STD_LOGIC;
+ outdataen : out STD_LOGIC;
+ Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
+ Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
+ );
+end cfft;
+
+
+architecture cfft of cfft is
+
+component address
+ generic (
+ WIDTH : Natural;
+ POINT : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ Iin : in std_logic_vector( WIDTH-1 downto 0 );
+ Qin : in std_logic_vector( WIDTH-1 downto 0 );
+ fftI : in std_logic_vector( WIDTH-1 downto 0 );
+ fftQ : in std_logic_vector( WIDTH-1 downto 0 );
+ wdataI : out std_logic_vector( WIDTH-1 downto 0 );
+ wdataQ : out std_logic_vector( WIDTH-1 downto 0 );
+ raddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
+ waddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
+ wen : out std_logic;
+ factorstart : out STD_LOGIC;
+ cfft4start : out STD_LOGIC;
+ outdataen : out std_logic;
+ inputbusy : out std_logic
+ );
+end component;
+
+component blockdram
+generic(
+ depth: integer;
+ Dwidth: integer;
+ Awidth: integer
+);
+port(
+ addra: IN std_logic_VECTOR(Awidth-1 downto 0);
+ clka: IN std_logic;
+ addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
+ clkb: IN std_logic;
+ dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
+ wea: IN std_logic;
+ dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
+end component;
+
+component cfft4
+ generic (
+ WIDTH : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ inv : in std_logic;
+ I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
+ Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
+ );
+end component;
+
+component div4limit
+ generic (
+ WIDTH : Natural
+ );
+ port(
+ clk : in std_logic;
+ D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
+ Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+ );
+end component;
+
+component mulfactor
+ generic (
+ WIDTH : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ angle : in signed(2*STAGE-1 downto 0);
+ I : in signed(WIDTH+1 downto 0);
+ Q : in signed(WIDTH+1 downto 0);
+ Iout : out signed(WIDTH+3 downto 0);
+ Qout : out signed(WIDTH+3 downto 0)
+ );
+end component;
+
+component rofactor
+ generic (
+ POINT : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ inv : in std_logic;
+ angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
+ );
+end component;
+signal wea,cfft4start,factorstart:std_logic:='0';
+signal wdataI,wdataQ,fftI,fftQ,Iramout,Qramout:std_logic_vector(WIDTH-1 downto 0):=(others=>'0');
+signal waddr,raddr:std_logic_vector( 2*STAGE-1 downto 0):=(others=>'0');
+signal Icfft4out,Qcfft4out:std_logic_vector( WIDTH+1 downto 0):=(others=>'0');
+signal angle:std_logic_vector( 2*STAGE-1 downto 0 ):=( others=>'0');
+signal Imulout,Qmulout:signed( WIDTH+3 downto 0):=(others=>'0');
+signal inv_reg:std_logic:='0';
+
+begin
+
+Aaddress:address
+generic map (
+ WIDTH=>WIDTH,
+ POINT=>POINT,
+ STAGE=>STAGE
+)
+port map (
+ clk=>clk,
+ rst=>rst,
+ start=>start,
+ Iin=>Iin,
+ Qin=>Qin,
+ fftI=>fftI,
+ fftQ=>fftQ,
+ wdataI=>wdataI,
+ wdataQ=>wdataQ,
+ raddr=>raddr,
+ waddr=>waddr,
+ wen=>wea,
+ factorstart=>factorstart,
+ cfft4start=>cfft4start,
+ outdataen=>outdataen,
+ inputbusy=>inputbusy
+ );
+
+Iram:blockdram
+generic map (
+ depth=>POINT,
+ Dwidth=>WIDTH,
+ Awidth=>2*STAGE
+)
+port map (
+ addra=>waddr,
+ clka=>clk,
+ addrb=>raddr,
+ clkb=>clk,
+ dia=>wdataI,
+ wea=>wea,
+ dob=>Iramout
+);
+
+Qram:blockdram
+generic map (
+ depth=>POINT,
+ Dwidth=>WIDTH,
+ Awidth=>2*STAGE
+)
+port map (
+ addra=>waddr,
+ clka=>clk,
+ addrb=>raddr,
+ clkb=>clk,
+ dia=>wdataQ,
+ wea=>wea,
+ dob=>Qramout
+);
+
+acfft4:cfft4
+generic map (
+ WIDTH=>WIDTH
+)
+port map (
+ clk=>clk,
+ rst=>rst,
+ start=>cfft4start,
+ inv=>inv_reg,
+ I=>Iramout,
+ Q=>Qramout,
+ Iout=>Icfft4out,
+ Qout=>Qcfft4out
+ );
+
+Iout<=Icfft4out;
+Qout<=Qcfft4out;
+
+Ilimit:div4limit
+generic map (
+ WIDTH=>WIDTH
+)
+port map (
+ clk=>clk,
+ D=>std_logic_vector(Imulout),
+ Q=>fftI
+ );
+Qlimit:div4limit
+generic map (
+ WIDTH=>WIDTH
+)
+port map (
+ clk=>clk,
+ D=>std_logic_vector(Qmulout),
+ Q=>fftQ
+ );
+
+amulfactor:mulfactor
+generic map (
+ WIDTH=>WIDTH,
+ STAGE=>STAGE
+)
+port map (
+ clk=>clk,
+ rst=>rst,
+ angle=>signed(angle),
+ I=>signed(Icfft4out),
+ Q=>signed(Qcfft4out),
+ Iout=>Imulout,
+ Qout=>Qmulout
+ );
+
+arofactor:rofactor
+generic map (
+ POINT=>POINT,
+ STAGE=>STAGE
+)
+port map (
+ clk=>clk,
+ rst=>rst,
+ start=>factorstart,
+ inv=>inv_reg,
+ angle=>angle
+ );
+
+process( clk, rst )
+begin
+ if rst='1' then
+ inv_reg<='0';
+ elsif clk'event and clk='1' then
+ if start='1' then
+ inv_reg<=inv;
+ end if;
+ end if;
+end process;
+
+
+
+end cfft;
Index: implementaciones/fft/pkg/cfft/tags/arelease/src/p2r_CordicPipe.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/src/p2r_CordicPipe.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/src/p2r_CordicPipe.vhd (revision 396)
@@ -0,0 +1,170 @@
+--
+-- file: p2r_CordicPipe.vhd
+-- author: Richard Herveille
+-- rev. 1.0 initial release
+--
+
+--
+-- This file is come from WWW.OPENCORES.ORG
+
+---------------------------------------------------------------------------------------------------
+--
+-- Title : p2r_CordicPipe
+-- Design : cfft
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : p2r_CordicPipe.vhd
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Cordic arith pilepline
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity p2r_CordicPipe is
+ generic(
+ WIDTH : natural := 16;
+ PIPEID : natural := 1
+ );
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+
+ Xi : in signed(WIDTH -1 downto 0);
+ Yi : in signed(WIDTH -1 downto 0);
+ Zi : in signed(19 downto 0);
+
+ Xo : out signed(WIDTH -1 downto 0);
+ Yo : out signed(WIDTH -1 downto 0);
+ Zo : out signed(19 downto 0)
+ );
+end entity p2r_CordicPipe;
+
+architecture dataflow of p2r_CordicPipe is
+
+ --
+ -- functions
+ --
+
+ -- Function CATAN (constante arc-tangent).
+ -- This is a lookup table containing pre-calculated arc-tangents.
+ -- 'n' is the number of the pipe, returned is a 20bit arc-tangent value.
+ -- The numbers are calculated as follows: Z(n) = atan(1/2^n)
+ -- examples:
+ -- 20bit values => 2^20 = 2pi(rad)
+ -- 1(rad) = 2^20/2pi = 166886.053....
+ -- n:0, atan(1/1) = 0.7853...(rad)
+ -- 0.7853... * 166886.053... = 131072(dec) = 20000(hex)
+ -- n:1, atan(1/2) = 0.4636...(rad)
+ -- 0.4636... * 166886.053... = 77376.32(dec) = 12E40(hex)
+ -- n:2, atan(1/4) = 0.2449...(rad)
+ -- 0.2449... * 166886.053... = 40883.52(dec) = 9FB3(hex)
+ -- n:3, atan(1/8) = 0.1243...(rad)
+ -- 0.1243... * 166886.053... = 20753.11(dec) = 5111(hex)
+ --
+ function CATAN(n :natural) return integer is
+ variable result :integer;
+ begin
+ case n is
+ when 0 => result := 16#020000#;
+ when 1 => result := 16#012E40#;
+ when 2 => result := 16#09FB4#;
+ when 3 => result := 16#05111#;
+ when 4 => result := 16#028B1#;
+ when 5 => result := 16#0145D#;
+ when 6 => result := 16#0A2F#;
+ when 7 => result := 16#0518#;
+ when 8 => result := 16#028C#;
+ when 9 => result := 16#0146#;
+ when 10 => result := 16#0A3#;
+ when 11 => result := 16#051#;
+ when 12 => result := 16#029#;
+ when 13 => result := 16#014#;
+ when 14 => result := 16#0A#;
+ when 15 => result := 16#05#;
+ when 16 => result := 16#03#;
+ when 17 => result := 16#01#;
+ when others => result := 16#0#;
+ end case;
+ return result;
+ end CATAN;
+
+ -- function Delta is actually an arithmatic shift right
+ -- This strange construction is needed for compatibility with Xilinx WebPack
+ function Delta(Arg : signed; Cnt : natural) return signed is
+ variable tmp : signed(Arg'range);
+ constant lo : integer := Arg'high -cnt +1;
+ begin
+ for n in Arg'high downto lo loop
+ tmp(n) := Arg(Arg'high);
+ end loop;
+ for n in Arg'high -cnt downto 0 loop
+ tmp(n) := Arg(n +cnt);
+ end loop;
+ return tmp;
+ end function Delta;
+
+ function AddSub(dataa, datab : in signed; add_sub : in std_logic) return signed is
+ begin
+ if (add_sub = '1') then
+ return dataa + datab;
+ else
+ return dataa - datab;
+ end if;
+ end;
+
+ --
+ -- ARCHITECTURE BODY
+ --
+ signal dX, Xresult : signed(WIDTH -1 downto 0);
+ signal dY, Yresult : signed(WIDTH -1 downto 0);
+ signal atan, Zresult : signed(19 downto 0);
+
+ signal Zneg, Zpos : std_logic;
+
+begin
+
+ dX <= Delta(Xi, PIPEID);
+ dY <= Delta(Yi, PIPEID);
+ atan <= conv_signed( catan(PIPEID), 20);
+
+ -- generate adder structures
+ Zneg <= Zi(19);
+ Zpos <= not Zi(19);
+
+ -- xadd
+ Xresult <= AddSub(Xi, dY, Zneg);
+
+ -- yadd
+ Yresult <= AddSub(Yi, dX, Zpos);
+
+ -- zadd
+ Zresult <= AddSub(Zi, atan, Zneg);
+
+ gen_regs: process(clk)
+ begin
+ if(clk'event and clk='1') then
+ if (ena = '1') then
+ Xo <= Xresult;
+ Yo <= Yresult;
+ Zo <= Zresult;
+ end if;
+ end if;
+ end process;
+
+end architecture dataflow;
Index: implementaciones/fft/pkg/cfft/tags/arelease/src/address.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/src/address.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/src/address.vhd (revision 396)
@@ -0,0 +1,305 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : address
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : address.vhd
+-- Generated : Thu Oct 3 01:44:47 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Generate RAM read write address and start finish control signal
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.0
+-- Date : Oct 18 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 1
+-- Revision Number : 2
+-- Version : 1.2.1
+-- Date : Oct 19 2002
+-- Modifier : ZHAO Ming
+-- Desccription : modified fuction counter2address for syn
+-- add rmask1,rmask2,wmask1,wmask2 signal
+--
+---------------------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_signed.all;
+
+entity address is
+ generic (
+ WIDTH : Natural;
+ POINT : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ Iin : in std_logic_vector( WIDTH-1 downto 0 );
+ Qin : in std_logic_vector( WIDTH-1 downto 0 );
+ fftI : in std_logic_vector( WIDTH-1 downto 0 );
+ fftQ : in std_logic_vector( WIDTH-1 downto 0 );
+ wdataI : out std_logic_vector( WIDTH-1 downto 0 );
+ wdataQ : out std_logic_vector( WIDTH-1 downto 0 );
+ raddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);
+ waddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0);
+ wen : out std_logic;
+ factorstart : out STD_LOGIC;
+ cfft4start : out STD_LOGIC;
+ outdataen : out std_logic;
+ inputbusy : out std_logic
+ );
+end address;
+
+
+architecture address of address is
+
+
+-- function counter2addr(counter : std_logic_vector; state:std_logic_vector) return std_logic_vector is
+-- variable result :std_logic_vector(counter'range);
+-- variable istate : Natural;
+-- begin
+-- istate:=CONV_INTEGER(unsigned(state));
+-- if istate=0 then
+-- result := counter( 1 downto 0 )&counter( counter'high downto 2 );
+-- elsif istate=(counter'high-1)/2 then
+-- result := counter;
+-- elsif istate<(counter'high-1)/2 then
+-- result := counter( counter'high downto counter'high-istate*2+1 )&counter( 1 downto 0 )&counter( counter'high-istate*2 downto 2 );
+-- else
+-- result := counter;
+-- end if;
+-- return result;
+-- end counter2addr;
+
+ function counter2addr(
+ counter : std_logic_vector;
+ mask1:std_logic_vector;
+ mask2:std_logic_vector
+ ) return std_logic_vector is
+ variable result :std_logic_vector(counter'range);
+ begin
+ for n in mask1'range loop
+ if mask1(n)='1' then
+ result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
+ elsif mask2(n)='1' and n/=STAGE-1 then
+ result( 2*n+1 downto 2*n ):=counter( 2*n+3 downto 2*n+2 );
+ else
+ result( 2*n+1 downto 2*n ):=counter( 2*n+1 downto 2*n );
+ end if;
+ end loop;
+ return result;
+ end counter2addr;
+
+
+signal rstate,wstate,state:std_logic_vector( 3 downto 0 );
+signal rmask1,rmask2,wmask1,wmask2:std_logic_vector( STAGE-1 downto 0 );
+signal counter,wcounter,rcounter:std_logic_vector( STAGE*2-1 downto 0 );
+signal outcounter:std_logic_vector( STAGE*2 downto 0 );
+
+constant FFTDELAY:integer:=12+2*STAGE;
+constant FACTORDELAY:integer:=6;
+constant OUTDELAY:integer:=7;
+
+
+
+begin
+outdataen<=outcounter(STAGE*2);
+
+count:process( clk, rst )
+begin
+ if rst='1' then
+ counter<=( others=>'0' );
+ state<=CONV_STD_LOGIC_VECTOR( STAGE+1,4);
+ elsif clk'event and clk='1' then
+ if start='1' then
+ counter<=( others=>'0' );
+ state<=(others=>'0');
+ elsif unsigned(state)/=STAGE+1 then
+ counter<=unsigned(counter)+1;
+ if signed(counter)=-1 then
+ state<=unsigned(state)+1;
+ end if;
+ end if;
+ end if;
+end process count;
+
+readaddr:process( clk,rst )
+begin
+ if rst='1' then
+ raddr<=( others=>'0' );
+ rcounter<=( others=>'0' );
+ rstate<=( others=>'0' );
+ rmask1<=( others=>'0' );
+ rmask2<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ if unsigned(state)=0 and signed(counter)=-1 then
+ rmask1(STAGE-1)<='1';
+ rmask1(STAGE-2 downto 0)<=(others=>'0');
+ rmask2(STAGE-1)<='0';
+ rmask2(STAGE-2 downto 0)<=(others=>'1');
+ elsif signed(counter)=-1 then
+ rmask1<='0'&rmask1( STAGE-1 downto 1 );
+ rmask2<='0'&rmask2( STAGE-1 downto 1 );
+ end if;
+ if unsigned(state)/=STAGE+1 and signed(counter)=-1 then
+ rcounter<=( others=>'0' );
+ rstate<=state;
+ else
+ rcounter<=unsigned(rcounter)+1;
+ end if;
+ raddr<=counter2addr( rcounter, rmask1, rmask2 );
+-- modified for point configurable
+-- case rstate is
+-- when "000" =>
+-- raddr<=rcounter( 1 downto 0 )&rcounter( 9 downto 2);
+-- when "001" =>
+-- raddr<=rcounter( 9 downto 8 )&rcounter( 1 downto 0 )&rcounter( 7 downto 2);
+-- when "010" =>
+-- raddr<=rcounter( 9 downto 6 )&rcounter( 1 downto 0 )&rcounter( 5 downto 2);
+-- when "011" =>
+-- raddr<=rcounter( 9 downto 4 )&rcounter( 1 downto 0 )&rcounter( 3 downto 2);
+-- when "100" =>
+-- raddr<=rcounter( 9 downto 2 )&rcounter( 1 downto 0 );
+-- when others =>
+-- raddr<=( others=> '0' );
+-- end case;
+ end if;
+end process readaddr;
+
+writeaddr:process( clk,rst )
+begin
+ if rst='1' then
+ waddr<=( others=>'0' );
+ wcounter<=( others=>'0' );
+ wstate<=( others=>'0' );
+ wmask1<=( others=>'0' );
+ wmask2<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ if unsigned(state)=0 then
+ waddr<=counter;
+ else
+ if UNSIGNED(rstate)=0 and unsigned(rcounter)=FFTDELAY-1 then
+ wmask1(STAGE-1)<='1';
+ wmask1(STAGE-2 downto 0)<=(others=>'0');
+ wmask2(STAGE-1)<='0';
+ wmask2(STAGE-2 downto 0)<=(others=>'1');
+ elsif unsigned(rcounter)=FFTDELAY-1 then
+ wmask1<='0'&wmask1( STAGE-1 downto 1 );
+ wmask2<='0'&wmask2( STAGE-1 downto 1 );
+ end if;
+ if UNSIGNED(rstate)'0' );
+ wstate<=rstate;
+ else
+ wcounter<=unsigned(wcounter)+1;
+ end if;
+ waddr<=counter2addr( wcounter, wmask1, wmask2 );
+-- modified for point configurable
+-- case wstate is
+-- when "000" =>
+-- waddr<=wcounter( 1 downto 0 )&wcounter( 9 downto 2);
+-- when "001" =>
+-- waddr<=wcounter( 9 downto 8 )&wcounter( 1 downto 0 )&wcounter( 7 downto 2);
+-- when "010" =>
+-- waddr<=wcounter( 9 downto 6 )&wcounter( 1 downto 0 )&wcounter( 5 downto 2);
+-- when "011" =>
+-- waddr<=wcounter( 9 downto 4 )&wcounter( 1 downto 0 )&wcounter( 3 downto 2);
+-- when others =>
+-- waddr<=( others=> '0' );
+-- end case;
+ end if;
+ end if;
+end process writeaddr;
+
+writeen : process( clk, rst )
+begin
+ if rst='1' then
+ wen<='0';
+ elsif clk'event and clk='1' then
+ if unsigned(state)=0 then
+ wen<='1';
+ elsif unsigned(state)=1 and unsigned(counter)=0 then
+ wen<='0';
+ elsif unsigned(rstate)=0 and unsigned(rcounter)=FFTDELAY then
+ wen<='1';
+ elsif unsigned(rstate)=STAGE-1 and unsigned(rcounter)=FFTDELAY then
+ wen<='0';
+ end if;
+ end if;
+end process writeen;
+
+otherstart : process( clk, rst )
+begin
+ if rst='1' then
+ factorstart<='0';
+ cfft4start<='0';
+ outcounter<=(others=>'0');
+ inputbusy<='0';
+ elsif clk'event and clk='1' then
+ if start='1' then
+ inputbusy<='1';
+ elsif unsigned(state)=STAGE and unsigned(counter)=FFTDELAY then
+ inputbusy<='0';
+ end if;
+ if unsigned(state)=1 and unsigned(counter)=0 then
+ cfft4start<='1';
+ else
+ cfft4start<='0';
+ end if;
+ if unsigned(rstate)=0 and unsigned(rcounter)=FACTORDELAY then
+ factorstart<='1';
+ else
+ factorstart<='0';
+ end if;
+ if unsigned(state)=STAGE and unsigned(rcounter)=OUTDELAY then
+ outcounter<=CONV_STD_LOGIC_VECTOR(POINT,2*STAGE+1);
+ elsif outcounter(STAGE*2)='1' then
+ outcounter<=unsigned(outcounter)+1;
+ end if;
+ end if;
+end process otherstart;
+
+datasel : process( clk,rst )
+begin
+ if rst='1' then
+ wdataI<=( others=>'0' );
+ wdataQ<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ if unsigned(state)=0 then
+ wdataI<=Iin;
+ wdataQ<=Qin;
+ else
+ wdataI<=fftI;
+ wdataQ<=fftQ;
+ end if;
+ end if;
+end process datasel;
+
+end address;
Index: implementaciones/fft/pkg/cfft/tags/arelease/src/div4limit.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/src/div4limit.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/src/div4limit.vhd (revision 396)
@@ -0,0 +1,63 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : div4limit
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : div4limit.vhd
+-- Generated : Tue Jul 16 10:39:17 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Div 4 Limit to 12 bit
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity div4limit is
+ generic (
+ WIDTH : Natural
+ );
+ port(
+ clk : in std_logic;
+ D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
+ Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+ );
+end div4limit;
+
+architecture div4limit of div4limit is
+begin
+
+process( clk )
+variable Temp_D:std_logic_vector( WIDTH+1 downto 0 );
+begin
+ if clk'event and clk='1' then
+ Temp_D:=D( WIDTH+3 downto 2 )+D(1);
+ if Temp_D(WIDTH+1)='1' and Temp_D(WIDTH downto WIDTH-1)/="11" then
+ Temp_D(WIDTH+1 downto WIDTH-1):="111";
+ Temp_D(WIDTH-2 downto 1):=( others=>'0' );
+ Temp_D(0):='1';
+ elsif Temp_D(WIDTH+1)='0' and Temp_D(WIDTH downto WIDTH-1)/="00" then
+ Temp_D(WIDTH+1 downto WIDTH-1):="000";
+ Temp_D(WIDTH-2 downto 0):=( others=>'1' );
+ end if;
+ Q<=Temp_D(WIDTH-1 downto 0 );
+ end if;
+end process;
+
+end div4limit;
Index: implementaciones/fft/pkg/cfft/tags/arelease/src/p2r_cordic.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/src/p2r_cordic.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/src/p2r_cordic.vhd (revision 396)
@@ -0,0 +1,131 @@
+--
+-- VHDL implementation of cordic algorithm
+--
+-- File: p2r_cordic.vhd
+-- author: Richard Herveille
+-- rev. 1.0 initial release
+--
+
+--
+--
+-- This file is come from www.opencores.org
+--
+-- It has been modified by zhaom to enable 20 bit phase input
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Title : p2r_cordic
+-- Design : cfft
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : p2r_cordic.vhd
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Cordic arith pilepline
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity p2r_cordic is
+ generic(
+ PIPELINE : integer := 15;
+ WIDTH : integer := 16);
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+
+ Xi : in signed(WIDTH -1 downto 0);
+ Yi : in signed(WIDTH -1 downto 0) := (others => '0');
+ Zi : in signed(19 downto 0);
+
+ Xo : out signed(WIDTH -1 downto 0);
+ Yo : out signed(WIDTH -1 downto 0)
+ );
+end entity p2r_Cordic;
+
+
+architecture dataflow of p2r_cordic is
+
+ --
+ -- TYPE defenitions
+ --
+ type XYVector is array(PIPELINE downto 0) of signed(WIDTH -1 downto 0);
+ type ZVector is array(PIPELINE downto 0) of signed(19 downto 0);
+
+ --
+ -- COMPONENT declarations
+ --
+ component p2r_CordicPipe
+ generic(
+ WIDTH : natural := 16;
+ PIPEID : natural := 1
+ );
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+
+ Xi : in signed(WIDTH -1 downto 0);
+ Yi : in signed(WIDTH -1 downto 0);
+ Zi : in signed(19 downto 0);
+
+ Xo : out signed(WIDTH -1 downto 0);
+ Yo : out signed(WIDTH -1 downto 0);
+ Zo : out signed(19 downto 0)
+ );
+ end component p2r_CordicPipe;
+
+ --
+ -- SIGNALS
+ --
+ signal X, Y : XYVector;
+ signal Z : ZVector;
+
+ --
+ -- ACHITECTURE BODY
+ --
+begin
+ -- fill first nodes
+
+ -- fill X
+ X(0) <= Xi;
+
+ -- fill Y
+ Y(0) <= Yi;
+
+ -- fill Z
+ Z(0)(19 downto 0) <= Zi; -- modified by zhaom
+ --Z(0)(3 downto 0) <= (others => '0'); -- modified by zhaom
+
+ --
+ -- generate pipeline
+ --
+ gen_pipe:
+ for n in 1 to PIPELINE generate
+ Pipe: p2r_CordicPipe
+ generic map(WIDTH => WIDTH, PIPEID => n -1)
+ port map ( clk, ena, X(n-1), Y(n-1), Z(n-1), X(n), Y(n), Z(n) );
+ end generate gen_pipe;
+
+ --
+ -- assign outputs
+ --
+ Xo <= X(PIPELINE);
+ Yo <= Y(PIPELINE);
+end dataflow;
+
+
Index: implementaciones/fft/pkg/cfft/tags/arelease/src/cfft4.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/src/cfft4.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/src/cfft4.vhd (revision 396)
@@ -0,0 +1,128 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : cfft4
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : cfft4.vhd
+-- Generated : Wed Oct 2 15:49:06 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : 4 point fft
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_SIGNED.all;
+
+
+entity cfft4 is
+ generic (
+ WIDTH : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ start : in STD_LOGIC;
+ inv : in std_logic;
+ I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
+ Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
+ );
+end cfft4;
+
+
+architecture cfft4 of cfft4 is
+type RegAtype is array (3 downto 0) of std_logic_vector(WIDTH-1 downto 0);
+type RegBtype is array (3 downto 0) of std_logic_vector(WIDTH downto 0);
+
+signal counter : std_logic_vector( 1 downto 0 ):="00";
+signal RegAI,RegAQ : RegAtype;
+signal RegBI,RegBQ : RegBtype;
+begin
+
+
+count:process( clk,rst )
+begin
+ if rst='1' then
+ counter<="00";
+ elsif clk'event and clk='1' then
+ if start='1' then
+ counter<="00";
+ else
+ counter<=counter+1;
+ end if;
+ end if;
+end process count;
+
+
+-------------------------------------------------------------------------
+--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)--
+--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
+--2 rA(2)<=A2 B1<=rB(1)+rB(3)--
+--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)--
+-------------------------------------------------------------------------
+calculate:process( clk )
+begin
+ if clk'event and clk='1' then
+ case counter is
+--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)--
+ when "00" =>
+ RegAI(0)<=I;
+ RegAQ(0)<=Q;
+ RegBI(1)<=SXT(RegAI(0),WIDTH+1)-SXT(RegAI(2),WIDTH+1);
+ RegBQ(1)<=SXT(RegAQ(0),WIDTH+1)-SXT(RegAQ(2),WIDTH+1);
+ RegBI(2)<=SXT(RegAI(1),WIDTH+1)+SXT(RegAI(3),WIDTH+1);
+ RegBQ(2)<=SXT(RegAQ(1),WIDTH+1)+SXT(RegAQ(3),WIDTH+1);
+ Iout<=SXT(RegBI(1),WIDTH+2)-SXT(RegBI(3),WIDTH+2);
+ Qout<=SXT(RegBQ(1),WIDTH+2)-SXT(RegBQ(3),WIDTH+2);
+--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
+ when "01" =>
+ RegAI(1)<=I;
+ RegAQ(1)<=Q;
+ if inv='0' then
+ -- for fft *(-j)
+ RegBI(3)<=SXT(RegAQ(1),WIDTH+1)-SXT(RegAQ(3),WIDTH+1);
+ RegBQ(3)<=SXT(RegAI(3),WIDTH+1)-SXT(RegAI(1),WIDTH+1);
+ else
+ -- for fft *(j)
+ RegBI(3)<=SXT(RegAQ(3),WIDTH+1)-SXT(RegAQ(1),WIDTH+1);
+ RegBQ(3)<=SXT(RegAI(1),WIDTH+1)-SXT(RegAI(3),WIDTH+1);
+ end if;
+ Iout<=SXT(RegBI(0),WIDTH+2)+SXT(RegBI(2),WIDTH+2);
+ Qout<=SXT(RegBQ(0),WIDTH+2)+SXT(RegBQ(2),WIDTH+2);
+--2 rA(2)<=A2 B1<=rB(1)+rB(3)--
+ when "10" =>
+ RegAI(2)<=I;
+ RegAQ(2)<=Q;
+ Iout<=SXT(RegBI(1),WIDTH+2)+SXT(RegBI(3),WIDTH+2);
+ Qout<=SXT(RegBQ(1),WIDTH+2)+SXT(RegBQ(3),WIDTH+2);
+--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)--
+ when "11" =>
+ RegAI(3)<=I;
+ RegAQ(3)<=Q;
+ RegBI(0)<=SXT(RegAI(0),WIDTH+1)+SXT(RegAI(2),WIDTH+1);
+ RegBQ(0)<=SXT(RegAQ(0),WIDTH+1)+SXT(RegAQ(2),WIDTH+1);
+ Iout<=SXT(RegBI(0),WIDTH+2)-SXT(RegBI(2),WIDTH+2);
+ Qout<=SXT(RegBQ(0),WIDTH+2)-SXT(RegBQ(2),WIDTH+2);
+ when others => null;
+ end case;
+ end if;
+end process calculate;
+end cfft4;
Index: implementaciones/fft/pkg/cfft/tags/arelease/src/sc_corproc.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/src/sc_corproc.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/src/sc_corproc.vhd (revision 396)
@@ -0,0 +1,100 @@
+--
+-- This file is come from www.opencores.org
+--
+-- It has been modified by ZHAO Ming for 20 bit complex rotation
+--
+
+---------------------------------------------------------------------------------------------------
+--
+-- Title : sc_corproc
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : sc_corproc.vhd
+-- Generated : Tue Jul 16 10:39:17 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : complex rotation
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.0
+-- Date : Oct 18 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_signed.all;
+
+entity sc_corproc is
+ generic (
+ WIDTH : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+ Xin : in signed(WIDTH+1 downto 0);
+ Yin : in signed(WIDTH+1 downto 0);
+ Ain : in signed(2*STAGE-3 downto 0 );
+
+ sin : out signed(WIDTH+3 downto 0);
+ cos : out signed(WIDTH+3 downto 0)
+ );
+end entity sc_corproc;
+
+architecture dataflow of sc_corproc is
+ constant PipeLength : natural := 2*STAGE+2;
+
+ component p2r_cordic is
+ generic(
+ PIPELINE : integer := 15;
+ WIDTH : integer := 16);
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+
+ Xi : in signed(WIDTH -1 downto 0);
+ Yi : in signed(WIDTH -1 downto 0) := (others => '0');
+ Zi : in signed(19 downto 0);
+
+ Xo : out signed(WIDTH -1 downto 0);
+ Yo : out signed(WIDTH -1 downto 0)
+ );
+ end component p2r_cordic;
+signal phase:signed( 19 downto 0 );
+signal Xi,Yi:signed( WIDTH+7 downto 0 );
+signal Xo,Yo:signed( WIDTH+7 downto 0 );
+signal zeros:signed( 19-STAGE*2 downto 0 );
+begin
+ Xi<= Xin(WIDTH+1)&Xin&"00000";
+ Yi<= Yin(WIDTH+1)&Yin&"00000";
+ zeros<=(others=>'0');
+ phase<="00"&Ain&zeros;
+ cos<=Xo(WIDTH+7)&Xo( WIDTH+7 downto 5 );
+ sin<=Yo(WIDTH+7)&Yo( WIDTH+7 downto 5 );
+
+ u1: p2r_cordic
+ generic map(PIPELINE => PipeLength, WIDTH => WIDTH+8)
+ port map(clk => clk, ena => ena, Xi => Xi, Yi=>Yi,Zi => phase, Xo => Xo, Yo => Yo);
+end architecture dataflow;
Index: implementaciones/fft/pkg/cfft/tags/arelease/src/mulfactor.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/src/mulfactor.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/src/mulfactor.vhd (revision 396)
@@ -0,0 +1,126 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : mulfactor
+-- Design : cfft
+-- Author : ZHAO Ming
+-- email : sradio@opencores.org
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : mulfactor.vhd
+-- Generated : Thu Oct 3 00:37:40 2002
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : 360 degee complex rotation
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Oct 17 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Data width configurable
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 2
+-- Version : 1.2.1
+-- Date : Oct 18 2002
+-- Modifier : ZHAO Ming
+-- Desccription : Point configurable
+--
+---------------------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_SIGNED.all;
+
+entity mulfactor is
+ generic (
+ WIDTH : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ angle : in signed(2*STAGE-1 downto 0);
+ I : in signed(WIDTH+1 downto 0);
+ Q : in signed(WIDTH+1 downto 0);
+ Iout : out signed(WIDTH+3 downto 0);
+ Qout : out signed(WIDTH+3 downto 0)
+ );
+end mulfactor;
+
+
+architecture mulfactor of mulfactor is
+signal phase : signed( 2*STAGE-3 downto 0 );
+signal Xi,Yi : signed( WIDTH+1 downto 0 );
+component sc_corproc
+ generic(
+ WIDTH : Natural;
+ STAGE : Natural
+ );
+ port(
+ clk : in std_logic;
+ ena : in std_logic;
+ Xin : in signed(WIDTH+1 downto 0);
+ Yin : in signed(WIDTH+1 downto 0);
+ Ain : in signed(2*STAGE-3 downto 0 );
+
+ sin : out signed(WIDTH+3 downto 0);
+ cos : out signed(WIDTH+3 downto 0));
+end component;
+
+begin
+
+ u1: sc_corproc
+ generic map(
+ WIDTH=>WIDTH,
+ STAGE=>STAGE
+ )
+ port map (
+ clk=>clk,
+ ena=>'1',
+ Xin=>Xi,
+ Yin=>Yi,
+ Ain=>phase,
+
+ sin=>Qout,
+ cos=>Iout
+ );
+
+process( clk, rst )
+variable temp : std_logic_vector( 1 downto 0 );
+begin
+ if rst='1' then
+ phase<=( others=>'0' );
+ Xi<=( others=>'0' );
+ Yi<=( others=>'0' );
+ elsif clk'event and clk='1' then
+ phase<=angle( 2*STAGE-3 downto 0 );
+ temp:=std_logic_vector(angle( 2*STAGE-1 downto 2*STAGE-2 ));
+ case temp is
+ when "00" =>
+ Xi<=I;
+ Yi<=Q;
+ when "01" =>
+ Xi<=0-Q;
+ Yi<=I;
+ when "10" =>
+ Xi<=0-I;
+ Yi<=0-Q;
+ when "11" =>
+ Xi<=Q;
+ Yi<=0-I;
+ when others=>
+ null;
+ end case;
+ end if;
+end process;
+
+end mulfactor;
Index: implementaciones/fft/pkg/cfft/tags/arelease/src/blockdram.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/src/blockdram.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/src/blockdram.vhd (revision 396)
@@ -0,0 +1,68 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : blockram
+-- Design : cfft
+-- Author : MENG Lin
+-- email :
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : blockram.vhd
+-- Generated : unknown
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description : Dual port ram
+--
+---------------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library synplify;
+use synplify.attributes.all;
+
+entity blockdram is
+generic(
+ depth: integer;
+ Dwidth: integer;
+ Awidth: integer
+);
+port(
+ addra: IN std_logic_VECTOR(Awidth-1 downto 0);
+ clka: IN std_logic;
+ addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
+ clkb: IN std_logic;
+ dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
+ wea: IN std_logic;
+ dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
+end blockdram;
+
+architecture arch_blockdram of blockdram is
+
+type ram_memtype is array (depth-1 downto 0) of std_logic_vector
+ (Dwidth-1 downto 0);
+signal mem : ram_memtype := (others => (others => '0'));
+attribute syn_ramstyle of mem : signal is "block_ram";
+
+signal addrb_reg: std_logic_vector(Awidth-1 downto 0);
+
+begin
+ wr: process( clka )
+ begin
+ if rising_edge(clka) then
+ if wea = '1' then
+ mem(conv_integer(addra)) <= dia;
+ end if;
+ end if;
+ end process wr;
+
+ rd: process( clkb )
+ begin
+ if rising_edge(clkb) then
+ addrb_reg <= addrb;
+ end if;
+ end process rd;
+ dob <= mem(conv_integer(addrb_reg));
+end arch_blockdram;
+
Index: implementaciones/fft/pkg/cfft/tags/arelease/sim/tb_cfft1024x12.vhd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/sim/tb_cfft1024x12.vhd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/sim/tb_cfft1024x12.vhd (revision 396)
@@ -0,0 +1,165 @@
+---------------------------------------------------------------------------------------------------
+--
+-- Title : test bench
+-- Design : cfft
+-- Author : henning larsen
+-- email :
+--
+---------------------------------------------------------------------------------------------------
+--
+-- File : tb_cfft1024x12.vhd
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Description :
+--
+-- Simple "testbench" for cfft1024x12. It is realy just an excitation of inputs
+-- The output has to be evaluated manually. run for 125 us with current settings.
+-- Input is a dual sinsoid with constant amplitudes, and a DC value.
+-- Input is real valued only. A calculation of the power spectrum, and a frequency bin
+-- counter is included, but no reordering of output sequence is performed.
+-- Frequencies are easy to select such that a minimum of spill into side bins is obtained.
+-- Beware of the posibilty of saturation in the output. For single sinsoide,the saturation limit
+-- is 2^14/29.4=557 units of input amplitude.
+--
+-- henning larsen
+--
+---------------------------------------------------------------------------------------------------
+--
+-- Revisions : 0
+-- Revision Number : 1
+-- Version : 1.1.0
+-- Date : Nov 21 2002
+-- Modifier : ZHAO Ming
+-- Desccription : init release
+-- compare output position
+--
+---------------------------------------------------------------------------------------------------
+
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.math_real.all;
+USE ieee.std_logic_signed.all;
+
+ENTITY cfft1024x12_tester1 IS
+END cfft1024x12_tester1 ;
+ARCHITECTURE tester OF cfft1024x12_tester1 IS
+ -- Component Declarations
+ COMPONENT cfft1024X12
+ PORT (
+ clk : IN STD_LOGIC ;
+ rst : IN STD_LOGIC ;
+ start : IN STD_LOGIC ;
+ inv : IN std_logic ;
+ Iin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+ Qin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+ inputbusy : OUT STD_LOGIC ;
+ outdataen : OUT STD_LOGIC ;
+ Iout : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ Qout : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
+ OutPosition : out STD_LOGIC_VECTOR( 9 downto 0 )
+ );
+ END COMPONENT;
+
+ constant Tck_half : time:=10 ns;
+ constant Tckhalf : real:=10.0e-9;-- real value eqv of time, there is some conversion function
+ -- for this but could not find/remember.
+ constant ampl1 : real:=100.0;-- max amplitude is roughly 550=2^14/29.4 to avoid sturation in output
+ constant ampl2 : real:=200.0; -- .. but see intro comments
+ constant f1 : real := 100.0/TckHalf/2.0/1024.0;-- bin number =100
+ constant f2 : real := 33.0/TckHalf/2.0/1024.0;-- bin number =33
+ constant dc : real:=100.0;--bin number=0
+
+ signal c1,c2,cout: real;
+ signal clock : std_logic:='0';
+ signal reset : std_logic:='0';
+ signal start : std_logic:='0';
+ signal inv : std_logic ;
+ signal Iin : STD_LOGIC_VECTOR (11 DOWNTO 0);
+ signal Qin : STD_LOGIC_VECTOR (11 DOWNTO 0);
+ signal inputbusy : STD_LOGIC:='0' ;
+ signal outdataen : STD_LOGIC:='0' ;
+ signal Iout : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ signal Qout : STD_LOGIC_VECTOR (13 DOWNTO 0);
+ signal amp : real; -- power spectrum
+ signal bitRev : STD_LOGIC_VECTOR (9 DOWNTO 0);-- bin counter
+ signal OutPosition : STD_LOGIC_VECTOR( 9 downto 0 );
+
+BEGIN
+ -- Instance port mappings.
+ I0 : cfft1024X12
+ PORT MAP (
+ clk => clock,
+ rst => reset,
+ start => start,
+ inv => inv,
+ Iin => Iin,
+ Qin => Qin,
+ inputbusy => inputbusy,
+ outdataen => outdataen,
+ Iout => Iout,
+ Qout => Qout,
+ OutPosition => OutPosition
+ );
+
+----------------------------------------------------------------------------
+--
+-- control signals ,setup
+clock <= not clock after Tck_half;
+reset <= '1', '0' after 2*Tck_half;
+start <= '0', '1' after 3*Tck_half, '0' after 5*Tck_half;-- only one FFT is done
+inv <= '0';-- FFT
+
+----------------------------------------------------------------------------
+--
+sin_gen: process(clock, reset)
+ variable tid : real;
+ variable TM : real :=0.0 ;
+ begin
+ if Reset = '1' then
+ c1 <= 0.0;
+ c2 <= 0.0;
+ Iin<="000000000000" ;
+ Qin<="000000000000" ;
+ TM := 0.0;
+ tid := TM;
+ else
+ if clock'event and clock = '1' then
+ TM := TM + Tckhalf*2.0;
+ tid := TM;
+ c1 <= (ampl1 * sin(2.0*math_pi*f1*tid));
+ c2 <= (ampl2 * sin(2.0*math_pi*f2*tid));
+ cout <= c1+c2+dc;
+ Iin <= conv_std_logic_vector(integer(cout),Iin'length);
+ Qin <="000000000000" ;
+ end if;
+ end if;
+ end process sin_gen;
+----------------------------------------------------------------------------
+--
+--Output power spectrum, normalized with the gain of 29.4
+amp <= sqrt(real(CONV_integer(Iout)) * real(CONV_integer(Iout))
+ + real(CONV_integer(Qout)) * real(CONV_integer(Qout)))/29.4;
+----------------------------------------------------------------------------
+--
+-- radix 4 bit reversed counter
+radix4cnt: process (clock)
+variable cntr: std_logic_vector ( 9 downto 0);
+begin
+ if rising_edge(clock) then
+ if outdataen='1' then
+ cntr:=unsigned(cntr)+1;
+ else
+ cntr:=(others => '0');
+ end if;
+ for k in 1 to ((10) / 2) loop
+ bitRev(2*k-2)<= cntr(10-2*k);
+ bitRev(2*k-1)<= cntr(10-(-1+2*k));
+ end loop;
+ end if;
+end process radix4cnt;
+
+END tester;
Index: implementaciones/fft/pkg/cfft/tags/arelease/cfft.vsd
===================================================================
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Index: implementaciones/fft/pkg/cfft/tags/arelease/cfft.vsd
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/cfft.vsd (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/cfft.vsd (revision 396)
implementaciones/fft/pkg/cfft/tags/arelease/cfft.vsd
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+application/octet-stream
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Index: implementaciones/fft/pkg/cfft/tags/arelease/cfft_e.pdf
===================================================================
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Index: implementaciones/fft/pkg/cfft/tags/arelease/cfft_e.pdf
===================================================================
--- implementaciones/fft/pkg/cfft/tags/arelease/cfft_e.pdf (nonexistent)
+++ implementaciones/fft/pkg/cfft/tags/arelease/cfft_e.pdf (revision 396)
implementaciones/fft/pkg/cfft/tags/arelease/cfft_e.pdf
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+application/octet-stream
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