URL
https://opencores.org/ocsvn/phr/phr/trunk
Subversion Repositories phr
Compare Revisions
- This comparison shows the changes necessary to convert path
/phr/trunk/codigo
- from Rev 396 to Rev 408
- ↔ Reverse comparison
Rev 396 → Rev 408
/implementaciones/fftProject06/python/fftmemdata.py
0,0 → 1,20
#!/usr/bin/env python |
# -*- coding: utf-8 -*- |
|
import math |
|
decimal = 16 |
|
maximo = 0 |
|
for a in range (-64,64): |
for b in range (-62,64): |
mod = math.sqrt(math.pow(a*1.0/decimal,2)+math.pow(b*1.0/decimal,2))*32 |
print 'a=',a*1.0/decimal,'b=',b*1.0/decimal, 'mod=', mod*1.0/32 |
print 'a=',a, 'b=',b, 'mod=', int(round(mod)), '(0x{0:02x})'.format(int(round(mod))) |
print "" |
|
if mod>maximo: |
maximo = mod |
|
print "\nEl maximo es:", maximo |
implementaciones/fftProject06/python/fftmemdata.py
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/python/fftmemdatavhd.py
===================================================================
--- implementaciones/fftProject06/python/fftmemdatavhd.py (nonexistent)
+++ implementaciones/fftProject06/python/fftmemdatavhd.py (revision 408)
@@ -0,0 +1,44 @@
+#!/usr/bin/env python
+# -*- coding: utf-8 -*-
+
+import math
+import sys
+
+#decimal = 16
+
+values_count = 0
+lines_count = 0
+
+#values = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
+
+value = []
+
+spectrum = range(64) + range (-64,0)
+
+sys.stdout.write('\n\nNew memory block (00) ----------------\n')
+
+for a in spectrum :
+ for b in spectrum :
+ mag = math.sqrt(math.pow(a*1.0/4,2)+math.pow(b*1.0/4,2))*4
+
+ value = value + [mag]
+ values_count = values_count + 1
+
+ if values_count % 32 == 0:
+ sys.stdout.write(' INIT_{0:02x} => x"'.format(lines_count%64))
+ for i in range (31,-1,-1):
+ sys.stdout.write('{0:02x}'.format(int(round(value[i]))))
+ sys.stdout.write('",\n')
+
+ value = []
+
+ lines_count = lines_count + 1
+ if lines_count % 64 == 0:
+ sys.stdout.write('\n\nNew memory block ({0:02x}) ----------------\n'.format(lines_count/64))
+
+
+
+# print 'a=',a*1.0/decimal,'b=',b*1.0/decimal, 'mod=', mod*1.0/decimal
+# print 'a=',a, 'b=',b, 'mod=', int(round(mod)), '(0x{0:02x})'.format(int(round(mod)))
+# print ""
+
implementaciones/fftProject06/python/fftmemdatavhd.py
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/top.vhd
===================================================================
--- implementaciones/fftProject06/top.vhd (nonexistent)
+++ implementaciones/fftProject06/top.vhd (revision 408)
@@ -0,0 +1,242 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.vgapack.all;
+use work.fftpack.all;
+
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+ Port (
+ clock : in STD_LOGIC;
+ slow_clock : in std_logic;
+ reset : in STD_LOGIC;
+
+ sw : in std_logic_vector (7 downto 0);
+
+ display_char : out STD_LOGIC_VECTOR (3 downto 0);
+ display_seg : out STD_LOGIC_VECTOR (6 downto 0);
+
+ pmod_sdata1 : in std_logic;
+ pmod_sdata2 : in std_logic;
+ pmod_sclk : out std_logic;
+ pmod_ncs : out std_logic;
+
+ vgaHsync : out std_logic;
+ vgaVsync : out std_logic;
+ vgaRed : out std_logic;
+ vgaGreen : out std_logic;
+ vgaBlue : out std_logic);
+end top;
+
+architecture Behavioral of top is
+
+ COMPONENT sevseg_display
+ PORT(
+ clock : IN std_logic;
+ reset : IN std_logic;
+ data : IN std_logic_vector(15 downto 0);
+ segments : OUT std_logic_vector(6 downto 0);
+ char_sel : OUT std_logic_vector(3 downto 0)
+ );
+ END COMPONENT;
+
+ component adq
+ port (
+ clock : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ pmod_sdata1 : in std_logic;
+ pmod_sdata2 : in std_logic;
+ pmod_sclk : out std_logic;
+ pmod_ncs : out std_logic;
+ samples : out fftsamples);
+ end component;
+
+
+ component fft
+ Port (
+ iSamples : in fftsamples;
+ offtr : out fftsamples;
+ offti : out fftsamples);
+ end component;
+
+ component clocking
+ Port (
+ clock : in STD_LOGIC;
+ reset : in std_logic;
+ clk50M : out std_logic;
+ clk : out quadClock_type);
+ end component;
+
+ COMPONENT vgaController
+ Port (
+ clk : in quadClock_type;
+ reset : IN std_logic;
+ secuencia : in vga_samples_vector_type;
+ hsync : out STD_LOGIC;
+ vsync : out STD_LOGIC;
+ vgaRed : out STD_LOGIC;
+ vgaGreen : out STD_LOGIC;
+ vgaBlue : out STD_LOGIC);
+ END COMPONENT;
+
+ COMPONENT magComp
+ Port (
+ clk : in quadClock_type;
+ reset : in STD_LOGIC;
+ realInput : in fftMag_samples_vector_type;
+ imagInput : in fftMag_samples_vector_type;
+ magOutput : out fftMag_samples_vector_type);
+ END COMPONENT;
+
+
+ signal fftMag_input1 : fftMag_samples_vector_type;
+ signal fftMag_input2 : fftMag_samples_vector_type;
+ signal fftMag_output : fftMag_samples_vector_type;
+
+ signal mag_vga_samples_vector : vga_samples_vector_type;
+
+ -- clock
+ signal clk : quadClock_type;
+ signal clk50M : std_logic;
+
+ --fft
+ signal iSamples : fftsamples;
+ signal fftoutRe : fftsamples;
+ signal fftoutIm : fftsamples;
+
+ --seven segments display
+ signal sevdisplaydata : std_logic_vector(15 downto 0);
+
+
+begin
+
+
+--- input samples -----------------------------
+--process (sw)
+--begin
+-- for ii in 0 to 7 loop
+-- case sw(ii) is
+-- when '0' => isamples (ii) <= to_signed (0, RegisterLenght);
+-- when '1' => isamples (ii) <= to_signed (31, RegisterLenght);
+-- when others => isamples (ii) <= to_signed (0, RegisterLenght);
+-- end case;
+-- end loop;
+--end process;
+
+
+-- isamples (0) <= to_signed (0, RegisterLenght);
+-- isamples (1) <= to_signed (32, RegisterLenght);
+-- isamples (2) <= to_signed (0, RegisterLenght);
+-- isamples (3) <= to_signed (32, RegisterLenght);
+-- isamples (4) <= to_signed (0, RegisterLenght);
+-- isamples (5) <= to_signed (32, RegisterLenght);
+-- isamples (6) <= to_signed (0, RegisterLenght);
+-- isamples (7) <= to_signed (32, RegisterLenght);
+
+ Inst_adq: adq port map (
+ clock => clk50M,
+ reset => reset,
+ pmod_sdata1 => pmod_sdata1,
+ pmod_sdata2 => pmod_sdata2,
+ pmod_sclk => pmod_sclk,
+ pmod_ncs => pmod_ncs,
+ samples => iSamples
+ );
+
+ Inst_sevseg_display: sevseg_display PORT MAP(
+ clock => slow_clock,
+ reset => reset,
+ data => sevdisplaydata,
+ segments => display_seg,
+ char_sel => display_char
+ );
+
+ sevdisplaydata <= "000000"&std_logic_vector(iSamples(7));
+ ---------------------------------------------
+
+
+ Inst_fft: fft port map(
+ iSamples => iSamples,
+ offtr => fftoutRe,
+ offti => fftoutIm
+ );
+
+ Inst_clocking: clocking PORT MAP(
+ clock => clock,
+ reset => reset,
+ clk50M => clk50M,
+ clk => clk
+ );
+
+ fftMag_input1 <= (
+ std_logic_vector(fftoutRe(0)),
+ std_logic_vector(fftoutRe(1)),
+ std_logic_vector(fftoutRe(2)),
+ std_logic_vector(fftoutRe(3)),
+ std_logic_vector(fftoutRe(4)),
+ std_logic_vector(fftoutRe(5)),
+ std_logic_vector(fftoutRe(6)),
+ std_logic_vector(fftoutRe(7))
+ );
+
+ fftMag_input2 <= (
+ std_logic_vector(fftoutIm(0)),
+ std_logic_vector(fftoutIm(1)),
+ std_logic_vector(fftoutIm(2)),
+ std_logic_vector(fftoutIm(3)),
+ std_logic_vector(fftoutIm(4)),
+ std_logic_vector(fftoutIm(5)),
+ std_logic_vector(fftoutIm(6)),
+ std_logic_vector(fftoutIm(7))
+ );
+
+-- mag_vga_samples_vector <= ("00000","00001","00010","00011","00100","00101","00110","00111");
+-- fftMag_input1 <= (x"00", x"3f", x"7f", x"00", x"00", x"3f", x"00", x"00");
+-- fftMag_input2 <= (x"3f", x"00", x"00", x"ff", x"3f", x"00", x"00", x"00");
+
+ Inst_magComp: magComp PORT MAP(
+ clk => clk,
+ reset => reset,
+ realInput => fftMag_input1,
+ imagInput => fftMag_input2,
+ magOutput => fftMag_output
+ );
+
+
+ --type vga_samples_vector_type is array (0 to lr_col_num-1) of unsigned (4 downto 0);
+
+-- vga_input_samples_test : for k in 0 to 7 generate
+-- mag_vga_samples_vector(k) <= unsigned(iSamples(k)(9 downto 5));
+-- end generate;
+
+ vgaMagnitud: for i in mag_samples_number-1 downto 0 generate
+ mag_vga_samples_vector(i) <= unsigned (fftMag_output(i)(4 downto 0)); -- shouldd be
+-- bb bbbb bbbb
+-- b bbbb bbbb b
+-- - ---- shuld divide by 2^5=32
+-- mag_vga_samples_vector(i) <= unsigned (fftMag_output(i)(8 downto 4)); -- old
+ end generate;
+
+ Inst_vgaController: vgaController PORT MAP(
+ clk => clk,
+ reset => reset,
+ secuencia => mag_vga_samples_vector,
+ hsync => vgaHsync,
+ vsync => vgaVsync,
+ vgaRed => vgaRed,
+ vgaGreen => vgaGreen,
+ vgaBlue => vgaBlue
+ );
+
+
+
+
+end Behavioral;
+
implementaciones/fftProject06/top.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/fft_tb.vhd
===================================================================
--- implementaciones/fftProject06/fft_tb.vhd (nonexistent)
+++ implementaciones/fftProject06/fft_tb.vhd (revision 408)
@@ -0,0 +1,67 @@
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+use work.fftpack.all;
+
+
+ENTITY fft_tb IS
+END fft_tb;
+
+ARCHITECTURE behavior OF fft_tb IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT fft
+ PORT(
+ iSamples : IN fftsamples;
+ offtr : OUT fftsamples;
+ offti : OUT fftsamples
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal iSamples : fftsamples;
+
+ --Outputs
+ signal offtr : fftsamples;
+ signal offti : fftsamples;
+
+BEGIN
+
+-- isamples (0) <= to_signed (0, RegisterLenght);
+-- isamples (1) <= to_signed (16, RegisterLenght);
+-- isamples (2) <= to_signed (0, RegisterLenght);
+-- isamples (3) <= to_signed (16, RegisterLenght);
+-- isamples (4) <= to_signed (0, RegisterLenght);
+-- isamples (5) <= to_signed (16, RegisterLenght);
+-- isamples (6) <= to_signed (0, RegisterLenght);
+-- isamples (7) <= to_signed (16, RegisterLenght);
+
+ isamples (0) <= to_signed (0, RegisterLenght);
+ isamples (1) <= to_signed (0, RegisterLenght);
+ isamples (2) <= to_signed (32, RegisterLenght);
+ isamples (3) <= to_signed (32, RegisterLenght);
+ isamples (4) <= to_signed (0, RegisterLenght);
+ isamples (5) <= to_signed (0, RegisterLenght);
+ isamples (6) <= to_signed (32, RegisterLenght);
+ isamples (7) <= to_signed (32, RegisterLenght);
+ isamples (8) <= to_signed (0, RegisterLenght);
+ isamples (9) <= to_signed (0, RegisterLenght);
+ isamples (10) <= to_signed (32, RegisterLenght);
+ isamples (11) <= to_signed (32, RegisterLenght);
+ isamples (12) <= to_signed (0, RegisterLenght);
+ isamples (13) <= to_signed (0, RegisterLenght);
+ isamples (14) <= to_signed (32, RegisterLenght);
+ isamples (15) <= to_signed (32, RegisterLenght);
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: fft PORT MAP (
+ iSamples => iSamples,
+ offtr => offtr,
+ offti => offti
+ );
+
+END;
implementaciones/fftProject06/fft_tb.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/adq.vhd
===================================================================
--- implementaciones/fftProject06/adq.vhd (nonexistent)
+++ implementaciones/fftProject06/adq.vhd (revision 408)
@@ -0,0 +1,92 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.fftpack.all;
+
+entity adq is
+ Port (
+ clock : in STD_LOGIC;
+ reset : in STD_LOGIC;
+
+ pmod_sdata1 : in std_logic;
+ pmod_sdata2 : in std_logic;
+ pmod_sclk : out std_logic;
+ pmod_ncs : out std_logic;
+
+ samples : out fftsamples);
+end adq;
+
+
+architecture Behavioral of adq is
+
+ COMPONENT AD1RefComp
+ PORT(
+ CLK : IN std_logic;
+ RST : IN std_logic;
+ SDATA1 : IN std_logic;
+ SDATA2 : IN std_logic;
+ START : IN std_logic;
+ SCLK : OUT std_logic;
+ nCS : OUT std_logic;
+ DATA1 : OUT std_logic_vector(11 downto 0);
+ DATA2 : OUT std_logic_vector(11 downto 0);
+ DONE : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ signal data1 : std_logic_vector (11 downto 0) := (others => '0');
+ signal data2 : std_logic_vector (11 downto 0) := (others => '0');
+ signal convertAD : std_logic := '0';
+ signal done : std_logic;
+
+-- signal iSamples : fftsamples;
+
+begin
+
+ Inst_AD1RefComp: AD1RefComp PORT MAP(
+ CLK => clock,
+ RST => reset,
+ SDATA1 => pmod_sdata1,
+ SDATA2 => pmod_sdata2,
+ SCLK => pmod_sclk,
+ nCS => pmod_ncs,
+ DATA1 => data1,
+ DATA2 => data2,
+ START => done,
+ DONE => done
+ );
+
+ process (clock, reset)
+ variable clkCounter : integer := 0;
+ begin
+ if reset = '1' then
+ clkCounter := 0;
+ elsif rising_edge(clock) then
+ case clkCounter is
+ when 0 => clkCounter := clkCounter + 1; convertAD <= '0';
+ when 250000 => clkCounter := 0; convertAD <= '1'; --1250 implica fs=40kHz, 25000000 implica fs=2Hz
+ when others => clkCounter := clkCounter + 1;
+ end case;
+ end if;
+ end process;
+
+
+ process (convertAD, reset)
+ variable samplesVar : fftsamples := (others => (to_signed (0, RegisterLenght)));
+ begin
+ if reset = '1' then
+ samplesVar := (others => (to_signed (0, RegisterLenght)));
+ elsif falling_edge(convertAD) then
+ for jj in 0 to SN-2 loop
+ samplesVar(jj) := samplesVar(jj+1);
+ end loop;
+ samplesVar(SN-1) := "00000"&signed(data1(11 downto 7));
+ samples <= samplesVar;
+ end if;
+ end process;
+
+end Behavioral;
+
implementaciones/fftProject06/adq.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/vgacontroller_tb.vhd
===================================================================
--- implementaciones/fftProject06/vgacontroller_tb.vhd (nonexistent)
+++ implementaciones/fftProject06/vgacontroller_tb.vhd (revision 408)
@@ -0,0 +1,79 @@
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+use work.vgapack.all;
+
+
+ENTITY vgacontroller_tb IS
+END vgacontroller_tb;
+
+ARCHITECTURE behavior OF vgacontroller_tb IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT vgacontroller
+ PORT(
+ clock : IN std_logic;
+ reset : IN std_logic;
+ hsync : OUT std_logic;
+ vsync : OUT std_logic;
+ vgaRed : OUT std_logic;
+ vgaGreen : OUT std_logic;
+ vgaBlue : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clock : std_logic := '0';
+ signal reset : std_logic := '0';
+
+ --Outputs
+ signal hsync : std_logic;
+ signal vsync : std_logic;
+ signal vgaRed : std_logic;
+ signal vgaGreen : std_logic;
+ signal vgaBlue : std_logic;
+
+ -- Clock period definitions
+ constant clock_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: vgacontroller PORT MAP (
+ clock => clock,
+ reset => reset,
+ hsync => hsync,
+ vsync => vsync,
+ vgaRed => vgaRed,
+ vgaGreen => vgaGreen,
+ vgaBlue => vgaBlue
+ );
+
+ -- Clock process definitions
+ clock_process :process
+ begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+ end process;
+
+
+-- -- Stimulus process
+-- stim_proc: process
+-- begin
+-- -- hold reset state for 100 ns.
+-- reset <= '0';
+-- wait for 10 ns;
+-- reset <= '1';
+---- wait for clock_period*10;
+----
+---- -- insert stimulus here
+----
+---- wait;
+-- end process;
+
+END;
implementaciones/fftProject06/vgacontroller_tb.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/pines.ucf
===================================================================
--- implementaciones/fftProject06/pines.ucf (nonexistent)
+++ implementaciones/fftProject06/pines.ucf (revision 408)
@@ -0,0 +1,351 @@
+NET "clock" LOC = P43;
+
+NET "sw<0>" LOC = P85;
+NET "sw<1>" LOC = P88;
+NET "sw<2>" LOC = P90;
+NET "sw<3>" LOC = P94;
+NET "sw<4>" LOC = P97;
+NET "sw<5>" LOC = P4;
+NET "sw<6>" LOC = P6;
+NET "sw<7>" LOC = P9;
+
+net "pmod_sdata1" loc="P34";
+net "pmod_sdata2" loc="P32";
+net "pmod_sclk" loc="P30";
+net "pmod_ncs" loc="P46";
+
+net "slow_clock" loc="P40"; #
+
+net "display_char<3>" loc="P59";
+net "display_char<2>" loc="P57";
+net "display_char<1>" loc="P61";
+net "display_char<0>" loc="P60";
+
+net "display_seg<6>" loc="P65";
+net "display_seg<5>" loc="P64";
+net "display_seg<4>" loc="P72";
+net "display_seg<3>" loc="P70";
+net "display_seg<2>" loc="P28";
+net "display_seg<1>" loc="P62";
+net "display_seg<0>" loc="P73";
+
+NET "reset" LOC = "P77"; # BOTON 0 !!!!!!!!!!!!!!! # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+#NET "btn<1>" LOC = "P78"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
+#NET "btn<2>" LOC = "P82"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
+#NET "btn<3>" LOC = "P83"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
+
+NET "reset" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "clock" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#boton1
+#NET "reset" LOC = P77;
+#NET "hsync" LOC = P16;
+#NET "vsync" LOC = P13;
+#NET "red" LOC = P20;
+#NET "green" LOC = P19;
+#NET "blue" LOC = P15;
+
+NET "vgaHsync" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
+NET "vgaVsync" LOC = "P13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
+
+NET "vgaRed" LOC = "P20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
+NET "vgaGreen" LOC = "P19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
+NET "vgaBlue" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
+
+
+
+## VGA Connector
+
+
+
+##
+#
+#
+#
+###NET "SW0" LOC = "F12";
+##
+##NET "clock" LOC = "P43";
+##NET "reset" LOC = "P77"; #boton1
+##NET "hsync" LOC = "P16";
+##NET "vsync" LOC = "P13";
+##NET "red" LOC = "P20";
+##NET "green" LOC = "P19";
+##NET "blue" LOC = "P15";
+#
+#
+### This file is a general .ucf for Nexys2 rev A board
+### To use it in a project:
+### - remove or comment the lines corresponding to unused pins
+### - rename the used signals according to the project
+#
+### Signals Led<7>Â…Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
+### Both versions are provided in this file.
+### Keep only the appropriate one, and remove or comment the other one.
+#
+#
+### Clock pin for Nexys 2 Board
+#NET "clock" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+##NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
+#
+### onBoard USB controller
+### NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
+#
+### Data bus for both the DEPP and DSTM interfaces uncomment lines 19-26 if using either one
+##NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
+##NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
+##NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
+##NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
+##NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
+##NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
+##NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
+##NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
+#
+### If using the DEPP interface uncomment lines 29-32
+##NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
+##NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+##NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+##NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+#
+### If using the DSTM interface uncomment lines 35-44
+##NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
+##NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
+##NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+##NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+##NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
+##NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
+##NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+##NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
+##NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
+##NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
+#
+##NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
+##NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
+#
+### onBoard Cellular RAM and StrataFlash
+##NET "MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
+##NET "MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
+#
+##NET "RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
+##NET "RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
+##NET "RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
+##NET "RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
+##NET "RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
+##NET "RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
+##NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
+#
+##NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
+##NET "FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
+##NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
+#
+##NET "MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
+##NET "MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
+##NET "MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
+##NET "MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
+##NET "MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
+##NET "MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
+##NET "MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
+##NET "MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
+##NET "MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
+##NET "MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
+##NET "MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
+##NET "MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
+##NET "MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
+##NET "MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
+##NET "MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
+##NET "MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
+##NET "MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
+##NET "MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
+##NET "MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
+##NET "MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
+##NET "MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
+##NET "MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
+##NET "MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
+#
+##NET "MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
+##NET "MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
+##NET "MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
+##NET "MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
+##NET "MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
+##NET "MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
+##NET "MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
+##NET "MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
+##NET "MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
+##NET "MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
+##NET "MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
+##NET "MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
+##NET "MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
+##NET "MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
+##NET "MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
+##NET "MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
+#
+### 7 segment display
+##NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+##NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+##NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+##NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+##NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+##NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+##NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+##NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+#
+##NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+##NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+##NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+##NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+#
+### Leds
+##NET "Led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+##NET "Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+##NET "Led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+##NET "Led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+##NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+##NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+##NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+##NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+##NET "Led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
+##NET "Led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
+##NET "Led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
+##NET "Led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
+#
+### Switches
+#NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
+#NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
+#NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
+#NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
+#NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
+#NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
+#NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
+#NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+#
+### Buttons
+#NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+#NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
+#NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
+#NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
+#
+#NET "btn<3>" CLOCK_DEDICATED_ROUTE = FALSE;
+### VGA Connector
+#NET "vgaRed<1>" LOC = "R9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
+#NET "vgaRed<2>" LOC = "T8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
+#NET "vgaRed<3>" LOC = "R8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
+#NET "vgaGreen<1>" LOC = "N8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
+#NET "vgaGreen<2>" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
+#NET "vgaGreen<3>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
+#NET "vgaBlue<2>" LOC = "U5" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
+#NET "vgaBlue<3>" LOC = "U4" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
+#
+#NET "hsync" LOC = "T4" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
+#NET "vsync" LOC = "U3" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
+#
+##
+##NET "vgaRed<1>" IOSTANDARD = LVCMOS33;
+##NET "vgaRed<2>" IOSTANDARD = LVCMOS33;
+##NET "vgaRed<3>" IOSTANDARD = LVCMOS33;
+##NET "vgaGreen<1>" IOSTANDARD = LVCMOS33;
+##NET "vgaGreen<2>" IOSTANDARD = LVCMOS33;
+##NET "vgaGreen<3>" IOSTANDARD = LVCMOS33;
+##NET "vgaBlue<2>" IOSTANDARD = LVCMOS33;
+##NET "vgaBlue<3>" IOSTANDARD = LVCMOS33;
+##
+##NET "hsync" IOSTANDARD = LVCMOS33;
+##NET "vsync" IOSTANDARD = LVCMOS33;
+##
+##NET "vgaRed<1>" PULLUP;
+##NET "vgaRed<2>" PULLUP;
+##NET "vgaRed<3>" PULLUP;
+##NET "vgaGreen<1>" PULLUP;
+##NET "vgaGreen<2>" PULLUP;
+##NET "vgaGreen<3>" PULLUP;
+##NET "vgaBlue<2>" PULLUP;
+##NET "vgaBlue<3>" PULLUP;
+##NET "hsync" PULLUP;
+##NET "vsync" PULLUP;
+#
+#
+### PS/2 connector
+##NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
+##NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
+#
+### FX2 connector
+##NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
+##NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
+##NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
+##NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
+##NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
+##NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
+##NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
+##NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
+##NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
+##NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
+##NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
+##NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
+##NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
+##NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
+##NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
+##NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
+##NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
+##NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
+##NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
+##NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
+##NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
+##NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
+##NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
+##NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
+##NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
+##NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
+##NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
+##NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
+##NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
+##NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
+##NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
+##NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
+##NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
+##NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
+##NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
+##NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
+##NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
+##NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
+##NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+##NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+#
+### 12 pin connectors
+#
+###JA
+##NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+##NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+##NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+##NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+##NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
+##NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
+##NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
+##NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
+#
+###JB
+##NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
+##NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+##NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
+##NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
+##NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
+##NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+##NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+##NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+#
+###JC
+##NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+##NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
+##NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+##NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+##NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
+##NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+##NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
+##NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
+#
+###JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
+##NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+##NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+##NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+##NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
+#
+### RS232 connector
+##NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
+##NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
\ No newline at end of file
implementaciones/fftProject06/pines.ucf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/vgapack.vhd
===================================================================
--- implementaciones/fftProject06/vgapack.vhd (nonexistent)
+++ implementaciones/fftProject06/vgapack.vhd (revision 408)
@@ -0,0 +1,35 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.ALL;
+
+package vgapack is
+
+ constant col_num : integer := 640; --640
+ constant row_num : integer := 480; --480
+
+ constant b : integer := 95; -- 95
+ constant c : integer := 45; -- 45
+ constant d : integer := col_num;
+ constant e : integer := 20; -- 20
+
+ constant p : integer := 2; -- 2
+ constant q : integer := 32; -- 32
+ constant r : integer := row_num;
+ constant s : integer := 14; --14
+
+
+ constant x_step : integer := 80;
+ constant y_step : integer := 15;
+
+ constant lr_col_num : integer := 8;
+ constant lr_row_num : integer := 32;
+
+ type lr_display is array (0 to lr_row_num-1, 0 to lr_col_num-1) of STD_LOGIC;
+
+
+ type vga_samples_vector_type is array (0 to lr_col_num-1) of unsigned (4 downto 0);
+
+
+end vgapack;
+
implementaciones/fftProject06/vgapack.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/fftPack.vhd
===================================================================
--- implementaciones/fftProject06/fftPack.vhd (nonexistent)
+++ implementaciones/fftProject06/fftPack.vhd (revision 408)
@@ -0,0 +1,72 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.ALL;
+
+
+package fftPack is
+
+ constant registerLenght : integer := 10; -- numero de bits de cada registro
+ constant fractionalLenght : integer := 5; -- numero de bits para la parte fraccionaria
+ constant fftorder : integer := 3; --- ???
+ constant SN : integer := 2**fftorder; -- numero de samples
+
+ type fftsamples is array (0 to SN-1) of signed (registerLenght-1 downto 0);
+
+
+
+ constant mag_samples_number : integer := 8; -- debe coincidir con lr_col_num de vgapack.vhd ¡???
+
+ type fftMag_samples_vector_type is array (0 to mag_samples_number-1) of std_logic_vector (9 downto 0);
+
+ type quadClock_type is array (3 downto 0) of std_logic;
+--
+-- type is
+-- record
+-- : std_logic_vector( 7 downto 0);
+-- : std_logic;
+-- end record;
+--
+---- Declare constants
+--
+-- constant : time := ns;
+-- constant : integer := ;
+--
+---- Declare functions and procedure
+--
+-- function (signal : in ) return ;
+-- procedure ( : in );
+
+end fftPack;
+
+--
+--package body is
+--
+---- Example 1
+-- function (signal : in ) return is
+-- variable : ;
+-- begin
+-- := xor ;
+-- return ;
+-- end ;
+--
+--
+---- Example 2
+-- function (signal : in ;
+-- signal : in ) return is
+-- begin
+-- if ( = '1') then
+-- return ;
+-- else
+-- return 'Z';
+-- end if;
+-- end ;
+--
+---- Procedure Example
+-- procedure ( : in ) is
+--
+-- begin
+--
+-- end ;
+--
+--end ;
implementaciones/fftProject06/fftPack.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/twiddles.vhd
===================================================================
--- implementaciones/fftProject06/twiddles.vhd (nonexistent)
+++ implementaciones/fftProject06/twiddles.vhd (revision 408)
@@ -0,0 +1,77 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.fftpack.all;
+
+package twiddles is
+
+ -- fftorder = 3
+ -- array con los valores de omega (twiddle factors)
+ type omega is array (0 to 7) of signed (RegisterLenght-1 downto 0);
+
+ constant omega_real : omega := (
+ to_signed (32, RegisterLenght),
+ to_signed (23, RegisterLenght),
+ to_signed (0, RegisterLenght),
+ to_signed (-23, RegisterLenght),
+ to_signed (-32, RegisterLenght),
+ to_signed (-23, RegisterLenght),
+ to_signed (0, RegisterLenght),
+ to_signed (23, RegisterLenght));
+
+ constant omega_imag : omega := (
+ to_signed (0, RegisterLenght),
+ to_signed (-23, RegisterLenght),
+ to_signed (-32, RegisterLenght),
+ to_signed (-23, RegisterLenght),
+ to_signed (0, RegisterLenght),
+ to_signed (23, RegisterLenght),
+ to_signed (32, RegisterLenght),
+ to_signed (23, RegisterLenght));
+
+
+
+ -- fftorder = 4
+-- type omega is array (0 to 15) of signed (RegisterLenght-1 downto 0);
+--
+-- constant omega_real : omega := (
+-- to_signed (32, RegisterLenght),
+-- to_signed (30, RegisterLenght),
+-- to_signed (23, RegisterLenght),
+-- to_signed (12, RegisterLenght),
+-- to_signed (0, RegisterLenght),
+-- to_signed (-12, RegisterLenght),
+-- to_signed (-23, RegisterLenght),
+-- to_signed (-30, RegisterLenght),
+-- to_signed (-32, RegisterLenght),
+-- to_signed (-30, RegisterLenght),
+-- to_signed (-23, RegisterLenght),
+-- to_signed (-12, RegisterLenght),
+-- to_signed (0, RegisterLenght),
+-- to_signed (12, RegisterLenght),
+-- to_signed (23, RegisterLenght),
+-- to_signed (30, RegisterLenght));
+--
+-- constant omega_imag : omega := (
+-- to_signed (0, RegisterLenght),
+-- to_signed (-12, RegisterLenght),
+-- to_signed (-23, RegisterLenght),
+-- to_signed (-30, RegisterLenght),
+-- to_signed (-32, RegisterLenght),
+-- to_signed (-30, RegisterLenght),
+-- to_signed (-23, RegisterLenght),
+-- to_signed (-12, RegisterLenght),
+-- to_signed (0, RegisterLenght),
+-- to_signed (12, RegisterLenght),
+-- to_signed (23, RegisterLenght),
+-- to_signed (30, RegisterLenght),
+-- to_signed (32, RegisterLenght),
+-- to_signed (30, RegisterLenght),
+-- to_signed (23, RegisterLenght),
+-- to_signed (12, RegisterLenght));
+
+
+end twiddles;
+
implementaciones/fftProject06/twiddles.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/fft.vhd
===================================================================
--- implementaciones/fftProject06/fft.vhd (nonexistent)
+++ implementaciones/fftProject06/fft.vhd (revision 408)
@@ -0,0 +1,112 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.fftPack.all;
+
+entity fft is
+ Port (
+ iSamples : in fftsamples;
+ offtr : out fftsamples;
+ offti : out fftsamples);
+end fft;
+
+architecture Behavioral of fft is
+
+ type matrix is array (fftorder downto 0, 2**fftorder-1 downto 0) of signed (RegisterLenght-1 downto 0);
+ signal fftr : matrix;
+ signal ffti : matrix;
+
+ COMPONENT butterfly
+ generic (
+ twiddle : integer := 0;
+ BN : integer := RegisterLenght;
+ FBN : integer := FractionalLenght);
+ PORT(
+ i1r : IN signed (BN-1 downto 0);
+ i1i : IN signed (BN-1 downto 0);
+ i2r : IN signed (BN-1 downto 0);
+ i2i : IN signed (BN-1 downto 0);
+ o1r : OUT signed (BN-1 downto 0);
+ o1i : OUT signed (BN-1 downto 0);
+ o2r : OUT signed (BN-1 downto 0);
+ o2i : OUT signed (BN-1 downto 0));
+ END COMPONENT;
+
+begin
+
+
+ -- reordenamiento de las muestras (8 samples)
+ fftr (0,0) <= iSamples(0);
+ fftr (0,1) <= iSamples(4);
+ fftr (0,2) <= iSamples(2);
+ fftr (0,3) <= iSamples(6);
+ fftr (0,4) <= iSamples(1);
+ fftr (0,5) <= iSamples(5);
+ fftr (0,6) <= iSamples(3);
+ fftr (0,7) <= iSamples(7);
+
+---- reordenamiento de las muestras (16 samples)
+-- fftr (0,0) <= iSamples(0);
+-- fftr (0,1) <= iSamples(8);
+-- fftr (0,2) <= iSamples(4);
+-- fftr (0,3) <= iSamples(12);
+-- fftr (0,4) <= iSamples(2);
+-- fftr (0,5) <= iSamples(10);
+-- fftr (0,6) <= iSamples(6);
+-- fftr (0,7) <= iSamples(14);
+-- fftr (0,8) <= iSamples(1);
+-- fftr (0,9) <= iSamples(9);
+-- fftr (0,10) <= iSamples(5);
+-- fftr (0,11) <= iSamples(13);
+-- fftr (0,12) <= iSamples(3);
+-- fftr (0,13) <= iSamples(11);
+-- fftr (0,14) <= iSamples(7);
+-- fftr (0,15) <= iSamples(15);
+
+
+ hgcfg: for i in 0 to SN-1 generate
+ begin
+ ffti (0,i) <= to_signed (0, RegisterLenght);
+ offtr(i) <= fftr (fftorder,i);
+ offti(i) <= ffti (fftorder,i);
+ end generate;
+
+
+ pri : for nivel in 1 to fftorder generate
+ begin
+ seg : for i in 0 to 2**(nivel-1)-1 generate
+ begin
+ ter: for j in 0 to 2**fftorder-1 generate
+ begin
+ condicionalmente: if (j mod (2**nivel)) = 0 generate
+ begin
+
+ mariposa: butterfly
+ generic map (
+ --twiddle => i*(2**(4-nivel-1)),
+ twiddle => i*(2**(fftorder-nivel)),
+
+ BN => RegisterLenght,
+ FBN => FractionalLenght
+ )
+ PORT MAP(
+ i1r => fftr (nivel-1, i+j),
+ i1i => ffti (nivel-1, i+j),
+ i2r => fftr (nivel-1, i+j+2**(nivel-1)),
+ i2i => ffti (nivel-1, i+j+2**(nivel-1)),
+ o1r => fftr (nivel, i+j),
+ o1i => ffti (nivel, i+j),
+ o2r => fftr (nivel, i+j+2**(nivel-1)),
+ o2i => ffti (nivel, i+j+2**(nivel-1))
+ );
+
+ end generate;
+ end generate;
+ end generate;
+ end generate;
+
+
+end Behavioral;
+
implementaciones/fftProject06/fft.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/butterfly.vhd
===================================================================
--- implementaciones/fftProject06/butterfly.vhd (nonexistent)
+++ implementaciones/fftProject06/butterfly.vhd (revision 408)
@@ -0,0 +1,61 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.twiddles.all; -- Aqui estan declarados los valores para los
+ -- twiddle factors.
+
+entity butterfly is
+ generic (
+ twiddle : integer := 0; -- Indice del twiddle factor
+ BN : integer := 10; -- numero de bits para los registros
+ FBN : integer := 5); -- numero de bits destinados para la parte fraccionaria
+ Port (
+ i1r : in signed (BN-1 downto 0); -- entrada 1, parte real
+ i1i : in signed (BN-1 downto 0); -- entrada 1, parte imag
+ i2r : in signed (BN-1 downto 0); -- entrada 2, parte real
+ i2i : in signed (BN-1 downto 0); -- entrada 2, parte imag
+ o1r : out signed (BN-1 downto 0); -- salida 1, parte real
+ o1i : out signed (BN-1 downto 0); -- salida 1, parte imag
+ o2r : out signed (BN-1 downto 0); -- salida 2, parte real
+ o2i : out signed (BN-1 downto 0)); -- salida 2, parte imag
+end butterfly;
+
+architecture Behavioral of butterfly is
+
+ signal IntRes01 : signed (BN-1 downto 0);
+ signal IntRes02 : signed (BN-1 downto 0);
+
+ signal m01Sig : signed (2*BN-1 downto 0);
+ signal m02Sig : signed (2*BN-1 downto 0);
+ signal m03Sig : signed (2*BN-1 downto 0);
+ signal m04Sig : signed (2*BN-1 downto 0);
+
+begin
+
+ -- se pretende resolver la mariposa, en donde dados dos
+ -- numeros complejos de entrada y un factor de giro, las
+ -- dos salidas complejas quedan determinadas por:
+ -- o1r + j o1i = (i1r + j i1i) + (wr + jwi)*(i2r + j i2i)
+ -- o2r + j o2i = (i1r + j i1i) - (wr + jwi)*(i2r + j i2i)
+
+
+ m01Sig <= i2r * omega_real(twiddle) / (2**FBN);
+ m02Sig <= i2i * omega_imag(twiddle) / (2**FBN);
+
+ IntRes01 <= m01Sig(BN-1 downto 0) - m02Sig(BN-1 downto 0);
+
+ o1r <= i1r + IntRes01; -- o1r = i1r + (i2r*wr - i2i*wi)
+ o2r <= i1r - IntRes01; -- o2r = i1r - (i2r*wr - i2i*wi)
+
+
+ m03Sig <= i2i * omega_real(twiddle) / (2**FBN);
+ m04Sig <= i2r * omega_imag(twiddle) / (2**FBN);
+
+ IntRes02 <= m03Sig(BN-1 downto 0) + m04Sig(BN-1 downto 0);
+
+ o1i <= i1i + IntRes02; -- o1i = i1i + (i2r*wi + i2i*wr)
+ o2i <= i1i - IntRes02; -- o2i = i1i - (i2r*wi + i2i*wr)
+
+end Behavioral;
implementaciones/fftProject06/butterfly.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/sevseg_display.vhd
===================================================================
--- implementaciones/fftProject06/sevseg_display.vhd (nonexistent)
+++ implementaciones/fftProject06/sevseg_display.vhd (revision 408)
@@ -0,0 +1,94 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use ieee.std_logic_unsigned.all;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity sevseg_display is
+ Port (
+ clock : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ data : in STD_LOGIC_VECTOR (15 downto 0);
+ segments : out STD_LOGIC_VECTOR (6 downto 0);
+ char_sel : out STD_LOGIC_VECTOR (3 downto 0));
+end sevseg_display;
+
+architecture Behavioral of sevseg_display is
+ signal count : unsigned (1 downto 0);
+ signal char : std_logic_vector (3 downto 0);
+begin
+
+counter: process (clock, reset)
+ variable count_var : unsigned (1 downto 0) := "00";
+begin
+ if reset='1' then
+ count_var := (others => '0');
+ elsif falling_edge(clock) then
+ count_var := count + 1;
+ end if;
+ count <= count_var;
+end process;
+
+char_selector: process (clock, count)
+begin
+ if rising_edge(clock) then
+ case count is
+ when "00" => char_sel <= "1110";
+ when "01" => char_sel <= "1101";
+ when "10" => char_sel <= "1011";
+ when "11" => char_sel <= "0111";
+ when others => char_sel <= "1111";
+ end case;
+ end if;
+end process;
+
+data_selector: process (clock, count)
+begin
+ if rising_edge (clock) then
+ case count is
+ when "00" => char <= data(3 downto 0);
+ when "01" => char <= data(7 downto 4);
+ when "10" => char <= data(11 downto 8);
+ when "11" => char <= data(15 downto 12);
+ when others => char <= "0000";
+ end case;
+ end if;
+end process;
+
+
+bin2seven: process (char, reset)
+ variable segments_var : STD_LOGIC_VECTOR (6 downto 0);
+begin
+
+ if reset = '1' then
+ segments_var := "1111111";
+ else
+ case char is
+ when "0000" => segments_var := "0000001"; -- 0
+ when "0001" => segments_var := "1001111"; -- 1
+ when "0010" => segments_var := "0010010"; -- 2
+ when "0011" => segments_var := "0000110"; -- 3
+ when "0100" => segments_var := "1001100"; -- 4
+ when "0101" => segments_var := "0100100"; -- 5
+ when "0110" => segments_var := "0100000"; -- 6
+ when "0111" => segments_var := "0001111"; -- 7
+ when "1000" => segments_var := "0000000"; -- 8
+ when "1001" => segments_var := "0000100"; -- 9
+ when "1010" => segments_var := "0001000"; -- a
+ when "1011" => segments_var := "1100000"; -- b
+ when "1100" => segments_var := "0110001"; -- c
+ when "1101" => segments_var := "1000010"; -- d
+ when "1110" => segments_var := "0110000"; -- e
+ when "1111" => segments_var := "0111000"; -- f
+ when others => segments_var := "1111110";
+ end case;
+ end if;
+
+ segments <= segments_var;
+
+end process;
+
+
+end Behavioral;
+
implementaciones/fftProject06/sevseg_display.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/vgacontroller.vhd
===================================================================
--- implementaciones/fftProject06/vgacontroller.vhd (nonexistent)
+++ implementaciones/fftProject06/vgacontroller.vhd (revision 408)
@@ -0,0 +1,263 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+use work.vgapack.all;
+use work.fftpack.all;
+
+
+entity vgacontroller is
+ Port (
+ clk : in quadClock_type; -- 50MHz clock
+ reset : IN std_logic;
+
+ secuencia : in vga_samples_vector_type;
+
+ hsync : out STD_LOGIC;
+ vsync : out STD_LOGIC;
+
+ vgaRed : out STD_LOGIC;
+ vgaGreen : out STD_LOGIC;
+ vgaBlue : out STD_LOGIC);
+end vgacontroller;
+
+
+
+architecture Behavioral of vgacontroller is
+
+ signal red : std_logic;
+ signal green : std_logic;
+ signal blue : std_logic;
+
+ signal vsync_clk_en : std_logic;
+
+ signal frame_plain : std_logic;
+ signal frame_grid : std_logic;
+ signal frame_bars : std_logic;
+
+ signal hcntr : integer;
+ signal vcntr : integer;
+
+ signal bars : lr_display;
+
+ signal lr_x_ctr : integer;
+ signal step_x_ctr : integer;
+ signal lr_y_ctr : integer;
+ signal step_y_ctr : integer;
+
+ signal vsync_sig : std_logic;
+
+
+begin
+
+-- mving . . . --------------------------------
+
+process (secuencia)
+begin
+ for c in 0 to lr_col_num-1 loop
+ for r in 0 to lr_row_num-1 loop
+ if secuencia(c) > r then
+ bars (lr_row_num-1-r,c) <= '1';
+ else
+ bars (lr_row_num-1-r,c) <= '0';
+ end if;
+ end loop;
+ end loop;
+end process;
+
+
+-- horizontal counter and sync -------------
+
+process (clk(0), reset)
+ variable counter : integer := b+c+d+e-1;
+ variable vsync_clk_en_var : std_logic := '0';
+begin
+ if reset='1' then
+ counter := b+c+d+e-1;
+ elsif rising_edge(clk(0)) then
+
+ case counter is
+ when b+c+d+e-1 => counter := 0;
+ when others => counter := counter + 1;
+ end case;
+
+ if counter = d+e then
+ vsync_clk_en_var := '1';
+ else
+ vsync_clk_en_var := '0';
+ end if;
+
+ end if;
+
+ hcntr <= counter;
+ vsync_clk_en <= vsync_clk_en_var;
+
+end process;
+
+
+-- el siguiente process quizas se pueda optimizar con un clock enable
+process (clk(3))
+ variable hsync_var : std_logic := '1';
+begin
+ if rising_edge(clk(3)) then
+ if hcntr < d+e or hcntr >= d+e+b then
+ hsync_var := '1';
+ else
+ hsync_var := '0';
+ end if;
+ end if;
+ hsync <= hsync_var;
+end process;
+
+
+-- vertical counter and sync -------------------
+
+process (clk(1), reset)
+ variable counter : integer := r+s+p+q-1;
+begin
+ if reset='1' then
+ counter := r+s+p+q-1;
+ elsif rising_edge(clk(1)) and vsync_clk_en = '1' then
+ case counter is
+ when r+s+p+q-1 => counter := 0;
+ when others => counter := counter + 1;
+ end case;
+ end if;
+ vcntr <= counter;
+end process;
+
+-- quizas se pueda optimizar con un enable
+process (clk(3))
+ variable vsync_var : std_logic := '1';
+begin
+ if rising_edge(clk(3)) then
+ if vcntr < r+s or vcntr >= r+s+p then
+ vsync_var := '1';
+ else
+ vsync_var := '0';
+ end if;
+ end if;
+ vsync_sig <= vsync_var;
+end process;
+
+ vsync <= vsync_sig;
+
+-- drawings ------------------------------------
+
+plain_drawing_proc: process (clk(3))
+ variable var_var : std_logic := '0';
+begin
+ if rising_edge(clk(3)) then
+ if (hcntr < col_num and vcntr < row_num) then
+ var_var := '1';
+ else
+ var_var := '0';
+ end if;
+ end if;
+ frame_plain <= var_var;
+end process;
+
+
+grid_drawing_proc: process (clk(3))
+ variable var_var : std_logic := '0';
+begin
+ if rising_edge(clk(3)) then
+ if (hcntr = 0 and vcntr < 480) or
+ (hcntr = 639 and vcntr < 480) or
+
+ (hcntr = 79 and vcntr < 480) or
+ (hcntr = 159 and vcntr < 480) or
+ (hcntr = 239 and vcntr < 480) or
+ (hcntr = 319 and vcntr < 480) or
+ (hcntr = 399 and vcntr < 480) or
+ (hcntr = 479 and vcntr < 480) or
+ (hcntr = 559 and vcntr < 480) or
+
+ (vcntr = 120 and hcntr < 640) or
+ (vcntr = 240 and hcntr < 640) or
+ (vcntr = 360 and hcntr < 640) or
+
+ (vcntr = 0 and hcntr < 640) or
+ (vcntr = 479 and hcntr < 640) then
+ var_var := '1';
+ else
+ var_var := '0';
+ end if;
+ end if;
+ frame_grid <= var_var;
+end process;
+
+
+---- bars drawing ---------------------------------
+
+process (clk(2))
+ variable lr_x_ctr_var : integer := 0;
+ variable step_x_ctr_var : integer := 0;
+begin
+ if rising_edge(clk(2)) then
+ if hcntr = 0 then
+ lr_x_ctr_var := 0;
+ step_x_ctr_var := 0;
+ elsif step_x_ctr_var = x_step-1 then
+ lr_x_ctr_var := lr_x_ctr_var + 1;
+ step_x_ctr_var := 0;
+ else
+ step_x_ctr_var := step_x_ctr_var + 1;
+ end if;
+ lr_x_ctr <= lr_x_ctr_var;
+ step_x_ctr <= step_x_ctr_var;
+ end if;
+end process;
+
+
+process (clk(2))
+ variable lr_y_ctr_var : integer := 0;
+ variable step_y_ctr_var : integer := 0;
+begin
+ if rising_edge(clk(2)) and vsync_clk_en='1' then
+ if vcntr = 0 then
+ lr_y_ctr_var := 0;
+ step_y_ctr_var := 0;
+ elsif step_y_ctr_var = y_step-1 then
+ lr_y_ctr_var := lr_y_ctr_var + 1;
+ step_y_ctr_var := 0;
+ else
+ step_y_ctr_var := step_y_ctr_var + 1;
+ end if;
+ lr_y_ctr <= lr_y_ctr_var;
+ step_y_ctr <= step_y_ctr_var;
+ end if;
+end process;
+
+
+bars_drawing_proc: process (clk(3))
+ variable var_var : std_logic := '0';
+begin
+ if rising_edge(clk(3)) then
+ if (hcntr < col_num and vcntr < row_num) then
+ var_var := bars(lr_y_ctr,lr_x_ctr);
+ else
+ var_var := '0';
+ end if;
+ frame_bars <= var_var;
+ end if;
+end process;
+
+-- color assert -------------------------------
+
+red <= frame_plain and not frame_grid and not frame_bars;
+green <= frame_plain and not frame_grid and not frame_bars;
+blue <= frame_plain and not frame_grid;
+
+
+vgaRed <= blue;
+vgaGreen <= green;
+vgaBlue <= blue;
+
+
+end Behavioral;
+
implementaciones/fftProject06/vgacontroller.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/magComp.vhd
===================================================================
--- implementaciones/fftProject06/magComp.vhd (nonexistent)
+++ implementaciones/fftProject06/magComp.vhd (revision 408)
@@ -0,0 +1,150 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.fftpack.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+
+entity magComp is
+ Port ( clk : in quadClock_type;
+ reset : in STD_LOGIC;
+ realInput : in fftMag_samples_vector_type;
+ imagInput : in fftMag_samples_vector_type;
+ magOutput : out fftMag_samples_vector_type);
+end magComp;
+
+architecture Behavioral of magComp is
+
+ COMPONENT romMem
+ PORT(
+ clk : IN quadClock_type;
+ address : IN std_logic_vector(13 downto 0);
+ data : OUT std_logic_vector(7 downto 0)
+ );
+ END COMPONENT;
+
+ -- Counter signals
+ signal i_counter : integer;
+
+ -- Memory address signal
+ signal addrA : std_logic_vector (6 downto 0);
+ signal addrB : std_logic_vector (6 downto 0);
+ signal memAddress : std_logic_vector (13 downto 0);
+
+
+ -- Memory output
+ signal memData : std_logic_vector (7 downto 0);
+
+begin
+
+-- Counter -----------------------------------------------
+
+ process (clk(0), reset)
+ variable counter : integer := 0;
+ begin
+ if reset = '1' then
+ counter := 0;
+ elsif rising_edge (clk(0)) then
+ case counter is
+ when 7 => counter := 0;
+ when others => counter := counter + 1;
+ end case;
+ end if;
+ i_counter <= counter;
+ end process;
+
+
+-- Memory address ----------------------------------------
+
+process (i_counter)
+begin
+ case i_counter is
+ when 0 => addrA <= realInput(0)(9 downto 3);
+ when 1 => addrA <= realInput(1)(9 downto 3);
+ when 2 => addrA <= realInput(2)(9 downto 3);
+ when 3 => addrA <= realInput(3)(9 downto 3);
+ when 4 => addrA <= realInput(4)(9 downto 3);
+ when 5 => addrA <= realInput(5)(9 downto 3);
+ when 6 => addrA <= realInput(6)(9 downto 3);
+ when 7 => addrA <= realInput(7)(9 downto 3);
+ when others => addrA <= "0000000";
+ end case;
+end process;
+
+process (i_counter)
+begin
+ case i_counter is
+ when 0 => addrB <= imagInput(0)(9 downto 3);
+ when 1 => addrB <= imagInput(1)(9 downto 3);
+ when 2 => addrB <= imagInput(2)(9 downto 3);
+ when 3 => addrB <= imagInput(3)(9 downto 3);
+ when 4 => addrB <= imagInput(4)(9 downto 3);
+ when 5 => addrB <= imagInput(5)(9 downto 3);
+ when 6 => addrB <= imagInput(6)(9 downto 3);
+ when 7 => addrB <= imagInput(7)(9 downto 3);
+ when others => addrB <= "0000000";
+ end case;
+end process;
+
+process (addrA, addrB)
+begin
+ memAddress <= addrA & addrB;
+end process;
+
+
+-- Memory ------------------------------------------------
+
+ Inst_romMem: romMem PORT MAP(
+ clk => clk,
+ address => memAddress,
+ data => memData
+ );
+
+
+-- Update output -----------------------------------------
+
+-- process (clk(3))
+-- begin
+-- if rising_edge (clk(3)) then
+-- case i_counter is
+-- when 0 => magOutput(0) <= memData&"00";
+-- when 1 => magOutput(1) <= memData&"00";
+-- when 2 => magOutput(2) <= memData&"00";
+-- when 3 => magOutput(3) <= memData&"00";
+-- when 4 => magOutput(4) <= memData&"00";
+-- when 5 => magOutput(5) <= memData&"00";
+-- when 6 => magOutput(6) <= memData&"00";
+-- when 7 => magOutput(7) <= memData&"00";
+-- when others => null;
+-- end case;
+-- end if;
+-- end process;
+
+ process (clk(3))
+ begin
+ if rising_edge (clk(3)) then
+ case i_counter is
+ when 0 => magOutput(0) <= "00"&memData;
+ when 1 => magOutput(1) <= "00"&memData;
+ when 2 => magOutput(2) <= "00"&memData;
+ when 3 => magOutput(3) <= "00"&memData;
+ when 4 => magOutput(4) <= "00"&memData;
+ when 5 => magOutput(5) <= "00"&memData;
+ when 6 => magOutput(6) <= "00"&memData;
+ when 7 => magOutput(7) <= "00"&memData;
+ when others => null;
+ end case;
+ end if;
+ end process;
+
+end Behavioral;
+
implementaciones/fftProject06/magComp.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/adcontroller.vhd
===================================================================
--- implementaciones/fftProject06/adcontroller.vhd (nonexistent)
+++ implementaciones/fftProject06/adcontroller.vhd (revision 408)
@@ -0,0 +1,258 @@
+-------------------------------------------------------------------------
+-- AD1RefComp.VHD
+-------------------------------------------------------------------------
+-- Author : Ioana Dabacan
+-- CopyRight 2008 Digilent Ro.
+-------------------------------------------------------------------------
+-- Description : This file is the VHDL code for a PMOD-AD1 controller.
+--
+-------------------------------------------------------------------------
+-- Revision History:
+-- Feb/29/2008 Created (Ioana Dabacan)
+-------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-------------------------------------------------------------------------
+--Title : AD1 Reference Component
+--
+-- Inputs : 5
+-- Outputs : 5
+--
+-- Description: This is the AD1 Reference Component entity. The input
+-- ports are a 50 MHz clock and an asynchronous reset
+-- button along with the data from the ADC7476 that
+-- is serially shifted in on each clock cycle(SDATA1 and
+-- SDATA2). The outputs are the SCLK signal which clocks
+-- the PMOD-AD1 board at 12.5 MHz and a chip select
+-- signal (nCS) that enables the ADC7476 chips on the
+-- PMOD-AD1 board as well as two 12-bit output
+-- vectors labeled DATA1 and DATA2 which can be used by
+-- any external components. The START is used to tell
+-- the component when to start a conversion. After a
+-- conversion is done the component activates the DONE
+-- signal.
+--
+--------------------------------------------------------------------------
+
+entity AD1RefComp is
+ Port (
+ --General usage
+ CLK : in std_logic;
+ RST : in std_logic;
+
+ --Pmod interface signals
+ SDATA1 : in std_logic;
+ SDATA2 : in std_logic;
+ SCLK : out std_logic;
+ nCS : out std_logic;
+
+ --User interface signals
+ DATA1 : out std_logic_vector(11 downto 0);
+ DATA2 : out std_logic_vector(11 downto 0);
+ START : in std_logic;
+ DONE : out std_logic
+ );
+
+end AD1RefComp ;
+
+architecture AD1 of AD1RefComp is
+
+--------------------------------------------------------------------------------
+-- Title : Local signal assignments
+--
+-- Description : The following signals will be used to drive the
+-- processes of this VHDL file.
+--
+-- current_state : This signal will be the pointer that will point at the
+-- current state of the Finite State Machine of the
+-- controller.
+-- next_state : This signal will be the pointer that will point at the
+-- current state of the Finite State Machine of the
+-- controller.
+-- temp1 : This is a 16-bit vector that will store the 16-bits of data
+-- that are serially shifted-in form the first ADC7476 chip
+-- inside the PMOD-AD1 board.
+-- temp2 : This is a 16-bit vector that will store the 16-bits of data
+-- that are serially shifted-in form the second ADC7476 chip
+-- inside the PMOD-AD1 board.
+-- clk_div : This will be the divided 12.5 MHz clock signal that will
+-- clock the PMOD-AD1 board
+-- clk_counter : This counter will be used to create a divided clock signal.
+--
+-- shiftCounter : This counter will be used to count the shifted data from
+-- the ADC7476 chip inside the PMOD-AD1 board.
+-- enShiftCounter: This signal will be used to enable the counter for the
+-- shifted data from the ADC7476 chip inside the PMOD-AD1.
+-- enParalelLoad : This signal will be used to enable the load the shifted
+-- data in a register.
+--------------------------------------------------------------------------------
+
+type states is (Idle,
+ ShiftIn,
+ SyncData);
+ signal current_state : states;
+ signal next_state : states;
+
+ signal temp1 : std_logic_vector(15 downto 0);
+ signal temp2 : std_logic_vector(15 downto 0);
+ signal clk_div : std_logic;
+ signal clk_counter : std_logic_vector(1 downto 0);
+ signal shiftCounter : std_logic_vector(3 downto 0) := x"0";
+ signal enShiftCounter: std_logic;
+ signal enParalelLoad : std_logic;
+
+
+begin
+
+--------------------------------------------------------------------------------
+-- Title : clock divider process
+--
+-- Description : This is the process that will divide the 50 MHz clock
+-- down to a clock speed of 12.5 MHz to drive the ADC7476 chip.
+--------------------------------------------------------------------------------
+ clock_divide : process(rst,clk)
+ begin
+ if rst = '1' then
+ clk_counter <= "00";
+ elsif (clk = '1' and clk'event) then
+ clk_counter <= clk_counter + '1';
+ end if;
+ end process;
+
+ clk_div <= clk_counter(1);
+ SCLK <= not clk_counter(1);
+
+-----------------------------------------------------------------------------------
+--
+-- Title : counter
+--
+-- Description: This is the process were the converted data will be colected and
+-- output.When the enShiftCounter is activated, the 16-bits of data
+-- from the ADC7476 chips will be shifted inside the temporary
+-- registers. A 4-bit counter is used to keep shifting the data
+-- inside temp1 and temp2 for 16 clock cycles. When the enParalelLoad
+-- signal is generated inside the SyncData state, the converted data
+-- in the temporary shift registers will be placed on the outputs
+-- DATA1 and DATA2.
+--
+-----------------------------------------------------------------------------------
+
+counter : process(clk_div, enParalelLoad, enShiftCounter)
+ begin
+ if (clk_div = '1' and clk_div'event) then
+
+ if (enShiftCounter = '1') then
+ temp1 <= temp1(14 downto 0) & SDATA1;
+ temp2 <= temp2(14 downto 0) & SDATA2;
+ shiftCounter <= shiftCounter + '1';
+ elsif (enParalelLoad = '1') then
+ shiftCounter <= "0000";
+ DATA1 <= temp1(11 downto 0);
+ DATA2 <= temp2(11 downto 0);
+ end if;
+ end if;
+ end process;
+
+---------------------------------------------------------------------------------
+--
+-- Title : Finite State Machine
+--
+-- Description: This 3 processes represent the FSM that contains three states.
+-- The first state is the Idle state in which a temporary registers
+-- are assigned the updated value of the input "DATA1" and "DATA2".
+-- The next state is the ShiftIn state where the 16-bits of data
+-- from each of the ADCS7476 chips are left shifted in the temp1
+-- and temp2 shift registers. The third state, SyncData drives the
+-- output signal nCS high for 1 clock period maintainig nCS high
+-- also in the Idle state telling the ADCS7476 to mark the end of
+-- the conversion.
+-- Notes: The data will change on the lower edge of the clock signal. There
+-- is also an asynchronous reset that will reset all signals to
+-- their original state.
+--
+-----------------------------------------------------------------------------------
+
+-----------------------------------------------------------------------------------
+--
+-- Title : SYNC_PROC
+--
+-- Description: This is the process were the states are changed synchronously. At
+-- reset the current state becomes Idle state.
+--
+-----------------------------------------------------------------------------------
+SYNC_PROC: process (clk_div, rst)
+ begin
+ if (clk_div'event and clk_div = '1') then
+ if (rst = '1') then
+ current_state <= Idle;
+ else
+ current_state <= next_state;
+ end if;
+ end if;
+ end process;
+
+-----------------------------------------------------------------------------------
+--
+-- Title : OUTPUT_DECODE
+--
+-- Description: This is the process were the output signals are generated
+-- unsynchronously based on the state only (Moore State Machine).
+--
+-----------------------------------------------------------------------------------
+OUTPUT_DECODE: process (current_state)
+ begin
+ if current_state = Idle then
+ enShiftCounter <='0';
+ DONE <='1';
+ nCS <='1';
+ enParalelLoad <= '0';
+ elsif current_state = ShiftIn then
+ enShiftCounter <='1';
+ DONE <='0';
+ nCS <='0';
+ enParalelLoad <= '0';
+ else --if current_state = SyncData then
+ enShiftCounter <='0';
+ DONE <='0';
+ nCS <='1';
+ enParalelLoad <= '1';
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------
+--
+-- Title : NEXT_STATE_DECODE
+--
+-- Description: This is the process were the next state logic is generated
+-- depending on the current state and the input signals.
+--
+-----------------------------------------------------------------------------------
+ NEXT_STATE_DECODE: process (current_state, START, shiftCounter)
+ begin
+
+ next_state <= current_state; -- default is to stay in current state
+
+ case (current_state) is
+ when Idle =>
+ if START = '1' then
+ next_state <= ShiftIn;
+ end if;
+ when ShiftIn =>
+ if shiftCounter = x"F" then
+ next_state <= SyncData;
+ end if;
+ when SyncData =>
+ if START = '0' then
+ next_state <= Idle;
+ end if;
+ when others =>
+ next_state <= Idle;
+ end case;
+ end process;
+
+
+end AD1;
implementaciones/fftProject06/adcontroller.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/clocking.vhd
===================================================================
--- implementaciones/fftProject06/clocking.vhd (nonexistent)
+++ implementaciones/fftProject06/clocking.vhd (revision 408)
@@ -0,0 +1,111 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.fftpack.all;
+
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity clocking is
+ Port (
+ clock : in STD_LOGIC;
+ reset : in std_logic;
+ clk50M : out std_logic;
+ clk : out quadClock_type);
+end clocking;
+
+architecture Behavioral of clocking is
+
+ signal clkin_IBUFG : std_logic;
+
+ signal CLK000 : std_logic;
+ signal CLK090 : std_logic;
+ signal CLK180 : std_logic;
+ signal CLK270 : std_logic;
+
+ signal clk0 : std_logic;
+-- signal clk1 : std_logic;
+-- signal clk2 : std_logic;
+-- signal clk3 : std_logic;
+
+begin
+
+-- DCM ---------------------------------------------------
+
+ clk(0) <= clk0;
+
+ CLKIN_IBUFG_INST : IBUFG
+ port map (I=>clock,
+ O=>clkin_IBUFG);
+
+ clk50M <= clkin_IBUFG;
+
+ CLK0_BUFG_INST : BUFG
+ port map (I=>CLK000,
+ O=>clk0);
+
+ CLK1_BUFG_INST : BUFG
+ port map (I=>CLK090,
+ O=>clk(1));
+
+ CLK2_BUFG_INST : BUFG
+ port map (I=>CLK180,
+ O=>clk(2));
+
+ CLK3_BUFG_INST : BUFG
+ port map (I=>CLK270,
+ O=>clk(3));
+
+ -- DCM_SP: Digital Clock Manager Circuit
+ -- Spartan-3A
+ -- Xilinx HDL Language Template, version 12.3
+
+ DCM_SP_inst : DCM_SP
+ generic map (
+ CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+ -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+ CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
+ CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
+ CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
+ CLKIN_PERIOD => 20.000, -- Specify period of input clock
+ CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
+ CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
+ -- an integer from 0 to 15
+ DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL
+ DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+ PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
+ STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
+ port map (
+ CLK0 => CLK000, -- 0 degree DCM CLK ouptput
+ CLK180 => CLK180, -- 180 degree DCM CLK output
+ CLK270 => CLK270, -- 270 degree DCM CLK output
+ CLK2X => open, -- 2X DCM CLK output
+ CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+ CLK90 => CLK090, -- 90 degree DCM CLK output
+ CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+ CLKFX => open, -- DCM CLK synthesis out (M/D)
+ CLKFX180 => open, -- 180 degree CLK synthesis out
+ LOCKED => open, -- DCM LOCK status output
+ PSDONE => open, -- Dynamic phase adjust done output
+ STATUS => open, -- 8-bit DCM status bits output
+ CLKFB => clk0, -- DCM clock feedback
+ CLKIN => clkin_IBUFG, -- Clock input (from IBUFG, BUFG or DCM)
+ PSCLK => '0', -- Dynamic phase adjust clock input
+ PSEN => '0', -- Dynamic phase adjust enable input
+ PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
+ RST => reset -- DCM asynchronous reset input
+ );
+
+ -- End of DCM_SP_inst instantiation
+
+end Behavioral;
+
implementaciones/fftProject06/clocking.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: implementaciones/fftProject06/romMem.vhd
===================================================================
--- implementaciones/fftProject06/romMem.vhd (nonexistent)
+++ implementaciones/fftProject06/romMem.vhd (revision 408)
@@ -0,0 +1,871 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.fftpack.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity romMem is
+ Port (
+ clk : in quadClock_type;
+ address : in STD_LOGIC_VECTOR (13 downto 0);
+ data : out STD_LOGIC_VECTOR (7 downto 0));
+end romMem;
+
+architecture Behavioral of romMem is
+
+ type memOutputType is array (7 downto 0) of std_logic_vector(7 downto 0);
+ signal memOutput : memOutputType;
+
+begin
+
+process (clk(2))
+begin
+ if rising_edge(clk(2)) then
+ case address(13 downto 11) is
+ when "000" => data <= memOutput(0);
+ when "001" => data <= memOutput(1);
+ when "010" => data <= memOutput(2);
+ when "011" => data <= memOutput(3);
+ when "100" => data <= memOutput(4);
+ when "101" => data <= memOutput(5);
+ when "110" => data <= memOutput(6);
+ when "111" => data <= memOutput(7);
+ when others => data <= x"00";
+ end case;
+ end if;
+end process;
+
+
+---- membblock 000 ----------------------------------
+
+ -- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
+ -- Spartan-3A
+ -- Xilinx HDL Language Template, version 12.3
+
+ RAMB16_S9_inst00 : RAMB16_S9
+ generic map (
+ INIT => X"000", -- Value of output RAM registers at startup
+ SRVAL => X"000", -- Ouput value upon SSR assertion
+ WRITE_MODE => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ -- The following INIT_xx declarations specify the initial contents of the RAM
+ -- Address 0 to 511
+ INIT_00 => x"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100",
+ INIT_01 => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_02 => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_03 => x"0102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f20",
+ INIT_04 => x"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020101",
+ INIT_05 => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_06 => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_07 => x"0102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f20",
+ INIT_08 => x"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050404030202",
+ INIT_09 => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_0a => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_0b => x"0203040405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f20",
+ INIT_0c => x"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09090807060504040303",
+ INIT_0d => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_0e => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_0f => x"0304040506070809090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f20",
+ INIT_10 => x"1f1e1d1c1b1a19181716151413121110100f0e0d0c0b0a090807060605040404",
+ INIT_11 => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_12 => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_13 => x"04040506060708090a0b0c0d0e0f10101112131415161718191a1b1c1d1e1f20",
+ INIT_14 => x"1f1e1d1c1b1a19191817161514131211100f0e0d0c0b0a090908070606050505",
+ INIT_15 => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_16 => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_17 => x"05050606070809090a0b0c0d0e0f10111213141516171819191a1b1c1d1e1f20",
+ INIT_18 => x"201f1e1d1c1b1a191817161514131211100f0e0d0d0c0b0a0908080707060606",
+ INIT_19 => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252424232221",
+ INIT_1a => x"2223242425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_1b => x"060607070808090a0b0c0d0d0e0f101112131415161718191a1b1c1d1e1f2021",
+ INIT_1c => x"201f1e1d1c1b1a19181716151413121111100f0e0d0c0b0b0a09090808070707",
+ INIT_1d => x"3f3e3d3c3b3a39383736353433323131302f2e2d2c2b2a292827262524232221",
+ INIT_1e => x"22232425262728292a2b2c2d2e2f30313132333435363738393a3b3c3d3e3f40",
+ INIT_1f => x"0707080809090a0b0b0c0d0e0f10111112131415161718191a1b1c1d1e1f2021",
+ INIT_20 => x"201f1e1d1c1b1a19181716161514131211100f0e0e0d0c0b0b0a090909080808",
+ INIT_21 => x"403f3e3d3c3b3a393837363534333231302f2e2d2c2b2a292827262524232221",
+ INIT_22 => x"22232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f4040",
+ INIT_23 => x"08080909090a0b0b0c0d0e0e0f10111213141516161718191a1b1c1d1e1f2021",
+ INIT_24 => x"201f1e1d1c1c1b1a19181716151413121111100f0e0d0d0c0b0b0a0a09090909",
+ INIT_25 => x"403f3e3d3c3b3a393837363534333231302f2e2d2c2b2a292827262524232221",
+ INIT_26 => x"22232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f4041",
+ INIT_27 => x"0909090a0a0b0b0c0d0d0e0f10111112131415161718191a1b1c1c1d1e1f2021",
+ INIT_28 => x"21201f1e1d1c1b1a1918171615151413121110100f0e0d0d0c0c0b0b0a0a0a0a",
+ INIT_29 => x"403f3e3d3c3b3a393837363534333231302f2e2d2c2b2a292827262524232222",
+ INIT_2a => x"22232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f4041",
+ INIT_2b => x"0a0a0a0b0b0c0c0d0d0e0f1010111213141515161718191a1b1c1d1e1f202122",
+ INIT_2c => x"21201f1e1d1c1b1a191918171615141313121110100f0e0e0d0d0c0c0b0b0b0b",
+ INIT_2d => x"403f3e3d3c3b3a393837363534333231302f2e2d2c2b2a292928272625242322",
+ INIT_2e => x"23242526272829292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f4041",
+ INIT_2f => x"0b0b0b0c0c0d0d0e0e0f101011121313141516171819191a1b1c1d1e1f202122",
+ INIT_30 => x"21201f1e1e1d1c1b1a191817161615141312121110100f0e0e0d0d0d0c0c0c0c",
+ INIT_31 => x"403f3e3d3c3b3a39383736353433323131302f2e2d2c2b2a2928272625242322",
+ INIT_32 => x"232425262728292a2b2c2d2e2f30313132333435363738393a3b3c3d3e3f4041",
+ INIT_33 => x"0c0c0c0d0d0d0e0e0f101011121213141516161718191a1b1c1d1e1e1f202122",
+ INIT_34 => x"2221201f1e1d1c1b1a1a191817161515141312121110100f0f0e0e0e0d0d0d0d",
+ INIT_35 => x"403f3e3d3c3b3a39393837363534333231302f2e2d2c2b2a2928272625242323",
+ INIT_36 => x"232425262728292a2b2c2d2e2f30313233343536373839393a3b3c3d3e3f4041",
+ INIT_37 => x"0d0d0d0e0e0e0f0f101011121213141515161718191a1a1b1c1d1e1f20212223",
+ INIT_38 => x"2221201f1e1e1d1c1b1a1918181716151514131212111110100f0f0f0e0e0e0e",
+ INIT_39 => x"41403f3e3d3c3b3a393837363534333231302f2e2d2c2b2a2928282726252423",
+ INIT_3a => x"242526272828292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f404142",
+ INIT_3b => x"0e0e0e0f0f0f1010111112121314151516171818191a1b1c1d1e1e1f20212223",
+ INIT_3c => x"222221201f1e1d1c1b1b1a19181717161515141313121111111010100f0f0f0f",
+ INIT_3d => x"41403f3e3d3c3b3a393837363534333231302f2e2e2d2c2b2a29282726252423",
+ INIT_3e => x"2425262728292a2b2c2d2e2e2f303132333435363738393a3b3c3d3e3f404142",
+ INIT_3f => x"0f0f0f10101011111112131314151516171718191a1b1b1c1d1e1f2021222223",
+ -- The next set of INITP_xx are for the parity bits
+ -- Address 0 to 511
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 512 to 1023
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1024 to 1535
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1536 to 2047
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => memOutput(0), -- 8-bit Data Output
+ DOP => open, -- 1-bit parity Output
+ ADDR => address(10 downto 0), -- 11-bit Address Input
+ CLK => clk(1), -- Clock
+ DI => x"00", -- 8-bit Data Input
+ DIP => "0", -- 1-bit parity Input
+ EN => '1', -- RAM Enable Input
+ SSR => '0', -- Synchronous Set/Reset Input
+ WE => '0' -- Write Enable Input
+ );
+
+
+---- membblock 001 ----------------------------------
+
+ -- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
+ -- Spartan-3A
+ -- Xilinx HDL Language Template, version 12.3
+
+ RAMB16_S9_inst01 : RAMB16_S9
+ generic map (
+ INIT => X"000", -- Value of output RAM registers at startup
+ SRVAL => X"000", -- Ouput value upon SSR assertion
+ WRITE_MODE => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ -- The following INIT_xx declarations specify the initial contents of the RAM
+ -- Address 0 to 511
+ INIT_00 => x"232221201f1f1e1d1c1b1a1a1918171716151514131312121111111010101010",
+ INIT_01 => x"41403f3e3d3c3b3a39383736353434333231302f2e2d2c2b2a29282726262524",
+ INIT_02 => x"2526262728292a2b2c2d2e2f30313233343435363738393a3b3c3d3e3f404142",
+ INIT_03 => x"101010101111111212131314151516171718191a1a1b1c1d1e1f1f2021222324",
+ INIT_04 => x"23222221201f1e1d1d1c1b1a1919181717161515141413131212121111111111",
+ INIT_05 => x"41403f3e3d3c3b3b3a393837363534333231302f2e2d2c2b2b2a292827262524",
+ INIT_06 => x"25262728292a2b2b2c2d2e2f303132333435363738393a3b3b3c3d3e3f404142",
+ INIT_07 => x"111111111212121313141415151617171819191a1b1c1d1d1e1f202122222324",
+ INIT_08 => x"2423222120201f1e1d1c1c1b1a19191817171616151514141313131212121212",
+ INIT_09 => x"4241403f3e3d3c3b3a39383736353433323130302f2e2d2c2b2a292827262625",
+ INIT_0a => x"26262728292a2b2c2d2e2f30303132333435363738393a3b3c3d3e3f40414242",
+ INIT_0b => x"1212121213131314141515161617171819191a1b1c1c1d1e1f20202122232425",
+ INIT_0c => x"2424232221201f1f1e1d1c1c1b1a191918181716161515151414141313131313",
+ INIT_0d => x"4241403f3e3d3c3b3a39383736353534333231302f2e2d2c2b2a2a2928272625",
+ INIT_0e => x"262728292a2a2b2c2d2e2f30313233343535363738393a3b3c3d3e3f40414243",
+ INIT_0f => x"13131313141414151515161617181819191a1b1c1c1d1e1f1f20212223242425",
+ INIT_10 => x"252423222221201f1e1e1d1c1c1b1a1a19181817171616161515151414141414",
+ INIT_11 => x"4241403f3e3d3c3b3b3a393837363534333231302f2f2e2d2c2b2a2928272726",
+ INIT_12 => x"272728292a2b2c2d2e2f2f303132333435363738393a3b3b3c3d3e3f40414243",
+ INIT_13 => x"1414141415151516161617171818191a1a1b1c1c1d1e1e1f2021222223242526",
+ INIT_14 => x"25252423222121201f1e1e1d1c1c1b1a1a191918181717161616161515151515",
+ INIT_15 => x"424141403f3e3d3c3b3a39383736353433333231302f2e2d2c2b2b2a29282726",
+ INIT_16 => x"2728292a2b2b2c2d2e2f30313233333435363738393a3b3c3d3e3f4041414243",
+ INIT_17 => x"15151515161616161717181819191a1a1b1c1c1d1e1e1f202121222324252526",
+ INIT_18 => x"2625242423222121201f1e1e1d1c1c1b1b1a1a19191818171717171616161616",
+ INIT_19 => x"434241403f3e3d3c3b3a39383837363534333231302f2f2e2d2c2b2a29282827",
+ INIT_1a => x"2828292a2b2c2d2e2f2f30313233343536373838393a3b3c3d3e3f4041424344",
+ INIT_1b => x"1616161617171717181819191a1a1b1b1c1c1d1e1e1f20212122232424252627",
+ INIT_1c => x"272625242323222121201f1e1e1d1d1c1b1b1a1a191919181818181717171717",
+ INIT_1d => x"434241403f3e3d3d3c3b3a39383736353433333231302f2e2d2c2c2b2a292827",
+ INIT_1e => x"28292a2b2c2c2d2e2f30313233333435363738393a3b3c3d3d3e3f4041424344",
+ INIT_1f => x"17171717181818181919191a1a1b1b1c1d1d1e1e1f2021212223232425262727",
+ INIT_20 => x"27262625242323222121201f1f1e1d1d1c1c1b1b1a1a1a191919191818181818",
+ INIT_21 => x"43424241403f3e3d3c3b3a3938373736353433323130302f2e2d2c2b2a2a2928",
+ INIT_22 => x"292a2a2b2c2d2e2f3030313233343536373738393a3b3c3d3e3f404142424344",
+ INIT_23 => x"18181818191919191a1a1a1b1b1c1c1d1d1e1f1f202121222323242526262728",
+ INIT_24 => x"2827262625242323222121201f1f1e1e1d1d1c1c1b1b1b1a1a1a191919191919",
+ INIT_25 => x"44434241403f3e3d3c3c3b3a39383736353433333231302f2e2d2d2c2b2a2929",
+ INIT_26 => x"292a2b2c2d2d2e2f30313233333435363738393a3b3c3c3d3e3f404142434445",
+ INIT_27 => x"19191919191a1a1a1b1b1b1c1c1d1d1e1e1f1f20212122232324252626272829",
+ INIT_28 => x"28282726252524232322212120201f1f1e1e1d1d1c1c1c1b1b1b1a1a1a1a1a1a",
+ INIT_29 => x"4443424140403f3e3d3c3b3a3938373736353433323131302f2e2d2c2c2b2a29",
+ INIT_2a => x"2a2b2c2c2d2e2f3031313233343536373738393a3b3c3d3e3f40404142434445",
+ INIT_2b => x"1a1a1a1a1a1b1b1b1c1c1c1d1d1e1e1f1f202021212223232425252627282829",
+ INIT_2c => x"2928282726252524232322222120201f1f1e1e1e1d1d1c1c1c1c1b1b1b1b1b1b",
+ INIT_2d => x"4544434241403f3e3d3c3b3b3a39383736353434333231302f2f2e2d2c2b2b2a",
+ INIT_2e => x"2b2b2c2d2e2f2f30313233343435363738393a3b3b3c3d3e3f40414243444545",
+ INIT_2f => x"1b1b1b1b1b1c1c1c1c1d1d1e1e1e1f1f2020212222232324252526272828292a",
+ INIT_30 => x"2a292828272626252424232222212120201f1f1e1e1e1d1d1d1d1c1c1c1c1c1c",
+ INIT_31 => x"454443424140403f3e3d3c3b3a3938383736353433323231302f2e2e2d2c2b2b",
+ INIT_32 => x"2b2c2d2e2e2f3031323233343536373838393a3b3c3d3e3f4040414243444546",
+ INIT_33 => x"1c1c1c1c1c1d1d1d1d1e1e1e1f1f202021212222232424252626272828292a2b",
+ INIT_34 => x"2a2a29282827262625242423232222212120201f1f1f1e1e1e1e1d1d1d1d1d1d",
+ INIT_35 => x"454444434241403f3e3d3c3c3b3a3938373636353433323131302f2e2d2d2c2b",
+ INIT_36 => x"2c2d2d2e2f3031313233343536363738393a3b3c3c3d3e3f4041424344444546",
+ INIT_37 => x"1d1d1d1d1d1e1e1e1e1f1f1f20202121222223232424252626272828292a2a2b",
+ INIT_38 => x"2b2a2a292828272626252524242322222221212020201f1f1f1f1e1e1e1e1e1e",
+ INIT_39 => x"46454443424140403f3e3d3c3b3a393938373635343433323130302f2e2d2d2c",
+ INIT_3a => x"2d2d2e2f303031323334343536373839393a3b3c3d3e3f404041424344454647",
+ INIT_3b => x"1e1e1e1e1e1f1f1f1f202020212122222223242425252626272828292a2a2b2c",
+ INIT_3c => x"2c2b2a2a292828272726252524242323222222212121202020201f1f1f1f1f1f",
+ INIT_3d => x"46454444434241403f3e3d3d3c3b3a393837373635343333323130302f2e2d2d",
+ INIT_3e => x"2d2e2f303031323333343536373738393a3b3c3d3d3e3f404142434444454647",
+ INIT_3f => x"1f1f1f1f1f202020202121212222222323242425252627272828292a2a2b2c2d",
+ -- The next set of INITP_xx are for the parity bits
+ -- Address 0 to 511
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 512 to 1023
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1024 to 1535
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1536 to 2047
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => memOutput(1), -- 8-bit Data Output
+ DOP => open, -- 1-bit parity Output
+ ADDR => address(10 downto 0), -- 11-bit Address Input
+ CLK => clk(1), -- Clock
+ DI => x"00", -- 8-bit Data Input
+ DIP => "0", -- 1-bit parity Input
+ EN => '1', -- RAM Enable Input
+ SSR => '0', -- Synchronous Set/Reset Input
+ WE => '0' -- Write Enable Input
+ );
+
+
+---- membblock 010 ----------------------------------
+
+ -- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
+ -- Spartan-3A
+ -- Xilinx HDL Language Template, version 12.3
+
+ RAMB16_S9_inst02 : RAMB16_S9
+ generic map (
+ INIT => X"000", -- Value of output RAM registers at startup
+ SRVAL => X"000", -- Ouput value upon SSR assertion
+ WRITE_MODE => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ -- The following INIT_xx declarations specify the initial contents of the RAM
+ -- Address 0 to 511
+ INIT_00 => x"2d2c2b2b2a292928272726262525242423232322222221212121202020202020",
+ INIT_01 => x"4746454443424140403f3e3d3c3b3b3a3938373636353433323231302f2f2e2d",
+ INIT_02 => x"2e2f2f3031323233343536363738393a3b3b3c3d3e3f40404142434445464748",
+ INIT_03 => x"20202020202121212122222223232324242525262627272829292a2b2b2c2d2d",
+ INIT_04 => x"2d2d2c2b2b2a2929282827272626252524242323232222222222212121212121",
+ INIT_05 => x"4746454444434241403f3e3e3d3c3b3a393938373635353433323231302f2f2e",
+ INIT_06 => x"2f2f303132323334353536373839393a3b3c3d3e3e3f40414243444445464748",
+ INIT_07 => x"212121212122222222222323232424252526262727282829292a2b2b2c2d2d2e",
+ INIT_08 => x"2e2d2d2c2b2b2a2a292828272726262625252424242323232323222222222222",
+ INIT_09 => x"484746454443424241403f3e3d3c3c3b3a393838373635343433323231302f2f",
+ INIT_0a => x"2f303132323334343536373838393a3b3c3c3d3e3f4041424243444546474848",
+ INIT_0b => x"22222222222323232323242424252526262627272828292a2a2b2b2c2d2d2e2f",
+ INIT_0c => x"2f2e2d2d2c2c2b2a2a2929282827272626262525252424242424232323232323",
+ INIT_0d => x"48474645454443424140403f3e3d3c3b3b3a393837373635343433323131302f",
+ INIT_0e => x"303131323334343536373738393a3b3b3c3d3e3f404041424344454546474849",
+ INIT_0f => x"232323232324242424242525252626262727282829292a2a2b2c2c2d2d2e2f2f",
+ INIT_10 => x"302f2e2e2d2c2c2b2b2a2a292928282727272626262525252524242424242424",
+ INIT_11 => x"49484746454443434241403f3e3e3d3c3b3a3a39383737363534343332323130",
+ INIT_12 => x"3132323334343536373738393a3a3b3c3d3e3e3f404142434344454647484949",
+ INIT_13 => x"24242424242425252525262626272727282829292a2a2b2b2c2c2d2e2e2f3030",
+ INIT_14 => x"30302f2e2e2d2d2c2c2b2b2a2a29292828282727272626262625252525252525",
+ INIT_15 => x"4948474646454443424141403f3e3d3d3c3b3a39393837363635343433323231",
+ INIT_16 => x"3232333434353636373839393a3b3c3d3d3e3f4041414243444546464748494a",
+ INIT_17 => x"2525252525252626262627272728282829292a2a2b2b2c2c2d2d2e2e2f303031",
+ INIT_18 => x"3130302f2f2e2d2d2c2c2b2b2a2a2a2929282828282727272726262626262626",
+ INIT_19 => x"4a4948474645454443424140403f3e3d3c3c3b3a393938373636353434333232",
+ INIT_1a => x"32333434353636373839393a3b3c3c3d3e3f4040414243444545464748494a4a",
+ INIT_1b => x"262626262626272727272828282829292a2a2a2b2b2c2c2d2d2e2f2f30303132",
+ INIT_1c => x"323131302f2f2e2e2d2d2c2c2b2b2b2a2a292929292828282827272727272727",
+ INIT_1d => x"4a4948484746454443434241403f3f3e3d3c3c3b3a3939383736363534343332",
+ INIT_1e => x"333434353636373839393a3b3c3c3d3e3f3f4041424343444546474848494a4b",
+ INIT_1f => x"27272727272728282828292929292a2a2b2b2b2c2c2d2d2e2e2f2f3031313232",
+ INIT_20 => x"3332313130302f2f2e2e2d2d2c2c2b2b2b2a2a2a292929292928282828282828",
+ INIT_21 => x"4b4a4948474646454443424241403f3e3e3d3c3b3b3a39393837363635343433",
+ INIT_22 => x"3434353636373839393a3b3b3c3d3e3e3f4041424243444546464748494a4b4b",
+ INIT_23 => x"28282828282829292929292a2a2a2b2b2b2c2c2d2d2e2e2f2f30303131323333",
+ INIT_24 => x"33333232313130302f2f2e2e2d2d2c2c2c2b2b2b2a2a2a2a2a29292929292929",
+ INIT_25 => x"4b4a494948474645454443424141403f3e3e3d3c3b3b3a393938373736353534",
+ INIT_26 => x"35353637373839393a3b3b3c3d3e3e3f404141424344454546474849494a4b4c",
+ INIT_27 => x"2929292929292a2a2a2a2a2b2b2b2c2c2c2d2d2e2e2f2f303031313232333334",
+ INIT_28 => x"3434333232313130302f2f2f2e2e2d2d2d2c2c2c2b2b2b2b2b2a2a2a2a2a2a2a",
+ INIT_29 => x"4c4b4a494848474645444443424141403f3e3e3d3c3b3b3a3939383737363535",
+ INIT_2a => x"353637373839393a3b3b3c3d3e3e3f404141424344444546474848494a4b4c4d",
+ INIT_2b => x"2a2a2a2a2a2a2b2b2b2b2b2c2c2c2d2d2d2e2e2f2f2f30303131323233343435",
+ INIT_2c => x"35343433333232313130302f2f2f2e2e2e2d2d2d2c2c2c2c2c2b2b2b2b2b2b2b",
+ INIT_2d => x"4c4b4b4a494847474645444343424140403f3e3e3d3c3b3b3a39393837373636",
+ INIT_2e => x"3637373839393a3b3b3c3d3e3e3f404041424343444546474748494a4b4b4c4d",
+ INIT_2f => x"2b2b2b2b2b2b2c2c2c2c2c2d2d2d2e2e2e2f2f2f303031313232333334343536",
+ INIT_30 => x"36353534343333323231313030302f2f2e2e2e2e2d2d2d2d2d2c2c2c2c2c2c2c",
+ INIT_31 => x"4d4c4b4a4a494847464645444343424140403f3e3e3d3c3b3b3a393938383736",
+ INIT_32 => x"37383839393a3b3b3c3d3e3e3f404041424343444546464748494a4a4b4c4d4e",
+ INIT_33 => x"2c2c2c2c2c2c2d2d2d2d2d2e2e2e2e2f2f303030313132323333343435353636",
+ INIT_34 => x"373636353434333333323231313030302f2f2f2f2e2e2e2e2e2d2d2d2d2d2d2d",
+ INIT_35 => x"4d4d4c4b4a49494847464645444343424140403f3e3e3d3c3c3b3a3a39383837",
+ INIT_36 => x"3838393a3a3b3c3c3d3e3e3f40404142434344454646474849494a4b4c4d4d4e",
+ INIT_37 => x"2d2d2d2d2d2d2e2e2e2e2e2f2f2f2f3030303131323233333334343536363737",
+ INIT_38 => x"37373636353534343333333232313131303030302f2f2f2f2f2e2e2e2e2e2e2e",
+ INIT_39 => x"4e4d4c4c4b4a49484847464545444342424140403f3e3e3d3c3c3b3a3a393938",
+ INIT_3a => x"39393a3a3b3c3c3d3e3e3f40404142424344454546474848494a4b4c4c4d4e4f",
+ INIT_3b => x"2e2e2e2e2e2e2f2f2f2f2f303030303131313232333333343435353636373738",
+ INIT_3c => x"383837373636353534343333333232323131313130303030302f2f2f2f2f2f2f",
+ INIT_3d => x"4f4e4d4c4b4b4a49484847464545444342424140403f3e3e3d3c3c3b3b3a3939",
+ INIT_3e => x"393a3b3b3c3c3d3e3e3f40404142424344454546474848494a4b4b4c4d4e4f4f",
+ INIT_3f => x"2f2f2f2f2f2f3030303030313131313232323333333434353536363737383839",
+ -- The next set of INITP_xx are for the parity bits
+ -- Address 0 to 511
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 512 to 1023
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1024 to 1535
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1536 to 2047
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => memOutput(2), -- 8-bit Data Output
+ DOP => open, -- 1-bit parity Output
+ ADDR => address(10 downto 0), -- 11-bit Address Input
+ CLK => clk(1), -- Clock
+ DI => x"00", -- 8-bit Data Input
+ DIP => "0", -- 1-bit parity Input
+ EN => '1', -- RAM Enable Input
+ SSR => '0', -- Synchronous Set/Reset Input
+ WE => '0' -- Write Enable Input
+ );
+
+
+---- membblock 011 ----------------------------------
+
+ -- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
+ -- Spartan-3A
+ -- Xilinx HDL Language Template, version 12.3
+
+ RAMB16_S9_inst03 : RAMB16_S9
+ generic map (
+ INIT => X"000", -- Value of output RAM registers at startup
+ SRVAL => X"000", -- Ouput value upon SSR assertion
+ WRITE_MODE => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ -- The following INIT_xx declarations specify the initial contents of the RAM
+ -- Address 0 to 511
+ INIT_00 => x"3939383837373636353534343433333332323231313131313130303030303030",
+ INIT_01 => x"4f4e4e4d4c4b4b4a49484847464545444342424140403f3e3e3d3d3c3b3b3a3a",
+ INIT_02 => x"3a3b3b3c3d3d3e3e3f40404142424344454546474848494a4b4b4c4d4e4e4f50",
+ INIT_03 => x"303030303030313131313131323232333333343434353536363737383839393a",
+ INIT_04 => x"3a39393838373737363635353534343433333332323232323131313131313131",
+ INIT_05 => x"504f4e4d4d4c4b4a4a49484747464545444343424141403f3f3e3d3d3c3c3b3b",
+ INIT_06 => x"3b3c3c3d3d3e3f3f40414142434344454546474748494a4a4b4c4d4d4e4f5051",
+ INIT_07 => x"3131313131313132323232323333333434343535353636373737383839393a3b",
+ INIT_08 => x"3b3a3a3939383837373736363535353434343433333333333232323232323232",
+ INIT_09 => x"50504f4e4d4d4c4b4a4a49484747464545444343424141403f3f3e3e3d3c3c3b",
+ INIT_0a => x"3c3c3d3e3e3f3f40414142434344454546474748494a4a4b4c4d4d4e4f505051",
+ INIT_0b => x"323232323232323333333333343434343535353636373737383839393a3a3b3b",
+ INIT_0c => x"3c3b3b3a3a393938383837373636363535353534343434343333333333333333",
+ INIT_0d => x"5150504f4e4d4c4c4b4a4a4948474746454544434342414140403f3e3e3d3d3c",
+ INIT_0e => x"3d3d3e3e3f4040414142434344454546474748494a4a4b4c4c4d4e4f50505152",
+ INIT_0f => x"33333333333333343434343435353535363636373738383839393a3a3b3b3c3c",
+ INIT_10 => x"3d3c3c3b3b3a3a39393838383737373636363635353535353434343434343434",
+ INIT_11 => x"5251504f4f4e4d4c4c4b4a4a4948474746454544434342424140403f3f3e3e3d",
+ INIT_12 => x"3e3e3f3f4040414242434344454546474748494a4a4b4c4c4d4e4f4f50515252",
+ INIT_13 => x"3434343434343435353535353636363637373738383839393a3a3b3b3c3c3d3d",
+ INIT_14 => x"3d3d3c3c3b3b3b3a3a3939393838383737373736363636363535353535353535",
+ INIT_15 => x"525251504f4f4e4d4c4c4b4a4a494848474646454444434242414140403f3e3e",
+ INIT_16 => x"3e3f404041414242434444454646474848494a4a4b4c4c4d4e4f4f5051525253",
+ INIT_17 => x"353535353535353636363636373737373838383939393a3a3b3b3b3c3c3d3d3e",
+ INIT_18 => x"3e3e3d3d3c3c3c3b3b3a3a3a3939393838383837373737373636363636363636",
+ INIT_19 => x"53525151504f4f4e4d4c4c4b4a4a494848474646454444434342414140403f3f",
+ INIT_1a => x"3f404041414243434444454646474848494a4a4b4c4c4d4e4f4f505151525354",
+ INIT_1b => x"363636363636363737373737383838383939393a3a3a3b3b3c3c3c3d3d3e3e3f",
+ INIT_1c => x"3f3f3e3e3d3d3c3c3c3b3b3b3a3a3a3939393938383838383737373737373737",
+ INIT_1d => x"5453525151504f4e4e4d4c4c4b4a4a4948484746464545444343424241414040",
+ INIT_1e => x"404141424243434445454646474848494a4a4b4c4c4d4e4e4f50515152535454",
+ INIT_1f => x"373737373737373838383838393939393a3a3a3b3b3b3c3c3c3d3d3e3e3f3f40",
+ INIT_20 => x"40403f3f3e3e3d3d3d3c3c3b3b3b3b3a3a3a3939393939393838383838383838",
+ INIT_21 => x"545453525151504f4e4e4d4c4c4b4a4a49484847474645454444434342424140",
+ INIT_22 => x"4142424343444445454647474848494a4a4b4c4c4d4e4e4f5051515253545455",
+ INIT_23 => x"383838383838383939393939393a3a3a3b3b3b3b3c3c3d3d3d3e3e3f3f404040",
+ INIT_24 => x"414040403f3f3e3e3d3d3d3c3c3c3b3b3b3b3a3a3a3a3a3a3939393939393939",
+ INIT_25 => x"55545353525151504f4f4e4d4c4c4b4b4a494948474746464545444343424241",
+ INIT_26 => x"42424343444545464647474849494a4b4b4c4c4d4e4f4f505151525353545556",
+ INIT_27 => x"393939393939393a3a3a3a3a3a3b3b3b3b3c3c3c3d3d3d3e3e3f3f4040404141",
+ INIT_28 => x"4241414040403f3f3e3e3e3d3d3d3c3c3c3c3b3b3b3b3b3b3a3a3a3a3a3a3a3a",
+ INIT_29 => x"5655545353525151504f4f4e4d4d4c4b4b4a4949484847464645454444434342",
+ INIT_2a => x"434344444545464647484849494a4b4b4c4d4d4e4f4f50515152535354555656",
+ INIT_2b => x"3a3a3a3a3a3a3a3b3b3b3b3b3b3c3c3c3c3d3d3d3e3e3e3f3f40404041414242",
+ INIT_2c => x"43424241414040403f3f3f3e3e3e3d3d3d3d3c3c3c3c3c3c3b3b3b3b3b3b3b3b",
+ INIT_2d => x"565655545353525151504f4f4e4d4d4c4b4b4a4a494848474746464545444443",
+ INIT_2e => x"44444545464647474848494a4a4b4b4c4d4d4e4f4f5051515253535455565657",
+ INIT_2f => x"3b3b3b3b3b3b3b3c3c3c3c3c3c3d3d3d3d3e3e3e3f3f3f404040414142424343",
+ INIT_30 => x"44434342424141414040403f3f3f3e3e3e3e3d3d3d3d3d3d3c3c3c3c3c3c3c3c",
+ INIT_31 => x"57565655545353525151504f4f4e4d4d4c4c4b4a4a4949484847464645454444",
+ INIT_32 => x"444545464647484849494a4a4b4c4c4d4d4e4f4f505151525353545556565758",
+ INIT_33 => x"3c3c3c3c3c3c3c3d3d3d3d3d3d3e3e3e3e3f3f3f404040414141424243434444",
+ INIT_34 => x"44444443434242424141414040403f3f3f3f3e3e3e3e3e3e3d3d3d3d3d3d3d3d",
+ INIT_35 => x"585756565554535352515150504f4e4e4d4c4c4b4b4a49494848474746464545",
+ INIT_36 => x"4546464747484849494a4b4b4c4c4d4e4e4f5050515152535354555656575858",
+ INIT_37 => x"3d3d3d3d3d3d3d3e3e3e3e3e3e3f3f3f3f404040414141424242434344444445",
+ INIT_38 => x"4545444444434342424241414141404040403f3f3f3f3f3f3e3e3e3e3e3e3e3e",
+ INIT_39 => x"58585756565554545352525150504f4e4e4d4d4c4b4b4a4a4949484847474646",
+ INIT_3a => x"464747484849494a4a4b4b4c4d4d4e4e4f505051525253545455565657585859",
+ INIT_3b => x"3e3e3e3e3e3e3e3f3f3f3f3f3f40404040414141414242424343444444454546",
+ INIT_3c => x"4646454545444443434342424242414141414040404040403f3f3f3f3f3f3f3f",
+ INIT_3d => x"5958585756565554545352525150504f4f4e4d4d4c4c4b4b4a4a494948484747",
+ INIT_3e => x"47484849494a4a4b4b4c4c4d4d4e4f4f5050515252535454555656575858595a",
+ INIT_3f => x"3f3f3f3f3f3f3f40404040404041414141424242424343434444454545464647",
+ -- The next set of INITP_xx are for the parity bits
+ -- Address 0 to 511
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 512 to 1023
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1024 to 1535
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1536 to 2047
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => memOutput(3), -- 8-bit Data Output
+ DOP => open, -- 1-bit parity Output
+ ADDR => address(10 downto 0), -- 11-bit Address Input
+ CLK => clk(1), -- Clock
+ DI => x"00", -- 8-bit Data Input
+ DIP => "0", -- 1-bit parity Input
+ EN => '1', -- RAM Enable Input
+ SSR => '0', -- Synchronous Set/Reset Input
+ WE => '0' -- Write Enable Input
+ );
+
+
+---- membblock 100 ----------------------------------
+
+ -- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
+ -- Spartan-3A
+ -- Xilinx HDL Language Template, version 12.3
+
+ RAMB16_S9_inst04 : RAMB16_S9
+ generic map (
+ INIT => X"000", -- Value of output RAM registers at startup
+ SRVAL => X"000", -- Ouput value upon SSR assertion
+ WRITE_MODE => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ -- The following INIT_xx declarations specify the initial contents of the RAM
+ -- Address 0 to 511
+ INIT_00 => x"4747464645454544444443434342424242424141414141404040404040404040",
+ INIT_01 => x"5a5958585756565554545352525151504f4f4e4e4d4d4c4b4b4a4a4949484848",
+ INIT_02 => x"484849494a4a4b4b4c4d4d4e4e4f4f5051515252535454555656575858595a5b",
+ INIT_03 => x"4040404040404040414141414142424242424343434444444545454646474748",
+ INIT_04 => x"4646454545444443434342424242414141414040404040403f3f3f3f3f3f3f3f",
+ INIT_05 => x"5958585756565554545352525150504f4f4e4d4d4c4c4b4b4a4a494948484747",
+ INIT_06 => x"47484849494a4a4b4b4c4c4d4d4e4f4f5050515252535454555656575858595a",
+ INIT_07 => x"3f3f3f3f3f3f3f40404040404041414141424242424343434444454545464647",
+ INIT_08 => x"4545444444434342424241414141404040403f3f3f3f3f3f3e3e3e3e3e3e3e3e",
+ INIT_09 => x"58585756565554545352525150504f4e4e4d4d4c4b4b4a4a4949484847474646",
+ INIT_0a => x"464747484849494a4a4b4b4c4d4d4e4e4f505051525253545455565657585859",
+ INIT_0b => x"3e3e3e3e3e3e3e3f3f3f3f3f3f40404040414141414242424343444444454546",
+ INIT_0c => x"44444443434242424141414040403f3f3f3f3e3e3e3e3e3e3d3d3d3d3d3d3d3d",
+ INIT_0d => x"585756565554535352515150504f4e4e4d4c4c4b4b4a49494848474746464545",
+ INIT_0e => x"4546464747484849494a4b4b4c4c4d4e4e4f5050515152535354555656575858",
+ INIT_0f => x"3d3d3d3d3d3d3d3e3e3e3e3e3e3f3f3f3f404040414141424242434344444445",
+ INIT_10 => x"44434342424141414040403f3f3f3e3e3e3e3d3d3d3d3d3d3c3c3c3c3c3c3c3c",
+ INIT_11 => x"57565655545353525151504f4f4e4d4d4c4c4b4a4a4949484847464645454444",
+ INIT_12 => x"444545464647484849494a4a4b4c4c4d4d4e4f4f505151525353545556565758",
+ INIT_13 => x"3c3c3c3c3c3c3c3d3d3d3d3d3d3e3e3e3e3f3f3f404040414141424243434444",
+ INIT_14 => x"43424241414040403f3f3f3e3e3e3d3d3d3d3c3c3c3c3c3c3b3b3b3b3b3b3b3b",
+ INIT_15 => x"565655545353525151504f4f4e4d4d4c4b4b4a4a494848474746464545444443",
+ INIT_16 => x"44444545464647474848494a4a4b4b4c4d4d4e4f4f5051515253535455565657",
+ INIT_17 => x"3b3b3b3b3b3b3b3c3c3c3c3c3c3d3d3d3d3e3e3e3f3f3f404040414142424343",
+ INIT_18 => x"4241414040403f3f3e3e3e3d3d3d3c3c3c3c3b3b3b3b3b3b3a3a3a3a3a3a3a3a",
+ INIT_19 => x"5655545353525151504f4f4e4d4d4c4b4b4a4949484847464645454444434342",
+ INIT_1a => x"434344444545464647484849494a4b4b4c4d4d4e4f4f50515152535354555656",
+ INIT_1b => x"3a3a3a3a3a3a3a3b3b3b3b3b3b3c3c3c3c3d3d3d3e3e3e3f3f40404041414242",
+ INIT_1c => x"414040403f3f3e3e3d3d3d3c3c3c3b3b3b3b3a3a3a3a3a3a3939393939393939",
+ INIT_1d => x"55545353525151504f4f4e4d4c4c4b4b4a494948474746464545444343424241",
+ INIT_1e => x"42424343444545464647474849494a4b4b4c4c4d4e4f4f505151525353545556",
+ INIT_1f => x"393939393939393a3a3a3a3a3a3b3b3b3b3c3c3c3d3d3d3e3e3f3f4040404141",
+ INIT_20 => x"40403f3f3e3e3d3d3d3c3c3b3b3b3b3a3a3a3939393939393838383838383838",
+ INIT_21 => x"545453525151504f4e4e4d4c4c4b4a4a49484847474645454444434342424140",
+ INIT_22 => x"4142424343444445454647474848494a4a4b4c4c4d4e4e4f5051515253545455",
+ INIT_23 => x"383838383838383939393939393a3a3a3b3b3b3b3c3c3d3d3d3e3e3f3f404040",
+ INIT_24 => x"3f3f3e3e3d3d3c3c3c3b3b3b3a3a3a3939393938383838383737373737373737",
+ INIT_25 => x"5453525151504f4e4e4d4c4c4b4a4a4948484746464545444343424241414040",
+ INIT_26 => x"404141424243434445454646474848494a4a4b4c4c4d4e4e4f50515152535454",
+ INIT_27 => x"373737373737373838383838393939393a3a3a3b3b3b3c3c3c3d3d3e3e3f3f40",
+ INIT_28 => x"3e3e3d3d3c3c3c3b3b3a3a3a3939393838383837373737373636363636363636",
+ INIT_29 => x"53525151504f4f4e4d4c4c4b4a4a494848474646454444434342414140403f3f",
+ INIT_2a => x"3f404041414243434444454646474848494a4a4b4c4c4d4e4f4f505151525354",
+ INIT_2b => x"363636363636363737373737383838383939393a3a3a3b3b3c3c3c3d3d3e3e3f",
+ INIT_2c => x"3d3d3c3c3b3b3b3a3a3939393838383737373736363636363535353535353535",
+ INIT_2d => x"525251504f4f4e4d4c4c4b4a4a494848474646454444434242414140403f3e3e",
+ INIT_2e => x"3e3f404041414242434444454646474848494a4a4b4c4c4d4e4f4f5051525253",
+ INIT_2f => x"353535353535353636363636373737373838383939393a3a3b3b3b3c3c3d3d3e",
+ INIT_30 => x"3d3c3c3b3b3a3a39393838383737373636363635353535353434343434343434",
+ INIT_31 => x"5251504f4f4e4d4c4c4b4a4a4948474746454544434342424140403f3f3e3e3d",
+ INIT_32 => x"3e3e3f3f4040414242434344454546474748494a4a4b4c4c4d4e4f4f50515252",
+ INIT_33 => x"3434343434343435353535353636363637373738383839393a3a3b3b3c3c3d3d",
+ INIT_34 => x"3c3b3b3a3a393938383837373636363535353534343434343333333333333333",
+ INIT_35 => x"5150504f4e4d4c4c4b4a4a4948474746454544434342414140403f3e3e3d3d3c",
+ INIT_36 => x"3d3d3e3e3f4040414142434344454546474748494a4a4b4c4c4d4e4f50505152",
+ INIT_37 => x"33333333333333343434343435353535363636373738383839393a3a3b3b3c3c",
+ INIT_38 => x"3b3a3a3939383837373736363535353434343433333333333232323232323232",
+ INIT_39 => x"50504f4e4d4d4c4b4a4a49484747464545444343424141403f3f3e3e3d3c3c3b",
+ INIT_3a => x"3c3c3d3e3e3f3f40414142434344454546474748494a4a4b4c4d4d4e4f505051",
+ INIT_3b => x"323232323232323333333333343434343535353636373737383839393a3a3b3b",
+ INIT_3c => x"3a39393838373737363635353534343433333332323232323131313131313131",
+ INIT_3d => x"504f4e4d4d4c4b4a4a49484747464545444343424141403f3f3e3d3d3c3c3b3b",
+ INIT_3e => x"3b3c3c3d3d3e3f3f40414142434344454546474748494a4a4b4c4d4d4e4f5051",
+ INIT_3f => x"3131313131313132323232323333333434343535353636373737383839393a3b",
+ -- The next set of INITP_xx are for the parity bits
+ -- Address 0 to 511
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 512 to 1023
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1024 to 1535
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1536 to 2047
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => memOutput(4), -- 8-bit Data Output
+ DOP => open, -- 1-bit parity Output
+ ADDR => address(10 downto 0), -- 11-bit Address Input
+ CLK => clk(1), -- Clock
+ DI => x"00", -- 8-bit Data Input
+ DIP => "0", -- 1-bit parity Input
+ EN => '1', -- RAM Enable Input
+ SSR => '0', -- Synchronous Set/Reset Input
+ WE => '0' -- Write Enable Input
+ );
+
+
+---- membblock 101 ----------------------------------
+
+ -- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
+ -- Spartan-3A
+ -- Xilinx HDL Language Template, version 12.3
+
+ RAMB16_S9_inst05 : RAMB16_S9
+ generic map (
+ INIT => X"000", -- Value of output RAM registers at startup
+ SRVAL => X"000", -- Ouput value upon SSR assertion
+ WRITE_MODE => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ -- The following INIT_xx declarations specify the initial contents of the RAM
+ -- Address 0 to 511
+ INIT_00 => x"3939383837373636353534343433333332323231313131313130303030303030",
+ INIT_01 => x"4f4e4e4d4c4b4b4a49484847464545444342424140403f3e3e3d3d3c3b3b3a3a",
+ INIT_02 => x"3a3b3b3c3d3d3e3e3f40404142424344454546474848494a4b4b4c4d4e4e4f50",
+ INIT_03 => x"303030303030313131313131323232333333343434353536363737383839393a",
+ INIT_04 => x"383837373636353534343333333232323131313130303030302f2f2f2f2f2f2f",
+ INIT_05 => x"4f4e4d4c4b4b4a49484847464545444342424140403f3e3e3d3c3c3b3b3a3939",
+ INIT_06 => x"393a3b3b3c3c3d3e3e3f40404142424344454546474848494a4b4b4c4d4e4f4f",
+ INIT_07 => x"2f2f2f2f2f2f3030303030313131313232323333333434353536363737383839",
+ INIT_08 => x"37373636353534343333333232313131303030302f2f2f2f2f2e2e2e2e2e2e2e",
+ INIT_09 => x"4e4d4c4c4b4a49484847464545444342424140403f3e3e3d3c3c3b3a3a393938",
+ INIT_0a => x"39393a3a3b3c3c3d3e3e3f40404142424344454546474848494a4b4c4c4d4e4f",
+ INIT_0b => x"2e2e2e2e2e2e2f2f2f2f2f303030303131313232333333343435353636373738",
+ INIT_0c => x"373636353434333333323231313030302f2f2f2f2e2e2e2e2e2d2d2d2d2d2d2d",
+ INIT_0d => x"4d4d4c4b4a49494847464645444343424140403f3e3e3d3c3c3b3a3a39383837",
+ INIT_0e => x"3838393a3a3b3c3c3d3e3e3f40404142434344454646474849494a4b4c4d4d4e",
+ INIT_0f => x"2d2d2d2d2d2d2e2e2e2e2e2f2f2f2f3030303131323233333334343536363737",
+ INIT_10 => x"36353534343333323231313030302f2f2e2e2e2e2d2d2d2d2d2c2c2c2c2c2c2c",
+ INIT_11 => x"4d4c4b4a4a494847464645444343424140403f3e3e3d3c3b3b3a393938383736",
+ INIT_12 => x"37383839393a3b3b3c3d3e3e3f404041424343444546464748494a4a4b4c4d4e",
+ INIT_13 => x"2c2c2c2c2c2c2d2d2d2d2d2e2e2e2e2f2f303030313132323333343435353636",
+ INIT_14 => x"35343433333232313130302f2f2f2e2e2e2d2d2d2c2c2c2c2c2b2b2b2b2b2b2b",
+ INIT_15 => x"4c4b4b4a494847474645444343424140403f3e3e3d3c3b3b3a39393837373636",
+ INIT_16 => x"3637373839393a3b3b3c3d3e3e3f404041424343444546474748494a4b4b4c4d",
+ INIT_17 => x"2b2b2b2b2b2b2c2c2c2c2c2d2d2d2e2e2e2f2f2f303031313232333334343536",
+ INIT_18 => x"3434333232313130302f2f2f2e2e2d2d2d2c2c2c2b2b2b2b2b2a2a2a2a2a2a2a",
+ INIT_19 => x"4c4b4a494848474645444443424141403f3e3e3d3c3b3b3a3939383737363535",
+ INIT_1a => x"353637373839393a3b3b3c3d3e3e3f404141424344444546474848494a4b4c4d",
+ INIT_1b => x"2a2a2a2a2a2a2b2b2b2b2b2c2c2c2d2d2d2e2e2f2f2f30303131323233343435",
+ INIT_1c => x"33333232313130302f2f2e2e2d2d2c2c2c2b2b2b2a2a2a2a2a29292929292929",
+ INIT_1d => x"4b4a494948474645454443424141403f3e3e3d3c3b3b3a393938373736353534",
+ INIT_1e => x"35353637373839393a3b3b3c3d3e3e3f404141424344454546474849494a4b4c",
+ INIT_1f => x"2929292929292a2a2a2a2a2b2b2b2c2c2c2d2d2e2e2f2f303031313232333334",
+ INIT_20 => x"3332313130302f2f2e2e2d2d2c2c2b2b2b2a2a2a292929292928282828282828",
+ INIT_21 => x"4b4a4948474646454443424241403f3e3e3d3c3b3b3a39393837363635343433",
+ INIT_22 => x"3434353636373839393a3b3b3c3d3e3e3f4041424243444546464748494a4b4b",
+ INIT_23 => x"28282828282829292929292a2a2a2b2b2b2c2c2d2d2e2e2f2f30303131323333",
+ INIT_24 => x"323131302f2f2e2e2d2d2c2c2b2b2b2a2a292929292828282827272727272727",
+ INIT_25 => x"4a4948484746454443434241403f3f3e3d3c3c3b3a3939383736363534343332",
+ INIT_26 => x"333434353636373839393a3b3c3c3d3e3f3f4041424343444546474848494a4b",
+ INIT_27 => x"27272727272728282828292929292a2a2b2b2b2c2c2d2d2e2e2f2f3031313232",
+ INIT_28 => x"3130302f2f2e2d2d2c2c2b2b2a2a2a2929282828282727272726262626262626",
+ INIT_29 => x"4a4948474645454443424140403f3e3d3c3c3b3a393938373636353434333232",
+ INIT_2a => x"32333434353636373839393a3b3c3c3d3e3f4040414243444545464748494a4a",
+ INIT_2b => x"262626262626272727272828282829292a2a2a2b2b2c2c2d2d2e2f2f30303132",
+ INIT_2c => x"30302f2e2e2d2d2c2c2b2b2a2a29292828282727272626262625252525252525",
+ INIT_2d => x"4948474646454443424141403f3e3d3d3c3b3a39393837363635343433323231",
+ INIT_2e => x"3232333434353636373839393a3b3c3d3d3e3f4041414243444546464748494a",
+ INIT_2f => x"2525252525252626262627272728282829292a2a2b2b2c2c2d2d2e2e2f303031",
+ INIT_30 => x"302f2e2e2d2c2c2b2b2a2a292928282727272626262525252524242424242424",
+ INIT_31 => x"49484746454443434241403f3e3e3d3c3b3a3a39383737363534343332323130",
+ INIT_32 => x"3132323334343536373738393a3a3b3c3d3e3e3f404142434344454647484949",
+ INIT_33 => x"24242424242425252525262626272727282829292a2a2b2b2c2c2d2e2e2f3030",
+ INIT_34 => x"2f2e2d2d2c2c2b2a2a2929282827272626262525252424242424232323232323",
+ INIT_35 => x"48474645454443424140403f3e3d3c3b3b3a393837373635343433323131302f",
+ INIT_36 => x"303131323334343536373738393a3b3b3c3d3e3f404041424344454546474849",
+ INIT_37 => x"232323232324242424242525252626262727282829292a2a2b2c2c2d2d2e2f2f",
+ INIT_38 => x"2e2d2d2c2b2b2a2a292828272726262625252424242323232323222222222222",
+ INIT_39 => x"484746454443424241403f3e3d3c3c3b3a393838373635343433323231302f2f",
+ INIT_3a => x"2f303132323334343536373838393a3b3c3c3d3e3f4041424243444546474848",
+ INIT_3b => x"22222222222323232323242424252526262627272828292a2a2b2b2c2d2d2e2f",
+ INIT_3c => x"2d2d2c2b2b2a2929282827272626252524242323232222222222212121212121",
+ INIT_3d => x"4746454444434241403f3e3e3d3c3b3a393938373635353433323231302f2f2e",
+ INIT_3e => x"2f2f303132323334353536373839393a3b3c3d3e3e3f40414243444445464748",
+ INIT_3f => x"212121212122222222222323232424252526262727282829292a2b2b2c2d2d2e",
+ -- The next set of INITP_xx are for the parity bits
+ -- Address 0 to 511
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 512 to 1023
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1024 to 1535
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1536 to 2047
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => memOutput(5), -- 8-bit Data Output
+ DOP => open, -- 1-bit parity Output
+ ADDR => address(10 downto 0), -- 11-bit Address Input
+ CLK => clk(1), -- Clock
+ DI => x"00", -- 8-bit Data Input
+ DIP => "0", -- 1-bit parity Input
+ EN => '1', -- RAM Enable Input
+ SSR => '0', -- Synchronous Set/Reset Input
+ WE => '0' -- Write Enable Input
+ );
+
+
+---- membblock 110 ----------------------------------
+
+ -- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
+ -- Spartan-3A
+ -- Xilinx HDL Language Template, version 12.3
+
+ RAMB16_S9_inst06 : RAMB16_S9
+ generic map (
+ INIT => X"000", -- Value of output RAM registers at startup
+ SRVAL => X"000", -- Ouput value upon SSR assertion
+ WRITE_MODE => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ -- The following INIT_xx declarations specify the initial contents of the RAM
+ -- Address 0 to 511
+ INIT_00 => x"2d2c2b2b2a292928272726262525242423232322222221212121202020202020",
+ INIT_01 => x"4746454443424140403f3e3d3c3b3b3a3938373636353433323231302f2f2e2d",
+ INIT_02 => x"2e2f2f3031323233343536363738393a3b3b3c3d3e3f40404142434445464748",
+ INIT_03 => x"20202020202121212122222223232324242525262627272829292a2b2b2c2d2d",
+ INIT_04 => x"2c2b2a2a292828272726252524242323222222212121202020201f1f1f1f1f1f",
+ INIT_05 => x"46454444434241403f3e3d3d3c3b3a393837373635343333323130302f2e2d2d",
+ INIT_06 => x"2d2e2f303031323333343536373738393a3b3c3d3d3e3f404142434444454647",
+ INIT_07 => x"1f1f1f1f1f202020202121212222222323242425252627272828292a2a2b2c2d",
+ INIT_08 => x"2b2a2a292828272626252524242322222221212020201f1f1f1f1e1e1e1e1e1e",
+ INIT_09 => x"46454443424140403f3e3d3c3b3a393938373635343433323130302f2e2d2d2c",
+ INIT_0a => x"2d2d2e2f303031323334343536373839393a3b3c3d3e3f404041424344454647",
+ INIT_0b => x"1e1e1e1e1e1f1f1f1f202020212122222223242425252626272828292a2a2b2c",
+ INIT_0c => x"2a2a29282827262625242423232222212120201f1f1f1e1e1e1e1d1d1d1d1d1d",
+ INIT_0d => x"454444434241403f3e3d3c3c3b3a3938373636353433323131302f2e2d2d2c2b",
+ INIT_0e => x"2c2d2d2e2f3031313233343536363738393a3b3c3c3d3e3f4041424344444546",
+ INIT_0f => x"1d1d1d1d1d1e1e1e1e1f1f1f20202121222223232424252626272828292a2a2b",
+ INIT_10 => x"2a292828272626252424232222212120201f1f1e1e1e1d1d1d1d1c1c1c1c1c1c",
+ INIT_11 => x"454443424140403f3e3d3c3b3a3938383736353433323231302f2e2e2d2c2b2b",
+ INIT_12 => x"2b2c2d2e2e2f3031323233343536373838393a3b3c3d3e3f4040414243444546",
+ INIT_13 => x"1c1c1c1c1c1d1d1d1d1e1e1e1f1f202021212222232424252626272828292a2b",
+ INIT_14 => x"2928282726252524232322222120201f1f1e1e1e1d1d1c1c1c1c1b1b1b1b1b1b",
+ INIT_15 => x"4544434241403f3e3d3c3b3b3a39383736353434333231302f2f2e2d2c2b2b2a",
+ INIT_16 => x"2b2b2c2d2e2f2f30313233343435363738393a3b3b3c3d3e3f40414243444545",
+ INIT_17 => x"1b1b1b1b1b1c1c1c1c1d1d1e1e1e1f1f2020212222232324252526272828292a",
+ INIT_18 => x"28282726252524232322212120201f1f1e1e1d1d1c1c1c1b1b1b1a1a1a1a1a1a",
+ INIT_19 => x"4443424140403f3e3d3c3b3a3938373736353433323131302f2e2d2c2c2b2a29",
+ INIT_1a => x"2a2b2c2c2d2e2f3031313233343536373738393a3b3c3d3e3f40404142434445",
+ INIT_1b => x"1a1a1a1a1a1b1b1b1c1c1c1d1d1e1e1f1f202021212223232425252627282829",
+ INIT_1c => x"2827262625242323222121201f1f1e1e1d1d1c1c1b1b1b1a1a1a191919191919",
+ INIT_1d => x"44434241403f3e3d3c3c3b3a39383736353433333231302f2e2d2d2c2b2a2929",
+ INIT_1e => x"292a2b2c2d2d2e2f30313233333435363738393a3b3c3c3d3e3f404142434445",
+ INIT_1f => x"19191919191a1a1a1b1b1b1c1c1d1d1e1e1f1f20212122232324252626272829",
+ INIT_20 => x"27262625242323222121201f1f1e1d1d1c1c1b1b1a1a1a191919191818181818",
+ INIT_21 => x"43424241403f3e3d3c3b3a3938373736353433323130302f2e2d2c2b2a2a2928",
+ INIT_22 => x"292a2a2b2c2d2e2f3030313233343536373738393a3b3c3d3e3f404142424344",
+ INIT_23 => x"18181818191919191a1a1a1b1b1c1c1d1d1e1f1f202121222323242526262728",
+ INIT_24 => x"272625242323222121201f1e1e1d1d1c1b1b1a1a191919181818181717171717",
+ INIT_25 => x"434241403f3e3d3d3c3b3a39383736353433333231302f2e2d2c2c2b2a292827",
+ INIT_26 => x"28292a2b2c2c2d2e2f30313233333435363738393a3b3c3d3d3e3f4041424344",
+ INIT_27 => x"17171717181818181919191a1a1b1b1c1d1d1e1e1f2021212223232425262727",
+ INIT_28 => x"2625242423222121201f1e1e1d1c1c1b1b1a1a19191818171717171616161616",
+ INIT_29 => x"434241403f3e3d3c3b3a39383837363534333231302f2f2e2d2c2b2a29282827",
+ INIT_2a => x"2828292a2b2c2d2e2f2f30313233343536373838393a3b3c3d3e3f4041424344",
+ INIT_2b => x"1616161617171717181819191a1a1b1b1c1c1d1e1e1f20212122232424252627",
+ INIT_2c => x"25252423222121201f1e1e1d1c1c1b1a1a191918181717161616161515151515",
+ INIT_2d => x"424141403f3e3d3c3b3a39383736353433333231302f2e2d2c2b2b2a29282726",
+ INIT_2e => x"2728292a2b2b2c2d2e2f30313233333435363738393a3b3c3d3e3f4041414243",
+ INIT_2f => x"15151515161616161717181819191a1a1b1c1c1d1e1e1f202121222324252526",
+ INIT_30 => x"252423222221201f1e1e1d1c1c1b1a1a19181817171616161515151414141414",
+ INIT_31 => x"4241403f3e3d3c3b3b3a393837363534333231302f2f2e2d2c2b2a2928272726",
+ INIT_32 => x"272728292a2b2c2d2e2f2f303132333435363738393a3b3b3c3d3e3f40414243",
+ INIT_33 => x"1414141415151516161617171818191a1a1b1c1c1d1e1e1f2021222223242526",
+ INIT_34 => x"2424232221201f1f1e1d1c1c1b1a191918181716161515151414141313131313",
+ INIT_35 => x"4241403f3e3d3c3b3a39383736353534333231302f2e2d2c2b2a2a2928272625",
+ INIT_36 => x"262728292a2a2b2c2d2e2f30313233343535363738393a3b3c3d3e3f40414243",
+ INIT_37 => x"13131313141414151515161617181819191a1b1c1c1d1e1f1f20212223242425",
+ INIT_38 => x"2423222120201f1e1d1c1c1b1a19191817171616151514141313131212121212",
+ INIT_39 => x"4241403f3e3d3c3b3a39383736353433323130302f2e2d2c2b2a292827262625",
+ INIT_3a => x"26262728292a2b2c2d2e2f30303132333435363738393a3b3c3d3e3f40414242",
+ INIT_3b => x"1212121213131314141515161617171819191a1b1c1c1d1e1f20202122232425",
+ INIT_3c => x"23222221201f1e1d1d1c1b1a1919181717161515141413131212121111111111",
+ INIT_3d => x"41403f3e3d3c3b3b3a393837363534333231302f2e2d2c2b2b2a292827262524",
+ INIT_3e => x"25262728292a2b2b2c2d2e2f303132333435363738393a3b3b3c3d3e3f404142",
+ INIT_3f => x"111111111212121313141415151617171819191a1b1c1d1d1e1f202122222324",
+ -- The next set of INITP_xx are for the parity bits
+ -- Address 0 to 511
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 512 to 1023
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1024 to 1535
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1536 to 2047
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => memOutput(6), -- 8-bit Data Output
+ DOP => open, -- 1-bit parity Output
+ ADDR => address(10 downto 0), -- 11-bit Address Input
+ CLK => clk(1), -- Clock
+ DI => x"00", -- 8-bit Data Input
+ DIP => "0", -- 1-bit parity Input
+ EN => '1', -- RAM Enable Input
+ SSR => '0', -- Synchronous Set/Reset Input
+ WE => '0' -- Write Enable Input
+ );
+
+
+---- membblock 111 ----------------------------------
+
+ -- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
+ -- Spartan-3A
+ -- Xilinx HDL Language Template, version 12.3
+
+ RAMB16_S9_inst07 : RAMB16_S9
+ generic map (
+ INIT => X"000", -- Value of output RAM registers at startup
+ SRVAL => X"000", -- Ouput value upon SSR assertion
+ WRITE_MODE => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ -- The following INIT_xx declarations specify the initial contents of the RAM
+ -- Address 0 to 511
+ INIT_00 => x"232221201f1f1e1d1c1b1a1a1918171716151514131312121111111010101010",
+ INIT_01 => x"41403f3e3d3c3b3a39383736353434333231302f2e2d2c2b2a29282726262524",
+ INIT_02 => x"2526262728292a2b2c2d2e2f30313233343435363738393a3b3c3d3e3f404142",
+ INIT_03 => x"101010101111111212131314151516171718191a1a1b1c1d1e1f1f2021222324",
+ INIT_04 => x"222221201f1e1d1c1b1b1a19181717161515141313121111111010100f0f0f0f",
+ INIT_05 => x"41403f3e3d3c3b3a393837363534333231302f2e2e2d2c2b2a29282726252423",
+ INIT_06 => x"2425262728292a2b2c2d2e2e2f303132333435363738393a3b3c3d3e3f404142",
+ INIT_07 => x"0f0f0f10101011111112131314151516171718191a1b1b1c1d1e1f2021222223",
+ INIT_08 => x"2221201f1e1e1d1c1b1a1918181716151514131212111110100f0f0f0e0e0e0e",
+ INIT_09 => x"41403f3e3d3c3b3a393837363534333231302f2e2d2c2b2a2928282726252423",
+ INIT_0a => x"242526272828292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f404142",
+ INIT_0b => x"0e0e0e0f0f0f1010111112121314151516171818191a1b1c1d1e1e1f20212223",
+ INIT_0c => x"2221201f1e1d1c1b1a1a191817161515141312121110100f0f0e0e0e0d0d0d0d",
+ INIT_0d => x"403f3e3d3c3b3a39393837363534333231302f2e2d2c2b2a2928272625242323",
+ INIT_0e => x"232425262728292a2b2c2d2e2f30313233343536373839393a3b3c3d3e3f4041",
+ INIT_0f => x"0d0d0d0e0e0e0f0f101011121213141515161718191a1a1b1c1d1e1f20212223",
+ INIT_10 => x"21201f1e1e1d1c1b1a191817161615141312121110100f0e0e0d0d0d0c0c0c0c",
+ INIT_11 => x"403f3e3d3c3b3a39383736353433323131302f2e2d2c2b2a2928272625242322",
+ INIT_12 => x"232425262728292a2b2c2d2e2f30313132333435363738393a3b3c3d3e3f4041",
+ INIT_13 => x"0c0c0c0d0d0d0e0e0f101011121213141516161718191a1b1c1d1e1e1f202122",
+ INIT_14 => x"21201f1e1d1c1b1a191918171615141313121110100f0e0e0d0d0c0c0b0b0b0b",
+ INIT_15 => x"403f3e3d3c3b3a393837363534333231302f2e2d2c2b2a292928272625242322",
+ INIT_16 => x"23242526272829292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f4041",
+ INIT_17 => x"0b0b0b0c0c0d0d0e0e0f101011121313141516171819191a1b1c1d1e1f202122",
+ INIT_18 => x"21201f1e1d1c1b1a1918171615151413121110100f0e0d0d0c0c0b0b0a0a0a0a",
+ INIT_19 => x"403f3e3d3c3b3a393837363534333231302f2e2d2c2b2a292827262524232222",
+ INIT_1a => x"22232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f4041",
+ INIT_1b => x"0a0a0a0b0b0c0c0d0d0e0f1010111213141515161718191a1b1c1d1e1f202122",
+ INIT_1c => x"201f1e1d1c1c1b1a19181716151413121111100f0e0d0d0c0b0b0a0a09090909",
+ INIT_1d => x"403f3e3d3c3b3a393837363534333231302f2e2d2c2b2a292827262524232221",
+ INIT_1e => x"22232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f4041",
+ INIT_1f => x"0909090a0a0b0b0c0d0d0e0f10111112131415161718191a1b1c1c1d1e1f2021",
+ INIT_20 => x"201f1e1d1c1b1a19181716161514131211100f0e0e0d0c0b0b0a090909080808",
+ INIT_21 => x"403f3e3d3c3b3a393837363534333231302f2e2d2c2b2a292827262524232221",
+ INIT_22 => x"22232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f4040",
+ INIT_23 => x"08080909090a0b0b0c0d0e0e0f10111213141516161718191a1b1c1d1e1f2021",
+ INIT_24 => x"201f1e1d1c1b1a19181716151413121111100f0e0d0c0b0b0a09090808070707",
+ INIT_25 => x"3f3e3d3c3b3a39383736353433323131302f2e2d2c2b2a292827262524232221",
+ INIT_26 => x"22232425262728292a2b2c2d2e2f30313132333435363738393a3b3c3d3e3f40",
+ INIT_27 => x"0707080809090a0b0b0c0d0e0f10111112131415161718191a1b1c1d1e1f2021",
+ INIT_28 => x"201f1e1d1c1b1a191817161514131211100f0e0d0d0c0b0a0908080707060606",
+ INIT_29 => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252424232221",
+ INIT_2a => x"2223242425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_2b => x"060607070808090a0b0c0d0d0e0f101112131415161718191a1b1c1d1e1f2021",
+ INIT_2c => x"1f1e1d1c1b1a19191817161514131211100f0e0d0c0b0a090908070606050505",
+ INIT_2d => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_2e => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_2f => x"05050606070809090a0b0c0d0e0f10111213141516171819191a1b1c1d1e1f20",
+ INIT_30 => x"1f1e1d1c1b1a19181716151413121110100f0e0d0c0b0a090807060605040404",
+ INIT_31 => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_32 => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_33 => x"04040506060708090a0b0c0d0e0f10101112131415161718191a1b1c1d1e1f20",
+ INIT_34 => x"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09090807060504040303",
+ INIT_35 => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_36 => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_37 => x"0304040506070809090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f20",
+ INIT_38 => x"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050404030202",
+ INIT_39 => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_3a => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_3b => x"0203040405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f20",
+ INIT_3c => x"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020101",
+ INIT_3d => x"3f3e3d3c3b3a393837363534333231302f2e2d2c2b2a29282726252423222120",
+ INIT_3e => x"2122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40",
+ INIT_3f => x"0102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f20",
+ -- The next set of INITP_xx are for the parity bits
+ -- Address 0 to 511
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 512 to 1023
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1024 to 1535
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ -- Address 1536 to 2047
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => memOutput(7), -- 8-bit Data Output
+ DOP => open, -- 1-bit parity Output
+ ADDR => address(10 downto 0), -- 11-bit Address Input
+ CLK => clk(1), -- Clock
+ DI => x"00", -- 8-bit Data Input
+ DIP => "0", -- 1-bit parity Input
+ EN => '1', -- RAM Enable Input
+ SSR => '0', -- Synchronous Set/Reset Input
+ WE => '0' -- Write Enable Input
+ );
+
+
+end Behavioral;
+
implementaciones/fftProject06/romMem.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property