URL
https://opencores.org/ocsvn/phr/phr/trunk
Subversion Repositories phr
Compare Revisions
- This comparison shows the changes necessary to convert path
/phr/trunk/codigo
- from Rev 430 to Rev 431
- ↔ Reverse comparison
Rev 430 → Rev 431
/demos/projects/BtnDemo/_impact.log
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/demos/projects/BtnDemo/bitgen.ut
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/demos/projects/BtnDemo/btndemo.twr
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/demos/projects/BtnDemo/btndemo.syr
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/demos/projects/BtnDemo/btndemo.xst
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/demos/projects/BtnDemo/btndemo_map.ngm
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/demos/projects/BtnDemo/btndemo_pad.csv
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/demos/projects/BtnDemo/BtnDemo_summary.html
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/demos/projects/BtnDemo/btndemo.twx
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/demos/projects/BtnDemo/btndemo.dly
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/demos/projects/BtnDemo/btndemo.ut
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/demos/projects/BtnDemo/btndemo._prj
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/demos/projects/BtnDemo/_ngo/netlist.lst
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/demos/projects/BtnDemo/BtnDemo.prj
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/demos/projects/BtnDemo/BtnDemo_xst.xrpt
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/demos/projects/BtnDemo/BtnDemo_envsettings.html
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/demos/projects/BtnDemo/btndemo.mrp
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/demos/projects/BtnDemo/btndemo.xpi
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/demos/projects/BtnDemo/btndemo.pad
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/demos/projects/BtnDemo/btndemo.jid
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/demos/projects/BtnDemo/BtnDemo.ngc
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/demos/projects/BtnDemo/BtnDemo.xise
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/demos/projects/BtnDemo/BtnDemo.ngd
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/demos/projects/BtnDemo/_xmsgs/map.xmsgs
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/demos/projects/BtnDemo/_xmsgs/xst.xmsgs
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/demos/projects/BtnDemo/_xmsgs/ngdbuild.xmsgs
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/demos/projects/BtnDemo/_xmsgs/pn_parser.xmsgs
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/demos/projects/BtnDemo/btndemo.ucf
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/demos/projects/BtnDemo/btndemo.sprj
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/demos/projects/BtnDemo/btndemo.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
demos/projects/BtnDemo/btndemo.bit
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Index: demos/projects/BtnDemo/iseconfig/BtnDemo.projectmgr
===================================================================
--- demos/projects/BtnDemo/iseconfig/BtnDemo.projectmgr (revision 430)
+++ demos/projects/BtnDemo/iseconfig/BtnDemo.projectmgr (nonexistent)
@@ -1,63 +0,0 @@
-
-
-
-
-
-
-
-
- 2
-
-
- BtnDemo - Behavioral (/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd)
-
- 0
- 0
- 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000147000000020000000000000000000000000000000064ffffffff000000810000000000000002000001470000000100000000000000000000000100000000
- false
- BtnDemo - Behavioral (/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd)
-
-
-
- 1
- Configure Target Device
- Design Utilities
- Implement Design
- Synthesize - XST
- User Constraints
-
-
- Implement Design
-
- 0
- 0
- 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000
- false
- Implement Design
-
-
-
- 1
-
- 0
- 0
- 000000ff0000000000000001000000000000000001000000000000000000000000000000000000039f000000040101000100000000000000000000000064ffffffff0000008100000000000000040000007400000001000000000000005c00000001000000000000008400000001000000000000024b0000000100000000
- false
- BtnDemo.vhd
-
-
-
- 1
- work
-
- 0
- 0
- 000000ff00000000000000010000000000000000010000000000000000000000000000000000000124000000010001000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000
- false
- work
-
- 000000ff0000000000000002000001440000011d01000000060100000002
- Implementation
-
Index: demos/projects/BtnDemo/iseconfig/BtnDemo.xreport
===================================================================
--- demos/projects/BtnDemo/iseconfig/BtnDemo.xreport (revision 430)
+++ demos/projects/BtnDemo/iseconfig/BtnDemo.xreport (nonexistent)
@@ -1,217 +0,0 @@
-
-
-
- 2014-04-30T19:48:38
- BtnDemo
- Unknown
- /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/iseconfig/BtnDemo.xreport
- /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/
- 2014-04-30T19:13:54
- false
-
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Index: demos/projects/BtnDemo/btndemo.par
===================================================================
--- demos/projects/BtnDemo/btndemo.par (revision 430)
+++ demos/projects/BtnDemo/btndemo.par (nonexistent)
@@ -1,113 +0,0 @@
-Release 6.2.03i Par G.31a
-Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
-
-PANTHER:: Wed Jul 07 09:50:18 2004
-
-
-C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 btndemo_map.ncd
-btndemo.ncd btndemo.pcf
-
-
-Constraints file: btndemo.pcf
-
-Loading device database for application Par from file "btndemo_map.ncd".
- "btndemo" is an NCD, version 2.38, device xc2s200, package pq208, speed -5
-Loading device for application Par from file 'v200.nph' in environment
-C:/Xilinx.
-Device speed data version: PRODUCTION 1.27 2003-12-13.
-
-
-Resolved that IOB must be placed at site P71.
-Resolved that GCLKIOB must be placed at site P77.
-
-
-Device utilization summary:
-
- Number of External GCLKIOBs 1 out of 4 25%
- Number of External IOBs 1 out of 140 1%
- Number of LOCed External IOBs 1 out of 1 100%
-
-
-
-
-
-Overall effort level (-ol): Standard (set by user)
-Placer effort level (-pl): Standard (set by user)
-Placer cost table entry (-t): 1
-Router effort level (-rl): Standard (set by user)
-
-
-Phase 1.1
-Phase 1.1 (Checksum:989683) REAL time: 3 secs
-
-Phase 2.23
-Phase 2.23 (Checksum:1312cfe) REAL time: 4 secs
-
-Phase 3.3
-Phase 3.3 (Checksum:1c9c37d) REAL time: 4 secs
-
-Phase 4.5
-Phase 4.5 (Checksum:26259fc) REAL time: 4 secs
-
-Phase 5.8
-Phase 5.8 (Checksum:98996d) REAL time: 4 secs
-
-Phase 6.5
-Phase 6.5 (Checksum:39386fa) REAL time: 4 secs
-
-Phase 7.18
-Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs
-
-Writing design to file btndemo.ncd.
-
-Total REAL time to Placer completion: 5 secs
-Total CPU time to Placer completion: 1 secs
-
-
-Phase 1: 1 unrouted; REAL time: 5 secs
-
-Phase 2: 1 unrouted; REAL time: 5 secs
-
-Phase 3: 0 unrouted; REAL time: 5 secs
-
-Phase 4: 0 unrouted; REAL time: 5 secs
-
-Total REAL time to Router completion: 5 secs
-Total CPU time to Router completion: 1 secs
-
-Generating "par" statistics.
-
-
- The Delay Summary Report
-
- The SCORE FOR THIS DESIGN is: 100
-
-
-The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
-
- The AVERAGE CONNECTION DELAY for this design is: 0.935
- The MAXIMUM PIN DELAY IS: 0.935
- The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 0.312
-
- Listing Pin Delays by value: (nsec)
-
- d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
- --------- --------- --------- --------- --------- ---------
- 1 0 0 0 0 0
-
-Generating Pad Report.
-
-All signals are completely routed.
-
-Total REAL time to PAR completion: 24 secs
-Total CPU time to PAR completion: 5 secs
-
-Peak Memory Usage: 50 MB
-
-Placement: Completed - No errors found.
-Routing: Completed - No errors found.
-
-Writing design to file btndemo.ncd.
-
-
-PAR done.
Index: demos/projects/BtnDemo/BtnDemo.ngr
===================================================================
--- demos/projects/BtnDemo/BtnDemo.ngr (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.ngr (nonexistent)
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$0ax0f=(`fgn#aizaow`k*iwmgid~h} pip,pwsic&idhdi`/egnkv)wzf`noy} BulGahi(J}dOi`a!vifg?6u689:mk>;H78MGSAO>1GCJGLAM58I+17lVF:7B:4P@PW7>TSD=1_U]K=;T3:?SOB_V^R\H?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED?j;YQW[LKWDLGNBYO[INL\GJHT\[KBBY]>0:ZPPZTSDVZYC]K]TX48\adXAm;;7Ujb_LcikwPbzzcdb<>4Xeo\Ilhhz_oydaa3:Zpp<=_{}MFcikc3:`wj6=kmml0b{}cd]emiciidoo7~azrbg\hlhbfk;;7um3L1>7?tS5821?>=9:9>=5k5372f7~h6;3;0b<:56:&26?`b2:<;i:5k2;295?7|[=0:976512165=c=;?:n?6xIb;295?7=8rY?6<;58;30707?m39=5<5290;wA?>:3ym5d<3>2.:57>4}%a92>o22900c44?::p52<72;qU=:52d;78yv7?2909wS?7;{zutwKLNu>2;;5b3?amtJKNv>r@ARxyEF
\ No newline at end of file
Index: demos/projects/BtnDemo/BtnDemo.gise
===================================================================
--- demos/projects/BtnDemo/BtnDemo.gise (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.gise (nonexistent)
@@ -1,117 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- 11.1
-
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Index: demos/projects/BtnDemo/BtnDemo.lso
===================================================================
--- demos/projects/BtnDemo/BtnDemo.lso (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.lso (nonexistent)
@@ -1 +0,0 @@
-work
Index: demos/projects/BtnDemo/BtnDemo.bld
===================================================================
--- demos/projects/BtnDemo/BtnDemo.bld (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.bld (nonexistent)
@@ -1,36 +0,0 @@
-Release 12.3 ngdbuild M.70d (lin)
-Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
-
-Command Line: /opt/Xilinx/12.3/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -intstyle
-ise -dd _ngo -nt timestamp -i -p xc3s1000-fg320-4 BtnDemo.ngc BtnDemo.ngd
-
-Reading NGO file
-"/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.ngc"
-...
-Gathering constraint information from source properties...
-Done.
-
-Resolving constraint associations...
-Checking Constraint Associations...
-Done...
-
-Checking expanded design ...
-
-Partition Implementation Status
--------------------------------
-
- No Partitions were found in this design.
-
--------------------------------
-
-NGDBUILD Design Results Summary:
- Number of errors: 0
- Number of warnings: 0
-
-Total memory usage is 84120 kilobytes
-
-Writing NGD file "BtnDemo.ngd" ...
-Total REAL time to NGDBUILD completion: 4 sec
-Total CPU time to NGDBUILD completion: 2 sec
-
-Writing NGDBUILD log file "BtnDemo.bld"...
Index: demos/projects/BtnDemo/BtnDemo.cmd_log
===================================================================
--- demos/projects/BtnDemo/BtnDemo.cmd_log (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.cmd_log (nonexistent)
@@ -1,3 +0,0 @@
-xst -intstyle ise -ifn "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.xst" -ofn "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.syr"
-ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1000-fg320-4 BtnDemo.ngc BtnDemo.ngd
-map -intstyle ise -p xc3s1000-fg320-4 -cm area -ir off -pr off -c 100 -o BtnDemo_map.ncd BtnDemo.ngd BtnDemo.pcf
Index: demos/projects/BtnDemo/xlnx_auto_0_xdb/cst.xbcd
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: demos/projects/BtnDemo/xlnx_auto_0_xdb/cst.xbcd
===================================================================
--- demos/projects/BtnDemo/xlnx_auto_0_xdb/cst.xbcd (revision 430)
+++ demos/projects/BtnDemo/xlnx_auto_0_xdb/cst.xbcd (nonexistent)
demos/projects/BtnDemo/xlnx_auto_0_xdb/cst.xbcd
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: demos/projects/BtnDemo/btndemo.drc
===================================================================
--- demos/projects/BtnDemo/btndemo.drc (revision 430)
+++ demos/projects/BtnDemo/btndemo.drc (nonexistent)
@@ -1 +0,0 @@
-DRC detected 0 errors and 0 warnings.
Index: demos/projects/BtnDemo/BtnDemo_map.map
===================================================================
--- demos/projects/BtnDemo/BtnDemo_map.map (revision 430)
+++ demos/projects/BtnDemo/BtnDemo_map.map (nonexistent)
@@ -1,54 +0,0 @@
-Release 12.3 Map M.70d (lin)
-Xilinx Map Application Log File for Design 'BtnDemo'
-
-Design Information
-------------------
-Command Line : map -intstyle ise -p xc3s1000-fg320-4 -cm area -ir off -pr off
--c 100 -o BtnDemo_map.ncd BtnDemo.ngd BtnDemo.pcf
-Target Device : xc3s1000
-Target Package : fg320
-Target Speed : -4
-Mapper Version : spartan3 -- $Revision: 1.52 $
-Mapped Date : Wed Apr 30 19:14:28 2014
-
-vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
-INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
-INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.
-INFO:Security:54 - 'xc3s1000' is a WebPack part.
-INFO:Security:68 - Please run the Xilinx License Configuration Manager
- (xlcm or "Manage Xilinx Licenses")
- to assist in obtaining a license.
-WARNING:Security:43 - No license file was found in the standard Xilinx license
-directory.
-WARNING:Security:44 - No license file was found.
- Please run the Xilinx License Configuration Manager
- (xlcm or "Manage Xilinx Licenses")
- to assist in obtaining a license.
-ERROR:Security:9 - No 'ISE' nor 'WebPack' feature was available for part
-'xc3s1000'.
-----------------------------------------------------------------------
-No such feature exists.
-Feature: WebPack
-License path:
-/home/lguanuco/.Xilinx/*.lic:/opt/Xilinx/12.3/ISE_DS/ISE//data/*.lic:/opt/Xilinx
-/12.3/ISE_DS/ISE//coregen/core_licenses/Xilinx.lic:/opt/Xilinx/12.3/ISE_DS/ISE//
-coregen/core_licenses/XilinxFree.lic:
-FLEXnet Licensing error:-5,357. System Error: 2 "No such file or directory"
-For further information, refer to the FLEXnet Licensing documentation,
-available at "www.acresso.com".No such feature exists.
-Feature: ISE
-License path:
-/home/lguanuco/.Xilinx/*.lic:/opt/Xilinx/12.3/ISE_DS/ISE//data/*.lic:/opt/Xilinx
-/12.3/ISE_DS/ISE//coregen/core_licenses/Xilinx.lic:/opt/Xilinx/12.3/ISE_DS/ISE//
-coregen/core_licenses/XilinxFree.lic:
-FLEXnet Licensing error:-5,357
-For further information, refer to the FLEXnet Licensing documentation,
-available at "www.acresso.com".
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-ERROR:Map:258 - A problem was encountered attempting to get the license for this
- architecture.
-
-Design Summary
---------------
-Number of errors : 1
-Number of warnings : 0
Index: demos/projects/BtnDemo/BtnDemo.dhp
===================================================================
--- demos/projects/BtnDemo/BtnDemo.dhp (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.dhp (nonexistent)
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.2e
-$2dx4>763-Xnzd}foo8#5+72(-k0==661733=<>DsfMofc#xgd,1:?FIJE@^_II94CSGBP@B?3Jef|D`|t`9Fjqosq@dxxl5Jnukw}Kgjmk1MeakKeqgm`v>Wriecmeh|9;Rgqr`ue3]oxx[kltnppf>RhxOcgiAg|t99VjlrIidoo7X}jSucwahci|z;o7UGCIOZ.\AD'8';+_Y[M 1,2$DUDA@<0TilPIe33?]bjWDkacXjrrklj4665d8wqbXdfmboRo}iuj26>uslVfdkdmPuoqjckcc:2:96{>-026?pub%C<328qXm7=9:08274ed8:0:=;ltn3795>h5>380(?:5229~W<<4>3;1=>?lc11957003Z;>6>851;305fe7;3838>?4S8802?7=9:;ho==5296ef>b4>3:1=7?tS`802?7=9:;ho==5104a?k552h1D>=4?;N33>5=qN>0;6<4>:1yPe?51280:?3<7sg9>6<5a5;38K4c=82.:57>4$g85?!76291/=n4?;%3a>7=Hm3:0C<<50:M00?7|uk9:6=4?:183k522olmjkhif:l6>7673F;n6=5@2380xI603:0qo=l:183>5<7sg9>6<84n48245=H9l0;7)?8:228 4g=;>1/=i4=7:M1g?61=vs@1282x{e;m0;6=4?:1ym70<6?2d>6<>?;N3f>5=#9>08<6*>a;1;?!7c2;=0C?m50:M00?7|uF;865<7290;wc=::0:8j0<6891D=h4?;%34>66<,8k1?45+1e813>I5k3:0C>:51zL56<6stwi>h4?:183>5}i;<0:m6`::39L5`<73-n1>i5@4;28K62=9rwD=>4>{|a6<<7290:6=ua34815>h22=1D=h4?;%196==#9o0;7)j52e9Lf?65<7290;wc=::548j0"5938m7B7?j;N34>g=H910:<6A>c;`8K4b=991D><4m;N01>46h4=8:M07?d1>55r@A
\ No newline at end of file
Index: demos/projects/BtnDemo/BtnDemo.syr
===================================================================
--- demos/projects/BtnDemo/BtnDemo.syr (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.syr (nonexistent)
@@ -1,283 +0,0 @@
-Release 12.3 - xst M.70d (lin)
-Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--->
-Parameter TMPDIR set to xst/projnav.tmp
-
-
-Total REAL time to Xst completion: 1.00 secs
-Total CPU time to Xst completion: 0.04 secs
-
--->
-Parameter xsthdpdir set to xst
-
-
-Total REAL time to Xst completion: 1.00 secs
-Total CPU time to Xst completion: 0.04 secs
-
--->
-Reading design: BtnDemo.prj
-
-TABLE OF CONTENTS
- 1) Synthesis Options Summary
- 2) HDL Compilation
- 3) Design Hierarchy Analysis
- 4) HDL Analysis
- 5) HDL Synthesis
- 5.1) HDL Synthesis Report
- 6) Advanced HDL Synthesis
- 6.1) Advanced HDL Synthesis Report
- 7) Low Level Synthesis
- 8) Partition Report
- 9) Final Report
- 9.1) Device utilization summary
- 9.2) Partition Resource Summary
- 9.3) TIMING REPORT
-
-
-=========================================================================
-* Synthesis Options Summary *
-=========================================================================
----- Source Parameters
-Input File Name : "BtnDemo.prj"
-Input Format : mixed
-Ignore Synthesis Constraint File : NO
-
----- Target Parameters
-Output File Name : "BtnDemo"
-Output Format : NGC
-Target Device : xc3s1000-4-fg320
-
----- Source Options
-Top Module Name : BtnDemo
-Automatic FSM Extraction : YES
-FSM Encoding Algorithm : Auto
-Safe Implementation : No
-FSM Style : LUT
-RAM Extraction : Yes
-RAM Style : Auto
-ROM Extraction : Yes
-Mux Style : Auto
-Decoder Extraction : YES
-Priority Encoder Extraction : Yes
-Shift Register Extraction : YES
-Logical Shifter Extraction : YES
-XOR Collapsing : YES
-ROM Style : Auto
-Mux Extraction : Yes
-Resource Sharing : YES
-Asynchronous To Synchronous : NO
-Multiplier Style : Auto
-Automatic Register Balancing : No
-
----- Target Options
-Add IO Buffers : YES
-Global Maximum Fanout : 500
-Add Generic Clock Buffer(BUFG) : 8
-Register Duplication : YES
-Slice Packing : YES
-Optimize Instantiated Primitives : NO
-Use Clock Enable : Yes
-Use Synchronous Set : Yes
-Use Synchronous Reset : Yes
-Pack IO Registers into IOBs : Auto
-Equivalent register Removal : YES
-
----- General Options
-Optimization Goal : Speed
-Optimization Effort : 1
-Keep Hierarchy : No
-Netlist Hierarchy : As_Optimized
-RTL Output : Yes
-Global Optimization : AllClockNets
-Read Cores : YES
-Write Timing Constraints : NO
-Cross Clock Analysis : NO
-Hierarchy Separator : _
-Bus Delimiter : <>
-Case Specifier : Maintain
-Slice Utilization Ratio : 100
-BRAM Utilization Ratio : 100
-Verilog 2001 : YES
-Auto BRAM Packing : NO
-Slice Utilization Ratio Delta : 5
-
-=========================================================================
-
-
-=========================================================================
-* HDL Compilation *
-=========================================================================
-Compiling vhdl file "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd" in Library work.
-Entity compiled.
-Entity (Architecture ) compiled.
-
-=========================================================================
-* Design Hierarchy Analysis *
-=========================================================================
-Analyzing hierarchy for entity in library (architecture ).
-
-INFO:Xst:2555 - '-hierarchy_separator' switch is being deprecated in a future release.
-
-=========================================================================
-* HDL Analysis *
-=========================================================================
-Analyzing Entity in library (Architecture ).
-WARNING:Xst:2211 - "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd" line 70: Instantiating black box module .
-Entity analyzed. Unit generated.
-
-
-=========================================================================
-* HDL Synthesis *
-=========================================================================
-
-Performing bidirectional port resolution...
-
-Synthesizing Unit .
- Related source file is "/home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd".
-Unit synthesized.
-
-
-=========================================================================
-HDL Synthesis Report
-
-Found no macro
-=========================================================================
-
-=========================================================================
-* Advanced HDL Synthesis *
-=========================================================================
-
-
-=========================================================================
-Advanced HDL Synthesis Report
-
-Found no macro
-=========================================================================
-
-=========================================================================
-* Low Level Synthesis *
-=========================================================================
-
-Optimizing unit ...
-
-Mapping all equations...
-Building and optimizing final netlist ...
-Found area constraint ratio of 100 (+ 5) on block BtnDemo, actual ratio is 0.
-
-Final Macro Processing ...
-
-=========================================================================
-Final Register Report
-
-Found no macro
-=========================================================================
-
-=========================================================================
-* Partition Report *
-=========================================================================
-
-Partition Implementation Status
--------------------------------
-
- No Partitions were found in this design.
-
--------------------------------
-
-=========================================================================
-* Final Report *
-=========================================================================
-Final Results
-RTL Top Level Output File Name : BtnDemo.ngr
-Top Level Output File Name : BtnDemo
-Output Format : NGC
-Optimization Goal : Speed
-Keep Hierarchy : No
-
-Design Statistics
-# IOs : 2
-
-Cell Usage :
-# IO Buffers : 2
-# IBUFG : 1
-# OBUF : 1
-=========================================================================
-
-Device utilization summary:
----------------------------
-
-Selected Device : 3s1000fg320-4
-
- Number of Slices: 0 out of 7680 0%
- Number of IOs: 2
- Number of bonded IOBs: 2 out of 221 0%
-
----------------------------
-Partition Resource Summary:
----------------------------
-
- No Partitions were found in this design.
-
----------------------------
-
-
-=========================================================================
-TIMING REPORT
-
-NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
- FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
- GENERATED AFTER PLACE-and-ROUTE.
-
-Clock Information:
-------------------
-No clock signals found in this design
-
-Asynchronous Control Signals Information:
-----------------------------------------
-No asynchronous control signals found in this design
-
-Timing Summary:
----------------
-Speed Grade: -4
-
- Minimum period: No path found
- Minimum input arrival time before clock: No path found
- Maximum output required time after clock: No path found
- Maximum combinational path delay: 7.667ns
-
-Timing Detail:
---------------
-All values displayed in nanoseconds (ns)
-
-=========================================================================
-Timing constraint: Default path analysis
- Total number of paths / destination ports: 1 / 1
--------------------------------------------------------------------------
-Delay: 7.667ns (Levels of Logic = 2)
- Source: btn (PAD)
- Destination: led (PAD)
-
- Data Path: btn to led
- Gate Net
- Cell:in->out fanout Delay Delay Logical Name (Net Name)
- ---------------------------------------- ------------
- IBUFG:I->O 1 1.222 0.801 U1 (led_OBUF)
- OBUF:I->O 5.644 led_OBUF (led)
- ----------------------------------------
- Total 7.667ns (6.866ns logic, 0.801ns route)
- (89.6% logic, 10.4% route)
-
-=========================================================================
-
-
-Total REAL time to Xst completion: 8.00 secs
-Total CPU time to Xst completion: 3.66 secs
-
--->
-
-
-Total memory usage is 147212 kilobytes
-
-Number of errors : 0 ( 0 filtered)
-Number of warnings : 1 ( 0 filtered)
-Number of infos : 1 ( 0 filtered)
-
Index: demos/projects/BtnDemo/BtnDemo.xst
===================================================================
--- demos/projects/BtnDemo/BtnDemo.xst (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.xst (nonexistent)
@@ -1,56 +0,0 @@
-set -tmpdir "xst/projnav.tmp"
-set -xsthdpdir "xst"
-run
--ifn BtnDemo.prj
--ifmt mixed
--ofn BtnDemo
--ofmt NGC
--p xc3s1000-4-fg320
--top BtnDemo
--opt_mode Speed
--opt_level 1
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator _
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--verilog2001 YES
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--mux_style Auto
--decoder_extract YES
--priority_extract Yes
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--rom_style Auto
--auto_bram_packing NO
--mux_extract Yes
--resource_sharing YES
--async_to_sync NO
--mult_style Auto
--iobuf YES
--max_fanout 500
--bufg 8
--register_duplication YES
--register_balancing No
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Yes
--use_sync_set Yes
--use_sync_reset Yes
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
Index: demos/projects/BtnDemo/BtnDemo.vhd
===================================================================
--- demos/projects/BtnDemo/BtnDemo.vhd (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.vhd (nonexistent)
@@ -1,79 +0,0 @@
-------------------------------------------------------------------------
--- BtnDemo.vhd -- Demonstrate D2 On-Board Button and LED
-------------------------------------------------------------------------
--- Author: Gene Apperson
--- Copyright 2002 Digilent, Inc.
-------------------------------------------------------------------------
--- This module is an example to demonstrate the use of the on-board
--- button and LED on the D2 board.
---
--- Inputs:
--- btn - button on the D2 board
---
--- Outputs:
--- led - discrete LED on the D2 board
---
-------------------------------------------------------------------------
--- Revision History:
--- 03/31/2002(GeneA): created
-------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-entity BtnDemo is
- Port (
- btn : in std_logic;
- led : out std_logic
- );
-end BtnDemo;
-
-architecture Behavioral of BtnDemo is
-
- ------------------------------------------------------------------------
- -- Component Declarations
- ------------------------------------------------------------------------
-
- -- System Library Components
-
- component IBUFG
- port (
- I : in STD_LOGIC;
- O : out std_logic
- );
- end component;
-
- ------------------------------------------------------------------------
- -- Signal Declarations
- ------------------------------------------------------------------------
-
- signal bnbuf: std_logic;
-
- ------------------------------------------------------------------------
- -- Module Implementation
- ------------------------------------------------------------------------
-
-begin
-
- -- Instantiate an IBUFG for the button. The button on the D2 board is
- -- connected to a global clock input. The Xilinx ISE tools will
- -- automatically insert input and output buffers to connect the signal
- -- defined in the VHDL modules port. However, for non-clock signals, the
- -- tool will automatically try to insert an IBUF. This will generate an
- -- errror, as it isn't possible to instantiate an IBUF on a global clock
- -- line. To prevent this error, it is necessary to manually instantiate
- -- a clock input buffer for this line. The output of this buffer can then
- -- be used as a normal logic signal.
-
-U1: IBUFG port map (I => btn, O => bnbuf);
-
- -- Connect the D2 button to the D2 LED. The button on the D2
- -- is wired to generate a logic 1 when it is pressed. The LED on the
- -- D2 will illuminate when it is driven with a logic 1.
- led <= bnbuf;
-
- ------------------------------------------------------------------------
-
-end Behavioral;
Index: demos/projects/BtnDemo/xst/work/sub00/vhpl01.vho
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: demos/projects/BtnDemo/xst/work/sub00/vhpl01.vho
===================================================================
--- demos/projects/BtnDemo/xst/work/sub00/vhpl01.vho (revision 430)
+++ demos/projects/BtnDemo/xst/work/sub00/vhpl01.vho (nonexistent)
demos/projects/BtnDemo/xst/work/sub00/vhpl01.vho
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: demos/projects/BtnDemo/xst/work/sub00/vhpl00.vho
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: demos/projects/BtnDemo/xst/work/sub00/vhpl00.vho
===================================================================
--- demos/projects/BtnDemo/xst/work/sub00/vhpl00.vho (revision 430)
+++ demos/projects/BtnDemo/xst/work/sub00/vhpl00.vho (nonexistent)
demos/projects/BtnDemo/xst/work/sub00/vhpl00.vho
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: demos/projects/BtnDemo/xst/work/hdllib.ref
===================================================================
--- demos/projects/BtnDemo/xst/work/hdllib.ref (revision 430)
+++ demos/projects/BtnDemo/xst/work/hdllib.ref (nonexistent)
@@ -1,2 +0,0 @@
-EN btndemo NULL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd sub00/vhpl00 1398896049
-AR btndemo behavioral /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd sub00/vhpl01 1398896050
Index: demos/projects/BtnDemo/xst/work/hdpdeps.ref
===================================================================
--- demos/projects/BtnDemo/xst/work/hdpdeps.ref (revision 430)
+++ demos/projects/BtnDemo/xst/work/hdpdeps.ref (nonexistent)
@@ -1,9 +0,0 @@
-V3 4
-FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd 2004/07/06.17:44:56 M.70d
-EN work/BtnDemo 1398896049 \
- FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd \
- PB ieee/std_logic_1164 1284609568 PB ieee/std_logic_arith 1284609569 \
- PB ieee/STD_LOGIC_UNSIGNED 1284609570
-AR work/BtnDemo/Behavioral 1398896050 \
- FL /home/lguanuco/opencores/phr/trunk/codigo/demos/projects/BtnDemo/BtnDemo.vhd \
- EN work/BtnDemo 1398896049 CP IBUFG
Index: demos/projects/BtnDemo/BtnDemo.ptf
===================================================================
--- demos/projects/BtnDemo/BtnDemo.ptf (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.ptf (nonexistent)
@@ -1,4 +0,0 @@
-[btndemo]
-Design Entry Utilities=true
-Generate Programming File=true
-User Constraints=true
Index: demos/projects/BtnDemo/btndemo.prj
===================================================================
--- demos/projects/BtnDemo/btndemo.prj (revision 430)
+++ demos/projects/BtnDemo/btndemo.prj (nonexistent)
@@ -1 +0,0 @@
-vhdl work BtnDemo.vhd
Index: demos/projects/BtnDemo/webtalk_pn.xml
===================================================================
--- demos/projects/BtnDemo/webtalk_pn.xml (revision 430)
+++ demos/projects/BtnDemo/webtalk_pn.xml (nonexistent)
@@ -1,43 +0,0 @@
-
-
-
-
-
-
-
-
-
-
Index: demos/projects/BtnDemo/BtnDemo_ise5_bak.zip
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: demos/projects/BtnDemo/BtnDemo_ise5_bak.zip
===================================================================
--- demos/projects/BtnDemo/BtnDemo_ise5_bak.zip (revision 430)
+++ demos/projects/BtnDemo/BtnDemo_ise5_bak.zip (nonexistent)
demos/projects/BtnDemo/BtnDemo_ise5_bak.zip
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: demos/projects/BtnDemo/btndemo.ncd
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: demos/projects/BtnDemo/btndemo.ncd
===================================================================
--- demos/projects/BtnDemo/btndemo.ncd (revision 430)
+++ demos/projects/BtnDemo/btndemo.ncd (nonexistent)
demos/projects/BtnDemo/btndemo.ncd
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: demos/projects/BtnDemo/BtnDemo_ngdbuild.xrpt
===================================================================
--- demos/projects/BtnDemo/BtnDemo_ngdbuild.xrpt (revision 430)
+++ demos/projects/BtnDemo/BtnDemo_ngdbuild.xrpt (nonexistent)
@@ -1,69 +0,0 @@
-
-
-
-
-
-
-
-
-
- -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Index: demos/projects/BtnDemo/__projnav.log
===================================================================
--- demos/projects/BtnDemo/__projnav.log (revision 430)
+++ demos/projects/BtnDemo/__projnav.log (nonexistent)
@@ -1,1282 +0,0 @@
-ISE Auto-Make Log File
------------------------
-
-Updating: Edit Implementation Constraints (Constraints Editor)
-
-Starting: 'exewrap @__constEditor_exewrap.rsp'
-
-
-Creating TCL Process
-Starting: 'constraints_editor btndemo.ucf btndemo.ngd'
-
-
-Tcl c:/xilinx_webpack/data/projnav/constEditor.tcl detected that program 'constraints_editor btndemo.ucf btndemo.ngd' completed successfully.
-
-call Constraints Editor completed
-Starting: 'chkdate'
-
-
-Tcl c:/xilinx_webpack/data/projnav/constEditor.tcl detected that program 'chkdate' completed successfully.
-
- Existing implementation results have been retained !
- To incorporate your constraint changes, right click on the 'Implement Design' process and select 'Rerun All'.
-Done: completed successfully.
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-JHDPARSE - VHDL/Verilog Parser.
-ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
-
-Scanning BtnDemo.vhd
-Scanning BtnDemo.vhd
-Writing BtnDemo.jhd.
-
-JHDPARSE complete - 0 errors, 0 warnings.
-
-
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-
-
-
-Started process "Synthesize".
-
-
-=========================================================================
-* HDL Compilation *
-=========================================================================
-WARNING:HDLParsers:3215 - Unit work/BTNDEMO is now defined in a different file: was C:/Projects/RefDsgn/D2/BtnDemo/BtnDemo.vhd, now is F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd
-WARNING:HDLParsers:3215 - Unit work/BTNDEMO/BEHAVIORAL is now defined in a different file: was C:/Projects/RefDsgn/D2/BtnDemo/BtnDemo.vhd, now is F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd
-Compiling vhdl file F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd in Library work.
-Architecture behavioral of Entity btndemo is up to date.
-
-=========================================================================
-* HDL Analysis *
-=========================================================================
-
-Analyzing Entity (Architecture ).
-WARNING:Xst:766 - F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd line 70: Generating a Black Box for component .
-Entity analyzed. Unit generated.
-
-
-=========================================================================
-* HDL Synthesis *
-=========================================================================
-
-Synthesizing Unit .
- Related source file is F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd.
-Unit synthesized.
-
-
-=========================================================================
-HDL Synthesis Report
-
-Found no macro
-=========================================================================
-
-=========================================================================
-* Low Level Synthesis *
-=========================================================================
-Library "C:/XilinxISE/data/librtl.xst" Consulted
-
-Optimizing unit ...
-
-Mapping all equations...
-Loading device for application Xst from file 'v200.nph' in environment C:/XilinxISE.
-Building and optimizing final netlist ...
-Found area constraint ratio of 100 (+ 5) on block btndemo, actual ratio is 0.
-
-=========================================================================
-* Final Report *
-=========================================================================
-
-Device utilization summary:
----------------------------
-
-Selected Device : 2s200pq208-5
-
- Number of bonded IOBs: 2 out of 144 1%
-
-
-=========================================================================
-TIMING REPORT
-
-
-Clock Information:
-------------------
-No clock signals found in this design
-
-Timing Summary:
----------------
-Speed Grade: -5
-
- Minimum period: No path found
- Minimum input arrival time before clock: No path found
- Maximum output required time after clock: No path found
- Maximum combinational path delay: 8.404ns
-
-=========================================================================
-
-Completed process "Synthesize".
-
-
-
-Started process "Translate".
-
-
-Command Line: ngdbuild -quiet -dd f:\engineering\projects\web5.1\d2\btndemo/_ngo
--uc btndemo.ucf -insert_keep_hierarchy -p xc2s200-pq208-5 btndemo.ngc
-btndemo.ngd
-
-Reading NGO file "F:/Engineering/Projects/web5.1/D2/BtnDemo/btndemo.ngc" ...
-Reading component libraries for design expansion...
-
-Annotating constraints to design from file "btndemo.ucf" ...
-
-Checking timing specifications ...
-Checking expanded design ...
-
-NGDBUILD Design Results Summary:
- Number of errors: 0
- Number of warnings: 0
-
-Writing NGD file "btndemo.ngd" ...
-
-Writing NGDBUILD log file "btndemo.bld"...
-
-NGDBUILD done.
-
-Completed process "Translate".
-
-
-
-Started process "Map".
-
-Using target part "2s200pq208-5".
-Removing unused or disabled logic...
-Running cover...
-Running directed packing...
-Running delay-based LUT packing...
-Running related packing...
-
-Design Summary:
- Number of errors: 0
- Number of warnings: 1
- Number of Slices containing
- unrelated logic: 0 out of 0 0%
- Number of bonded IOBs: 1 out of 140 1%
- Number of GCLKIOBs: 1 out of 4 25%
-Total equivalent gate count for design: 0
-Additional JTAG gate count for IOBs: 96
-Peak Memory Usage: 52 MB
-
-Mapping completed.
-See MAP report file "btndemo_map.mrp" for details.
-
-Completed process "Map".
-
-Mapping Module btndemo . . .
-MAP command line:
-map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf
-Mapping Module btndemo: DONE
-
-
-
-Started process "Place & Route".
-
-Release 5.1i - Par F.23
-Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
-
-
-
-
-Constraints file: btndemo.pcf
-
-Loading device database for application par from file "btndemo_map.ncd".
- "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5
-Loading device for application par from file 'v200.nph' in environment
-C:/XilinxISE.
-Device speed data version: PRELIMINARY 1.25 2002-06-19.
-
-
-Resolving physical constraints.
-Finished resolving physical constraints.
-
-Device utilization summary:
-
- Number of External GCLKIOBs 1 out of 4 25%
- Number of External IOBs 1 out of 140 1%
- Number of LOCed External IOBs 1 out of 1 100%
-
-
-
-
-
-Overall effort level (-ol): 2 (set by user)
-Placer effort level (-pl): 2 (set by user)
-Placer cost table entry (-t): 1
-Router effort level (-rl): 2 (set by user)
-
-
-Phase 1.1
-Phase 1.1 (Checksum:989683) REAL time: 2 secs
-
-Phase 2.23
-Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs
-
-Phase 3.3
-Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs
-
-Phase 4.5
-Phase 4.5 (Checksum:26259fc) REAL time: 2 secs
-
-Phase 5.8
-Phase 5.8 (Checksum:98996d) REAL time: 2 secs
-
-Phase 6.5
-Phase 6.5 (Checksum:39386fa) REAL time: 2 secs
-
-Phase 7.18
-Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs
-
-Writing design to file btndemo.ncd.
-
-Total REAL time to placer completion: 2 secs
-Total CPU time to placer completion: 1 secs
-
-
-Starting Router REAL time: 2 secs
-
-Phase 1: 1 unrouted; REAL time: 2 secs
-
-Phase 2: 1 unrouted; REAL time: 2 secs
-
-Phase 3: 0 unrouted; REAL time: 2 secs
-
-Phase 4: 0 unrouted; REAL time: 2 secs
-
-Finished Router REAL time: 2 secs
-
-Total REAL time to router completion: 2 secs
-Total CPU time to router completion: 1 secs
-
-Generating "par" statistics.
-
-
-All signals are completely routed.
-
-Total REAL time to par completion: 7 secs
-Total CPU time to par completion: 2 secs
-
-Placement: Completed - No errors found.
-Routing: Completed - No errors found.
-
-Writing design to file btndemo.ncd.
-
-
-PAR done.
-
-Completed process "Place & Route".
-
-
-Started process "Generate Post-Place & Route Static Timing".
-
-
-Loading device database for application trce.exe from file "btndemo.ncd".
- "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5
-Loading device for application trce.exe from file 'v200.nph' in environment
-C:/XilinxISE.
-
-Analysis completed Fri Mar 28 16:52:32 2003
---------------------------------------------------------------------------------
-
-Generating Report ...
-
-
-Completed process "Generate Post-Place & Route Static Timing".
-
-Place & Route Module btndemo . . .
-PAR command line: par -w -ol 2 -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf
-PAR completed successfully
-
-
-
-
-Started process "Generate Programming File".
-
-Release 5.1i - Bitgen F.23
-Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
-
-Loading device database for application Bitgen from file "btndemo.ncd".
- "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5
-Loading device for application Bitgen from file 'v200.nph' in environment
-C:/XilinxISE.
-Opened constraints file btndemo.pcf.
-
-Fri Mar 28 16:52:34 2003
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Creating bit map...
-Saving bit stream in "btndemo.bit".
-Bitstream generation is complete.
-
-Completed process "Generate Programming File".
-
-
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-
-
-Started process "Generate Programming File".
-
-Release 5.1i - Bitgen F.23
-Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
-
-Loading device database for application Bitgen from file "btndemo.ncd".
- "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5
-Loading device for application Bitgen from file 'v200.nph' in environment
-C:/XilinxISE.
-Opened constraints file btndemo.pcf.
-
-Mon Mar 31 17:13:29 2003
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Creating bit map...
-Saving bit stream in "btndemo.bit".
-Bitstream generation is complete.
-
-Completed process "Generate Programming File".
-
-
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-
-
-
-Started process "Synthesize".
-
-
-=========================================================================
-* HDL Compilation *
-=========================================================================
-WARNING:HDLParsers:3215 - Unit work/BTNDEMO is now defined in a different file: was F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd, now is E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd
-WARNING:HDLParsers:3215 - Unit work/BTNDEMO/BEHAVIORAL is now defined in a different file: was F:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd, now is E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd
-Compiling vhdl file E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd in Library work.
-Architecture behavioral of Entity btndemo is up to date.
-
-=========================================================================
-* HDL Analysis *
-=========================================================================
-
-Analyzing Entity (Architecture ).
-WARNING:Xst:766 - E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd line 70: Generating a Black Box for component .
-Entity analyzed. Unit generated.
-
-
-=========================================================================
-* HDL Synthesis *
-=========================================================================
-
-Synthesizing Unit .
- Related source file is E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd.
-Unit synthesized.
-
-
-=========================================================================
-HDL Synthesis Report
-
-Found no macro
-=========================================================================
-
-=========================================================================
-* Low Level Synthesis *
-=========================================================================
-Library "C:/XilinxISE/data/librtl.xst" Consulted
-
-Optimizing unit ...
-
-Mapping all equations...
-Loading device for application Xst from file 'v200.nph' in environment C:/XilinxISE.
-Building and optimizing final netlist ...
-Found area constraint ratio of 100 (+ 5) on block btndemo, actual ratio is 0.
-
-=========================================================================
-* Final Report *
-=========================================================================
-
-Device utilization summary:
----------------------------
-
-Selected Device : 2s200pq208-5
-
- Number of bonded IOBs: 2 out of 144 1%
-
-
-=========================================================================
-TIMING REPORT
-
-
-Clock Information:
-------------------
-No clock signals found in this design
-
-Timing Summary:
----------------
-Speed Grade: -5
-
- Minimum period: No path found
- Minimum input arrival time before clock: No path found
- Maximum output required time after clock: No path found
- Maximum combinational path delay: 8.404ns
-
-=========================================================================
-
-Completed process "Synthesize".
-
-
-
-Started process "Translate".
-
-
-Command Line: ngdbuild -quiet -dd e:\engineering\projects\web5.1\d2\btndemo/_ngo
--uc btndemo.ucf -insert_keep_hierarchy -p xc2s200-pq208-5 btndemo.ngc
-btndemo.ngd
-
-Reading NGO file "E:/Engineering/Projects/web5.1/D2/BtnDemo/btndemo.ngc" ...
-Reading component libraries for design expansion...
-
-Annotating constraints to design from file "btndemo.ucf" ...
-
-Checking timing specifications ...
-Checking expanded design ...
-
-NGDBUILD Design Results Summary:
- Number of errors: 0
- Number of warnings: 0
-
-Writing NGD file "btndemo.ngd" ...
-
-Writing NGDBUILD log file "btndemo.bld"...
-
-NGDBUILD done.
-
-Completed process "Translate".
-
-
-
-Started process "Map".
-
-Using target part "2s200pq208-5".
-Removing unused or disabled logic...
-Running cover...
-Running directed packing...
-Running delay-based LUT packing...
-Running related packing...
-
-Design Summary:
- Number of errors: 0
- Number of warnings: 1
- Number of Slices containing
- unrelated logic: 0 out of 0 0%
- Number of bonded IOBs: 1 out of 140 1%
- Number of GCLKIOBs: 1 out of 4 25%
-Total equivalent gate count for design: 0
-Additional JTAG gate count for IOBs: 96
-Peak Memory Usage: 52 MB
-
-Mapping completed.
-See MAP report file "btndemo_map.mrp" for details.
-
-Completed process "Map".
-
-Mapping Module btndemo . . .
-MAP command line:
-map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf
-Mapping Module btndemo: DONE
-
-
-
-Started process "Place & Route".
-
-Release 5.1i - Par F.23
-Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
-
-
-
-
-Constraints file: btndemo.pcf
-
-Loading device database for application par from file "btndemo_map.ncd".
- "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5
-Loading device for application par from file 'v200.nph' in environment
-C:/XilinxISE.
-Device speed data version: PRELIMINARY 1.25 2002-06-19.
-
-
-Resolving physical constraints.
-Finished resolving physical constraints.
-
-Device utilization summary:
-
- Number of External GCLKIOBs 1 out of 4 25%
- Number of External IOBs 1 out of 140 1%
- Number of LOCed External IOBs 1 out of 1 100%
-
-
-
-
-
-Overall effort level (-ol): 2 (set by user)
-Placer effort level (-pl): 2 (set by user)
-Placer cost table entry (-t): 1
-Router effort level (-rl): 2 (set by user)
-
-
-Phase 1.1
-Phase 1.1 (Checksum:989683) REAL time: 2 secs
-
-Phase 2.23
-Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs
-
-Phase 3.3
-Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs
-
-Phase 4.5
-Phase 4.5 (Checksum:26259fc) REAL time: 2 secs
-
-Phase 5.8
-Phase 5.8 (Checksum:98996d) REAL time: 2 secs
-
-Phase 6.5
-Phase 6.5 (Checksum:39386fa) REAL time: 2 secs
-
-Phase 7.18
-Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs
-
-Writing design to file btndemo.ncd.
-
-Total REAL time to placer completion: 3 secs
-Total CPU time to placer completion: 1 secs
-
-
-Starting Router REAL time: 3 secs
-
-Phase 1: 1 unrouted; REAL time: 3 secs
-
-Phase 2: 1 unrouted; REAL time: 3 secs
-
-Phase 3: 0 unrouted; REAL time: 3 secs
-
-Phase 4: 0 unrouted; REAL time: 3 secs
-
-Finished Router REAL time: 3 secs
-
-Total REAL time to router completion: 3 secs
-Total CPU time to router completion: 1 secs
-
-Generating "par" statistics.
-
-
-All signals are completely routed.
-
-Total REAL time to par completion: 6 secs
-Total CPU time to par completion: 2 secs
-
-Placement: Completed - No errors found.
-Routing: Completed - No errors found.
-
-Writing design to file btndemo.ncd.
-
-
-PAR done.
-
-Completed process "Place & Route".
-
-
-Started process "Generate Post-Place & Route Static Timing".
-
-
-Loading device database for application trce.exe from file "btndemo.ncd".
- "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5
-Loading device for application trce.exe from file 'v200.nph' in environment
-C:/XilinxISE.
-
-Analysis completed Thu May 29 12:19:52 2003
---------------------------------------------------------------------------------
-
-Generating Report ...
-
-
-Completed process "Generate Post-Place & Route Static Timing".
-
-Place & Route Module btndemo . . .
-PAR command line: par -w -ol 2 -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf
-PAR completed successfully
-
-
-
-
-Started process "Generate Programming File".
-
-Release 5.1i - Bitgen F.23
-Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
-
-Loading device database for application Bitgen from file "btndemo.ncd".
- "btndemo" is an NCD, version 2.37, device xc2s200, package pq208, speed -5
-Loading device for application Bitgen from file 'v200.nph' in environment
-C:/XilinxISE.
-Opened constraints file btndemo.pcf.
-
-Thu May 29 12:19:55 2003
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Creating bit map...
-Saving bit stream in "btndemo.bit".
-Bitstream generation is complete.
-
-Completed process "Generate Programming File".
-
-
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-
-
-
-Started process "Synthesize".
-
-
-=========================================================================
-* HDL Compilation *
-=========================================================================
-WARNING:HDLParsers:3215 - Unit work/BTNDEMO is now defined in a different file: was E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd, now is X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd
-WARNING:HDLParsers:3215 - Unit work/BTNDEMO/BEHAVIORAL is now defined in a different file: was E:/Engineering/Projects/web5.1/D2/BtnDemo/BtnDemo.vhd, now is X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd
-Compiling vhdl file X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd in Library work.
-Entity (Architecture ) compiled.
-
-=========================================================================
-* HDL Analysis *
-=========================================================================
-Analyzing Entity (Architecture ).
-WARNING:Xst:766 - X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd line 70: Generating a Black Box for component .
-Entity analyzed. Unit generated.
-
-
-=========================================================================
-* HDL Synthesis *
-=========================================================================
-
-Synthesizing Unit .
- Related source file is X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd.
-Unit synthesized.
-
-
-=========================================================================
-* Advanced HDL Synthesis *
-=========================================================================
-
-Advanced RAM inference ...
-Advanced multiplier inference ...
-Advanced Registered AddSub inference ...
-Dynamic shift register inference ...
-
-=========================================================================
-HDL Synthesis Report
-
-Found no macro
-=========================================================================
-
-=========================================================================
-* Low Level Synthesis *
-=========================================================================
-
-Optimizing unit ...
-Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.
-
-Mapping all equations...
-Building and optimizing final netlist ...
-Found area constraint ratio of 100 (+ 5) on block btndemo, actual ratio is 0.
-
-=========================================================================
-* Final Report *
-=========================================================================
-
-Device utilization summary:
----------------------------
-
-Selected Device : 2s200pq208-5
-
- Number of bonded IOBs: 2 out of 144 1%
-
-
-=========================================================================
-TIMING REPORT
-
-
-Clock Information:
-------------------
-No clock signals found in this design
-
-Timing Summary:
----------------
-Speed Grade: -5
-
- Minimum period: No path found
- Minimum input arrival time before clock: No path found
- Maximum output required time after clock: No path found
- Maximum combinational path delay: 8.404ns
-
-=========================================================================
-Completed process "Synthesize".
-
-
-
-Started process "Translate".
-
-
-Command Line: ngdbuild -intstyle ise -dd x:\barron\config\d2\basic\btndemo/_ngo
--uc btndemo.ucf -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd
-
-Reading NGO file "X:/Barron/config/D2/BASIC/BtnDemo/btndemo.ngc" ...
-Reading component libraries for design expansion...
-
-Annotating constraints to design from file "btndemo.ucf" ...
-
-Checking timing specifications ...
-Checking expanded design ...
-
-NGDBUILD Design Results Summary:
- Number of errors: 0
- Number of warnings: 0
-
-Total memory usage is 39036 kilobytes
-
-Writing NGD file "btndemo.ngd" ...
-
-Writing NGDBUILD log file "btndemo.bld"...
-
-NGDBUILD done.
-Completed process "Translate".
-
-
-
-Started process "Map".
-
-Using target part "2s200pq208-5".
-Removing unused or disabled logic...
-Running cover...
-Running directed packing...
-Running delay-based LUT packing...
-Running related packing...
-
-Design Summary:
-Number of errors: 0
-Number of warnings: 1
-Logic Utilization:
-Logic Distribution:
- Number of Slices containing only related logic: 0 out of 0 0%
- Number of Slices containing unrelated logic: 0 out of 0 0%
- *See NOTES below for an explanation of the effects of unrelated logic
- Number of bonded IOBs: 1 out of 140 1%
- Number of GCLKIOBs: 1 out of 4 25%
-
-Total equivalent gate count for design: 0
-Additional JTAG gate count for IOBs: 96
-Peak Memory Usage: 61 MB
-
-NOTES:
-
- Related logic is defined as being logic that shares connectivity -
- e.g. two LUTs are "related" if they share common inputs.
- When assembling slices, Map gives priority to combine logic that
- is related. Doing so results in the best timing performance.
-
- Unrelated logic shares no connectivity. Map will only begin
- packing unrelated logic into a slice once 99% of the slices are
- occupied through related logic packing.
-
- Note that once logic distribution reaches the 99% level through
- related logic packing, this does not mean the device is completely
- utilized. Unrelated logic packing will then begin, continuing until
- all usable LUTs and FFs are occupied. Depending on your timing
- budget, increased levels of unrelated logic packing may adversely
- affect the overall timing performance of your design.
-
-
-Mapping completed.
-See MAP report file "btndemo_map.mrp" for details.
-Completed process "Map".
-
-Mapping Module btndemo . . .
-MAP command line:
-map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf
-Mapping Module btndemo: DONE
-
-
-
-Started process "Place & Route".
-
-
-
-
-
-Constraints file: btndemo.pcf
-
-Loading device database for application Par from file "btndemo_map.ncd".
- "btndemo" is an NCD, version 2.38, device xc2s200, package pq208, speed -5
-Loading device for application Par from file 'v200.nph' in environment
-C:/Xilinx.
-Device speed data version: PRODUCTION 1.27 2003-12-13.
-
-
-Resolving physical constraints.
-Finished resolving physical constraints.
-
-Device utilization summary:
-
- Number of External GCLKIOBs 1 out of 4 25%
- Number of External IOBs 1 out of 140 1%
- Number of LOCed External IOBs 1 out of 1 100%
-
-
-
-
-
-Overall effort level (-ol): Standard (set by user)
-Placer effort level (-pl): Standard (set by user)
-Placer cost table entry (-t): 1
-Router effort level (-rl): Standard (set by user)
-
-
-Phase 1.1
-Phase 1.1 (Checksum:989683) REAL time: 3 secs
-
-Phase 2.23
-Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs
-
-Phase 3.3
-Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs
-
-Phase 4.5
-Phase 4.5 (Checksum:26259fc) REAL time: 3 secs
-
-Phase 5.8
-Phase 5.8 (Checksum:98996d) REAL time: 4 secs
-
-Phase 6.5
-Phase 6.5 (Checksum:39386fa) REAL time: 4 secs
-
-Phase 7.18
-Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs
-
-Writing design to file btndemo.ncd.
-
-Total REAL time to Placer completion: 6 secs
-Total CPU time to Placer completion: 1 secs
-
-
-Phase 1: 1 unrouted; REAL time: 6 secs
-
-Phase 2: 1 unrouted; REAL time: 6 secs
-
-Phase 3: 0 unrouted; REAL time: 6 secs
-
-Phase 4: 0 unrouted; REAL time: 6 secs
-
-Total REAL time to Router completion: 7 secs
-Total CPU time to Router completion: 2 secs
-
-Generating "par" statistics.
-
-Generating Pad Report.
-
-All signals are completely routed.
-
-Total REAL time to PAR completion: 16 secs
-Total CPU time to PAR completion: 5 secs
-
-Peak Memory Usage: 50 MB
-
-Placement: Completed - No errors found.
-Routing: Completed - No errors found.
-
-Writing design to file btndemo.ncd.
-
-
-PAR done.
-Completed process "Place & Route".
-
-
-Started process "Generate Post-Place & Route Static Timing".
-
-WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This
- generally indicates that there is an inconsistency between versions of the
- speed and device data files. Please check to ensure that the XILINX
- environment variable is set correctly, if the MYXILINX variable is set, make
- sure that it is pointing to patch files that are compatable with the version
- of software that the XILINX variable points to.
-WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This
- generally indicates that there is an inconsistency between versions of the
- speed and device data files. Please check to ensure that the XILINX
- environment variable is set correctly, if the MYXILINX variable is set, make
- sure that it is pointing to patch files that are compatable with the version
- of software that the XILINX variable points to.
-
-Analysis completed Tue Jul 06 17:46:21 2004
---------------------------------------------------------------------------------
-
-Generating Report ...
-
-Completed process "Generate Post-Place & Route Static Timing".
-
-Place & Route Module btndemo . . .
-PAR command line: par -w -intstyle ise -ol std -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf
-PAR completed successfully
-
-
-
-
-Started process "Generate Programming File".
-
-Completed process "Generate Programming File".
-
-
-
-Project Navigator Auto-Make Log File
--------------------------------------
-
-
-
-
-Started process "Synthesize".
-
-
-=========================================================================
-* HDL Compilation *
-=========================================================================
-Compiling vhdl file X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd in Library work.
-Architecture behavioral of Entity btndemo is up to date.
-
-=========================================================================
-* HDL Analysis *
-=========================================================================
-Analyzing Entity (Architecture ).
-WARNING:Xst:766 - X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd line 70: Generating a Black Box for component .
-Entity analyzed. Unit generated.
-
-
-=========================================================================
-* HDL Synthesis *
-=========================================================================
-
-Synthesizing Unit .
- Related source file is X:/Barron/config/D2/BASIC/BtnDemo/BtnDemo.vhd.
-Unit synthesized.
-
-
-=========================================================================
-* Advanced HDL Synthesis *
-=========================================================================
-
-Advanced RAM inference ...
-Advanced multiplier inference ...
-Advanced Registered AddSub inference ...
-Dynamic shift register inference ...
-
-=========================================================================
-HDL Synthesis Report
-
-Found no macro
-=========================================================================
-
-=========================================================================
-* Low Level Synthesis *
-=========================================================================
-
-Optimizing unit ...
-Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.
-
-Mapping all equations...
-Building and optimizing final netlist ...
-Found area constraint ratio of 100 (+ 5) on block btndemo, actual ratio is 0.
-
-=========================================================================
-* Final Report *
-=========================================================================
-
-Device utilization summary:
----------------------------
-
-Selected Device : 2s200pq208-5
-
- Number of bonded IOBs: 2 out of 144 1%
-
-
-=========================================================================
-TIMING REPORT
-
-
-Clock Information:
-------------------
-No clock signals found in this design
-
-Timing Summary:
----------------
-Speed Grade: -5
-
- Minimum period: No path found
- Minimum input arrival time before clock: No path found
- Maximum output required time after clock: No path found
- Maximum combinational path delay: 8.404ns
-
-=========================================================================
-Completed process "Synthesize".
-
-
-
-Started process "Translate".
-
-
-Command Line: ngdbuild -intstyle ise -dd x:\barron\config\d2\basic\btndemo/_ngo
--uc btndemo.ucf -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd
-
-Reading NGO file "X:/Barron/config/D2/BASIC/BtnDemo/btndemo.ngc" ...
-Reading component libraries for design expansion...
-
-Annotating constraints to design from file "btndemo.ucf" ...
-
-Checking timing specifications ...
-Checking expanded design ...
-
-NGDBUILD Design Results Summary:
- Number of errors: 0
- Number of warnings: 0
-
-Total memory usage is 39036 kilobytes
-
-Writing NGD file "btndemo.ngd" ...
-
-Writing NGDBUILD log file "btndemo.bld"...
-
-NGDBUILD done.
-Completed process "Translate".
-
-
-
-Started process "Map".
-
-Using target part "2s200pq208-5".
-Removing unused or disabled logic...
-Running cover...
-Running directed packing...
-Running delay-based LUT packing...
-Running related packing...
-
-Design Summary:
-Number of errors: 0
-Number of warnings: 1
-Logic Utilization:
-Logic Distribution:
- Number of Slices containing only related logic: 0 out of 0 0%
- Number of Slices containing unrelated logic: 0 out of 0 0%
- *See NOTES below for an explanation of the effects of unrelated logic
- Number of bonded IOBs: 1 out of 140 1%
- Number of GCLKIOBs: 1 out of 4 25%
-
-Total equivalent gate count for design: 0
-Additional JTAG gate count for IOBs: 96
-Peak Memory Usage: 61 MB
-
-NOTES:
-
- Related logic is defined as being logic that shares connectivity -
- e.g. two LUTs are "related" if they share common inputs.
- When assembling slices, Map gives priority to combine logic that
- is related. Doing so results in the best timing performance.
-
- Unrelated logic shares no connectivity. Map will only begin
- packing unrelated logic into a slice once 99% of the slices are
- occupied through related logic packing.
-
- Note that once logic distribution reaches the 99% level through
- related logic packing, this does not mean the device is completely
- utilized. Unrelated logic packing will then begin, continuing until
- all usable LUTs and FFs are occupied. Depending on your timing
- budget, increased levels of unrelated logic packing may adversely
- affect the overall timing performance of your design.
-
-
-Mapping completed.
-See MAP report file "btndemo_map.mrp" for details.
-Completed process "Map".
-
-Mapping Module btndemo . . .
-MAP command line:
-map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf
-Mapping Module btndemo: DONE
-
-
-
-Started process "Place & Route".
-
-
-
-
-
-Constraints file: btndemo.pcf
-
-Loading device database for application Par from file "btndemo_map.ncd".
- "btndemo" is an NCD, version 2.38, device xc2s200, package pq208, speed -5
-Loading device for application Par from file 'v200.nph' in environment
-C:/Xilinx.
-Device speed data version: PRODUCTION 1.27 2003-12-13.
-
-
-Resolving physical constraints.
-Finished resolving physical constraints.
-
-Device utilization summary:
-
- Number of External GCLKIOBs 1 out of 4 25%
- Number of External IOBs 1 out of 140 1%
- Number of LOCed External IOBs 1 out of 1 100%
-
-
-
-
-
-Overall effort level (-ol): Standard (set by user)
-Placer effort level (-pl): Standard (set by user)
-Placer cost table entry (-t): 1
-Router effort level (-rl): Standard (set by user)
-
-
-Phase 1.1
-Phase 1.1 (Checksum:989683) REAL time: 3 secs
-
-Phase 2.23
-Phase 2.23 (Checksum:1312cfe) REAL time: 4 secs
-
-Phase 3.3
-Phase 3.3 (Checksum:1c9c37d) REAL time: 4 secs
-
-Phase 4.5
-Phase 4.5 (Checksum:26259fc) REAL time: 4 secs
-
-Phase 5.8
-Phase 5.8 (Checksum:98996d) REAL time: 4 secs
-
-Phase 6.5
-Phase 6.5 (Checksum:39386fa) REAL time: 4 secs
-
-Phase 7.18
-Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs
-
-Writing design to file btndemo.ncd.
-
-Total REAL time to Placer completion: 5 secs
-Total CPU time to Placer completion: 1 secs
-
-
-Phase 1: 1 unrouted; REAL time: 5 secs
-
-Phase 2: 1 unrouted; REAL time: 5 secs
-
-Phase 3: 0 unrouted; REAL time: 5 secs
-
-Phase 4: 0 unrouted; REAL time: 5 secs
-
-Total REAL time to Router completion: 5 secs
-Total CPU time to Router completion: 1 secs
-
-Generating "par" statistics.
-
-Generating Pad Report.
-
-All signals are completely routed.
-
-Total REAL time to PAR completion: 24 secs
-Total CPU time to PAR completion: 5 secs
-
-Peak Memory Usage: 50 MB
-
-Placement: Completed - No errors found.
-Routing: Completed - No errors found.
-
-Writing design to file btndemo.ncd.
-
-
-PAR done.
-Completed process "Place & Route".
-
-
-Started process "Generate Post-Place & Route Static Timing".
-
-WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This
- generally indicates that there is an inconsistency between versions of the
- speed and device data files. Please check to ensure that the XILINX
- environment variable is set correctly, if the MYXILINX variable is set, make
- sure that it is pointing to patch files that are compatable with the version
- of software that the XILINX variable points to.
-WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This
- generally indicates that there is an inconsistency between versions of the
- speed and device data files. Please check to ensure that the XILINX
- environment variable is set correctly, if the MYXILINX variable is set, make
- sure that it is pointing to patch files that are compatable with the version
- of software that the XILINX variable points to.
-
-Analysis completed Wed Jul 07 09:50:48 2004
---------------------------------------------------------------------------------
-
-Generating Report ...
-
-Completed process "Generate Post-Place & Route Static Timing".
-
-Place & Route Module btndemo . . .
-PAR command line: par -w -intstyle ise -ol std -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf
-PAR completed successfully
-
-
-
-
-Started process "Generate Programming File".
-
-Completed process "Generate Programming File".
-
-
Index: demos/projects/BtnDemo/btndemo.bgn
===================================================================
--- demos/projects/BtnDemo/btndemo.bgn (revision 430)
+++ demos/projects/BtnDemo/btndemo.bgn (nonexistent)
@@ -1,103 +0,0 @@
-Release 6.2.03i - Bitgen G.31a
-Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
-
-Loading device database for application Bitgen from file "btndemo.ncd".
- "btndemo" is an NCD, version 2.38, device xc2s200, package pq208, speed -5
-Loading device for application Bitgen from file 'v200.nph' in environment
-C:/Xilinx.
-Opened constraints file btndemo.pcf.
-
-Wed Jul 07 09:50:55 2004
-
-C:/Xilinx/bin/nt/bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:JtagClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No btndemo.ncd
-
-Summary of Bitgen Options:
-+----------------------+----------------------+
-| Option Name | Current Setting |
-+----------------------+----------------------+
-| Compress | (Not Specified)* |
-+----------------------+----------------------+
-| Readback | (Not Specified)* |
-+----------------------+----------------------+
-| DebugBitstream | No** |
-+----------------------+----------------------+
-| ConfigRate | 4** |
-+----------------------+----------------------+
-| StartupClk | JtagClk |
-+----------------------+----------------------+
-| CclkPin | Pullup** |
-+----------------------+----------------------+
-| DonePin | Pullup** |
-+----------------------+----------------------+
-| M0Pin | Pullup** |
-+----------------------+----------------------+
-| M1Pin | Pullup** |
-+----------------------+----------------------+
-| M2Pin | Pullup** |
-+----------------------+----------------------+
-| ProgPin | Pullup** |
-+----------------------+----------------------+
-| TckPin | Pullup** |
-+----------------------+----------------------+
-| TdiPin | Pullup** |
-+----------------------+----------------------+
-| TdoPin | Pullup |
-+----------------------+----------------------+
-| TmsPin | Pullup** |
-+----------------------+----------------------+
-| UnusedPin | Pulldown** |
-+----------------------+----------------------+
-| GSR_cycle | 6** |
-+----------------------+----------------------+
-| GWE_cycle | 6** |
-+----------------------+----------------------+
-| GTS_cycle | 5** |
-+----------------------+----------------------+
-| LCK_cycle | NoWait** |
-+----------------------+----------------------+
-| DONE_cycle | 4** |
-+----------------------+----------------------+
-| Persist | No* |
-+----------------------+----------------------+
-| DriveDone | No** |
-+----------------------+----------------------+
-| DonePipe | No** |
-+----------------------+----------------------+
-| Security | None** |
-+----------------------+----------------------+
-| UserID | 0xFFFFFFFF** |
-+----------------------+----------------------+
-| Gclkdel0 | 11111** |
-+----------------------+----------------------+
-| Gclkdel1 | 11111** |
-+----------------------+----------------------+
-| Gclkdel2 | 11111** |
-+----------------------+----------------------+
-| Gclkdel3 | 11111** |
-+----------------------+----------------------+
-| ActiveReconfig | No* |
-+----------------------+----------------------+
-| ActivateGclk | No* |
-+----------------------+----------------------+
-| PartialMask0 | (Not Specified)* |
-+----------------------+----------------------+
-| PartialMask1 | (Not Specified)* |
-+----------------------+----------------------+
-| PartialGclk | (Not Specified)* |
-+----------------------+----------------------+
-| PartialLeft | (Not Specified)* |
-+----------------------+----------------------+
-| PartialRight | (Not Specified)* |
-+----------------------+----------------------+
-| IEEE1532 | No* |
-+----------------------+----------------------+
-| Binary | No** |
-+----------------------+----------------------+
- * Default setting.
- ** The specified setting matches the default setting.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Creating bit map...
-Saving bit stream in "btndemo.bit".
-Bitstream generation is complete.
Index: demos/projects/BtnDemo/btndemo.ngc
===================================================================
--- demos/projects/BtnDemo/btndemo.ngc (revision 430)
+++ demos/projects/BtnDemo/btndemo.ngc (nonexistent)
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.2e
-$0cx=>EHEDC_XHJ8;BPFEQCC=2M%?;H78MGSAO>1GCJGLAM58J@RPG[A:7B:4OCWE0>VFZ]<0_B[]CD68P\VB:2_:o6[\ES]UMVOEDL30ZDKX_U[SA4b{R3951<5289:on><:3:713}i9;0:7c?<:39'544;09567dk991>5::6:&f>0=#13;27o?9:181>7<4s-h1=;5Gd:k21?6=3f;<6=44bb83>7<729q/n7:4He9K55=n;3:17b950;9~f4>=8381<7>t$c8;?Mb<@8:0e>4?::m4>5<6=4={_36?8e=;2wx=54?:3y>g?1<5821?6s|1683>7}Y9>16=548;|m55<728qCh6sa1083>4}Ol2we=?4?:0yK`>{zutJKOv?9:cag7<04itJKNv>r@ARxyEF
\ No newline at end of file
Index: demos/projects/BtnDemo/btndemo.pcf
===================================================================
--- demos/projects/BtnDemo/btndemo.pcf (revision 430)
+++ demos/projects/BtnDemo/btndemo.pcf (nonexistent)
@@ -1,5 +0,0 @@
-SCHEMATIC START ;
-// created by map version G.31a on Wed Jul 07 09:50:09 2004
-COMP "led" LOCATE = SITE "P71" LEVEL 1;
-COMP "btn" LOCATE = SITE "P77" LEVEL 1;
-SCHEMATIC END ;
Index: demos/projects/BtnDemo/btndemo.ngd
===================================================================
--- demos/projects/BtnDemo/btndemo.ngd (revision 430)
+++ demos/projects/BtnDemo/btndemo.ngd (nonexistent)
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.2e
-$26x50=#Zl|bdaa:!3-=5(3&:*/o6<|212su76?%<90NXH>0:@VMIBX\HXLIYO]CI78GNDRN01HC@CFTUGG3>EUMH^NHh5KRB]PQFEB[ZL^@55JXQCM@@B?3OXDAR[LF49D*67f92C>7DLZFF08MK>2CDXT^J7:NJFWGUQ?1GCLJJD29OKF1I33FH^J>5@UU18T2743Y=3_CN[RZVPD3g?]OKAGR&TIL/0/3#WQSE(9$:,L]LIH48\VRKAK<0TilPIea8\anXX{cfXt~jf:ZglZVuad\n~~g`n028\akXEh`d~[k}shmm55=_ldUFeca}Vdppmjh43Qy?6l{n69apkbbef90`hj7;mgg[JDRN11ekilzimf;?vvfz}ke>k5wc3q145+2%y{9<564xhnjj}siuIJ{=i5O@y0g>C<328qX:74=i:h097)<9:368yV3=:k0j6<=>cb20>7>3=>1X=?4<0;29567dk991>5::c:Q6>66=83;8=nm?3;0;0=?7d=i3;8=nm?3;0;000<,:08=6F8;wV;>5<62808w^852c8b>456kj:86?6;579'66<6<2\947s6>3:0q)?j:09a6a<72;0?6>u+2181`>N5:2c9o7>5;n0f>5<6F=5:&13?2<,8:1h6Fi;%32>65=83.9;7?n;:a6c<72;0;6=u+2182=>N5:2B996*=7;08Lc=#990:m6*>1;10?ld=83.9;7j4;n3;>5<#:>0:m65rb3a94?7=83:p(?951e9K67=Om2.:<7j4$0195f=n9m0;6)<8:0f8?xd5m3:1=7>50z&13?7c3A897Ek4$0295d=#9:0:n6a>d;29 71=9m10q~{t:o0;6?u22082<>;5n3h0q~{I01?L7c28q:6pT6:0y27?{zf821<7?tH308yk7>290:wE<=;H3g>4}52tP263;~yx{GHJq:h7:l092f<7{GHKq;qMN_{|BC
\ No newline at end of file
Index: demos/projects/BtnDemo/btndemo.ngm
===================================================================
--- demos/projects/BtnDemo/btndemo.ngm (revision 430)
+++ demos/projects/BtnDemo/btndemo.ngm (nonexistent)
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.2e
-$40x50=#Zl|bdaa:!3-53(?&8*/=85+Rdtjwlii2);%5= ;.2"'g>4t:9:{}?>7-418FP@682H^EAJPT@PDAQGUKA?0OFLZF89@KHKN\]OO;6M]E@VF@`=CZJUXYNMJSRDVH==BPYKEHHJ;;GPBCg=AZHMHC[K]EEc8BWG@WKKXIIo4FSCD[FIRF]20J_AB_TAE55=AzhmGeo ctm8JTDB682LymjBfb/nwh?IE]O;;7K|ngMka*irk2FZJH<64FscdHld)d}f1T[EPGBNHMGSA=2M%?4:EFJ@TF\LN+\B][-GNJJQ753NOEI_O[EE"SKVR*O:::7D;4ICWEC7=NF11BBKK]RDF5?LIDGDZ=7DA[YQG7?LVFL>1GEO\NRX48HJGCMM90@BM8;MMDMFGK02FoaRZvpd`8IDVBPYKEHHJ9;LCST@Bf3DK[S@AKUMGg?HGWW]CFI^ZNMQ`8IDVX^LXXEB@l;LcikwPbzzcdbn5BiomqR`ttafd<7CK[WNPH5>I33FH^J95@P@F0?JSS;2Z<=>5_7618TDB33YKYX55_HXQJGDJ>3ZCLSNAZNU18WKM13ZE^^NK<;RP@b>RFZNO_S]O]TU[SA1=SQYO97X?l;TQFVZPN[@HGI45YIDU\P\VB9m1SEAGAX,ZGF%6)9)Y_YO.?.0"BWFON>2RXXAGMc:ZUOZADDBCIYK84Xe`\Mac^c`VZye`Zvpdd8\anXX{cfZh||inl4?]boW]kln6Vkm^@jjaoio8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`<;Yqw7>dsf>1ixcjjmn18h`b?3eooSBLZF29neu>0?47?<:012gf642;2?9;ua4782?k202;1/?k4?lc1196=22?2Y:i7:j:08274ed8:0949;l;R490`<6289:on><:3:7<<=T9l0?h7>5123`g55=:1>3h6]=3;6g>45=9:;ho==5296;b>U12=n1<7?<1ba37?4?<1l0h9o50;396~U02=21=>4>30a`46<50=?=7):54g9K<>h5=3>;in<6be9'61<3n2.9:7?<;wV16?6=93;1?v]8:5:956<6;8ih<>4=8575?!5e2;:0Z9=52zw13?7<};21<6s+3081?g2f2909694<{%1;>1g<@:k0b9:50:k7=?6=3f>i6=44b2;95?4=83:p(>65169K7d=O;m1/8?4:;%3a>4><@8k0(=h:h0:6):=:3f8?xd3k3;1>7>50z&06=O9h1/=o4=d:&2`?363g>?6?5f1782>!2528207bf;0e?k232:1b?=4>:%61>66<3th?n7?51;294~"3:39;7E=n;I3:?!7e2;n0(=z{=31<7=t^5;896?=9?16844<0:p0f<72;q6?44=a:?7g?713ty?n7>53z\7f>;3k38j70:m:228yxh6i3:1=vFc;295~N4i2C8<7?t2;Ya?7|9o0vb9:52:~rQd=83;1=7=tS687`?6=9:;ho==5296;a>"4j3997)=>:39K51=O9<1i8l4?:387>6}Ok2.8;7<4ne87?k542:1e894?;h6:>5<7<729q/?54=:k1/=o4=d:Jb?k232;1/><4>0:k22?7=3f8j6<44}c6:>4<6290;w)=7:0a8 4d=911/=k4=f:Jb?k232:1/><4i;n15>4<i6<4>:183!5?2;i0(602;k019m5179~w1d=839p19m52`9>0g<4<2T?n6srn3d94?7|f=>1<6sa3183>4}i<=0:7p`<1;295~h3<380qpsr@AAx70<>::o=597r@A@x55}383:1<7<524824>{|<80;6=4=:34954=zs=;1<7>52;04>44;6=4?:38150;096<<6<2wp8<4?:181>7g=9<1vw9>50;296?4e28<0qv:>:183>7<5k3;<7pu;0;294?4=:m0:46st4083>5<52;o1=45r}ABSxFG
\ No newline at end of file
Index: demos/projects/BtnDemo/d2but.cdf
===================================================================
--- demos/projects/BtnDemo/d2but.cdf (revision 430)
+++ demos/projects/BtnDemo/d2but.cdf (nonexistent)
@@ -1,16 +0,0 @@
-JedecChain;
-FileRevision(JESDxxA);
-/* NoviceMode */
-/* Active Mode BS */
-/* Mode BS */
-/* Cable Parallel lpt1 */
- P ActionCode(Cfg)
- Device
- PartName(xc2s200)
- File("E:\Engineering\Projects\web5.1\D2\BtnDemo\btndemo.bit")
- ;
-/* Mode SS */
-/* Mode SM */
-/* Mode BSFILE */
-/* Mode HW140 */
-ChainEnd;
Index: demos/projects/BtnDemo/btndemo.ngr
===================================================================
--- demos/projects/BtnDemo/btndemo.ngr (revision 430)
+++ demos/projects/BtnDemo/btndemo.ngr (nonexistent)
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.2e
-$0cx=>EHEDC_XHJ8;BPFEQCC=2M%?;H78MGSAO>1GCJGLAM38K1=WI[^87_ZC4:VZT@4<]830ZDKX_U[SA7b7}ABs57=GHq;>6K4=:0yP5?742;0:?3;09567dk991>5::4:f21?6=93;p_<4>3;09567dk991>5::3:tE:0196?749ji;?7<74418 g<23k;>6=4=:081!?=9<1Gi7?t$682=>{Kn3;p(<95c:j51<722e::7>5;cc94?4=83:p(44;;Md95~h603>=7pg<:188k3<722wx=94?:3y]51=:i390q~?9:181[7134k1:6sr}|CDF}6:3im>hj>c1CDG}7uIJ[wpNO
\ No newline at end of file
Index: demos/projects/BtnDemo/_impact.cmd
===================================================================
--- demos/projects/BtnDemo/_impact.cmd (revision 430)
+++ demos/projects/BtnDemo/_impact.cmd (nonexistent)
@@ -1,15 +0,0 @@
-setpreference -novice
-setpreference -stop_on_failure
-setPreference -fixClock
-setPreference -PC4_200K
-setMode -bs
-setMode -bs
-setMode -bs
-setCable -port auto
-setMode -bs
-setMode -bs
-Identify
-setAttribute -position 1 -attr configFileName -value E:\Engineering\Projects\web5.1\D2\BtnDemo\btndemo.bit
-setMode -bs
-setMode -bs
-Program -p 1
Index: demos/projects/BtnDemo/btndemo.cup
===================================================================
--- demos/projects/BtnDemo/btndemo.cup (revision 430)
+++ demos/projects/BtnDemo/btndemo.cup (nonexistent)
@@ -1 +0,0 @@
-cleaned up XST temp files
Index: demos/projects/BtnDemo/btndemo_last_par.ncd
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: demos/projects/BtnDemo/btndemo_last_par.ncd
===================================================================
--- demos/projects/BtnDemo/btndemo_last_par.ncd (revision 430)
+++ demos/projects/BtnDemo/btndemo_last_par.ncd (nonexistent)
demos/projects/BtnDemo/btndemo_last_par.ncd
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: demos/projects/BtnDemo/BtnDemo_map.mrp
===================================================================
--- demos/projects/BtnDemo/BtnDemo_map.mrp (revision 430)
+++ demos/projects/BtnDemo/BtnDemo_map.mrp (nonexistent)
@@ -1,37 +0,0 @@
-Release 12.3 Map M.70d (lin)
-Xilinx Mapping Report File for Design 'BtnDemo'
-
-Design Information
-------------------
-Command Line : map -intstyle ise -p xc3s1000-fg320-4 -cm area -ir off -pr off
--c 100 -o BtnDemo_map.ncd BtnDemo.ngd BtnDemo.pcf
-Target Device : xc3s1000
-Target Package : fg320
-Target Speed : -4
-Mapper Version : spartan3 -- $Revision: 1.52 $
-Mapped Date : Wed Apr 30 19:14:28 2014
-
-Design Summary
---------------
-Number of errors : 1
-Number of warnings : 0
-
-Section 1 - Errors
-------------------
-ERROR:Security:9 - No 'ISE' nor 'WebPack' feature was available for part
-'xc3s1000'.
-ERROR:Map:258 - A problem was encountered attempting to get the license for this
- architecture.
-
-Section 2 - Warnings
---------------------
-WARNING:Security:43 - No license file was found in the standard Xilinx license
-directory.
-WARNING:Security:44 - No license file was found.
-
-Section 3 - Informational
--------------------------
-INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
-INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.
-INFO:Security:54 - 'xc3s1000' is a WebPack part.
-INFO:Security:68 - Please run the Xilinx License Configuration Manager
Index: demos/projects/BtnDemo/btndemo_ngdbuild.nav
===================================================================
--- demos/projects/BtnDemo/btndemo_ngdbuild.nav (revision 430)
+++ demos/projects/BtnDemo/btndemo_ngdbuild.nav (nonexistent)
@@ -1,2 +0,0 @@
-
-
demos/projects/BtnDemo/btndemo_map.ncd
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: demos/projects/BtnDemo/BtnDemo.zip
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: demos/projects/BtnDemo/BtnDemo.zip
===================================================================
--- demos/projects/BtnDemo/BtnDemo.zip (revision 430)
+++ demos/projects/BtnDemo/BtnDemo.zip (nonexistent)
demos/projects/BtnDemo/BtnDemo.zip
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: demos/projects/BtnDemo/btndemo_pad.txt
===================================================================
--- demos/projects/BtnDemo/btndemo_pad.txt (revision 430)
+++ demos/projects/BtnDemo/btndemo_pad.txt (nonexistent)
@@ -1,232 +0,0 @@
-Release 6.2.03i - Par G.31a
-Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
-
-Wed Jul 07 09:50:35 2004
-
-
-INPUT FILE: btndemo_map.ncd
-OUTPUT FILE: btndemo_pad.txt
-PART TYPE: xc2s200
-SPEED GRADE: -5
-PACKAGE: pq208
-
-Pinout by Pin Number:
-
------ |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |
-Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|
-P1 | | |GND | | | | | | | | | |
-P2 | | |TMS | | | | | | | | | |
-P3 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P4 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | |
-P5 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P6 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | |
-P7 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P8 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P9 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | |
-P10 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P11 | | |GND | | | | | | | | | |
-P12 | | |VCCO | | |0 | | | | |na | |
-P13 | | |VCCINT | | | | | | | |2.5 | |
-P14 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P15 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P16 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P17 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P18 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P19 | | |GND | | | | | | | | | |
-P20 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | |
-P21 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P22 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P23 | |IOB | |UNUSED | |(0,7)*** | | | | | | |
-P24 | |PCIIOB |IO_IRDY |UNUSED | |(0,7)*** | | | | | | |
-P25 | | |GND | | | | | | | | | |
-P26 | | |VCCO | | |0 | | | | |na | |
-P27 | |PCIIOB |IO_TRDY |UNUSED | |(0,6)*** | | | | | | |
-P28 | | |VCCINT | | | | | | | |2.5 | |
-P29 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P30 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P31 | |IOB |IO_VREF_6 |UNUSED | |(0,6)*** | | | | | | |
-P32 | | |GND | | | | | | | | | |
-P33 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P34 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P35 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P36 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P37 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P38 | | |VCCINT | | | | | | | |2.5 | |
-P39 | | |VCCO | | |0 | | | | |na | |
-P40 | | |GND | | | | | | | | | |
-P41 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P42 | |IOB |IO_VREF_6 |UNUSED | |(0,6)*** | | | | | | |
-P43 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P44 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P45 | |IOB |IO_VREF_6 |UNUSED | |(0,6)*** | | | | | | |
-P46 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P47 | |IOB |IO_VREF_6 |UNUSED | |(0,6)*** | | | | | | |
-P48 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P49 | |IOB | |UNUSED | |(0,6)*** | | | | | | |
-P50 | | |M1 | | | | | | | | | |
-P51 | | |GND | | | | | | | | | |
-P52 | | |M0 | | | | | | | | | |
-P53 | | |VCCO | | |0 | | | | |na | |
-P54 | | |M2 | | | | | | | | | |
-P55 | | |NC | | | | | | | | | |
-P56 | | |NC | | | | | | | | | |
-P57 | |IOB |IO_VREF_5 |UNUSED | |(0,5)*** | | | | | | |
-P58 | |IOB | |UNUSED | |(0,5)*** | | | | | | |
-P59 | |IOB |IO_VREF_5 |UNUSED | |(0,5)*** | | | | | | |
-P60 | |IOB | |UNUSED | |(0,5)*** | | | | | | |
-P61 | |IOB | |UNUSED | |(0,5)*** | | | | | | |
-P62 | |IOB |IO_VREF_5 |UNUSED | |(0,5)*** | | | | | | |
-P63 | |IOB | |UNUSED | |(0,5)*** | | | | | | |
-P64 | | |GND | | | | | | | | | |
-P65 | | |VCCO | | |0 | | | | |na | |
-P66 | | |VCCINT | | | | | | | |2.5 | |
-P67 | |IOB | |UNUSED | |(0,5)*** | | | | | | |
-P68 | |IOB | |UNUSED | |(0,5)*** | | | | | | |
-P69 | |IOB | |UNUSED | |(0,5)*** | | | | | | |
-P70 | |IOB | |UNUSED | |(0,5)*** | | | | | | |
-P71 |led |IOB | |OUTPUT |LVTTL |(0,5)*** |12 |SLOW |NONE** | | |LOCATED |
-P72 | | |GND | | | | | | | | | |
-P73 | |IOB |IO_VREF_5 |UNUSED | |(0,5)*** | | | | | | |
-P74 | |IOB | |UNUSED | |(0,5)*** | | | | | | |
-P75 | |IOB | |UNUSED | |(0,5)*** | | | | | | |
-P76 | | |VCCINT | | | | | | | |2.5 | |
-P77 |btn |GCLKIOB |GCK1 |INPUT |LVTTL |(0,5)*** | | | | | |LOCATED |
-P78 | | |VCCO | | |0 | | | | |na | |
-P79 | | |GND | | | | | | | | | |
-P80 | |GCLKIOB |GCK0 |UNUSED | |(0,4)*** | | | | | | |
-P81 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P82 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P83 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P84 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | |
-P85 | | |GND | | | | | | | | | |
-P86 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P87 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P88 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P89 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P90 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P91 | | |VCCINT | | | | | | | |2.5 | |
-P92 | | |VCCO | | |0 | | | | |na | |
-P93 | | |GND | | | | | | | | | |
-P94 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P95 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | |
-P96 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P97 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P98 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | |
-P99 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P100 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | |
-P101 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P102 | |IOB | |UNUSED | |(0,4)*** | | | | | | |
-P103 | | |GND | | | | | | | | | |
-P104 | | |DONE | | | | | | | | | |
-P105 | | |VCCO | | |0 | | | | |na | |
-P106 | | |PROGRAM | | | | | | | | | |
-P107 | |IOB |IO_INIT |UNUSED | |(0,3)*** | | | | | | |
-P108 | |IOB |IO_D7 |UNUSED | |(0,3)*** | | | | | | |
-P109 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | |
-P110 | |IOB | |UNUSED | |(0,3)*** | | | | | | |
-P111 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | |
-P112 | |IOB | |UNUSED | |(0,3)*** | | | | | | |
-P113 | |IOB | |UNUSED | |(0,3)*** | | | | | | |
-P114 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | |
-P115 | |IOB |IO_D6 |UNUSED | |(0,3)*** | | | | | | |
-P116 | | |GND | | | | | | | | | |
-P117 | | |VCCO | | |0 | | | | |na | |
-P118 | | |VCCINT | | | | | | | |2.5 | |
-P119 | |IOB |IO_D5 |UNUSED | |(0,3)*** | | | | | | |
-P120 | |IOB | |UNUSED | |(0,3)*** | | | | | | |
-P121 | |IOB | |UNUSED | |(0,3)*** | | | | | | |
-P122 | |IOB | |UNUSED | |(0,3)*** | | | | | | |
-P123 | |IOB | |UNUSED | |(0,3)*** | | | | | | |
-P124 | | |GND | | | | | | | | | |
-P125 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | |
-P126 | |IOB |IO_D4 |UNUSED | |(0,3)*** | | | | | | |
-P127 | |IOB | |UNUSED | |(0,3)*** | | | | | | |
-P128 | | |VCCINT | | | | | | | |2.5 | |
-P129 | |PCIIOB |IO_TRDY |UNUSED | |(0,3)*** | | | | | | |
-P130 | | |VCCO | | |0 | | | | |na | |
-P131 | | |GND | | | | | | | | | |
-P132 | |PCIIOB |IO_IRDY |UNUSED | |(0,2)*** | | | | | | |
-P133 | |IOB | |UNUSED | |(0,2)*** | | | | | | |
-P134 | |IOB | |UNUSED | |(0,2)*** | | | | | | |
-P135 | |IOB |IO_D3 |UNUSED | |(0,2)*** | | | | | | |
-P136 | |IOB |IO_VREF_2 |UNUSED | |(0,2)*** | | | | | | |
-P137 | | |GND | | | | | | | | | |
-P138 | |IOB | |UNUSED | |(0,2)*** | | | | | | |
-P139 | |IOB | |UNUSED | |(0,2)*** | | | | | | |
-P140 | |IOB | |UNUSED | |(0,2)*** | | | | | | |
-P141 | |IOB | |UNUSED | |(0,2)*** | | | | | | |
-P142 | |IOB |IO_D2 |UNUSED | |(0,2)*** | | | | | | |
-P143 | | |VCCINT | | | | | | | |2.5 | |
-P144 | | |VCCO | | |0 | | | | |na | |
-P145 | | |GND | | | | | | | | | |
-P146 | |IOB |IO_D1 |UNUSED | |(0,2)*** | | | | | | |
-P147 | |IOB |IO_VREF_2 |UNUSED | |(0,2)*** | | | | | | |
-P148 | |IOB | |UNUSED | |(0,2)*** | | | | | | |
-P149 | |IOB | |UNUSED | |(0,2)*** | | | | | | |
-P150 | |IOB |IO_VREF_2 |UNUSED | |(0,2)*** | | | | | | |
-P151 | |IOB | |UNUSED | |(0,2)*** | | | | | | |
-P152 | |IOB |IO_VREF_2 |UNUSED | |(0,2)*** | | | | | | |
-P153 | |IOB |IO_DIN_D0 |UNUSED | |(0,2)*** | | | | | | |
-P154 | |IOB |IO_DOUT_BUSY|UNUSED | |(0,2)*** | | | | | | |
-P155 | | |CCLK | | | | | | | | | |
-P156 | | |VCCO | | |0 | | | | |na | |
-P157 | | |TDO | | | | | | | | | |
-P158 | | |GND | | | | | | | | | |
-P159 | | |TDI | | | | | | | | | |
-P160 | |IOB |IO_CS |UNUSED | |(0,1)*** | | | | | | |
-P161 | |IOB |IO_WRITE |UNUSED | |(0,1)*** | | | | | | |
-P162 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | |
-P163 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P164 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | |
-P165 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P166 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P167 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | |
-P168 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P169 | | |GND | | | | | | | | | |
-P170 | | |VCCO | | |0 | | | | |na | |
-P171 | | |VCCINT | | | | | | | |2.5 | |
-P172 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P173 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P174 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P175 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P176 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P177 | | |GND | | | | | | | | | |
-P178 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | |
-P179 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P180 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P181 | |IOB | |UNUSED | |(0,1)*** | | | | | | |
-P182 | |GCLKIOB |GCK2 |UNUSED | |(0,1)*** | | | | | | |
-P183 | | |GND | | | | | | | | | |
-P184 | | |VCCO | | |0 | | | | |na | |
-P185 | |GCLKIOB |GCK3 |UNUSED | |0 | | | | | | |
-P186 | | |VCCINT | | | | | | | |2.5 | |
-P187 | |IOB | |UNUSED | |0 | | | | | | |
-P188 | |IOB | |UNUSED | |0 | | | | | | |
-P189 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | |
-P190 | | |GND | | | | | | | | | |
-P191 | |IOB | |UNUSED | |0 | | | | | | |
-P192 | |IOB | |UNUSED | |0 | | | | | | |
-P193 | |IOB | |UNUSED | |0 | | | | | | |
-P194 | |IOB | |UNUSED | |0 | | | | | | |
-P195 | |IOB | |UNUSED | |0 | | | | | | |
-P196 | | |VCCINT | | | | | | | |2.5 | |
-P197 | | |VCCO | | |0 | | | | |na | |
-P198 | | |GND | | | | | | | | | |
-P199 | |IOB | |UNUSED | |0 | | | | | | |
-P200 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | |
-P201 | |IOB | |UNUSED | |0 | | | | | | |
-P202 | |IOB | |UNUSED | |0 | | | | | | |
-P203 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | |
-P204 | |IOB | |UNUSED | |0 | | | | | | |
-P205 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | |
-P206 | |IOB | |UNUSED | |0 | | | | | | |
-P207 | | |TCK | | | | | | | | | |
-P208 | | |VCCO | | |0 | | | | |na | |
-
------ |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |
-
-* Default value.
-** This default Pullup/Pulldown value can be overridden in Bitgen.
-*** In some smaller packages, the VCCO bank number of a pin may trail
- the VREF bank number (VCCO,VREF).
-
Index: demos/projects/BtnDemo/btndemo.cmd_log
===================================================================
--- demos/projects/BtnDemo/btndemo.cmd_log (revision 430)
+++ demos/projects/BtnDemo/btndemo.cmd_log (nonexistent)
@@ -1,25 +0,0 @@
-xst -quiet -ifn __projnav/btndemo.xst -ofn btndemo.syr
-ngdbuild -quiet -dd f:\engineering\projects\web5.1\d2\btndemo/_ngo -uc btndemo.ucf -insert_keep_hierarchy -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd
-map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf
-par -w -ol 2 -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf
-trce -quiet -e 3 -l 3 -xml btndemo btndemo.ncd -o btndemo.twr btndemo.pcf
-bitgen -f btndemo.ut btndemo.ncd
-bitgen -f btndemo.ut btndemo.ncd
-xst -quiet -ifn __projnav/btndemo.xst -ofn btndemo.syr
-ngdbuild -quiet -dd e:\engineering\projects\web5.1\d2\btndemo/_ngo -uc btndemo.ucf -insert_keep_hierarchy -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd
-map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf
-par -w -ol 2 -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf
-trce -quiet -e 3 -l 3 -xml btndemo btndemo.ncd -o btndemo.twr btndemo.pcf
-bitgen -f btndemo.ut btndemo.ncd
-xst -intstyle ise -ifn __projnav/btndemo.xst -ofn btndemo.syr
-ngdbuild -intstyle ise -dd x:\barron\config\d2\basic\btndemo/_ngo -uc btndemo.ucf -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd
-map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf
-par -w -intstyle ise -ol std -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf
-trce -intstyle ise -e 3 -l 3 -xml btndemo btndemo.ncd -o btndemo.twr btndemo.pcf
-bitgen -intstyle ise -f btndemo.ut btndemo.ncd
-xst -intstyle ise -ifn __projnav/btndemo.xst -ofn btndemo.syr
-ngdbuild -intstyle ise -dd x:\barron\config\d2\basic\btndemo/_ngo -uc btndemo.ucf -p xc2s200-pq208-5 btndemo.ngc btndemo.ngd
-map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o btndemo_map.ncd btndemo.ngd btndemo.pcf
-par -w -intstyle ise -ol std -t 1 btndemo_map.ncd btndemo.ncd btndemo.pcf
-trce -intstyle ise -e 3 -l 3 -xml btndemo btndemo.ncd -o btndemo.twr btndemo.pcf
-bitgen -intstyle ise -f btndemo.ut btndemo.ncd