OpenCores
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    /phr/trunk/doc/financiamiento
    from Rev 107 to Rev 109
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Rev 107 → Rev 109

/adec/informes/manual_usuario/PHR_manual.vrs
0,0 → 1,4
\relax
\vrslabel{versionsnummer}{{1}{1}}
\vrslabel{versionsnummertio}{{0}{1}}
\vrslabel{versionsnummerhundra}{{0}{1}}
/adec/informes/manual_usuario/PHR_manual.aux
0,0 → 1,9
\relax
\catcode`"\active
\catcode`<\active
\catcode`>\active
\@nameuse{es@quoting}
\select@language{spanish}
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\@writefile{lof}{\select@language{spanish}}
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/adec/informes/manual_usuario/PHR_manual.tex
0,0 → 1,25
\documentclass[a4paper]{report}
%-- Package
\usepackage[utf8]{inputenc}
\usepackage[spanish]{babel}
\usepackage[a4paper]{geometry}
\usepackage[pdftex]{graphicx}
\usepackage{fancyhdr}
\usepackage{listings}
\usepackage{textcomp}
\usepackage{cclicenses}
 
%-- Título, autores, etc.
\title{Manual de Usuario \\ \textbf{\textsc{Plataforma de Hardware Configurable}}}
\author{Luis Alberto Guanuco\thanks{Tesista -- Centro Universitario de Desarrollo en Automación y Robótica (CUDAR)}\\
Sergio Daniel Olmedo\thanks{Docente -- CUDAR}\\
Pablo Cayuela \thanks{Docente -- Laboratorio de Técnicas Digitales e Informática (LTDI)}}
\date{Octubre 2013\\\cc{}\ccby{}\ccsa{}}
 
 
\begin{document}
 
\maketitle{}
 
 
\end{document}
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adec/informes/manual_usuario/ref/estructura_del_manual.svg =================================================================== --- adec/informes/manual_usuario/ref/estructura_del_manual.svg (nonexistent) +++ adec/informes/manual_usuario/ref/estructura_del_manual.svg (revision 109) @@ -0,0 +1,473 @@ + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + Hardware + Software + + + + PHR + S3power + OOCDLink + Caracteristicas generales --> Diagrama 3d identificación de sus partes.Herramienta de software EDA --> KiCAD --> Acceder a los archivos del diseñoDispositivos PLDs (CPLD, FPGA) --> Características tecnológicas --> Sobre familia FPGA --> Recursos de la FPGA utilizadaAlimentación --> Características generales --> Especificaciones para la FPGA del fabricante (Xilinx Inc.) --> redes de capacitores de bypass y desacople --> Consejos de "ruteo" (PCB) --> Esquema de conexión en bloque (socket) --> esquemático y foto/3d.Componentes --> (Llaves,pulsadores,led, rs232,clks, etc). (por c/u)--> ubicación en placa (foto) --> características eléctrica --> esquemático --> conexión a puerto FPGA (siempre tabla) --> consejo de uso "sano"Puerto JTAG --> Descripción Eléctrica del protocolo JTAG --> Ubicación en placa (foto) --> esquemático --> Modos de configuración de la FPGA --> conexión a puerto FPGA (siempre tabla) --> consejo de uso "sano" + Introducción + Caracteristicas HW/SWDiagramas en bloquesLicencias Libres/Abiertas + Apéndice + Esquemáticosarchivo/s UCF de la placa PHRscripts de OpenOCD y xc3sprogDirectorio de proyeecto (repo. SVN) + + Index: adec/informes/manual_usuario/Makefile =================================================================== --- adec/informes/manual_usuario/Makefile (nonexistent) +++ adec/informes/manual_usuario/Makefile (revision 109) @@ -0,0 +1,10 @@ +PHR_manual.pdf: PHR_manual.tex + pdflatex $^ + pdflatex $^ + evince PHR_manual.pdf & + + +clean: + rm PHR_manual.pdf + rm PHR_manual.log + rm PHR_manual.aux
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