OpenCores
URL https://opencores.org/ocsvn/phr/phr/trunk

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    /phr/trunk/doc/financiamiento
    from Rev 109 to Rev 111
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Rev 109 → Rev 111

/adec/informes/manual_usuario/ref/estructura_del_manual.svg
115,6 → 115,62
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y="121.94328"
id="tspan3172"> --&gt; Diagrama 3d identificación de sus partes.</tspan><tspan
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id="tspan3234">Herramienta de software EDA</tspan><tspan
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id="tspan3285"> --&gt; KiCAD</tspan><tspan
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y="195.74223"
id="tspan3289"> --&gt; Acceder a los archivos del diseño</tspan><tspan
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y="214.19197"
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id="tspan3260"> --&gt; Características tecnológicas</tspan><tspan
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y="269.54117"
id="tspan3262"> --&gt; Sobre familia FPGA</tspan><tspan
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y="287.99091"
id="tspan3268"> --&gt; Recursos de la FPGA utilizada</tspan><tspan
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y="306.44064"
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id="tspan3301"> --&gt; Características generales</tspan><tspan
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id="tspan3287"> --&gt; Especificaciones para la FPGA del fabricante (Xilinx Inc.)</tspan><tspan
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id="tspan3291"> --&gt; redes de capacitores de bypass y desacople</tspan><tspan
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x="256.83859"
y="398.68933"
id="tspan3305"> --&gt; Consejos de &quot;ruteo&quot; (PCB)</tspan><tspan
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x="256.83859"
y="417.1391"
id="tspan3309"> --&gt; Esquema de conexión en bloque (socket)</tspan><tspan
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y="435.58884"
id="tspan3323"> --&gt; esquemático y foto/3d.</tspan><tspan
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id="tspan3184"> (por c/u)--&gt; ubicación en placa (foto)</tspan><tspan
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id="tspan3186"> --&gt; características eléctrica</tspan><tspan
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id="tspan3194"> --&gt; esquemático</tspan><tspan
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y="564.737"
id="tspan3188"> --&gt; conexión a puerto FPGA (siempre tabla)</tspan><tspan
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id="tspan3214"> --&gt; consejo de uso &quot;sano&quot;</tspan><tspan
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id="tspan3252"> --&gt; Ubicación en placa (foto)</tspan><tspan
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y="675.43542"
id="tspan3256"> --&gt; esquemático</tspan><tspan
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id="tspan3345"> --&gt; Modos de configuración de la FPGA</tspan><tspan
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id="tspan3351"> --&gt; conexión a puerto FPGA (siempre tabla)</tspan><tspan
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x="256.83859"
y="730.78461"
id="tspan3258"> --&gt; consejo de uso &quot;sano&quot;</tspan><tspan
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id="tspan2926-9-63">Esquemáticos</tspan><tspan
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y="1019.8459"
id="tspan3380">archivo/s UCF de la placa PHR</tspan><tspan
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id="tspan3386">scripts de OpenOCD y xc3sprog</tspan><tspan
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id="tspan3390">Directorio de proyeecto (repo. SVN)</tspan><tspan
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x="256.83859"
sodipodi:role="line"> --&gt; Diagrama 3d identificación de sus partes.</tspan><tspan
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y="140.39302"
x="256.83859"
sodipodi:role="line" /><tspan
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sodipodi:role="line">Dispositivos PLDs (CPLD, FPGA)</tspan><tspan
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y="177.2925"
x="256.83859"
sodipodi:role="line"> --&gt; Características tecnológicas</tspan><tspan
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y="195.74223"
x="256.83859"
sodipodi:role="line"> --&gt; Sobre familia FPGA</tspan><tspan
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x="256.83859"
sodipodi:role="line"> --&gt; Recursos de la FPGA utilizada</tspan><tspan
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x="256.83859"
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sodipodi:role="line">Alimentación</tspan><tspan
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x="256.83859"
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y="287.99091"
x="256.83859"
sodipodi:role="line"> --&gt; Especificaciones para la FPGA del fabricante (Xilinx Inc.)</tspan><tspan
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y="306.44064"
x="256.83859"
sodipodi:role="line"> --&gt; redes de capacitores de bypass y desacople</tspan><tspan
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y="324.89038"
x="256.83859"
sodipodi:role="line"> --&gt; Consejos de &quot;ruteo&quot; (PCB)</tspan><tspan
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y="343.34012"
x="256.83859"
sodipodi:role="line"> --&gt; Esquema de conexión en bloque (socket)</tspan><tspan
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y="361.78986"
x="256.83859"
sodipodi:role="line"> --&gt; esquemático y foto/3d.</tspan><tspan
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y="380.23959"
x="256.83859"
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sodipodi:role="line">Componentes</tspan><tspan
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x="256.83859"
sodipodi:role="line"> --&gt; (Llaves,pulsadores,led, rs232,clks, etc).</tspan><tspan
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x="256.83859"
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x="256.83859"
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sodipodi:role="line"> --&gt; esquemático</tspan><tspan
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x="256.83859"
sodipodi:role="line"> --&gt; conexión a puerto FPGA (siempre tabla)</tspan><tspan
id="tspan3214"
y="509.38779"
x="256.83859"
sodipodi:role="line"> --&gt; consejo de uso &quot;sano&quot;</tspan><tspan
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y="527.83752"
x="256.83859"
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sodipodi:role="line">Puerto JTAG</tspan><tspan
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x="256.83859"
sodipodi:role="line"> --&gt; Descripción Eléctrica del protocolo JTAG</tspan><tspan
id="tspan3252"
y="583.18671"
x="256.83859"
sodipodi:role="line"> --&gt; Ubicación en placa (foto)</tspan><tspan
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y="601.63647"
x="256.83859"
sodipodi:role="line"> --&gt; esquemático</tspan><tspan
id="tspan3345"
y="620.08618"
x="256.83859"
sodipodi:role="line"> --&gt; Modos de configuración de la FPGA</tspan><tspan
id="tspan3351"
y="638.53595"
x="256.83859"
sodipodi:role="line"> --&gt; conexión a puerto FPGA (siempre tabla)</tspan><tspan
id="tspan3258"
y="656.98566"
x="256.83859"
sodipodi:role="line"> --&gt; consejo de uso &quot;sano&quot;</tspan><tspan
id="tspan3246"
y="675.43542"
x="256.83859"
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x="256.83859"
sodipodi:role="line" /><tspan
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xml:space="preserve"><tspan
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x="802.85846"
sodipodi:role="line"> --&gt; Función de la placa</tspan><tspan
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sodipodi:role="line"> --&gt; UTIC - INTI</tspan><tspan
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sodipodi:role="line" /><tspan
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sodipodi:role="line">Dispositivo central TPS75300</tspan><tspan
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sodipodi:role="line"> --&gt; Características</tspan><tspan
id="tspan3287-2"
y="214.19197"
x="802.85846"
sodipodi:role="line"> --&gt; Especificaciones referidas a la familia spartan3 (por TI)</tspan><tspan
id="tspan3305-2"
y="232.64171"
x="802.85846"
sodipodi:role="line"> --&gt; Consejos de &quot;ruteo&quot; (PCB)</tspan><tspan
id="tspan3912"
y="251.09145"
x="802.85846"
sodipodi:role="line" /><tspan
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sodipodi:role="line">Descripción componentes de la placa placa</tspan><tspan
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y="287.99091"
x="802.85846"
sodipodi:role="line"> --&gt; ubicación en placa (foto)</tspan><tspan
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y="306.44064"
x="802.85846"
sodipodi:role="line"> --&gt; características eléctrica</tspan><tspan
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y="324.89038"
x="802.85846"
sodipodi:role="line"> --&gt; esquemático</tspan><tspan
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y="343.34012"
x="802.85846"
sodipodi:role="line" /><tspan
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sodipodi:role="line">Manipulación de la placa y conexiones</tspan><tspan
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sodipodi:role="line" /><tspan
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sodipodi:role="line">Consejo de uso &quot;sano&quot;</tspan><tspan
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sodipodi:role="line"
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y="121.94328"
id="tspan3589"> --&gt; SMD</tspan><tspan
sodipodi:role="line"
x="-49.122669"
y="140.39302"
id="tspan3591"> --&gt; PCB</tspan><tspan
sodipodi:role="line"
x="-49.122669"
y="158.84276"
id="tspan3602"></tspan><tspan
sodipodi:role="line"
x="-49.122669"
y="177.2925"
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sodipodi:role="line"
x="-49.122669"
y="195.74223"
id="tspan3604"> --&gt; KiCAD</tspan><tspan
sodipodi:role="line"
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sodipodi:role="line"
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sodipodi:role="line"
x="1268.3159"
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sodipodi:role="line"
x="1268.3159"
y="158.84276"
id="tspan3262-8"> --&gt; Características (arquitectura)</tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="177.2925"
id="tspan3902"> --&gt; Sobre protocolos seriales (principalmente JTAG)</tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="195.74223"
id="tspan3268-36"> --&gt; Referencia (por FTDI)</tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="214.19197"
id="tspan3178-3" /><tspan
sodipodi:role="line"
x="1268.3159"
y="232.64171"
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sodipodi:role="line"
x="1268.3159"
y="251.09145"
id="tspan3293-4"> --&gt; Alimentación</tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="269.54117"
id="tspan3942"> --&gt; Frecuencia de funcionamiento</tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="287.99091"
id="tspan3946"> --&gt; Puertos disponibles </tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="306.44064"
id="tspan3970"> --&gt; Puerto JTAG</tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="324.89038"
id="tspan3972"> --&gt; Descripción Eléctrica del protocolo JTAG</tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="343.34012"
id="tspan3184-7" /><tspan
sodipodi:role="line"
x="1268.3159"
y="361.78986"
id="tspan3974"> (por c/u)--&gt; ubicación en placa (foto)</tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="380.23959"
id="tspan3186-5"> --&gt; características eléctrica</tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="398.68933"
id="tspan3956"> --&gt; esquemático</tspan><tspan
sodipodi:role="line"
x="1268.3159"
y="417.1391"
id="tspan3960" /><tspan
sodipodi:role="line"
x="1268.3159"
y="435.58884"
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sodipodi:role="line"
x="1268.3159"
y="454.03857"
id="tspan3998" /><tspan
sodipodi:role="line"
x="1268.3159"
y="472.48831"
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x="-512.21716"
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x="2530.1853"
sodipodi:role="line">archivo/s UCF de la placa PHR</tspan><tspan
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y="157.94473"
x="2530.1853"
sodipodi:role="line">scripts de OpenOCD y xc3sprog</tspan><tspan
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y="184.61496"
x="2530.1853"
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y="211.28519"
x="2530.1853"
sodipodi:role="line">Licencia del repositorio (cuerto del documento GPL v3)</tspan><tspan
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x="2530.1853"
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sodipodi:role="line">Drivers placa OOCDLink</tspan></text>
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y="121.94328"
x="2122.2534"
sodipodi:role="line"> --&gt; libftdi (libre)</tspan><tspan
id="tspan4244"
y="140.39302"
x="2122.2534"
sodipodi:role="line"> --&gt; D2XX (privativo)</tspan><tspan
id="tspan4234"
y="158.84276"
x="2122.2534"
sodipodi:role="line" /><tspan
id="tspan4520"
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x="2122.2534"
sodipodi:role="line">Instalar drivers (libftdi)</tspan><tspan
id="tspan4210"
y="195.74223"
x="2122.2534"
sodipodi:role="line"> --&gt; SO GNU/Linux</tspan><tspan
id="tspan4220"
y="214.19197"
x="2122.2534"
sodipodi:role="line"> --&gt; SO Windows</tspan><tspan
id="tspan3283-5-1"
y="232.64171"
x="2122.2534"
sodipodi:role="line"> --&gt; SO OSX </tspan><tspan
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x="2122.2534"
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id="tspan3283-5-1-5">(para c/u) --&gt; Características</tspan><tspan
sodipodi:role="line"
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y="140.39302"
id="tspan5059"> --&gt; dispositivos soportados</tspan><tspan
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x="2417.5278"
y="158.84276"
id="tspan5061"> --&gt; requerimientos </tspan><tspan
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x="2417.5278"
y="177.2925"
id="tspan5063"> --&gt; limitaciones</tspan><tspan
sodipodi:role="line"
x="2417.5278"
y="195.74223"
id="tspan5055"> --&gt; Instalación</tspan><tspan
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y="232.64171"
id="tspan5049"> --&gt; SO Windows</tspan><tspan
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y="251.09145"
id="tspan5065"> --&gt; Generación de scripts</tspan><tspan
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id="tspan5067"> --&gt; ejemplos</tspan><tspan
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id="tspan5069" /><tspan
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y="324.89038"
id="tspan5079"> --&gt; Directorio y archivos para la placa PHR</tspan><tspan
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y="343.34012"
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