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/chapter2.tex
1,8 → 1,9
%*****************************************************************************************
m%*****************************************************************************************
%*********************************** Second Chapter **************************************
%*****************************************************************************************
 
\chapter{Fundamentos y Planteamiento del Desarrollo}
\chapter{Fundamentos Básicos}
\label{chap:fundamentos}
 
\ifpdf
\graphicspath{{Chapter2/Figs/Raster/}{Chapter2/Figs/PDF/}{Chapter2/Figs/}}
10,10 → 11,12
\graphicspath{{Chapter2/Figs/Vector/}{Chapter2/Figs/}}
\fi
 
%La \emph{electrónica} ha revolucionado del siglo XX y sigue siendo un impacto en el siglo XXI. El nacimiento y subsecuente crecimiento de la industria de la computación, la creación del teléfono móvil y la \emph{digitalización} de los servicios de televisión y radio son ejemplos de grandes logros tecnológicos que la electrónica ha ofrecido. En las décadas de 1970 y 1980, los sistemas electrónicos se encontraban compuestos de componentes estándares como microprocesadores y varios circuitos integrados (\textsl{Integrated Circuits}, ICs), todo esto sobre una placa de circuitos impresos (\textsl{Print Circuit Boards}, PCBs. Como el nivel de integración creció, el proceso de fabricación de los PCBs se convirtió cada vez más complejo. Esto se debió al incremento de transistores y pines de entrada/salida que implicó el uso de placas multi-capas, logrando desarrollar placas con hasta 20 capas. Así, la probabilidad de conexiones de componentes en forma incorrecta aumentó, particularmente la posibilidad de diseñar con éxitos y probar un sistema en forma funcional antes de ingresar a un proceso de producción.
 
\section{Dispositivos Lógicos Programables}
\label{sec:pld}
\label{sec:fund-pld}
 
Los \emph{Dispositivos Lógicos Programables} (PLDs) fueron introducidos a medidos de 1970s. La idea era construir circuitos lógicos combinacionales que fueran \emph{programables}. Contrariamente a los microprocesadores, los cuales pueden \emph{correr} un programa sobre un hardware \emph{fijo}, la programabilidad de los PLDs hace referencia a niveles de \emph{hardware}. En otras palabras. un PLD es un chip de \emph{propósitos generales} cuyo \emph{hardware} puede ser reconfigurado dependiendo de especificaciones particulares del programador.
Los \emph{Dispositivos Lógicos Programables} (PLDs) fueron introducidos a medidos de 1970s. La idea era construir circuitos lógicos combinacionales que fueran \emph{programables}. Contrariamente a los microprocesadores, los cuales pueden \emph{correr} un programa sobre un hardware \emph{fijo}, la programabilidad de los PLDs hace referencia a niveles de \emph{hardware}. En otras palabras, un PLD es un chip de \emph{propósitos generales} cuyo \emph{hardware} puede ser reconfigurado dependiendo de especificaciones particulares del programador.
 
EL primer PLD se llamaba PAL (\textsl{Programmable Array Logic}). Estos dispositivos disponían solo de compuertas lógicas (no tenían flip-flop), por lo que solo permitía la implementación de circuitos \emph{combinacionales}. Para salvar este problema, Los \emph{\textsl{registered}} PLDs fueron lanzados pocos después, los cuales incluían un flip-flop por cada salida del circuito. Con esta versión de los PAL, se podría implementar funciones \emph{secuenciales} simples.
 
29,26 → 32,174
 
\begin{table}[h]
\centering
\begin{tabular}[h]{|c | l l|}
\begin{tabular}[h]{|c|ll|}
\hline
\multirow{5}{*}{PLDs} & \multirow{3}{*}{Sample PLD (SPLD)} & \multicolumn{1}{|l|}{PAL} \\
& \multicolumn{1}{|l|}{}& Registered PAL \\
& \multicolumn{1}{|l|}{}& GAL \\ \cline{2-3}
& Complex PLD (CPLD) & \\ \cline{2-3}
& FPGA & \\
& & \multicolumn{1}{|l|}{Registered PAL} \\
& & \multicolumn{1}{|l|}{GAL} \\ \cline{2-3}
& Complex PLD (CPLD) & \\ \cline{2-3}
& FPGA & \\
\hline
\end{tabular}
\caption{Evolución de los PLDs}
\caption{Evolución de los PLDs.}
\label{tab:evo-plds}
\end{table}
 
Por último, todos los PLDs (\textsl{simple} o \textsl{complex}) son no volátiles. Estos puede ser OTP (\textsl{One-Time Programmable}), en la que pequeños fusibles electrónicos son usados para la reprogramación, de igual forma que las EEPROM o memorias Flash. Las FPGAs, por otra lado, son en su mayoría volátiles. Para estas últimas se deben usar dispositivos externos para cargar las conexiones.
 
Actualmente los dispositivos más utilizados son los CPLDs y FPGAs. De estas dos tecnología, se optó por trabajar con las FPGAs pues, como bien se dijo antes, cuentan con mayor recursos de \textsl{hardware} que los CPLDs. Lo que permitirá dar un mayor margen a los desarrollos digitales que se quieran implementar. Se detallará con mayor profundidad la tecnología y estructura de las FPGAs.
%Actualmente los dispositivos más utilizados son los CPLDs y FPGAs. De estas dos tecnología, se optó por trabajar con las FPGAs pues, como bien se dijo antes, cuentan con mayor recursos de \textsl{hardware} que los CPLDs. Lo que permitirá dar un mayor margen a los desarrollos digitales que se quieran implementar. Se detallará con mayor profundidad la tecnología y estructura de las FPGAs.
 
\subsection{FPGAs}
\label{sec:pld-fpga}
\section{SPLDs}
\label{sec:fund-pld-spld}
 
Como se mencionó anteriormente, los dispositivos PAL, PLA y GAL se clasifican como los \textsl{Simple} PLD (SPLDs). Una descripción de las arquitecturas de cada uno de estos dispositivos se presenta a continuación.
 
\subsection{PALs}
\label{sec:fund-pld-spld-pal}
 
Los \textsl{Programmable Array Logic} (PAL) son introducidos por Monolithic Memories Inc. a mediados de 1970. Su arquitectura básica se ilustra en la Figura \ref{fig:pal-arch}, donde se representa con un pequeño círculo las conexiones programables. Como puede verse, el circuito esta compuesto de un arreglo de compuertas AND \emph{programables}, seguido por un arreglo \emph{fijo} de compuertas OR.
 
La implementación de la Figura \ref{fig:pal-arch} se basa en que cualquier función combinacional puede ser representada como una Suma de Productos (SOP); es decir, si $a_1$, $a_2$, $\cdots$, $a_N$ son las entradas lógicas, entonces cualquier salida combinacional $x$ puede ser compuesta como
\begin{equation}
\label{eq:sop}
x = m_1 + m_2 + \cdots + m_M \text{ ,}
\end{equation}
donde $m_i = f_1\left(a_1,a_2,\cdots,a_N\right)$ son los términos mínimos de la función $x$. Por ejemplo
\begin{equation}
\label{eq:sop-2}
x = a_1\bar{a}_2 + a_2a_3\bar{a}_4 + \bar{a}_1\bar{a}_2a_3a_4\bar{a}_5
\end{equation}
 
Por lo tanto, el producto (términos mínimos) puede ser obtenido por medio de las compuertas AND, cuya salidas están conectadas a una compuerta OR para calcular su suma.
 
\begin{figure}
\centering
\includegraphics[width=0.5\textwidth]{PAL}
\caption{Arquitectura básica de una PAL.}
\label{fig:pal-arch}
\end{figure}
 
La principal limitación de esta arquitectura es el hecho de que solo permite la implementación de funciones combinacionales solamente. Para solucionar este problema, las \textsl{registered} PALs fueron lanzadas a fines de la década de 1970s. Estas incluían un flip-flop en cada salida (luego de la compuerta OR en la Figura \ref{fig:pal-arch}), de esta manera permitió la implementación de funciones secuenciales (aunque muy simples).
 
La primeras tecnologías empleadas en la fabricación de los dispositivos PALs fue bipolar, con una tensión de alimentación de 5V y un consumo de corriente al rededor de 200mA. La máxima frecuencia rondaba los 100Mhz, y las celdas programables eran de PROM (\textsl{fuse links}) o EPROM (con un tiemp de borrado de 20min. UV).
 
\subsection{PLAs}
\label{sec:fund-pld-spld-pla}
 
Los PLA (\textsl{Programmable Logic Array}) fueron introducidos a mediados de 1970s (por Signetics Inc.). La arquitectura básica de un PLA se ilustra simbólicamente en la Figura \ref{fig:pla-arch}. Si comparamos esta arquitectura con la Figura \ref{fig:pal-arch}, se observa que la única diferencia fundamental entre estos es que mientras una PAL tiene compuertas AND programables y otras compuertas OR fijas, en el caso de las PLA \emph{ambas} (las compuertas AND y OR) son programables. De esta manera se logra una ventaja en la flexibilidad del diseño. Sin embargo, se presentan elevados tiempos de retardos en los nodos de conexión internos que reducen la velocidad de funcionamiento del circuito.
 
\begin{figure}
\centering
\includegraphics[width=0.6\textwidth]{PLA}
\caption{Arquitectura básica de una PLA.}
\label{fig:pla-arch}
\end{figure}
 
La tecnología que se empleó en la fabricación de las PLAs fue la misma que en el caso de las PALs. Aunque las PLAs se encuentran obsoletas actualmente, estos han reaparecido como parte de las arquitecturas de las primeras familias de los CPLDs de baja potencia, como por ejemplo la familia de los \emph{CoolRunner} (de Xilinx Inc.).
 
\subsection{GALs}
\label{sec:fund-pld-spld-gal}
 
La arquitectura de las GAL (\textsl{Generic} PAL) fueron introducidas por Lattice Inc. en los comienzos de 1980s. Este contenía varias mejoras sobre los primeros dispositivos PALs:
\begin{enumerate}
\item Se construyeron sealidas más sofisticadas de las celdas (\emph{Macrocell}), las que incluían, además de flip-flop, varias compuertas y multiplexores.
\item Las Macrocell eran programables, permitiendo varios modos de operación.
\item Una señal de ``retorno'' desde la salida a la Marocell al arreglo reprogramable se incluyó, confiriendo al circuito mayor versatilidad.
\item Se utilizaron EEPROM en lugar de la PROM o EPROM.
\end{enumerate}
Como se mencionó, la GAL es el único SPLD que todavía es fabricado en un encapsulado estándar. Además, éste también sirvió como parte en la construcción de la mayoría de los CPLDs.
 
La Figura \ref{fig:gal-arch} muestra un ejemplo de un dispositivo GAL, el GAL16V8. Este circuito cuenta con 16 entradas y 8 salidas, en un \textsl{package} de 20 pines. En cada salida hay una Macrocell (luego de la compuerta OR), que contiene, además del flip-flop, compuertas lógicas y multiplexores. Las interconexiones programables son representadas por pequeños círculos. Una señal de realimentación desde la Macrocell al arreglo programable puede también ser observado. Notar que esta arquitectura se asemeja directamente a la de la PAL (Figura \ref{fig:pal-arch}), excepto por la presencia de una macrocell en cada salida y la señal de realimentación.
 
\begin{figure}
\centering
\includegraphics[width=0.9\textwidth]{GAL}
\caption{Dispositivo GAL 16V8.}
\label{fig:gal-arch}
\end{figure}
 
Actualmente los dispositivos GALs usan tecnología CMOS, alimentados a 3.3V, tecnología EEPROM o Flash, y alcanzan frecuencias máximas que rondan los 250Mhz. Varias compañías fabrican estos dispositivos (Lattice, Atmel, Texas Instruments, etc.).
 
\section{CPLDs}
\label{sec:fund-pld-cpld}
 
La estructura fundamental en la arquitectura de los CPLDs se ilustra en la Figura \ref{fig:cpld-arch}. Como se puede ver, este consiste en varios PLDs (en general del tipo GAL) con una matriz de \textsl{switches} programables usadas para conectarlos todos juntos a al bloque de entrada y salida. Además, los CPLDs contiene normalmente otras características, como soporte JTAG e interfaz a otros estándares lógicos (1.8V, 2.5V, 5V, etc.).
 
\begin{figure}
\centering
\includegraphics[width=0.4\textwidth]{CPLD}
\caption{Arquitectura básica de un CPLD.}
\label{fig:cpld-arch}
\end{figure}
 
Son varias las compañías que fabrican CPLDs, entre las más reconocidas tenemos Xilinx, Altera, Lattice, Atmel, Cypress, etc. En las Tablas \ref{tab:char-cpld-xilinx} y \ref{tab:char-cpld-altera} se disponen de las características de dos CPLDs, Xilinx y Altera. Como puede verse, más ade 500 Macrocells y más de 10000 compuertas pueden encontrarse en estos dispositivos.
 
\begin{table}%[h]
\centering
{\footnotesize
\begin{tabular}[c]{|m{0.2\textwidth}|m{0.2\textwidth}|m{0.2\textwidth}|m{0.2\textwidth}|}%{|l|l|l|l|}
\hline
Familia & \textbf{XC9500 (XVm, XL)} & \textbf{CoolRunner XPLA3} & \textbf{CoolRunner II} \\
\hline
Macrocell & 36 -- 288 & 32 -- 512 & 32 -- 512 \\
\hline
\textsl{System gates} & 800 -- 6,400 & 750 -- 12,000 & 750 -- 12,000 \\
\hline
Pines I/O & 34 --192 & 36 -- 260 & 33 -- 270 \\
\hline
Frec. máxima interna & 222 Mhz & 213 Mhz & 350 Mhz \\
\hline
\multirow{2}{*}{\textsl{Building Block}} & GAL 54V18 (XV, XL) & Bloques PLA & Bloques PLA \\
& GAL 36V18 (--) & & \\
\hline
Voltaje & 2.5 V (XV), 3.3 V (XL), 5 V & 3.3 V & 1.8 V \\
\hline
Interconexiones & Flash & EEPROM & \\
\hline
Tecnología & 0.35 $\mu$ CMOS & 0.35 $\mu$ CMOS & 0.18 $\mu$ CMOS \\
\hline
Corriente estática & 11 -- 500 mA & < 0.1 mA & 22 $\mu$A -- 1 mA \\
\hline
\end{tabular}
} % END \footnotesize{} segmentation
\caption{Características de los CPLDs de Xilinx.}
\label{tab:char-cpld-xilinx}
\end{table}
 
\begin{table}%[h]
\centering
{\footnotesize
\begin{tabular}[c]{|m{0.2\textwidth}|m{0.2\textwidth}|m{0.2\textwidth}|m{0.2\textwidth}|}%{|l|l|l|l|}
\hline
Familia & \textbf{MAX7000 (B, AE, S)} & \textbf{MAX3000 (A)} & \textbf{MAX II (G)} \\
\hline
\multirow{2}{*}{Macrocell /} & 32 -- 512 macrocells & 32 -- 512 macrocells & 192 -- 1,700 macrocells \\
LUTs & & & 240 -- 2,210 LUTs \\
\hline
\textsl{System gates} & 600 -- 10,000 & 600 -- 10,000 & \\
\hline
Pines I/O & 32 --512 & 34 -- 208 & 80 -- 272 \\
\hline
Frec. máxima interna & 303 Mhz & 227 Mhz & 304 Mhz \\
\hline
Voltaje & 2.5 V (B), 3.3 V (AE), 5 V (S) & 3.3 V & 1.8 V (G), 2.5 V, 3.3 V \\
\hline
Interconexiones & EEPROM & EEPROM & Flash + SRAM \\
\hline
\multirow{2}{*}{Tecnología} & 0.22 $\mu$ CMOS EEPROM & 0.3 $\mu$ & 0.18 $\mu$ \\
& 4 capas de metal (7000 B) & 4 capas de metal & 6 capas de metal \\
\hline
Corriente estática & 9 -- 450 mA & 9 -- 150 mA & 2 --50 mA \\
\hline
\end{tabular}
} % END \footnotesize{} segmentation
\caption{Características de los CPLDs de Altera.}
\label{tab:char-cpld-altera}
\end{table}
 
\section{FPGAs}
\label{sec:fund-pld-fpga}
 
Las FPGAs fueron introducidas al mercado por la empresa Xilinx Inc. a mediados de 1980s. Estos dispositivos se diferencian de los CPLDs en su arquitectura, tecnología de almacenamiento, funcionalidades integradas, y costo, y además están orientadas a la implementación de altos rendimientos y grandes tamaños en lo que se refiere a recursos de hardware.
 
La arquitectura básica de una FPGA se ilustra en la Figura \ref{fig:fpga-arch}. Esta consiste de una matriz de \emph{CLBs} (\textsl{Configurable Logic Blocks}), interconectados por un arreglo de matrices de conmutadores (\emph{\textsl{Switch Matrix}}). Para caracterizar con más detalle estos dispositivo se debe recurrir a la información de los fabricantes, donde además se puede disponer de un interfaz JTAG a diversos niveles lógicos, otra funcionalidad como memorias SRAM, multiplicadores de clock (PLL o DLL), interfaz PCI, etc. Algunos chips también incluyen bloques dedicados como multiplicadores, DPSs, y microprocesadores.
56,7 → 207,7
\begin{figure}
\centering
\includegraphics[width=0.4\textwidth]{fpga_arch}
\caption{Arquitectura básica de una FPGA}
\caption{Arquitectura básica de una FPGA.}
\label{fig:fpga-arch}
\end{figure}
 
73,14 → 224,14
\label{fig:pkg-fpga}
\end{figure}
 
Varias compañías fabrican FPGAs, como Xilinx., Actel, Altera, QuickLogic, Atmel, etc. Ejemplo de dos fabricantes (Xilinx y Actel) se disponen en las Tablas \ref{tab:char-xilinx} y \ref{tab:char-actel}. Como puede verse, estos dispositivos pueden contener miles de flip-flops y varios millones de compuertas lógicas.
Varias compañías fabrican FPGAs, como Xilinx., Actel, Altera, QuickLogic, Atmel, etc. Ejemplo de dos fabricantes (Xilinx y Actel) se disponen en las Tablas \ref{tab:char-fpga-xilinx} y \ref{tab:char-fpga-actel}. Como puede verse, estos dispositivos pueden contener miles de flip-flops y varios millones de compuertas lógicas.
 
\begin{table}[h]
\begin{table}%[h]
\centering
{\footnotesize
\begin{tabular}[c]{|m{0.1\textwidth}|m{0.1\textwidth}|m{0.1\textwidth}|m{0.1\textwidth}|m{0.1\textwidth}|m{0.1\textwidth}|m{0.1\textwidth}|m{0.1\textwidth}|}
\hline
Familia & Virtex II Pro & Virtex II & Virtex E & Virtex & Spartan 3 & Spartan IIE & Spartan II \\
Familia & \textbf{Virtex II Pro} & \textbf{Virtex II} & \textbf{Virtex E} & \textbf{Virtex} & \textbf{Spartan 3} & \textbf{Spartan IIE} & \textbf{Spartan II} \\
\hline
CLBs & 352 -- 11.024 & 64 -- 11.648 & 384 -- 16.224 & 384 -- 6.144 & 192 -- 8.320 & 384 -- 3.456 & 96 -- 1.176 \\
\hline
107,15 → 258,15
\end{tabular}
} % END \footnotesize{} segmentation
\caption{Características de FPGAs fabricadas por Xilinx.}
\label{tab:char-xilinx}
\label{tab:char-fpga-xilinx}
\end{table}
 
\begin{table}[h]
\begin{table}%[h]
\centering
{\footnotesize
\begin{tabular}[c]{|m{0.13\textwidth}|m{0.13\textwidth}|m{0.13\textwidth}|m{0.13\textwidth}|m{0.13\textwidth}|m{0.13\textwidth}|}
\hline
Familia & Accelerator & ProASIC & MX & SX & eX \\
Familia & \textbf{Accelerator} & \textbf{ProASIC} & \textbf{MX} & \textbf{SX} & \textbf{eX} \\
\hline
Módulos lógicos & 2.016 -- 32.256 & 5.376 -- 56.320 & 295 -- 2.438 & 768 -- 6.036 & 192 -- 768 \\
\hline
140,7 → 291,7
\end{tabular}
} % END \footnotesize{} segmentation
\caption{Características de FPGAs fabricadas por Actel.}
\label{tab:char-actel}
\label{tab:char-fpga-actel}
\end{table}
 
Nótese que todas las FPGAs de Xilinx usan SRAM para almacenar las interconexiones, por lo que son reprogramables, pero volátiles (es así que requieren de una ROM externa). en cambio, las FPGAs de Actel son no-volátiles (estos usan fusibles electrónicos), pero no son reprogramables (excepto una familia, la cual usa memoria \textsl{Flash}). Ya que cada enfoque tiene sus propias ventajas y desventajas, la aplicación real dictará cual arquitectura de chip es la apropiada.
158,26 → 309,36
\nomenclature[z-pci]{PCI}{\textsl{Peripheral Component Interconnect}}
\nomenclature[z-dsp]{DSP}{\textsl{Digital Signal Processor}}
 
\section{Ámbito de implementación}
\label{sec:amb-impl}
 
\subsection{Antecedentes}
\label{sec:amb-impl-antec}
\section{Lenguajes Descriptivos de \textsl{Hardware}}
\label{sec:fund-hdl}
 
\begin{landscape}
\section{Diseño de sistemas digitales}
\label{sec:fund-sist-digitales}
 
\section*{Subplots}
I can cite Wall-E (see Fig.~\ref{fig:WallE}) and Minions in despicable me (Fig.~\ref{fig:Minnion}) or I can cite the whole figure as Fig.~\ref{fig:animations}
\section{Influencia de la Programabilidad}
\label{sec:infl-program}
 
En muchos textos la ley de Moore es usada para destacar la evolución de la tecnología de silicio en la industria de los dispositivos semiconductores. Poro hay otro interesante punto de vista particularmente para los dispositivos PLDs, la \emph{onda de Makimoto} que fue publicada por primera vez en Enero de 1991 por la revista \textsl{Electronics Weekly}. Este concepto se basa en la observación de Tsugio Makimoto quién notó que la tecnología se desplazaba entre la \emph{estandarización} y la \emph{personalización} (véase la Figura xxxxx). En el comienzo de la década de 1960s, un número de componentes estándares fueron desarrollados, llamados series lógicas 7400 (por Texas Instruments). Dispositivos que servían para crear diversas aplicaciones digitales. Entrada la década de 1970s, la época de los dispositivos personalizados (LSI, siglas en inglés de \textsl{Low-Scape Integration}) comenzó a desarrollarse donde los chips eran creados para aplicaciones específicas como ser una calculadora. El chip fue incrementando su nivel de integración y así fue que nació el termino integración a media escala (MSI, siglas en inglés de \textsl{Medium-Scale Integration}). La evolución de los microprocesadores en la década de 1970s llevó a la estandarización de chips que fueran usados para un amplio rango de aplicaciones. Es entonces que en 1980s nació el ASIC (\textsl{Application-Specific Integrated Circuit}) donde el diseñador podría superar la limitación de la secuencialidad de los microprocesadores, quienes poseían varias limitaciones en aplicaciones en DSP (\textsl{Digital Signal Processing}) donde se requería un mayor nivel de cálculos.
 
\begin{figure}
\centering
\subfloat[A Tom and Jerry]{\label{fig:TomJerry}\includegraphics[width=0.3\textwidth]{TomandJerry}}
\subfloat[A Wall-E]{\label{fig:WallE}\includegraphics[width=0.3\textwidth]{WallE}}
\subfloat[A Minion]{\label{fig:Minnion}\includegraphics[width=0.3\textwidth]{minion}}
\caption{Best Animations}
\label{fig:animations}
\end{figure}
 
 
\end{landscape}
% Aquí se podría poner algo sobre el paper "The Role of the Laboratory in Undergraduate Engineering Education".
 
 
%\begin{landscape}
 
% \section*{Subplots}
% I can cite Wall-E (see Fig.~\ref{fig:WallE}) and Minions in despicable me (Fig.~\ref{fig:Minnion}) or I can cite the whole figure as Fig.~\ref{fig:animations}
 
% \begin{figure}
% \centering
% \subfloat[A Tom and Jerry]{\label{fig:TomJerry}\includegraphics[width=0.3\textwidth]{TomandJerry}}
% \subfloat[A Wall-E]{\label{fig:WallE}\includegraphics[width=0.3\textwidth]{WallE}}
% \subfloat[A Minion]{\label{fig:Minnion}\includegraphics[width=0.3\textwidth]{minion}}
% \caption{Best Animations}
% \label{fig:animations}
% \end{figure}
 
 
% \end{landscape}
/Figs/Raster/CPLD.svg
0,0 → 1,1925
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