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    from Rev 357 to Rev 358
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Rev 357 → Rev 358

/codigo/implementaciones/fft/vhdl/fft8/fft.vhd
0,0 → 1,145
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
 
entity fft is
generic (
BN : integer := 10);
Port (
sam0r : in signed (BN-1 downto 0);
sam1r : in signed (BN-1 downto 0);
sam2r : in signed (BN-1 downto 0);
sam3r : in signed (BN-1 downto 0);
sam4r : in signed (BN-1 downto 0);
sam5r : in signed (BN-1 downto 0);
sam6r : in signed (BN-1 downto 0);
sam7r : in signed (BN-1 downto 0);
-- sam0i : in signed (BN-1 downto 0);
-- sam1i : in signed (BN-1 downto 0);
-- sam2i : in signed (BN-1 downto 0);
-- sam3i : in signed (BN-1 downto 0);
-- sam4i : in signed (BN-1 downto 0);
-- sam5i : in signed (BN-1 downto 0);
-- sam6i : in signed (BN-1 downto 0);
-- sam7i : in signed (BN-1 downto 0);
fft0r : out signed (BN-1 downto 0);
fft1r : out signed (BN-1 downto 0);
fft2r : out signed (BN-1 downto 0);
fft3r : out signed (BN-1 downto 0);
fft4r : out signed (BN-1 downto 0);
fft5r : out signed (BN-1 downto 0);
fft6r : out signed (BN-1 downto 0);
fft7r : out signed (BN-1 downto 0);
fft0i : out signed (BN-1 downto 0);
fft1i : out signed (BN-1 downto 0);
fft2i : out signed (BN-1 downto 0);
fft3i : out signed (BN-1 downto 0);
fft4i : out signed (BN-1 downto 0);
fft5i : out signed (BN-1 downto 0);
fft6i : out signed (BN-1 downto 0);
fft7i : out signed (BN-1 downto 0));
end fft;
 
architecture Behavioral of fft is
 
type matrix is array (3 downto 0,7 downto 0) of signed (BN-1 downto 0);
signal fftr : matrix;
signal ffti : matrix;
COMPONENT butterfly
generic (
tweedle : integer := 7;
BN : integer := 10);
PORT(
i1r : IN signed (9 downto 0);
i1i : IN signed (9 downto 0);
i2r : IN signed (9 downto 0);
i2i : IN signed (9 downto 0);
o1r : OUT signed (9 downto 0);
o1i : OUT signed (9 downto 0);
o2r : OUT signed (9 downto 0);
o2i : OUT signed (9 downto 0)
);
END COMPONENT;
begin
 
fftr (0,0) <= sam0r;
fftr (0,1) <= sam4r;
fftr (0,2) <= sam2r;
fftr (0,3) <= sam6r;
fftr (0,4) <= sam1r;
fftr (0,5) <= sam5r;
fftr (0,6) <= sam3r;
fftr (0,7) <= sam7r;
ffti (0,0) <= to_signed (0, 10);
ffti (0,1) <= to_signed (0, 10);
ffti (0,2) <= to_signed (0, 10);
ffti (0,3) <= to_signed (0, 10);
ffti (0,4) <= to_signed (0, 10);
ffti (0,5) <= to_signed (0, 10);
ffti (0,6) <= to_signed (0, 10);
ffti (0,7) <= to_signed (0, 10);
fft0r <= fftr (3,0);
fft1r <= fftr (3,1);
fft2r <= fftr (3,2);
fft3r <= fftr (3,3);
fft4r <= fftr (3,4);
fft5r <= fftr (3,5);
fft6r <= fftr (3,6);
fft7r <= fftr (3,7);
fft0i <= ffti (3,0);
fft1i <= ffti (3,1);
fft2i <= ffti (3,2);
fft3i <= ffti (3,3);
fft4i <= ffti (3,4);
fft5i <= ffti (3,5);
fft6i <= ffti (3,6);
fft7i <= ffti (3,7);
 
primero : for nivel in 1 to 3 generate
begin
segundo : for i in 0 to 2**(nivel-1)-1 generate
begin
tercero: for j in 0 to 7 generate
begin
cuarto: if (j mod (2**nivel)) = 0 generate
begin
mariposa: butterfly
generic map (
tweedle => i*(2**(4-nivel-1)),
BN => BN
)
PORT MAP(
i1r => fftr (nivel-1, i+j),
i1i => ffti (nivel-1, i+j),
i2r => fftr (nivel-1, i+j+2**(nivel-1)),
i2i => ffti (nivel-1, i+j+2**(nivel-1)),
o1r => fftr (nivel, i+j),
o1i => ffti (nivel, i+j),
o2r => fftr (nivel, i+j+2**(nivel-1)),
o2i => ffti (nivel, i+j+2**(nivel-1))
);
end generate;
end generate;
end generate;
end generate;
 
 
end Behavioral;
 
/codigo/implementaciones/fft/vhdl/fft8/butterfly.vhd
0,0 → 1,88
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
--use work.common.all;
 
 
entity butterfly is
generic (
tweedle : integer := 7;
BN : integer := 10);
Port (
i1r : in signed (BN-1 downto 0);
i1i : in signed (BN-1 downto 0);
i2r : in signed (BN-1 downto 0);
i2i : in signed (BN-1 downto 0);
o1r : out signed (BN-1 downto 0);
o1i : out signed (BN-1 downto 0);
o2r : out signed (BN-1 downto 0);
o2i : out signed (BN-1 downto 0));
end butterfly;
 
architecture Behavioral of butterfly is
 
 
signal IntRes01 : signed (BN-1 downto 0);
signal IntRes02 : signed (BN-1 downto 0);
signal m01Sig : signed (2*BN-1 downto 0);
signal m02Sig : signed (2*BN-1 downto 0);
signal m03Sig : signed (2*BN-1 downto 0);
signal m04Sig : signed (2*BN-1 downto 0);
 
-- array con los valores de omega (tweedle factors)
type omega is array (7 downto 0) of signed (BN-1 downto 0);
signal omega_real : omega; -- Parte real de omega
signal omega_imag : omega; -- Parte real de omega
begin
 
m01Sig <= i2r * omega_real(tweedle) / 32;
m02Sig <= i2i * omega_imag(tweedle) / 32;
IntRes01 <= m01Sig(BN-1 downto 0) - m02Sig(BN-1 downto 0);
o1r <= i1r + IntRes01;
o2r <= i1r - IntRes01;
 
 
m03Sig <= i2i * omega_real(tweedle) / 32;
m04Sig <= i2r * omega_imag(tweedle) / 32;
IntRes02 <= m03Sig(BN-1 downto 0) + m04Sig(BN-1 downto 0);
o1i <= i1i + IntRes02;
o2i <= i1i - IntRes02;
omega_real(0) <= to_signed (32, 10);
omega_real(1) <= to_signed (23, 10);
omega_real(2) <= to_signed (0, 10);
omega_real(3) <= to_signed (-23, 10);
omega_real(4) <= to_signed (-32, 10);
omega_real(5) <= to_signed (-23, 10);
omega_real(6) <= to_signed (0, 10);
omega_real(7) <= to_signed (23, 10);
omega_imag(0) <= to_signed (0, 10);
omega_imag(1) <= to_signed (-23, 10);
omega_imag(2) <= to_signed (-32, 10);
omega_imag(3) <= to_signed (-23, 10);
omega_imag(4) <= to_signed (0, 10);
omega_imag(5) <= to_signed (23, 10);
omega_imag(6) <= to_signed (32, 10);
omega_imag(7) <= to_signed (23, 10);
 
--
--m1Sig <= inputReal * inputImag / 32;
--outputImag <= m1Sig (BN-1 downto 0);
--
 
end Behavioral;
 

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