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  • This comparison shows the changes necessary to convert path
    /pit/trunk/bench
    from Rev 16 to Rev 19
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Rev 16 → Rev 19

/verilog/tst_bench_top.v
177,8 → 177,9
assign ack = ack_1 || ack_2 || ack_3 || ack_4;
 
// hookup wishbone_PIT_master core - Parameters take all default values
// Async Reset, 16 bit Bus, 16 bit Granularity
pit_top pit_1(
// Async Reset, 16 bit Bus, 16 bit Granularity,Wait States
pit_top #(.SINGLE_CYCLE(1'b0))
pit_1(
// wishbone interface
.wb_clk_i(mstr_test_clk),
.wb_rst_i(1'b0),

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