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URL https://opencores.org/ocsvn/pit/pit/trunk

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  • This comparison shows the changes necessary to convert path 
    /pit/trunk/rtl
    from Rev 21 to Rev 22
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Rev 21 → Rev 22

/sys_verilog/pit_prescale.sv
65,7 → 65,7
// This was going to be a "generate" block but iverilog does't support that
// command so we'll just have to trust the compiler to simplify the logic based
// on the setting of the constant "DECADE_CNTR"
always @*
always_comb
if ( DECADE_CNTR )
case (divisor)
0: end_count = 1;
80,7 → 80,7
default: end_count = 20_000;
endcase
else
case (divisor)
unique case (divisor)
0: end_count = 1;
1: end_count = 2;
2: end_count = 4;
111,7 → 111,7
// If the "NO_PRESCALE" parameter is set the compiler should hopefully strip
// these counter bits when the module is compiled because the only place the
// register outputs go to drive a signal "rollover" that is already a constant.
always @(posedge bus_clk or negedge async_rst_b)
always_ff @(posedge bus_clk or negedge async_rst_b)
if ( !async_rst_b )
cnt_n <= 1;
else if ( !counter_sync || rollover)
/sys_verilog/pit_regs.sv
75,7 → 75,7
assign pit_pre_scl = NO_PRESCALE ? 4'b0 : pit_pre;
 
// generate wishbone write registers
always @(posedge bus_clk or negedge async_rst_b)
always_ff @(posedge bus_clk or negedge async_rst_b)
if (!async_rst_b)
begin
pit_slave <= 1'b0;
123,7 → 123,7
endcase
 
// generate interrupt request signals
always @(posedge bus_clk or negedge async_rst_b)
always_ff @(posedge bus_clk or negedge async_rst_b)
if (!async_rst_b)
pit_irq_o <= 0;
else if (sync_reset)
/sys_verilog/pit_wb_bus.sv
91,7 → 91,7
 
// generate acknowledge output signal, By using register all accesses takes two cycles.
// Accesses in back to back clock cycles are not possable.
always @(posedge wb_clk_i or negedge async_rst_b)
always_ff @(posedge wb_clk_i or negedge async_rst_b)
if (!async_rst_b)
bus_wait_state <= 1'b0;
else if (sync_reset)
101,12 → 101,12
 
// Capture address in first cycle of WISHBONE Bus tranaction
// Only used when Wait states are enabled
always @(posedge wb_clk_i)
always_ff @(posedge wb_clk_i)
if ( module_sel ) // Clock gate for power saving
addr_latch <= wb_adr_i;
 
// WISHBONE Read Data Mux
always @*
always_comb
case ({eight_bit_bus, address}) // synopsys parallel_case
// 8 bit Bus, 8 bit Granularity
4'b1_000: wb_dat_o = read_regs[ 7: 0]; // 8 bit read address 0
123,7 → 123,7
endcase
 
// generate wishbone write register strobes -- one hot if 8 bit bus
always @*
always_comb
begin
write_regs = 0;
if (wb_wacc)
/sys_verilog/pit_top.sv
74,21 → 74,22
logic pit_slave; // PIT in Slave Mode, ext_sync_i selected
logic [ 3:0] pit_pre_scl; // Prescaler modulo
logic counter_sync; //
logic pit_flag; //
// Wishbone Bus interface
pit_wb_bus #(.ARST_LVL(ARST_LVL),
.SINGLE_CYCLE(SINGLE_CYCLE),
.DWIDTH(DWIDTH))
wishbone(*,
.irq_source ( cnt_flag_o ),
.read_regs ( // in -- status register bits
{ cnt_n,
mod_value,
{pit_slave, DECADE_CNTR, NO_PRESCALE, 1'b0, pit_pre_scl,
5'b0, cnt_flag_o, pit_ien, cnt_sync_o}
}
)
);
wishbone(
.irq_source ( cnt_flag_o ),
.read_regs ( // in -- status register bits
{ cnt_n,
mod_value,
{pit_slave, DECADE_CNTR, NO_PRESCALE, 1'b0, pit_pre_scl,
5'b0, cnt_flag_o, pit_ien, cnt_sync_o}
}
),
.*);
 
// -----------------------------------------------------------------------------
pit_regs #(.ARST_LVL(ARST_LVL),
95,24 → 96,24
.COUNT_SIZE(COUNT_SIZE),
.NO_PRESCALE(NO_PRESCALE),
.DWIDTH(DWIDTH))
regs(*,
.bus_clk ( wb_clk_i ),
.write_bus ( wb_dat_i )
);
regs(
.bus_clk ( wb_clk_i ),
.write_bus ( wb_dat_i ),
.*);
 
// -----------------------------------------------------------------------------
pit_prescale #(.COUNT_SIZE(PRE_COUNT_SIZE),
.DECADE_CNTR(DECADE_CNTR),
.NO_PRESCALE(NO_PRESCALE))
prescale(*,
prescale(
.bus_clk ( wb_clk_i ),
.divisor ( pit_pre_scl )
);
.divisor ( pit_pre_scl ),
.*);
 
// -----------------------------------------------------------------------------
pit_count #(.COUNT_SIZE(COUNT_SIZE))
counter(*,
.bus_clk ( wb_clk_i )
);
counter(
.bus_clk ( wb_clk_i ),
.*);
 
endmodule // pit_top
/sys_verilog/pit_count.sv
67,7 → 67,7
assign clear_counter = !counter_sync;
 
// Div N Counter
always @(posedge bus_clk or negedge async_rst_b)
always_ff @(posedge bus_clk or negedge async_rst_b)
if ( !async_rst_b )
cnt_n <= 1;
else if ( clear_counter || rollover || no_div)
76,7 → 76,7
cnt_n <= cnt_n + 1;
 
// Counter Rollover Flag and Interrupt
always @(posedge bus_clk or negedge async_rst_b)
always_ff @(posedge bus_clk or negedge async_rst_b)
if ( !async_rst_b )
cnt_flag_o <= 0;
else if ( clear_counter || pit_flg_clr)
85,7 → 85,7
cnt_flag_o <= 1;
 
// PIT Output Register
always @(posedge bus_clk or negedge async_rst_b)
always_ff @(posedge bus_clk or negedge async_rst_b)
if ( !async_rst_b )
pit_o <= 0;
else

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