URL
https://opencores.org/ocsvn/pit/pit/trunk
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- This comparison shows the changes necessary to convert path
/pit/trunk
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/bench/verilog/wb_master_model.v
146,8 → 146,8
input delay; |
integer delay; |
|
input [awidth -1:0] a; |
output [dwidth -1:0] d; |
input [awidth -1:0] a; |
output [dwidth -1:0] d; |
|
begin |
|
168,7 → 168,8
while(~ack) @(posedge clk); |
|
// negate wishbone signals |
#1; |
d = din; // Grab the data on the posedge of clock |
#1; // Delay the clearing (hold time of the control signals |
cyc = 1'b0; |
stb = 1'bx; |
adr = {awidth{1'bx}}; |