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https://opencores.org/ocsvn/pit/pit/trunk
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/pit/trunk
- from Rev 14 to Rev 15
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Rev 14 → Rev 15
/bench/verilog/tst_bench_top.v
123,7 → 123,7
always #20 mstr_test_clk = ~mstr_test_clk; |
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always @(posedge mstr_test_clk) |
vector = vector + 1; |
vector <= vector + 1; |
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// hookup wishbone master model |
wb_master_model #(.dwidth(16), .awidth(32)) |