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Rev 20 → Rev 21

/rtl/sys_verilog/pit_prescale.sv
0,0 → 1,124
////////////////////////////////////////////////////////////////////////////////
//
// Programable Interrupt Timer - Prescale Counter
//
// Author: Bob Hayes
// rehayes@opencores.org
//
// Downloaded from: http://www.opencores.org/projects/pit.....
//
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011, Robert Hayes
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the <organization> nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
////////////////////////////////////////////////////////////////////////////////
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module pit_prescale #(parameter COUNT_SIZE = 15,
parameter DECADE_CNTR = 1,
parameter NO_PRESCALE = 0)
(
output prescale_out, //
output counter_sync, //
input async_rst_b, //
input sync_reset, // Syncronous reset signal
input bus_clk, // Reference Clock
input cnt_sync_o, // Syncronous counter enable
input ext_sync_i, // Enable from external PIT
input pit_slave, // PIT Slave Mode
input [3:0] divisor // Count Divisor
);
// Warning: This counter has no safety net if the divisor changes while the
// counter is active. There may need to be an addtional latch
// register for"divisor" that captures on the falling edge of
// "cnt_sync_o" or when "cnt_n" rolls over to eliminate this problem.
 
logic [COUNT_SIZE-1:0] cnt_n; // Div N counter
logic [COUNT_SIZE-1:0] end_count; // Psudo register for decoding
 
logic div_1; //
logic rollover; //
 
// This was going to be a "generate" block but iverilog does't support that
// command so we'll just have to trust the compiler to simplify the logic based
// on the setting of the constant "DECADE_CNTR"
always @*
if ( DECADE_CNTR )
case (divisor)
0: end_count = 1;
1: end_count = 2;
2: end_count = 4;
3: end_count = 8;
4: end_count = 10;
5: end_count = 100;
6: end_count = 1_000;
7: end_count = 10_000;
8: end_count = 20_000;
default: end_count = 20_000;
endcase
else
case (divisor)
0: end_count = 1;
1: end_count = 2;
2: end_count = 4;
3: end_count = 8;
4: end_count = 16;
5: end_count = 32;
6: end_count = 64;
7: end_count = 128;
8: end_count = 256;
9: end_count = 512;
10: end_count = 1024;
11: end_count = 2048;
12: end_count = 4096;
13: end_count = 8192;
14: end_count = 16384;
15: end_count = 32768;
endcase
 
assign counter_sync = pit_slave ? ext_sync_i : cnt_sync_o;
 
assign div_1 = (end_count == 1);
 
assign rollover = NO_PRESCALE || (cnt_n == end_count);
 
assign prescale_out = (pit_slave && div_1 && ext_sync_i) || rollover;
 
// Div N Counter
// If the "NO_PRESCALE" parameter is set the compiler should hopefully strip
// these counter bits when the module is compiled because the only place the
// register outputs go to drive a signal "rollover" that is already a constant.
always @(posedge bus_clk or negedge async_rst_b)
if ( !async_rst_b )
cnt_n <= 1;
else if ( !counter_sync || rollover)
cnt_n <= 1;
else
cnt_n <= cnt_n + 1;
 
 
endmodule // pit_prescale
 
/rtl/sys_verilog/pit_regs.sv
0,0 → 1,136
////////////////////////////////////////////////////////////////////////////////
//
// WISHBONE revB.2 compliant Programable Interrupt Timer - Control registers
//
// Author: Bob Hayes
// rehayes@opencores.org
//
// Downloaded from: http://www.opencores.org/projects/pit.....
//
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011, Robert Hayes
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the <organization> nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
////////////////////////////////////////////////////////////////////////////////
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module pit_regs #(parameter ARST_LVL = 1'b0, // asynchronous reset level
parameter COUNT_SIZE = 16,
parameter NO_PRESCALE = 1'b0,
parameter DWIDTH = 16)
(
output logic [COUNT_SIZE-1:0] mod_value, // Main Counter Modulo Value
output [ 3:0] pit_pre_scl, // PIT Prescaler Value
output logic pit_slave, // PIT Slave Mode
output logic pit_flg_clr, // Clear PIT Rollover Flag
output logic pit_ien, // PIT Interrupt Enable
output logic cnt_sync_o, // PIT Counter Enable
output logic pit_irq_o, // PIT interrupt
input bus_clk, // Control register bus clock
input async_rst_b, // Async reset signal
input sync_reset, // Syncronous reset signal
input pit_flag, // PIT Rollover Flag
input [DWIDTH-1:0] write_bus, // Write Data Bus
input [ 3:0] write_regs, // Write Register strobes
input cnt_flag_o // Counter Rollover Flag
);
 
 
// registers
logic [ 3:0] pit_pre; // Optional register for PIT Prescale Counter modulo
// This register should be removed durning synthesis
// if the "NO_PRESCALE" parameter is set
 
// Wires
logic [15:0] write_data; // Data bus mux for 8 or 16 bit module bus
 
//
// module body
//
assign write_data = (DWIDTH == 8) ? {write_bus[7:0], write_bus[7:0]} : write_bus;
assign pit_pre_scl = NO_PRESCALE ? 4'b0 : pit_pre;
 
// generate wishbone write registers
always @(posedge bus_clk or negedge async_rst_b)
if (!async_rst_b)
begin
pit_slave <= 1'b0;
pit_pre <= 4'b0;
pit_flg_clr <= 1'b0;
pit_ien <= 1'b0;
cnt_sync_o <= 1'b0;
mod_value <= 0;
end
else if (sync_reset)
begin
pit_slave <= 1'b0;
pit_pre <= 4'b0;
pit_flg_clr <= 1'b0;
pit_ien <= 1'b0;
cnt_sync_o <= 1'b0;
mod_value <= 0;
end
else
case (write_regs) // synopsys parallel_case
4'b0011 :
begin
pit_slave <= write_data[15];
pit_pre <= write_data[11:8];
pit_flg_clr <= write_data[2];
pit_ien <= write_data[1];
cnt_sync_o <= write_data[0];
end
4'b0001 :
begin
pit_flg_clr <= write_data[2];
pit_ien <= write_data[1];
cnt_sync_o <= write_data[0];
end
4'b0010 :
begin
pit_slave <= write_data[7];
pit_pre <= write_data[3:0];
end
4'b1100 : mod_value <= write_data;
4'b0100 : mod_value[ 7:0] <= write_data[7:0];
4'b1000 : mod_value[15:8] <= write_data[7:0];
default:
pit_flg_clr <= 1'b0;
endcase
 
// generate interrupt request signals
always @(posedge bus_clk or negedge async_rst_b)
if (!async_rst_b)
pit_irq_o <= 0;
else if (sync_reset)
pit_irq_o <= 0;
else
pit_irq_o <= cnt_flag_o && pit_ien; // interrupt signal is only generated
// when IEN (interrupt enable bit is set)
 
 
endmodule // pit_regs
/rtl/sys_verilog/pit_wb_bus.sv
0,0 → 1,144
////////////////////////////////////////////////////////////////////////////////
//
// WISHBONE revB.2 compliant Programable Interrupt Timer - Bus interface
//
// Author: Bob Hayes
// rehayes@opencores.org
//
// Downloaded from: http://www.opencores.org/projects/pit.....
//
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011, Robert Hayes
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the <organization> nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
////////////////////////////////////////////////////////////////////////////////
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module pit_wb_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
parameter DWIDTH = 16,
parameter SINGLE_CYCLE = 1'b0)
(
// Wishbone Signals
output logic [DWIDTH-1:0] wb_dat_o, // databus output - Pseudo Register
output wb_ack_o, // bus cycle acknowledge output
input wb_clk_i, // master clock input
input wb_rst_i, // synchronous active high reset
input arst_i, // asynchronous reset
input [ 2:0] wb_adr_i, // lower address bits
input [DWIDTH-1:0] wb_dat_i, // databus input
input wb_we_i, // write enable input
input wb_stb_i, // stobe/core select signal
input wb_cyc_i, // valid bus cycle input
input [1:0] wb_sel_i, // Select byte in word bus transaction
// PIT Control Signals
output logic [ 3:0] write_regs, // Decode write control register
output async_rst_b, //
output sync_reset, //
input irq_source, //
input [47:0] read_regs // status register bits
);
 
 
// registers
logic bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state
logic [2:0] addr_latch; // Capture WISHBONE Address
 
// Wires
logic eight_bit_bus;
logic module_sel; // This module is selected for bus transaction
logic wb_wacc; // WISHBONE Write Strobe
logic wb_racc; // WISHBONE Read Access (Clock gating signal)
logic [2:0] address; // Select either direct or latched address
 
//
// module body
//
 
// generate internal resets
assign eight_bit_bus = (DWIDTH == 8);
 
assign async_rst_b = arst_i ^ ARST_LVL;
assign sync_reset = wb_rst_i;
 
// generate wishbone signals
assign module_sel = wb_cyc_i && wb_stb_i;
assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
assign wb_racc = module_sel && !wb_we_i;
assign wb_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
assign address = SINGLE_CYCLE ? wb_adr_i : addr_latch;
 
// generate acknowledge output signal, By using register all accesses takes two cycles.
// Accesses in back to back clock cycles are not possable.
always @(posedge wb_clk_i or negedge async_rst_b)
if (!async_rst_b)
bus_wait_state <= 1'b0;
else if (sync_reset)
bus_wait_state <= 1'b0;
else
bus_wait_state <= module_sel && !bus_wait_state;
 
// Capture address in first cycle of WISHBONE Bus tranaction
// Only used when Wait states are enabled
always @(posedge wb_clk_i)
if ( module_sel ) // Clock gate for power saving
addr_latch <= wb_adr_i;
 
// WISHBONE Read Data Mux
always @*
case ({eight_bit_bus, address}) // synopsys parallel_case
// 8 bit Bus, 8 bit Granularity
4'b1_000: wb_dat_o = read_regs[ 7: 0]; // 8 bit read address 0
4'b1_001: wb_dat_o = read_regs[15: 8]; // 8 bit read address 1
4'b1_010: wb_dat_o = read_regs[23:16]; // 8 bit read address 2
4'b1_011: wb_dat_o = read_regs[31:24]; // 8 bit read address 3
4'b1_100: wb_dat_o = read_regs[39:32]; // 8 bit read address 4
4'b1_101: wb_dat_o = read_regs[47:40]; // 8 bit read address 5
// 16 bit Bus, 16 bit Granularity
4'b0_000: wb_dat_o = read_regs[15: 0]; // 16 bit read access address 0
4'b0_001: wb_dat_o = read_regs[31:16];
4'b0_010: wb_dat_o = read_regs[47:32];
default: wb_dat_o = 0;
endcase
 
// generate wishbone write register strobes -- one hot if 8 bit bus
always @*
begin
write_regs = 0;
if (wb_wacc)
case ({eight_bit_bus, address}) // synopsys parallel_case
// 8 bit Bus, 8 bit Granularity
4'b1_000 : write_regs = 4'b0001;
4'b1_001 : write_regs = 4'b0010;
4'b1_010 : write_regs = 4'b0100;
4'b1_011 : write_regs = 4'b1000;
// 16 bit Bus, 16 bit Granularity
4'b0_000 : write_regs = 4'b0011;
4'b0_001 : write_regs = 4'b1100;
default: ;
endcase
end
 
endmodule // pit_wb_bus
/rtl/sys_verilog/pit_top.sv
0,0 → 1,118
////////////////////////////////////////////////////////////////////////////////
//
// WISHBONE revB.2 compliant Programable Interrupt Timer - Top-level
//
// Author: Bob Hayes
// rehayes@opencores.org
//
// Downloaded from: http://www.opencores.org/projects/pit.....
//
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011, Robert Hayes
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the <organization> nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
////////////////////////////////////////////////////////////////////////////////
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module pit_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
parameter PRE_COUNT_SIZE = 15, // Prescale Counter size
parameter COUNT_SIZE = 16, // Main counter size
parameter DECADE_CNTR = 1'b1, // Prescale rollover decode
parameter NO_PRESCALE = 1'b0, // Remove prescale function
parameter SINGLE_CYCLE = 1'b0, // No bus wait state added
parameter DWIDTH = 16) // Data bus width
(
// Wishbone Signals
output [DWIDTH-1:0] wb_dat_o, // databus output
output wb_ack_o, // bus cycle acknowledge output
input wb_clk_i, // master clock input
input wb_rst_i, // synchronous active high reset
input arst_i, // asynchronous reset
input [2:0] wb_adr_i, // lower address bits
input [DWIDTH-1:0] wb_dat_i, // databus input
input wb_we_i, // write enable input
input wb_stb_i, // stobe/core select signal
input wb_cyc_i, // valid bus cycle input
input [1:0] wb_sel_i, // Select byte in word bus transaction
// PIT IO Signals
output pit_o, // PIT output pulse
output pit_irq_o, // PIT interrupt request signal output
output cnt_flag_o, // PIT Flag Out
output cnt_sync_o, // PIT Master Enable for Slave PIT's
input ext_sync_i // Counter enable from Master PIT
);
logic [COUNT_SIZE-1:0] mod_value; // Main Counter Modulo
logic [COUNT_SIZE-1:0] cnt_n; // PIT Counter Value
logic async_rst_b; // Asyncronous reset
logic sync_reset; // Syncronous reset
logic [ 3:0] write_regs; // Control register write strobes
logic prescale_out; //
logic pit_flg_clr; // Clear PIT Rollover Status Bit
logic pit_slave; // PIT in Slave Mode, ext_sync_i selected
logic [ 3:0] pit_pre_scl; // Prescaler modulo
logic counter_sync; //
// Wishbone Bus interface
pit_wb_bus #(.ARST_LVL(ARST_LVL),
.SINGLE_CYCLE(SINGLE_CYCLE),
.DWIDTH(DWIDTH))
wishbone(*,
.irq_source ( cnt_flag_o ),
.read_regs ( // in -- status register bits
{ cnt_n,
mod_value,
{pit_slave, DECADE_CNTR, NO_PRESCALE, 1'b0, pit_pre_scl,
5'b0, cnt_flag_o, pit_ien, cnt_sync_o}
}
)
);
 
// -----------------------------------------------------------------------------
pit_regs #(.ARST_LVL(ARST_LVL),
.COUNT_SIZE(COUNT_SIZE),
.NO_PRESCALE(NO_PRESCALE),
.DWIDTH(DWIDTH))
regs(*,
.bus_clk ( wb_clk_i ),
.write_bus ( wb_dat_i )
);
 
// -----------------------------------------------------------------------------
pit_prescale #(.COUNT_SIZE(PRE_COUNT_SIZE),
.DECADE_CNTR(DECADE_CNTR),
.NO_PRESCALE(NO_PRESCALE))
prescale(*,
.bus_clk ( wb_clk_i ),
.divisor ( pit_pre_scl )
);
 
// -----------------------------------------------------------------------------
pit_count #(.COUNT_SIZE(COUNT_SIZE))
counter(*,
.bus_clk ( wb_clk_i )
);
 
endmodule // pit_top
/rtl/sys_verilog/pit_count.sv
0,0 → 1,95
////////////////////////////////////////////////////////////////////////////////
//
// Programable Interrupt Timer - Main Counter
//
// Author: Bob Hayes
// rehayes@opencores.org
//
// Downloaded from: http://www.opencores.org/projects/pit.....
//
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011, Robert Hayes
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the <organization> nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
////////////////////////////////////////////////////////////////////////////////
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module pit_count #(parameter COUNT_SIZE = 16)
(
output logic [COUNT_SIZE-1:0] cnt_n, // Modulo Counter value
output logic cnt_flag_o, // Counter Rollover Flag
output logic pit_o, // PIT output pulse
input async_rst_b, //
input sync_reset, // Syncronous reset signal
input bus_clk, // Reference Clock
input counter_sync, // Syncronous counter enable
input prescale_out, // Increment Counter
input pit_flg_clr, // Clear PIT Rollover Flag
input [COUNT_SIZE-1:0] mod_value // Count Divisor
);
 
// Warning: This counter has no saftynet if the mod_value changes while the counter
// is active. There may need to be an addtional latch register for
// "mod_value" that captures on the falling edge of "counter_sync" or
// when "cnt_n" rolls over to eliminate this problem.
 
 
logic rollover; // Counter has reached the mod_value
logic no_div; // Modulo set for Zero or One
logic clear_counter; // Set counter to initial state
 
assign no_div = (mod_value == 1) || ~|mod_value;
 
assign rollover = ((cnt_n == mod_value) || no_div) && prescale_out;
 
assign clear_counter = !counter_sync;
 
// Div N Counter
always @(posedge bus_clk or negedge async_rst_b)
if ( !async_rst_b )
cnt_n <= 1;
else if ( clear_counter || rollover || no_div)
cnt_n <= 1;
else if ( prescale_out )
cnt_n <= cnt_n + 1;
 
// Counter Rollover Flag and Interrupt
always @(posedge bus_clk or negedge async_rst_b)
if ( !async_rst_b )
cnt_flag_o <= 0;
else if ( clear_counter || pit_flg_clr)
cnt_flag_o <= 0;
else if ( rollover )
cnt_flag_o <= 1;
 
// PIT Output Register
always @(posedge bus_clk or negedge async_rst_b)
if ( !async_rst_b )
pit_o <= 0;
else
pit_o <= rollover && counter_sync && !sync_reset;
 
endmodule // pit_count
 
/rtl/verilog/pit_wb_bus.v
119,6 → 119,7
4'b0_000: wb_dat_o = read_regs[15: 0]; // 16 bit read access address 0
4'b0_001: wb_dat_o = read_regs[31:16];
4'b0_010: wb_dat_o = read_regs[47:32];
default: wb_dat_o = 0;
endcase
 
// generate wishbone write register strobes -- one hot if 8 bit bus

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