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URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

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  • This comparison shows the changes necessary to convert path
    /pit/trunk
    from Rev 4 to Rev 5
    Reverse comparison

Rev 4 → Rev 5

/doc/PIT_specs.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
doc/PIT_specs.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/PIT_specs.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/PIT_specs.pdf =================================================================== --- doc/PIT_specs.pdf (nonexistent) +++ doc/PIT_specs.pdf (revision 5)
doc/PIT_specs.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/src/PIT_specs.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/src/PIT_specs.pdf =================================================================== --- doc/src/PIT_specs.pdf (revision 4) +++ doc/src/PIT_specs.pdf (nonexistent)
doc/src/PIT_specs.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/src/PIT_specs.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/src/PIT_specs.doc =================================================================== --- doc/src/PIT_specs.doc (nonexistent) +++ doc/src/PIT_specs.doc (revision 5)
doc/src/PIT_specs.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sim/verilog/run/pit_waves.sav =================================================================== --- sim/verilog/run/pit_waves.sav (revision 4) +++ sim/verilog/run/pit_waves.sav (nonexistent) @@ -1,62 +0,0 @@ -[size] 1197 666 -[pos] -1 -1 -*-16.338505 72000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] tst_bench_top. -[treeopen] tst_bench_top.pit_1. -[treeopen] tst_bench_top.pit_2. -[treeopen] tst_bench_top.pit_3. -[treeopen] tst_bench_top.pit_4. -@22 -tst_bench_top.test_num[7:0] -@28 -tst_bench_top.pit_1.wb_clk_i -@22 -tst_bench_top.pit_1.wb_dat_i[15:0] -tst_bench_top.pit_1.wb_dat_o[15:0] -@28 -tst_bench_top.sync_reset -tst_bench_top.pit_1.arst_i -tst_bench_top.pit_1.wb_stb_i -@22 -tst_bench_top.mstr_psx_modx.cntrl_val[15:0] -@200 --Control Register -@22 -tst_bench_top.pit_1.regs.mod_value[15:0] -tst_bench_top.pit_1.regs.pit_pre_scl[3:0] -tst_bench_top.pit_1.regs.write_bus[15:0] -@28 -tst_bench_top.pit_1.regs.pit_slave -@200 --Modulo Counter -@22 -tst_bench_top.pit_1.counter.mod_value[15:0] -@28 -tst_bench_top.pit_1.counter.rollover -@22 -tst_bench_top.pit_1.counter.cnt_n[15:0] -@28 -tst_bench_top.pit_1.counter.counter_sync -tst_bench_top.pit_1.counter.prescale_out -tst_bench_top.pit_1.pit_o -@200 --Prescaler -@22 -tst_bench_top.pit_1.prescale.cnt_n[14:0] -tst_bench_top.pit_1.prescale.end_count[14:0] -@28 -tst_bench_top.pit_1.prescale.rollover -@200 --Slave PIT -@22 -tst_bench_top.pit_2.prescale.cnt_n[14:0] -tst_bench_top.pit_2.counter.cnt_n[15:0] -@200 --Slave 1 -@28 -tst_bench_top.pit_3.cnt_flag_o -tst_bench_top.pit_3.pit_o -@200 --Byte Mode Slave -@22 -tst_bench_top.pit_4.counter.cnt_n[15:0]

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