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https://opencores.org/ocsvn/pit/pit/trunk
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- This comparison shows the changes necessary to convert path
/pit
- from Rev 23 to Rev 24
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Rev 23 → Rev 24
/trunk/bench/sys_verilog/tst_bench_top.sv
36,7 → 36,6
//////////////////////////////////////////////////////////////////////////////// |
// 45678901234567890123456789012345678901234567890123456789012345678901234567890 |
|
|
`include "timescale.v" |
|
module tst_bench_top(); |
68,7 → 67,7
logic scl, scl0_o, scl0_oen, scl1_o, scl1_oen; |
logic sda, sda0_o, sda0_oen, sda1_o, sda1_oen; |
|
// Name Address Locations |
// Name the Address Locations of the PIT Wishbone control registers |
parameter PIT_CNTRL = 5'b0_0000; |
parameter PIT_MOD = 5'b0_0001; |
parameter PIT_COUNT = 5'b0_0010; |
80,18 → 79,19
parameter CTR_EN = 8'b1000_0000; // core enable bit |
parameter CTR_IEN = 8'b0100_0000; // core interrupt enable bit |
|
// Name the control/status bits of the PIT registers |
parameter PIT_CNTRL_SLAVE = 16'h8000; // PIT Slave mode |
parameter PIT_CNTRL_FLAG = 16'h0004; // PIT Rollover Flag |
parameter PIT_CNTRL_IRQEN = 16'h0002; // PIT Interupt Enable |
parameter PIT_CNTRL_ENA = 16'h0001; // PIT Enable |
|
parameter SLAVE_0_CNTRL = 5'b0_1000; |
parameter SLAVE_0_MOD = 5'b0_1001; |
parameter SLAVE_0_COUNT = 5'b0_1010; |
parameter SLAVE_0_CNTRL = 5'b0_1000 + PIT_CNTRL; |
parameter SLAVE_0_MOD = 5'b0_1000 + PIT_MOD; |
parameter SLAVE_0_COUNT = 5'b0_1000 + PIT_COUNT; |
|
parameter SLAVE_1_CNTRL = 5'b1_0000; |
parameter SLAVE_1_MOD = 5'b1_0001; |
parameter SLAVE_1_COUNT = 5'b1_0010; |
parameter SLAVE_1_CNTRL = 5'b1_0000 + PIT_CNTRL; |
parameter SLAVE_1_MOD = 5'b1_0000 + PIT_MOD; |
parameter SLAVE_1_COUNT = 5'b1_0000 + PIT_COUNT; |
|
parameter SLAVE_2_CNTRL_0 = 5'b1_1000; |
parameter SLAVE_2_CNTRL_1 = 5'b1_1001; |
103,10 → 103,10
// initial values and testbench setup |
initial |
begin |
mstr_test_clk = 0; |
vector = 0; |
test_num = 0; |
error_count = 0; |
mstr_test_clk <= 0; |
vector <= 0; |
test_num <= 0; |
error_count <= 0; |
|
`ifdef WAVES |
$shm_open("waves"); |
145,14 → 145,43
end |
|
// Add up errors tha come from WISHBONE read compares |
always @u0.cmp_error_detect |
always @master.cmp_error_detect |
begin |
error_count <= error_count + 1; |
end |
|
// Define a seperate interface for each PIT instance since each PIT |
// intstance has small differences |
wishbone_if #(.D_WIDTH (16), |
.A_WIDTH (3)) |
wb_1( |
.wb_clk (mstr_test_clk), |
.wb_rst (1'b0), |
.arst (rstn)); |
|
wishbone_if wb_2( |
.wb_clk (mstr_test_clk), |
.wb_rst (sync_reset), |
.arst (1'b0)); |
|
wishbone_if wb_3( |
.wb_clk (mstr_test_clk), |
.wb_rst (sync_reset), |
.arst (1'b1)); |
|
wishbone_if #(.D_WIDTH (8)) |
wb_4( |
.wb_clk (mstr_test_clk), |
.wb_rst (sync_reset), |
.arst (1'b1)); |
|
// hookup wishbone master model |
wb_master_model #(.dwidth(16), .awidth(32)) |
u0 ( |
master ( |
.wb_1(wb_1), |
.wb_2(wb_2), |
.wb_3(wb_3), |
.wb_4(wb_4), |
.clk(mstr_test_clk), |
.rst(rstn), |
.adr(adr), |
182,25 → 211,18
|
assign ack = ack_1 || ack_2 || ack_3 || ack_4; |
|
// hookup wishbone_PIT_master core - Parameters take all default values |
|
// hookup wishbone_PIT_slave core - Parameters take all default values |
// Async Reset, 16 bit Bus, 16 bit Granularity,Wait States |
pit_top #(.SINGLE_CYCLE(1'b0)) |
pit_1( |
pit_top pit_1( |
// wishbone interface |
.wb_clk_i(mstr_test_clk), |
.wb_rst_i(1'b0), |
.arst_i(rstn), |
.wb_adr_i(adr[2:0]), |
.wb_dat_i(dat_o), |
.wb_dat_o(dat0_i), |
.wb_we_i(we), |
.wb_stb_i(stb0), |
.wb_cyc_i(cyc), |
.wb_sel_i( 2'b11 ), |
.wb_ack_o(ack_1), |
.pit_irq_o(inta_1), |
.wb (wb_1), |
.wb_dat_o (dat0_i), |
.wb_stb (stb0), |
.wb_ack (ack_1), |
|
.pit_o(pit_1_out), |
.pit_irq_o (inta_1), |
.pit_o (pit_1_out), |
.ext_sync_i(1'b0), |
.cnt_sync_o(count_en_1), |
.cnt_flag_o(count_flag_1) |
211,19 → 233,12
pit_top #(.ARST_LVL(1'b1)) |
pit_2( |
// wishbone interface |
.wb_clk_i(mstr_test_clk), |
.wb_rst_i(sync_reset), |
.arst_i(1'b0), |
.wb_adr_i(adr[2:0]), |
.wb_dat_i(dat_o), |
.wb (wb_2), |
.wb_dat_o(dat1_i), |
.wb_we_i(we), |
.wb_stb_i(stb1), |
.wb_cyc_i(cyc), |
.wb_sel_i( 2'b11 ), |
.wb_ack_o(ack_2), |
.wb_stb (stb1), |
.wb_ack (ack_2), |
|
.pit_irq_o(inta_2), |
|
.pit_o(pit_2_out), |
.ext_sync_i(count_en_1), |
.cnt_sync_o(count_en_2), |
235,19 → 250,12
pit_top #(.NO_PRESCALE(1'b1)) |
pit_3( |
// wishbone interface |
.wb_clk_i(mstr_test_clk), |
.wb_rst_i(sync_reset), |
.arst_i(1'b1), |
.wb_adr_i(adr[2:0]), |
.wb_dat_i(dat_o), |
.wb (wb_3), |
.wb_dat_o(dat2_i), |
.wb_we_i(we), |
.wb_stb_i(stb2), |
.wb_cyc_i(cyc), |
.wb_sel_i( 2'b11 ), |
.wb_ack_o(ack_3), |
.wb_stb (stb2), |
.wb_ack (ack_3), |
|
.pit_irq_o(inta_3), |
|
.pit_o(pit_3_out), |
.ext_sync_i(count_en_1), |
.cnt_sync_o(count_en_3), |
256,22 → 264,15
|
// hookup wishbone_PIT_slave core |
// 8 bit Bus, 8 bit Granularity |
pit_top #(.DWIDTH(8)) |
pit_top #(.D_WIDTH(8)) |
pit_4( |
// wishbone interface |
.wb_clk_i(mstr_test_clk), |
.wb_rst_i(sync_reset), |
.arst_i(1'b1), |
.wb_adr_i(adr[2:0]), |
.wb_dat_i(dat_o[7:0]), |
.wb (wb_4), |
.wb_dat_o(dat3_i[7:0]), |
.wb_we_i(we), |
.wb_stb_i(stb3), |
.wb_cyc_i(cyc), |
.wb_sel_i( 2'b11 ), |
.wb_ack_o(ack_4), |
.wb_stb (stb3), |
.wb_ack (ack_4), |
|
.pit_irq_o(inta_4), |
|
.pit_o(pit_4_out), |
.ext_sync_i(count_en_1), |
.cnt_sync_o(count_en_4), |
278,7 → 279,7
.cnt_flag_o(count_flag_4) |
); |
|
// Test Program |
// Main Test Program ----------------------------------------------------------- |
initial |
begin |
$display("\nstatus: %t Testbench started", $time); |
307,29 → 308,29
|
reg_test_8; |
|
u0.wb_write(1, SLAVE_0_CNTRL, PIT_CNTRL_SLAVE); // Enable Slave Mode |
u0.wb_write(1, SLAVE_1_CNTRL, PIT_CNTRL_SLAVE); // Enable Slave Mode |
u0.wb_write(1, SLAVE_2_CNTRL_1, 16'h0080); // Enable Slave Mode |
u0.wb_write(1, SLAVE_0_MOD, 16'h000a); // load Modulo |
u0.wb_write(1, SLAVE_1_MOD, 16'h0010); // load Modulo |
u0.wb_write(1, SLAVE_2_MOD_0, 16'h0010); // load Modulo |
master.wb_write(1, SLAVE_0_CNTRL, PIT_CNTRL_SLAVE); // Enable Slave Mode |
master.wb_write(1, SLAVE_1_CNTRL, PIT_CNTRL_SLAVE); // Enable Slave Mode |
master.wb_write(1, SLAVE_2_CNTRL_1, 16'h0080); // Enable Slave Mode |
master.wb_write(1, SLAVE_0_MOD, 16'h000a); // load Modulo |
master.wb_write(1, SLAVE_1_MOD, 16'h0010); // load Modulo |
master.wb_write(1, SLAVE_2_MOD_0, 16'h0010); // load Modulo |
|
// Set Master Mode PS=0, Modulo=16 |
test_num = test_num + 1; |
$display("TEST #%d Starts at vector=%d, ms_test", test_num, vector); |
|
u0.wb_write(1, PIT_MOD, 16'h0010); // load prescaler hi-byte |
u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_ENA); // Enable to start counting |
master.wb_write(1, PIT_MOD, 16'h0010); // load prescaler hi-byte |
master.wb_write(1, PIT_CNTRL, PIT_CNTRL_ENA); // Enable to start counting |
$display("status: %t programmed registers", $time); |
|
wait_flag_set; // Wait for Counter to tomeout |
u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); // |
master.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); // |
|
wait_flag_set; // Wait for Counter to tomeout |
u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); // |
master.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); // |
|
repeat(10) @(posedge mstr_test_clk); |
u0.wb_write(1, PIT_CNTRL, 16'b0); // |
master.wb_write(1, PIT_CNTRL, 16'b0); // |
|
repeat(10) @(posedge mstr_test_clk); |
|
341,13 → 342,13
|
wrap_up; |
|
end // Main Test Flow |
end // Main Test Flow ------------------------------------------------------ |
|
// Poll for flag set |
task wait_flag_set; |
u0.wb_read(1, PIT_CNTRL, q); |
master.wb_read(1, PIT_CNTRL, q); |
while(~|(q & PIT_CNTRL_FLAG)) |
u0.wb_read(1, PIT_CNTRL, q); // poll it until it is set |
master.wb_read(1, PIT_CNTRL, q); // poll it until it is set |
$display("PIT Flag set detected at vector =%d", vector); |
endtask |
|
355,54 → 356,55
task reg_test_16; |
test_num = test_num + 1; |
$display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector); |
u0.wb_cmp(0, PIT_CNTRL, 16'h4000); // verify reset |
u0.wb_cmp(0, PIT_MOD, 16'h0000); // verify reset |
u0.wb_cmp(0, PIT_COUNT, 16'h0001); // verify reset |
master.wb_cmp(0, PIT_CNTRL, 16'h4000); // verify reset |
master.wb_cmp(0, PIT_MOD, 16'h0000); // verify reset |
master.wb_cmp(0, PIT_COUNT, 16'h0001); // verify reset |
|
u0.wb_write(1, PIT_CNTRL, 16'hfffe); // load prescaler lo-byte |
u0.wb_cmp( 0, PIT_CNTRL, 16'hCf02); // verify write data |
u0.wb_write(1, PIT_CNTRL, 16'h0000); // load prescaler lo-byte |
u0.wb_cmp( 0, PIT_CNTRL, 16'h4000); // verify write data |
master.wb_write(1, PIT_CNTRL, 16'hfffe); // load prescaler lo-byte |
master.wb_cmp( 0, PIT_CNTRL, 16'hCf02); // verify write data |
master.wb_write(1, PIT_CNTRL, 16'h0000); // load prescaler lo-byte |
master.wb_cmp( 0, PIT_CNTRL, 16'h4000); // verify write data |
|
u0.wb_write(1, PIT_MOD, 16'h5555); // load prescaler lo-byte |
u0.wb_cmp( 0, PIT_MOD, 16'h5555); // verify write data |
u0.wb_write(1, PIT_MOD, 16'haaaa); // load prescaler lo-byte |
u0.wb_cmp( 0, PIT_MOD, 16'haaaa); // verify write data |
master.wb_write(1, PIT_MOD, 16'h5555); // load prescaler lo-byte |
master.wb_cmp( 0, PIT_MOD, 16'h5555); // verify write data |
master.wb_write(1, PIT_MOD, 16'haaaa); // load prescaler lo-byte |
master.wb_cmp( 0, PIT_MOD, 16'haaaa); // verify write data |
|
u0.wb_write(0, PIT_COUNT, 16'hfffe); |
u0.wb_cmp( 0, PIT_COUNT, 16'h0001); // verify register not writable |
master.wb_write(0, PIT_COUNT, 16'hfffe); |
master.wb_cmp( 0, PIT_COUNT, 16'h0001); // verify register not writable |
endtask |
|
// Check the registers when the PIT is configured for 8-bit mode |
task reg_test_8; |
test_num = test_num + 1; |
$display("TEST #%d Starts at vector=%d, reg_test_8", test_num, vector); |
u0.wb_cmp(0, SLAVE_2_CNTRL_0, 16'h0000); // verify reset |
u0.wb_cmp(0, SLAVE_2_CNTRL_1, 16'h0040); // verify reset |
u0.wb_cmp(0, SLAVE_2_MOD_0, 16'h0000); // verify reset |
u0.wb_cmp(0, SLAVE_2_MOD_1, 16'h0000); // verify reset |
u0.wb_cmp(0, SLAVE_2_COUNT_0, 16'h0001); // verify reset |
u0.wb_cmp(0, SLAVE_2_COUNT_1, 16'h0000); // verify reset |
master.wb_cmp(0, SLAVE_2_CNTRL_0, 16'h0000); // verify reset |
master.wb_cmp(0, SLAVE_2_CNTRL_1, 16'h0040); // verify reset |
master.wb_cmp(0, SLAVE_2_MOD_0, 16'h0000); // verify reset |
master.wb_cmp(0, SLAVE_2_MOD_1, 16'h0000); // verify reset |
master.wb_cmp(0, SLAVE_2_COUNT_0, 16'h0001); // verify reset |
master.wb_cmp(0, SLAVE_2_COUNT_1, 16'h0000); // verify reset |
|
u0.wb_write(1, SLAVE_2_CNTRL_0, 16'hfffe); // load prescaler lo-byte |
u0.wb_cmp( 0, SLAVE_2_CNTRL_0, 16'h0002); // verify write data |
u0.wb_write(1, SLAVE_2_CNTRL_0, 16'h0000); // load prescaler lo-byte |
u0.wb_cmp( 0, SLAVE_2_CNTRL_0, 16'h0000); // verify write data |
u0.wb_cmp( 0, SLAVE_2_CNTRL_1, 16'h0040); // verify write data |
master.wb_write(1, SLAVE_2_CNTRL_0, 16'hfffe); // load prescaler lo-byte |
master.wb_cmp( 0, SLAVE_2_CNTRL_0, 16'h0002); // verify write data |
master.wb_write(1, SLAVE_2_CNTRL_0, 16'h0000); // load prescaler lo-byte |
master.wb_cmp( 0, SLAVE_2_CNTRL_0, 16'h0000); // verify write data |
master.wb_cmp( 0, SLAVE_2_CNTRL_1, 16'h0040); // verify write data |
|
u0.wb_write(1, SLAVE_2_MOD_0, 16'hff55); // load prescaler lo-byte |
u0.wb_cmp( 0, SLAVE_2_MOD_0, 16'h0055); // verify write data |
u0.wb_write(1, SLAVE_2_MOD_0, 16'hffaa); // load prescaler lo-byte |
u0.wb_cmp( 0, SLAVE_2_MOD_0, 16'h00aa); // verify write data |
u0.wb_write(1, SLAVE_2_MOD_1, 16'hff66); // load prescaler lo-byte |
u0.wb_cmp( 0, SLAVE_2_MOD_1, 16'h0066); // verify write data |
u0.wb_write(1, SLAVE_2_MOD_1, 16'hff99); // load prescaler lo-byte |
u0.wb_cmp( 0, SLAVE_2_MOD_1, 16'h0099); // verify write data |
u0.wb_write(1, SLAVE_2_MOD_1, 16'hff00); // load prescaler lo-byte |
master.wb_write(1, SLAVE_2_MOD_0, 16'hff55); // load prescaler lo-byte |
master.wb_cmp( 0, SLAVE_2_MOD_0, 16'h0055); // verify write data |
master.wb_write(1, SLAVE_2_MOD_0, 16'hffaa); // load prescaler lo-byte |
master.wb_cmp( 0, SLAVE_2_MOD_0, 16'h00aa); // verify write data |
master.wb_write(1, SLAVE_2_MOD_1, 16'hff66); // load prescaler lo-byte |
master.wb_cmp( 0, SLAVE_2_MOD_1, 16'h0066); // verify write data |
master.wb_write(1, SLAVE_2_MOD_1, 16'hff99); // load prescaler lo-byte |
master.wb_cmp( 0, SLAVE_2_MOD_1, 16'h0099); // verify write data |
master.wb_write(1, SLAVE_2_MOD_1, 16'hff00); // load prescaler lo-byte |
|
u0.wb_write(0, SLAVE_2_COUNT_0, 16'hfffe); |
u0.wb_cmp( 0, SLAVE_2_COUNT_0, 16'h0001); // verify register not writable |
u0.wb_write(0, SLAVE_2_COUNT_1, 16'hfffe); |
u0.wb_cmp( 0, SLAVE_2_COUNT_1, 16'h0000); // verify register not writable |
master.wb_write(0, SLAVE_2_COUNT_0, 16'hfffe); |
master.wb_cmp( 0, SLAVE_2_COUNT_0, 16'h0001); // verify register not writable |
master.wb_write(0, SLAVE_2_COUNT_1, 16'hfffe); |
master.wb_cmp( 0, SLAVE_2_COUNT_1, 16'h0000); // verify register not writable |
endtask |
|
task mstr_psx_modx( |
415,20 → 417,21
// program internal registers |
|
cntrl_val = {1'b0, 3'b0, ps_val, 8'b0} | PIT_CNTRL_IRQEN; |
u0.wb_write(1, PIT_MOD, mod_val); // load modulo |
u0.wb_write(1, PIT_CNTRL, ( cntrl_val | PIT_CNTRL_ENA)); // Enable to start counting |
master.wb_write(1, PIT_MOD, mod_val); // load modulo |
master.wb_write(1, PIT_CNTRL, ( cntrl_val | PIT_CNTRL_ENA)); // Enable to start counting |
|
wait_flag_set; // Wait for Counter to timeout |
u0.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); // |
master.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); // |
|
wait_flag_set; // Wait for Counter to timeout |
u0.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); // |
master.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); // |
|
repeat(10) @(posedge mstr_test_clk); |
|
u0.wb_write(1, PIT_CNTRL, 16'b0); // |
master.wb_write(1, PIT_CNTRL, 16'b0); // |
endtask |
|
// End the simulation and print out the final results |
task wrap_up; |
test_num = test_num + 1; |
repeat(10) @(posedge mstr_test_clk); |
/trunk/bench/sys_verilog/wb_master_model.sv
1,57 → 1,51
/////////////////////////////////////////////////////////////////////// |
//// //// |
//// WISHBONE rev.B2 Wishbone Master model //// |
//// //// |
//// //// |
//// Author: Richard Herveille //// |
//// richard@asics.ws //// |
//// www.asics.ws //// |
//// //// |
//// Downloaded from: http://www.opencores.org/projects/mem_ctrl //// |
//// //// |
/////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Richard Herveille //// |
//// richard@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
/////////////////////////////////////////////////////////////////////// |
|
// CVS Log |
//////////////////////////////////////////////////////////////////////////////// |
// |
// $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $ |
// WISHBONE rev.B2 Wishbone Master model |
// |
// $Date: 2004/02/28 15:40:42 $ |
// $Revision: 1.4 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
// Author: Bob Hayes |
// rehayes@opencores.org |
// |
// Change History: |
// Downloaded from: http://www.opencores.org/projects/pit..... |
// |
//////////////////////////////////////////////////////////////////////////////// |
// Copyright (c) 2011, Robert Hayes |
// |
// All rights reserved. |
// |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// * Redistributions of source code must retain the above copyright |
// notice, this list of conditions and the following disclaimer. |
// * Redistributions in binary form must reproduce the above copyright |
// notice, this list of conditions and the following disclaimer in the |
// documentation and/or other materials provided with the distribution. |
// * Neither the name of the <organization> nor the |
// names of its contributors may be used to endorse or promote products |
// derived from this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY |
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY |
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
//////////////////////////////////////////////////////////////////////////////// |
// 45678901234567890123456789012345678901234567890123456789012345678901234567890 |
|
`include "timescale.v" |
|
module wb_master_model #(parameter dwidth = 32, |
parameter awidth = 32) |
( |
// Wishbone Signals |
wishbone_if.master wb_1, // Define the interface instance name |
wishbone_if.master wb_2, // Define the interface instance name |
wishbone_if.master wb_3, // Define the interface instance name |
wishbone_if.master wb_4, // Define the interface instance name |
output logic cyc, |
output logic stb, |
output logic we, |
66,17 → 60,41
input logic rty // No Connect |
); |
|
//////////////////////////////////////////////////////////////////// |
////////////////////////////////// |
// |
// Local Wires |
// |
|
|
logic [dwidth -1:0] q; |
logic [dwidth-1:0] q; |
|
event cmp_error_detect; |
|
//////////////////////////////////////////////////////////////////// |
assign wb_1.wb_adr = adr[2:0]; |
assign wb_1.wb_sel = 2'b11; |
assign wb_1.wb_we = we; |
assign wb_1.wb_cyc = cyc; |
assign wb_1.wb_dat = dout; |
|
assign wb_2.wb_adr = adr[2:0]; |
assign wb_2.wb_sel = 2'b11; |
assign wb_2.wb_we = we; |
assign wb_2.wb_cyc = cyc; |
assign wb_2.wb_dat = dout; |
|
assign wb_3.wb_adr = adr[2:0]; |
assign wb_3.wb_sel = 2'b11; |
assign wb_3.wb_we = we; |
assign wb_3.wb_cyc = cyc; |
assign wb_3.wb_dat = dout; |
|
assign wb_4.wb_adr = adr[2:0]; |
assign wb_4.wb_sel = 2'b11; |
assign wb_4.wb_we = we; |
assign wb_4.wb_cyc = cyc; |
assign wb_4.wb_dat = dout[7:0]; |
|
////////////////////////////////// |
// |
// Memory Logic |
// |
83,17 → 101,17
|
initial |
begin |
adr = 'x; |
dout = 'x; |
cyc = 1'b0; |
stb = 1'bx; |
we = 1'hx; |
sel = 'x; |
adr <= 'x; |
dout <= 'x; |
cyc <= 1'b0; |
stb <= 1'bx; |
we <= 1'hx; |
sel <= 'x; |
#1; |
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)"); |
end |
|
//////////////////////////////////////////////////////////////////// |
////////////////////////////////// |
// |
// Wishbone write cycle |
// |
130,7 → 148,7
|
endtask |
|
//////////////////////////////////////////////////////////////////// |
////////////////////////////////// |
// |
// Wishbone read cycle |
// |
169,7 → 187,7
|
endtask |
|
//////////////////////////////////////////////////////////////////// |
////////////////////////////////// |
// |
// Wishbone compare cycle (read data from location and compare with expected data) |
// |
188,6 → 206,6
end |
endtask |
|
endmodule |
endmodule : wb_master_model |
|
|
/trunk/rtl/sys_verilog/pit_regs.sv
36,8 → 36,7
//////////////////////////////////////////////////////////////////////////////// |
// 45678901234567890123456789012345678901234567890123456789012345678901234567890 |
|
module pit_regs #(parameter ARST_LVL = 1'b0, // asynchronous reset level |
parameter COUNT_SIZE = 16, |
module pit_regs #(parameter COUNT_SIZE = 16, |
parameter NO_PRESCALE = 1'b0, |
parameter DWIDTH = 16) |
( |
96,7 → 95,7
end |
else |
case (write_regs) // synopsys parallel_case |
4'b0011 : |
4'b0011 : // 16-bit write |
begin |
pit_slave <= write_data[15]; |
pit_pre <= write_data[11:8]; |
104,13 → 103,13
pit_ien <= write_data[1]; |
cnt_sync_o <= write_data[0]; |
end |
4'b0001 : |
4'b0001 : // 8-bit low byte write |
begin |
pit_flg_clr <= write_data[2]; |
pit_ien <= write_data[1]; |
cnt_sync_o <= write_data[0]; |
end |
4'b0010 : |
4'b0010 : // 8-bit high byte write |
begin |
pit_slave <= write_data[7]; |
pit_pre <= write_data[3:0]; |
/trunk/rtl/sys_verilog/pit_wb_bus.sv
36,33 → 36,67
//////////////////////////////////////////////////////////////////////////////// |
// 45678901234567890123456789012345678901234567890123456789012345678901234567890 |
|
module pit_wb_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level |
parameter DWIDTH = 16, |
parameter SINGLE_CYCLE = 1'b0) |
interface wishbone_if #(parameter D_WIDTH = 16, |
parameter A_WIDTH = 3) |
|
// These signals maintain their direction without regard to master or slave |
// Some signals may not be connected in every instance of the interface usage |
(logic [D_WIDTH-1:0] wb_dat_i, // databus input |
logic wb_clk, // master clock input |
|
// These signals will change direction based on interface usage |
logic arst, // asynchronous reset |
logic wb_rst, // synchronous active high reset |
logic [A_WIDTH-1:0] wb_adr, // lower address bits |
logic wb_we, // write enable input |
logic wb_cyc, // valid bus cycle input |
logic [2:0] wb_sel // Select bytes in word bus transaction |
); |
|
// Define the signal directions when the interface is used as a slave |
modport slave (input wb_clk, |
arst, |
wb_rst, |
wb_adr, |
wb_dat_i, |
wb_we, |
wb_cyc, |
wb_sel); |
|
// define the signal directions when the interface is used as a master |
modport master (output wb_adr, |
wb_we, |
wb_cyc, |
wb_sel, |
input wb_clk, |
wb_dat_i, |
arst, |
wb_rst); |
|
endinterface // wishbone_if |
|
module pit_wb_bus #(parameter D_WIDTH = 16, |
parameter S_WIDTH = 2, |
parameter A_WIDTH = 3, |
parameter ARST_LVL = 1'b0, // asynchronous reset level |
parameter SINGLE_CYCLE = 1'b0) // Add a wait state to bus transcation |
( |
// Wishbone Signals |
output logic [DWIDTH-1:0] wb_dat_o, // databus output - Pseudo Register |
output wb_ack_o, // bus cycle acknowledge output |
input wb_clk_i, // master clock input |
input wb_rst_i, // synchronous active high reset |
input arst_i, // asynchronous reset |
input [ 2:0] wb_adr_i, // lower address bits |
input [DWIDTH-1:0] wb_dat_i, // databus input |
input wb_we_i, // write enable input |
input wb_stb_i, // stobe/core select signal |
input wb_cyc_i, // valid bus cycle input |
input [1:0] wb_sel_i, // Select byte in word bus transaction |
wishbone_if.slave wb, // Define the interface instance name |
output logic [D_WIDTH-1:0] wb_dat_o, // databus output - Pseudo Register |
output logic wb_ack, // bus cycle acknowledge output |
input logic wb_stb, // stobe/core select signal |
// PIT Control Signals |
output logic [ 3:0] write_regs, // Decode write control register |
output async_rst_b, // |
output sync_reset, // |
input irq_source, // |
input [47:0] read_regs // status register bits |
output logic [ 3:0] write_regs, // Decode write control register |
output async_rst_b, // |
output sync_reset, // |
input irq_source, // |
input [47:0] read_regs // status register bits |
); |
|
|
// registers |
logic bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state |
logic bus_wait_state; // Holdoff wb_ack for one clock to add wait state |
logic [2:0] addr_latch; // Capture WISHBONE Address |
|
// Wires |
77,21 → 111,21
// |
|
// generate internal resets |
assign eight_bit_bus = (DWIDTH == 8); |
assign eight_bit_bus = (D_WIDTH == 8); |
|
assign async_rst_b = arst_i ^ ARST_LVL; |
assign sync_reset = wb_rst_i; |
assign async_rst_b = wb.arst ^ ARST_LVL; |
assign sync_reset = wb.wb_rst; |
|
// generate wishbone signals |
assign module_sel = wb_cyc_i && wb_stb_i; |
assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE); |
assign wb_racc = module_sel && !wb_we_i; |
assign wb_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel); |
assign address = SINGLE_CYCLE ? wb_adr_i : addr_latch; |
assign module_sel = wb.wb_cyc && wb_stb; |
assign wb_wacc = module_sel && wb.wb_we && (wb_ack || SINGLE_CYCLE); |
assign wb_racc = module_sel && !wb.wb_we; |
assign wb_ack = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel); |
assign address = SINGLE_CYCLE ? wb.wb_adr : addr_latch; |
|
// generate acknowledge output signal, By using register all accesses takes two cycles. |
// Accesses in back to back clock cycles are not possable. |
always_ff @(posedge wb_clk_i or negedge async_rst_b) |
always_ff @(posedge wb.wb_clk or negedge async_rst_b) |
if (!async_rst_b) |
bus_wait_state <= 1'b0; |
else if (sync_reset) |
101,9 → 135,10
|
// Capture address in first cycle of WISHBONE Bus tranaction |
// Only used when Wait states are enabled |
always_ff @(posedge wb_clk_i) |
// Synthesis tool should be enabled to remove these registers in SINGLE_CYCLE mode |
always_ff @(posedge wb.wb_clk) |
if ( module_sel ) // Clock gate for power saving |
addr_latch <= wb_adr_i; |
addr_latch <= wb.wb_adr; |
|
// WISHBONE Read Data Mux |
always_comb |
119,7 → 154,7
4'b0_000: wb_dat_o = read_regs[15: 0]; // 16 bit read access address 0 |
4'b0_001: wb_dat_o = read_regs[31:16]; |
4'b0_010: wb_dat_o = read_regs[47:32]; |
default: wb_dat_o = 0; |
default: wb_dat_o = '0; |
endcase |
|
// generate wishbone write register strobes -- one hot if 8 bit bus |
/trunk/rtl/sys_verilog/pit_top.sv
36,26 → 36,19
//////////////////////////////////////////////////////////////////////////////// |
// 45678901234567890123456789012345678901234567890123456789012345678901234567890 |
|
module pit_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level |
module pit_top #(parameter D_WIDTH = 16, |
parameter ARST_LVL = 1'b0, // asynchronous reset level |
parameter SINGLE_CYCLE = 1'b0, // Add a wait state to bus transcation |
parameter PRE_COUNT_SIZE = 15, // Prescale Counter size |
parameter COUNT_SIZE = 16, // Main counter size |
parameter DECADE_CNTR = 1'b1, // Prescale rollover decode |
parameter NO_PRESCALE = 1'b0, // Remove prescale function |
parameter SINGLE_CYCLE = 1'b0, // No bus wait state added |
parameter DWIDTH = 16) // Data bus width |
parameter NO_PRESCALE = 1'b0) // Remove prescale function |
( |
// Wishbone Signals |
output [DWIDTH-1:0] wb_dat_o, // databus output |
output wb_ack_o, // bus cycle acknowledge output |
input wb_clk_i, // master clock input |
input wb_rst_i, // synchronous active high reset |
input arst_i, // asynchronous reset |
input [2:0] wb_adr_i, // lower address bits |
input [DWIDTH-1:0] wb_dat_i, // databus input |
input wb_we_i, // write enable input |
input wb_stb_i, // stobe/core select signal |
input wb_cyc_i, // valid bus cycle input |
input [1:0] wb_sel_i, // Select byte in word bus transaction |
wishbone_if.slave wb, // Wishbone interface instance |
output logic [D_WIDTH-1:0] wb_dat_o, // databus output - Pseudo Register |
output logic wb_ack, // bus cycle acknowledge output |
input logic wb_stb, // stobe/core select signal |
// PIT IO Signals |
output pit_o, // PIT output pulse |
output pit_irq_o, // PIT interrupt request signal output |
77,28 → 70,30
logic pit_flag; // |
|
// Wishbone Bus interface |
pit_wb_bus #(.ARST_LVL(ARST_LVL), |
.SINGLE_CYCLE(SINGLE_CYCLE), |
.DWIDTH(DWIDTH)) |
pit_wb_bus #(.ARST_LVL (ARST_LVL), |
.D_WIDTH (D_WIDTH)) |
wishbone( |
.irq_source ( cnt_flag_o ), |
.read_regs ( // in -- status register bits |
{ cnt_n, |
mod_value, |
{pit_slave, DECADE_CNTR, NO_PRESCALE, 1'b0, pit_pre_scl, |
5'b0, cnt_flag_o, pit_ien, cnt_sync_o} |
} |
), |
// Wishbone Signals |
.wb ( wb ), |
.wb_stb ( wb_stb ), |
.wb_ack ( wb_ack ), |
.irq_source ( cnt_flag_o ), |
.read_regs ( // in -- status register bits |
{ cnt_n, |
mod_value, |
{pit_slave, DECADE_CNTR, NO_PRESCALE, 1'b0, pit_pre_scl, |
5'b0, cnt_flag_o, pit_ien, cnt_sync_o} |
} |
), |
.*); |
|
// ----------------------------------------------------------------------------- |
pit_regs #(.ARST_LVL(ARST_LVL), |
.COUNT_SIZE(COUNT_SIZE), |
pit_regs #(.COUNT_SIZE(COUNT_SIZE), |
.NO_PRESCALE(NO_PRESCALE), |
.DWIDTH(DWIDTH)) |
.D_WIDTH(D_WIDTH)) |
regs( |
.bus_clk ( wb_clk_i ), |
.write_bus ( wb_dat_i ), |
.bus_clk ( wb.wb_clk ), |
.write_bus ( wb.wb_dat ), |
.*); |
|
// ----------------------------------------------------------------------------- |
106,7 → 101,7
.DECADE_CNTR(DECADE_CNTR), |
.NO_PRESCALE(NO_PRESCALE)) |
prescale( |
.bus_clk ( wb_clk_i ), |
.bus_clk ( wb.wb_clk ), |
.divisor ( pit_pre_scl ), |
.*); |
|
113,7 → 108,7
// ----------------------------------------------------------------------------- |
pit_count #(.COUNT_SIZE(COUNT_SIZE)) |
counter( |
.bus_clk ( wb_clk_i ), |
.bus_clk ( wb.wb_clk ), |
.*); |
|
endmodule // pit_top |
/trunk/rtl/sys_verilog/pit_wb_if.sv
0,0 → 1,80
//////////////////////////////////////////////////////////////////////////////// |
// |
// WISHBONE revB.2 compliant -- Wishbone Bus interface |
// |
// Author: Bob Hayes |
// rehayes@opencores.org |
// |
// Downloaded from: http://www.opencores.org/projects/pit..... |
// |
//////////////////////////////////////////////////////////////////////////////// |
// Copyright (c) 2011, Robert Hayes |
// |
// All rights reserved. |
// |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// * Redistributions of source code must retain the above copyright |
// notice, this list of conditions and the following disclaimer. |
// * Redistributions in binary form must reproduce the above copyright |
// notice, this list of conditions and the following disclaimer in the |
// documentation and/or other materials provided with the distribution. |
// * Neither the name of the <organization> nor the |
// names of its contributors may be used to endorse or promote products |
// derived from this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY |
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY |
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
//////////////////////////////////////////////////////////////////////////////// |
// 45678901234567890123456789012345678901234567890123456789012345678901234567890 |
|
// The signal names lose their "_i", "_o" postfix since that is relative to |
// their usage in a specific instance declaration. |
|
interface wishbone_if #(parameter D_WIDTH = 16, |
parameter A_WIDTH = 3, |
parameter S_WIDTH = 2) |
|
// These signals are connected in the top-most instance instantation |
(input logic wb_clk, // master clock input |
input logic arst, // asynchronous reset |
input logic wb_rst); // synchronous active high reset |
|
// These signals are hierarchal to the instance instantation and bridge |
// between all the modules that use the same top-most instantiation. |
// These signals may change direction based on interface usage |
logic [D_WIDTH-1:0] wb_dat; // databus |
logic [A_WIDTH-1:0] wb_adr; // address bits |
logic wb_we; // write enable input |
logic wb_cyc; // valid bus cycle input |
logic [S_WIDTH-1:0] wb_sel; // Select bytes in word bus transaction |
|
// Define the signal directions when the interface is used as a slave |
modport slave (input wb_clk, |
arst, |
wb_rst, |
wb_adr, |
wb_we, |
wb_cyc, |
wb_sel, |
wb_dat); |
|
// define the signal directions when the interface is used as a master |
modport master (output wb_adr, |
wb_we, |
wb_cyc, |
wb_sel, |
wb_dat, |
input wb_clk, |
arst, |
wb_rst); |
|
endinterface // wishbone_if |
trunk/rtl/sys_verilog/pit_wb_if.sv
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/README.rtf
===================================================================
--- trunk/README.rtf (nonexistent)
+++ trunk/README.rtf (revision 24)
@@ -0,0 +1,23 @@
+{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf360
+{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
+{\colortbl;\red255\green255\blue255;}
+\margl1440\margr1440\vieww12120\viewh8240\viewkind0
+\pard\tx720\tx1440\tx2160\tx2880\tx3600\tx4320\tx5040\tx5760\tx6480\tx7200\tx7920\tx8640\ql\qnatural\pardirnatural
+
+\f0\fs24 \cf0 // 45678901234567890123456789012345678901234567890123456789012345678901234567890\
+////////////////////////////////////////////////////////////////////////////////\
+////////////////////////////////////////////////////////////////////////////////\
+// SVN tag: None\
+\
+Feb 10,2010\
+RTL - Update to the WISHBONE interface when wait states are enabled to trade 16 data flops for 3 address registers. This change now also requires single cycle timing on the WISHBONE address bus, multi-cycle timing is still allowed on the WISHBONE write data bus. In the old design WISHBONE read cycles required the address to be decoded and the read data to be latched in the first cycle and the there was a whole cycle to drive the read data bus. The new design latches the address in the first cycle then decodes the address and outputs the data in the second cycle. (The WISHBONE bus doesn't require the address or data to be latched for multi-cycle operation but by doing this it is hoped some power will be saved in the combinational logic by reducing the decoding activity at each address change.)\
+\
+Testbench - Minor change to add parameter to pit instance.\
+\
+Doc -\
+\
+July 31, 2011\
+Added rtl/sys_verilog and bench/verilog/sys_verilog directories. This is the first pass at an upgrade to System Verilog. The changes were to uses new types, "logic" and "bit", new always blocks, "always_ff "and "always_comb", and ".*" for signal name passing. \
+\
+Oct 24, 2011\
+Updated the rtl/sys_verilog directory to include a Wishbone "interface". The bench/sys_verilog was also updated to include the Wishbone interface. Because there are four different instances of the pit module(based on i/o connections and parameters) the test bench required four different instances of the Wishbone interface to connect each pit instance. Because of this there was no significant reduction in the lines of code required in the testbench, and shows some of the pitfalls to be encountered when you get outside of the box of using interfaces as taught in class examples.}
\ No newline at end of file