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  • This comparison shows the changes necessary to convert path 
    /pltbutils/tags/alpha0004/example/vhdl
    from Rev 15 to Rev 20
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Rev 15 → Rev 20

/tb_example.vhd
0,0 → 1,144
----------------------------------------------------------------------
---- ----
---- PlTbUtils Example Testbench ----
---- ----
---- This file is part of the PlTbUtils project ----
---- http://opencores.org/project,pltbutils ----
---- ----
---- Description: ----
---- PlTbUtils is a collection of functions, procedures and ----
---- components for easily creating stimuli and checking response ----
---- in automatic self-checking testbenches. ----
---- ----
---- This file is an example which demonstrates how PlTbUtils ----
---- can be used. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Per Larsson, pela@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.txt_util.all;
use work.pltbutils_func_pkg.all;
use work.pltbutils_comp_pkg.all;
 
entity tb_example is
generic (
G_WIDTH : integer := 8;
G_CLK_PERIOD : time := 10 ns;
G_DISABLE_BUGS : integer range 0 to 1 := 0
);
end entity tb_example;
 
architecture bhv of tb_example is
 
-- Simulation status- and control signals
signal test_num : integer;
-- VHDL-1993:
--signal test_name : string(pltbutils_test_name'range);
--signal info : string(pltbutils_info'range);
-- VHDL-2002:
signal test_name : string(pltbutils_sc.test_name'range);
signal info : string(pltbutils_sc.info'range);
 
signal checks : integer;
signal errors : integer;
signal stop_sim : std_logic;
-- DUT stimuli and response signals
signal clk : std_logic;
signal rst : std_logic;
signal carry_in : std_logic;
signal x : std_logic_vector(G_WIDTH-1 downto 0);
signal y : std_logic_vector(G_WIDTH-1 downto 0);
signal sum : std_logic_vector(G_WIDTH-1 downto 0);
signal carry_out : std_logic;
begin
 
-- Simulation status and control for viewing in waveform window
-- VHDL-1993:
--test_num <= pltbutils_test_num;
--test_name <= pltbutils_test_name;
--checks <= pltbutils_chk_cnt;
--errors <= pltbutils_err_cnt;
-- VHDL-2002:
test_num <= pltbutils_sc.test_num;
test_name <= pltbutils_sc.test_name;
info <= pltbutils_sc.info;
checks <= pltbutils_sc.chk_cnt;
errors <= pltbutils_sc.err_cnt;
stop_sim <= pltbutils_sc.stop_sim;
dut0 : entity work.dut_example
generic map (
G_WIDTH => G_WIDTH,
G_DISABLE_BUGS => G_DISABLE_BUGS
)
port map (
clk_i => clk,
rst_i => rst,
carry_i => carry_in,
x_i => x,
y_i => y,
sum_o => sum,
carry_o => carry_out
);
clkgen0 : pltbutils_clkgen
generic map(
G_PERIOD => G_CLK_PERIOD
)
port map(
clk_o => clk,
stop_sim_i => stop_sim
);
tc0 : entity work.tc_example
generic map (
G_WIDTH => G_WIDTH,
G_DISABLE_BUGS => G_DISABLE_BUGS
)
port map(
clk => clk,
rst => rst,
carry_in => carry_in,
x => x,
y => y,
sum => sum,
carry_out => carry_out
);
end architecture bhv;
/tc_example.vhd
0,0 → 1,66
----------------------------------------------------------------------
---- ----
---- PlTbUtils Example Testcase Entity for Example Testbench ----
---- ----
---- This file is part of the PlTbUtils project ----
---- http://opencores.org/project,pltbutils ----
---- ----
---- Description: ----
---- PlTbUtils is a collection of functions, procedures and ----
---- components for easily creating stimuli and checking response ----
---- in automatic self-checking testbenches. ----
---- ----
---- This file is an example which demonstrates how PlTbUtils ----
---- can be used. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Per Larsson, pela@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity tc_example is
generic (
G_WIDTH : integer := 8;
G_DISABLE_BUGS : integer range 0 to 1 := 0
);
port (
clk : in std_logic;
rst : out std_logic;
carry_in : out std_logic;
x : out std_logic_vector(G_WIDTH-1 downto 0);
y : out std_logic_vector(G_WIDTH-1 downto 0);
sum : in std_logic_vector(G_WIDTH-1 downto 0);
carry_out : in std_logic
);
end entity tc_example;
/tc1.vhd
0,0 → 1,106
----------------------------------------------------------------------
---- ----
---- PlTbUtils Example Testcase Architecture for ----
---- Example Testbench ----
---- ----
---- This file is part of the PlTbUtils project ----
---- http://opencores.org/project,pltbutils ----
---- ----
---- Description: ----
---- PlTbUtils is a collection of functions, procedures and ----
---- components for easily creating stimuli and checking response ----
---- in automatic self-checking testbenches. ----
---- ----
---- This file is a template, which can be used as a base when ----
---- testbenches which use PlTbUtils. ----
---- Copy this file to your preferred location and rename the ----
---- copied file and its contents, by replacing the word ----
---- "template" with a name for your design. ----
---- Also remove informative comments enclosed in < ... > . ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Per Larsson, pela@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pltbutils_func_pkg.all;
 
-- NOTE: The purpose of the following code is to demonstrate some of the
-- features in PlTbUtils, not to do a thorough verification.
architecture tc1 of tc_example is
begin
p_tc1 : process
begin
startsim("tc1", pltbutils_sc);
rst <= '1';
carry_in <= '0';
x <= (others => '0');
y <= (others => '0');
testname(1, "Reset test", pltbutils_sc);
waitclks(2, clk, pltbutils_sc);
check("Sum during reset", sum, 0, pltbutils_sc);
check("Carry out during reset", carry_out, '0', pltbutils_sc);
rst <= '0';
testname(2, "Simple sum test", pltbutils_sc);
carry_in <= '0';
x <= std_logic_vector(to_unsigned(1, x'length));
y <= std_logic_vector(to_unsigned(2, x'length));
waitclks(2, clk, pltbutils_sc);
check("Sum", sum, 3, pltbutils_sc);
check("Carry out", carry_out, '0', pltbutils_sc);
testname(3, "Simple carry in test", pltbutils_sc);
print(G_DISABLE_BUGS=0, pltbutils_sc, "Bug here somewhere");
carry_in <= '1';
x <= std_logic_vector(to_unsigned(1, x'length));
y <= std_logic_vector(to_unsigned(2, x'length));
waitclks(2, clk, pltbutils_sc);
check("Sum", sum, 4, pltbutils_sc);
check("Carry out", carry_out, '0', pltbutils_sc);
print(pltbutils_sc, "");
 
testname(4, "Simple carry out test", pltbutils_sc);
carry_in <= '0';
x <= std_logic_vector(to_unsigned(2**G_WIDTH-1, x'length));
y <= std_logic_vector(to_unsigned(1, x'length));
waitclks(2, clk, pltbutils_sc);
check("Sum", sum, 0, pltbutils_sc);
check("Carry out", carry_out, '1', pltbutils_sc);
 
endsim(pltbutils_sc, true);
wait;
end process p_tc1;
end architecture tc1;
/tb_example_files.lst
0,0 → 1,3
tc_example.vhd
tc1.vhd
tb_example.vhd
/dut_example.vhd
0,0 → 1,100
----------------------------------------------------------------------
---- ----
---- PlTbUtils Example DUT ----
---- ----
---- This file is part of the PlTbUtils project ----
---- http://opencores.org/project,pltbutils ----
---- ----
---- Description: ----
---- PlTbUtils is a collection of functions, procedures and ----
---- components for easily creating stimuli and checking response ----
---- in automatic self-checking testbenches. ----
---- ----
---- This file is an example component for use as DUT ----
---- (Device Under Test) in tb_example.vhd, which demonstrates ----
---- how PlTbUtils can be used. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Per Larsson, pela@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity dut_example is
generic (
G_WIDTH : integer := 8;
G_DISABLE_BUGS : integer range 0 to 1 := 1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
carry_i : in std_logic;
x_i : in std_logic_vector(G_WIDTH-1 downto 0);
y_i : in std_logic_vector(G_WIDTH-1 downto 0);
sum_o : out std_logic_vector(G_WIDTH-1 downto 0);
carry_o : out std_logic
);
end entity dut_example;
 
architecture rtl of dut_example is
signal x : unsigned(G_WIDTH downto 0);
signal y : unsigned(G_WIDTH downto 0);
signal c : unsigned(G_WIDTH downto 0);
signal sum : unsigned(G_WIDTH downto 0);
begin
 
x <= resize(unsigned(x_i), G_WIDTH+1);
y <= resize(unsigned(y_i), G_WIDTH+1);
c <= resize(unsigned(std_logic_vector'('0' & carry_i)), G_WIDTH+1);
p_sum : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
sum <= (others => '0');
else
if G_DISABLE_BUGS = 1 then
sum <= x + y + c;
else
sum <= x + y;
end if;
end if;
end if;
end process;
sum_o <= std_logic_vector(sum(sum'high-1 downto 0));
carry_o <= sum(sum'high);
end architecture rtl;
 
/dut_example_files.lst
0,0 → 1,100
dut_example.vhd

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