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    /potato/branches
    from Rev 39 to Rev 40
    Reverse comparison

Rev 39 → Rev 40

/cache-playground/example/toplevel.vhd
209,8 → 209,8
uart1: entity work.pp_soc_uart
generic map(
FIFO_DEPTH => 64,
--SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz
SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz
SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz
--SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz
) port map(
clk => system_clk,
reset => reset,
301,7 → 301,7
else
case ad_state is
when IDLE =>
if p_cyc_out = '1' and p_stb_out = '1' then
if p_cyc_out = '1' then
if p_adr_out(31 downto 13) = b"0000000000000000000" then
active_module <= MODULE_IMEM;
ad_state <= BUSY;
324,6 → 324,8
active_module <= MODULE_DUMMY;
ad_state <= BUSY;
end if;
else
active_module <= MODULE_NONE;
end if;
when BUSY =>
if p_cyc_out = '0' then
/cache-playground/benchmarks/platform.h
9,7 → 9,7
#define PLATFORM_H
 
// Clock frequency in Hz:
#define SYSTEM_CLK_FREQ 60000000
#define SYSTEM_CLK_FREQ 50000000
 
// Macro for using the addresses below in C code:
#define IO_ADDRESS(x) ((volatile void *) x)

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