URL
https://opencores.org/ocsvn/potato/potato/trunk
Subversion Repositories potato
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- This comparison shows the changes necessary to convert path
/potato/branches
- from Rev 50 to Rev 51
- ↔ Reverse comparison
Rev 50 → Rev 51
/new-privileged-isa/tests/timer.S
0,0 → 1,56
# The Potato Processor - A simple RISC-V based processor for FPGAs |
# (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net> |
# Report bugs and issues on <http://opencores.org/project,potato,bugtracker> |
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# Simplified timer interrupt test. |
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#include "riscv_test.h" |
#include "test_macros.h" |
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#define TIMER_DELTA_T 10 |
#define MIE_STIE MIP_STIP |
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RVTEST_RV32M |
RVTEST_CODE_BEGIN |
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li s8, 0 # Number of timer interrupts taken |
li s9, 10 # Number of timer interrupts to wait for |
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# Set the time of the next timer interrupt: |
csrr a0, mtime |
addi a0, a0, TIMER_DELTA_T |
csrw mtimecmp, a0 |
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# Enable the timer interrupt: |
li a0, (1 << 7) |
csrs mie, a0 |
csrs mstatus, MSTATUS_IE |
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wait_for_count: |
# TODO: wfi not yet supported |
j wait_for_count |
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mtvec_handler: |
li t0, (1 << 31) + 1 # Interrupt bit set + timer interrupt exception code |
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csrr t1, mcause |
bne t0, t1, fail # Fail if not timer interrupt |
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addi s8, s8, 1 |
beq s8, s9, pass # Pass the test if the correct number of interrupts have been taken |
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# Reset the timer: |
csrr a0, mtime |
addi a0, a0, TIMER_DELTA_T |
csrw mtimecmp, a0 |
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eret |
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TEST_PASSFAIL |
RVTEST_CODE_END |
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.data |
RVTEST_DATA_BEGIN |
TEST_DATA |
RVTEST_DATA_END |
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/new-privileged-isa/riscv-tests/scall.S
0,0 → 1,49
# See LICENSE for license details. |
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#***************************************************************************** |
# scall.S |
#----------------------------------------------------------------------------- |
# |
# Test syscall trap. |
# |
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#include "riscv_test.h" |
#include "test_macros.h" |
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RVTEST_RV32M |
RVTEST_CODE_BEGIN |
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#define sscratch mscratch |
#define sstatus mstatus |
#define scause mcause |
#define sepc mepc |
#define stvec_handler mtvec_handler |
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#undef CAUSE_SUPERVISOR_ECALL |
#define CAUSE_SUPERVISOR_ECALL CAUSE_MACHINE_ECALL |
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li TESTNUM, 2 |
scall |
j fail |
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j pass |
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TEST_PASSFAIL |
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stvec_handler: |
li t1, CAUSE_SUPERVISOR_ECALL |
csrr t0, scause |
bne t0, t1, fail |
csrr t0, sepc |
addi t0, t0, 8 |
csrw sepc, t0 |
sret |
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RVTEST_CODE_END |
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.data |
RVTEST_DATA_BEGIN |
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TEST_DATA |
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RVTEST_DATA_END |
/new-privileged-isa/riscv-tests/sbreak.S
0,0 → 1,46
# See LICENSE for license details. |
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#***************************************************************************** |
# scall.S |
#----------------------------------------------------------------------------- |
# |
# Test syscall trap. |
# |
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#include "riscv_test.h" |
#include "test_macros.h" |
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RVTEST_RV32M |
RVTEST_CODE_BEGIN |
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#define sscratch mscratch |
#define sstatus mstatus |
#define scause mcause |
#define sepc mepc |
#define stvec_handler mtvec_handler |
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li TESTNUM, 2 |
sbreak |
j fail |
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j pass |
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TEST_PASSFAIL |
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stvec_handler: |
li t1, CAUSE_BREAKPOINT |
csrr t0, scause |
bne t0, t1, fail |
csrr t0, sepc |
addi t0, t0, 8 |
csrw sepc, t0 |
sret |
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RVTEST_CODE_END |
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.data |
RVTEST_DATA_BEGIN |
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TEST_DATA |
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RVTEST_DATA_END |
/new-privileged-isa/Makefile
39,7 → 39,6
# ISA tests to use from the riscv-tests repository: |
RISCV_TESTS += \ |
simple \ |
ma_addr \ |
add \ |
addi \ |
and \ |
75,10 → 74,14
lbu \ |
lh \ |
lhu \ |
lw |
lw \ |
ma_addr \ |
sbreak \ |
scall |
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# Local tests to run: |
LOCAL_TESTS ?= \ |
timer \ |
sw-jal |
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all: potato.prj run-tests |