OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /potato/trunk/testbenches
    from Rev 7 to Rev 58
    ↔ Reverse comparison
  •

Rev 7 → Rev 58

/tb_processor.vhd
12,54 → 12,25
 
entity tb_processor is
generic(
IMEM_SIZE : natural := 2048; --! Size of the instruction memory in bytes.
DMEM_SIZE : natural := 2048; --! Size of the data memory in bytes.
IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
IMEM_SIZE : natural := 4096; --! Size of the instruction memory in bytes.
DMEM_SIZE : natural := 4096; --! Size of the data memory in bytes.
RESET_ADDRESS : std_logic_vector := x"00000200"; --! Processor reset address
IMEM_START_ADDR : std_logic_vector := x"00000100"; --! Instruction memory start address
IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
);
end entity tb_processor;
 
architecture testbench of tb_processor is
 
-- Processor component prototype:
component pp_core is
port(
-- Common inputs:
clk : in std_logic; --! Processor clock
reset : in std_logic; --! Reset signal
timer_clk : in std_logic; --! Timer clock input
-- Instruction memory interface:
imem_address : out std_logic_vector(31 downto 0); --! Address of the next instruction
imem_data_in : in std_logic_vector(31 downto 0); --! Instruction input
imem_req : out std_logic;
imem_ack : in std_logic;
 
-- Data memory interface:
dmem_address : out std_logic_vector(31 downto 0); --! Data address
dmem_data_in : in std_logic_vector(31 downto 0); --! Input from the data memory
dmem_data_out : out std_logic_vector(31 downto 0); --! Ouptut to the data memory
dmem_data_size : out std_logic_vector( 1 downto 0); --! Size of the data, 1 = 8 bits, 2 = 16 bits, 0 = 32 bits.
dmem_read_req : out std_logic; --! Data memory read request
dmem_read_ack : in std_logic; --! Data memory read acknowledge
dmem_write_req : out std_logic; --! Data memory write request
dmem_write_ack : in std_logic; --! Data memory write acknowledge
 
-- Tohost/fromhost interface:
fromhost_data : in std_logic_vector(31 downto 0); --! Data from the host/simulator.
fromhost_write_en : in std_logic; --! Write enable signal from the host/simulator.
tohost_data : out std_logic_vector(31 downto 0); --! Data to the host/simulator.
tohost_write_en : out std_logic; --! Write enable signal to the host/simulator.
 
-- External interrupt input:
irq : in std_logic_vector(7 downto 0) --! IRQ input
);
end component pp_core;
 
-- Clock signal:
signal clk : std_logic := '0';
constant clk_period : time := 10 ns;
 
-- Timer clock signal:
signal timer_clk : std_logic := '0';
constant timer_clk_period : time := 100 ns;
 
-- Common inputs:
signal reset : std_logic := '1';
 
92,9 → 63,9
-- Memory array type:
type memory_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant IMEM_BASE : natural := 0;
constant IMEM_END : natural := IMEM_SIZE - 1;
constant DMEM_BASE : natural := IMEM_SIZE;
constant DMEM_END : natural := IMEM_SIZE + DMEM_SIZE - 1;
constant IMEM_END : natural := IMEM_BASE + IMEM_SIZE - 1;
constant DMEM_BASE : natural := IMEM_END + 1;
constant DMEM_END : natural := IMEM_END + DMEM_SIZE;
 
-- Memories:
signal imem_memory : memory_array(IMEM_BASE to IMEM_END);
104,11 → 75,13
 
begin
 
uut: pp_core
port map(
uut: entity work.pp_core
generic map(
RESET_ADDRESS => RESET_ADDRESS
) port map(
clk => clk,
reset => reset,
timer_clk => clk,
timer_clk => timer_clk,
imem_address => imem_address,
imem_data_in => imem_data_in,
imem_req => imem_req,
140,6 → 113,18
end if;
end process clock;
 
timer_clock: process
begin
timer_clk <= '0';
wait for timer_clk_period / 2;
timer_clk <= '1';
wait for timer_clk_period / 2;
 
if simulation_finished then
wait;
end if;
end process timer_clock;
 
--! Initializes the instruction memory from file.
imem_init: process
file imem_file : text open READ_MODE is IMEM_FILENAME;
147,7 → 132,8
variable input_index : natural;
variable input_value : std_logic_vector(31 downto 0);
begin
for i in IMEM_BASE / 4 to IMEM_END / 4 loop
for i in to_integer(unsigned(IMEM_START_ADDR)) / 4 to IMEM_END / 4 loop
--for i in IMEM_BASE / 4 to IMEM_END / 4 loop
if not endfile(imem_file) then
readline(imem_file, input_line);
hread(input_line, input_value);
211,7 → 197,7
when b"10" => -- 16 bits
dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out( 7 downto 0);
dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
when others => -- Reserved for possible future 64 bit support
when others =>
end case;
dmem_write_ack <= '1';
end if;
259,7 → 245,7
dmem_data_in( 7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)) + 0);
when b"01" => -- 8 bits
dmem_data_in(7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)));
when others => -- Reserved for possible future 64 bit support
when others =>
end case;
dmem_read_ack <= '1';
end if;
/tb_soc.vhd
14,10 → 14,12
--! @brief Testbench providing a full SoC architecture connected with a Wishbone bus.
entity tb_soc is
generic(
IMEM_SIZE : natural := 2048; --! Size of the instruction memory in bytes.
DMEM_SIZE : natural := 2048; --! Size of the data memory in bytes.
IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
IMEM_SIZE : natural := 4096; --! Size of the instruction memory in bytes.
DMEM_SIZE : natural := 4096; --! Size of the data memory in bytes.
RESET_ADDRESS : std_logic_vector := x"00000200"; --! Processor reset address
IMEM_START_ADDR : std_logic_vector := x"00000100"; --! Instruction memory start address
IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
);
end entity tb_soc;
 
27,6 → 29,9
signal clk : std_logic;
constant clk_period : time := 10 ns;
 
signal timer_clk : std_logic;
constant timer_clk_period : time := 100 ns;
 
-- Reset:
signal reset : std_logic := '1';
 
93,9 → 98,12
begin
 
processor: entity work.pp_potato
port map(
generic map(
RESET_ADDRESS => RESET_ADDRESS
) port map(
clk => clk,
reset => processor_reset,
timer_clk => timer_clk,
irq => irq,
fromhost_data => fromhost_data,
fromhost_updated => fromhost_updated,
200,17 → 208,18
variable input_value : std_logic_vector(31 downto 0);
variable temp : std_logic_vector(31 downto 0);
constant DMEM_START : natural := IMEM_SIZE;
constant DMEM_START_ADDR : natural := IMEM_SIZE;
begin
if not initialized then
-- Read the instruction memory file:
for i in 0 to IMEM_SIZE loop
for i in 0 to (IMEM_SIZE / 4) - 1 loop
exit when endfile(imem_file);
 
readline(imem_file, input_line);
hread(input_line, input_value);
 
init_adr_out <= std_logic_vector(to_unsigned(i * 4, init_adr_out'length));
init_adr_out <= std_logic_vector(to_unsigned(to_integer(unsigned(IMEM_START_ADDR)) + (i * 4),
init_adr_out'length));
init_dat_out <= input_value;
init_cyc_out <= '1';
init_stb_out <= '1';
226,13 → 235,12
wait for clk_period;
 
-- Read the data memory file:
for i in 0 to DMEM_SIZE loop
for i in 0 to (DMEM_SIZE / 4) - 1 loop
exit when endfile(dmem_file);
readline(dmem_file, input_line);
hread(input_line, input_value);
 
 
-- Swap endianness, TODO: prevent this, fix scripts/extract_hex.sh
temp(7 downto 0) := input_value(31 downto 24);
temp(15 downto 8) := input_value(23 downto 16);
241,7 → 249,7
 
input_value := temp;
 
init_adr_out <= std_logic_vector(to_unsigned(DMEM_START + (i * 4), init_adr_out'length));
init_adr_out <= std_logic_vector(to_unsigned(DMEM_START_ADDR + (i * 4), init_adr_out'length));
init_dat_out <= input_value;
init_cyc_out <= '1';
init_stb_out <= '1';
273,6 → 281,18
end if;
end process clock;
 
timer_clock: process
begin
timer_clk <= '1';
wait for timer_clk_period / 2;
timer_clk <= '0';
wait for timer_clk_period / 2;
 
if simulation_finished then
wait;
end if;
end process timer_clock;
 
stimulus: process
begin
wait for clk_period * 2;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.