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    /potato/trunk
    from Rev 11 to Rev 12
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Rev 11 → Rev 12

/example/tb_toplevel.vhd
0,0 → 1,58
-- Practical Test Application for the Potato Processor
-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
 
entity tb_toplevel is
end entity tb_toplevel;
 
architecture testbench of tb_toplevel is
 
signal clk : std_logic;
constant clk_period : time := 10 ns;
signal reset_n : std_logic := '0';
signal external_interrupt : std_logic := '0';
signal switches : std_logic_vector(15 downto 0);
signal leds : std_logic_vector(15 downto 0);
 
signal uart_rxd : std_logic := '1';
signal uart_txd : std_logic;
 
begin
 
switches <= x"a0a0";
 
uut: entity work.toplevel
port map(
clk => clk,
reset_n => reset_n,
external_interrupt => external_interrupt,
switches => switches,
leds => leds,
uart_rxd => uart_rxd,
uart_txd => uart_txd
);
 
clock: process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process clock;
 
stimulus: process
begin
wait for clk_period * 125;
reset_n <= '0';
wait for clk_period * 3;
reset_n <= '1';
 
wait;
end process stimulus;
 
end architecture testbench;
/example/imem_wrapper.vhd
1,6 → 1,6
-- Practical Test Application for the Potato Processor
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato-test/issues>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
/example/toplevel.vhd
1,6 → 1,6
-- Practical Test Application for the Potato Processor
-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato-test/issues>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
/example/tb_imem_wrapper.vhd
0,0 → 1,69
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
 
entity tb_imem_wrapper is
end entity tb_imem_wrapper;
 
architecture testbench of tb_imem_wrapper is
 
-- Clock signal:
signal clk : std_logic := '0';
constant clk_period : time := 10 ns;
 
-- Reset signal:
signal reset : std_logic := '1';
-- Wishbone signals:
signal wb_adr_in : std_logic_vector(10 downto 0);
signal wb_dat_out : std_logic_vector(31 downto 0);
signal wb_cyc_in : std_logic := '0';
signal wb_stb_in : std_logic := '0';
signal wb_ack_out : std_logic;
 
begin
 
uut: entity work.imem_wrapper
port map(
clk => clk,
reset => reset,
wb_adr_in => wb_adr_in,
wb_dat_out => wb_dat_out,
wb_cyc_in => wb_cyc_in,
wb_stb_in => wb_stb_in,
wb_ack_out => wb_ack_out
);
 
clock: process
begin
clk <= '1';
wait for clk_period;
clk <= '0';
wait for clk_period;
end process clock;
 
stimulus: process
begin
wait for clk_period * 2;
reset <= '0';
wait for clk_period;
 
-- Read an instruction:
wb_adr_in <= (others => '0');
wb_cyc_in <= '1';
wb_stb_in <= '1';
wait for clk_period;
wait until wb_ack_out = '1';
wait for clk_period;
wb_cyc_in <= '0';
wb_stb_in <= '0';
 
-- TODO: Make testbench automated.
 
wait;
end process stimulus;
 
end architecture testbench;
/example/README
6,11 → 6,12
## Quick Start
 
In order to use the design, first import all source files from the folders
`src/`, `soc/` and `example/` into your project.
`src/`, `soc/` and `example/` into your project. Make sure the testbench files
(the files starting with "tb_") is added as simulation-only files.
 
### Clocking
 
Then add a clock generator using the Clocking Wizard. To seamlessly integrate
Add a clock generator using the Clocking Wizard. To seamlessly integrate
it into the design, name it "clock_generator". Choose the following options:
 
* Frequency Synthesis
26,7 → 27,7
Choose "Single Port ROM" as memory type, name it "instruction_rom" and set
port A width to 32 bits and port A depth to 2048. Initialize it with your
application binary and, optionally, fill the remaining memory locations with
0x00000013.
0x00000013 (no-operation opcode).
 
### Test it!
 
/example/nexys4_constraints.xdc
1,8 → 1,8
# Practical Test Application for the Potato Processor
# (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
# Report bugs and issues on <https://github.com/skordal/potato-test/issues>
# The Potato Processor - A simple processor for FPGAs
# (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
# Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
# Operating conditions:
# Set operating conditions to improve temperature estimation:
set_operating_conditions -airflow 0
set_operating_conditions -heatsink low
 
91,4 → 91,4
set_property PACKAGE_PIN R2 [get_ports {leds[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[14]}]
set_property PACKAGE_PIN P2 [get_ports {leds[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[15]}]

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