URL
https://opencores.org/ocsvn/potato/potato/trunk
Subversion Repositories potato
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- This comparison shows the changes necessary to convert path
/potato/trunk
- from Rev 20 to Rev 21
- ↔ Reverse comparison
Rev 20 → Rev 21
/example/toplevel.vhd
108,7 → 108,7
MODULE_UART, -- UART module |
MODULE_TIMER, -- Timer module |
MODULE_DUMMY, -- Dummy module, used for invalid addresses |
MODULE_NONE -- Boring no-module mode, uses the dummy module |
MODULE_NONE -- Boring no-module mode |
); |
signal active_module : module_name; |
|
209,7 → 209,8
uart1: entity work.pp_soc_uart |
generic map( |
FIFO_DEPTH => 64, |
SAMPLE_CLK_DIVISOR => 27 |
--SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz |
SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz |
) port map( |
clk => system_clk, |
reset => reset, |
320,7 → 321,6
active_module <= MODULE_TIMER; |
ad_state <= BUSY; |
else |
--active_module <= MODULE_NONE; |
active_module <= MODULE_DUMMY; |
ad_state <= BUSY; |
end if; |
/example/README
17,7 → 17,7
* Frequency Synthesis |
* Safe Clock Startup |
|
Set up two output clocks, `clk_out1` with frequency 50 MHz, and `clk_out2` with |
Set up two output clocks, `clk_out1` with frequency 60 MHz, and `clk_out2` with |
a frequency of 10 MHz. Rename the corresponding ports to `system_clk` and |
`timer_clk` respectively. Name the input clock `clk`. |
|
/benchmarks/platform.h
9,7 → 9,7
#define PLATFORM_H |
|
// Clock frequency in Hz: |
#define SYSTEM_CLK_FREQ 50000000 |
#define SYSTEM_CLK_FREQ 60000000 |
|
// Macro for using the addresses below in C code: |
#define IO_ADDRESS(x) ((volatile void *) x) |