OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /potato/trunk
    from Rev 45 to Rev 58
    ↔ Reverse comparison
  •

Rev 45 → Rev 58

/tests.ld
9,17 → 9,18
* 2048 bytes (each) of separate instruction and data memory.
*/
 
OUTPUT_ARCH(riscv);
ENTRY(_start);
 
SECTIONS
{
.text 0x0 :
.text 0x100 :
{
*(.init*)
*(.text*)
*(.text.init)
*(.text)
}
 
.data 0x800 :
.data 0x1000 :
{
__data_begin = .;
*(.data*)
33,6 → 34,6
}
__data_end = .;
 
__stack_top = 0x1000;
__stack_top = 0x2000;
}
 
/tests/scall.S File deleted
/tests/sbreak.S File deleted
/tests/timer.S
0,0 → 1,56
# The Potato Processor - A simple RISC-V based processor for FPGAs
# (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
# Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
# Simplified timer interrupt test.
 
#include "riscv_test.h"
#include "test_macros.h"
 
#define TIMER_DELTA_T 10
#define MIE_STIE MIP_STIP
 
RVTEST_RV32M
RVTEST_CODE_BEGIN
 
li s8, 0 # Number of timer interrupts taken
li s9, 10 # Number of timer interrupts to wait for
 
# Set the time of the next timer interrupt:
csrr a0, mtime
addi a0, a0, TIMER_DELTA_T
csrw mtimecmp, a0
 
# Enable the timer interrupt:
li a0, (1 << 7)
csrs mie, a0
csrs mstatus, MSTATUS_IE
 
wait_for_count:
# TODO: wfi not yet supported
j wait_for_count
 
mtvec_handler:
li t0, (1 << 31) + 1 # Interrupt bit set + timer interrupt exception code
 
csrr t1, mcause
bne t0, t1, fail # Fail if not timer interrupt
addi s8, s8, 1
beq s8, s9, pass # Pass the test if the correct number of interrupts have been taken
 
# Reset the timer:
csrr a0, mtime
addi a0, a0, TIMER_DELTA_T
csrw mtimecmp, a0
 
eret
 
TEST_PASSFAIL
RVTEST_CODE_END
 
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
 
/tests/sw-jal.S
6,7 → 6,7
#include "test_macros.h"
 
.section .text
RVTEST_RV32U
RVTEST_RV32M
RVTEST_CODE_BEGIN
 
test_1:
33,9 → 33,14
test_failed:
RVTEST_FAIL
.section .data
RVTEST_DATA_BEGIN
TEST_DATA
 
# Allocate a 32-bit word to store some data into
.section .data
#.section .data
temp:
.word 0x00000000
 
RVTEST_DATA_END
 
/riscv-tests/hwacha_xcpt.h
0,0 → 1,21
// See LICENSE for license details.
 
#ifndef _HWACHA_XCPT_H
#define _HWACHA_XCPT_H
 
#include "encoding.h"
 
#define HWACHA_CAUSE_ILLEGAL_CFG CAUSE_ILLEGAL_INSTRUCTION // AUX: 0=illegal nxpr, 1=illegal nfpr
#define HWACHA_CAUSE_ILLEGAL_INSTRUCTION CAUSE_ILLEGAL_INSTRUCTION // AUX: instruction
#define HWACHA_CAUSE_PRIVILEGED_INSTRUCTION CAUSE_ILLEGAL_INSTRUCTION // AUX: instruction
#define HWACHA_CAUSE_TVEC_ILLEGAL_REGID CAUSE_ILLEGAL_INSTRUCTION // AUX: instruction
#define HWACHA_CAUSE_VF_MISALIGNED_FETCH CAUSE_MISALIGNED_FETCH // AUX: pc
#define HWACHA_CAUSE_VF_FAULT_FETCH CAUSE_FAULT_FETCH // AUX: pc
#define HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION CAUSE_ILLEGAL_INSTRUCTION // AUX: pc
#define HWACHA_CAUSE_VF_ILLEGAL_REGID CAUSE_ILLEGAL_INSTRUCTION // AUX: pc
#define HWACHA_CAUSE_MISALIGNED_LOAD CAUSE_MISALIGNED_LOAD // AUX: badvaddr
#define HWACHA_CAUSE_MISALIGNED_STORE CAUSE_MISALIGNED_STORE // AUX: badvaddr
#define HWACHA_CAUSE_FAULT_LOAD CAUSE_FAULT_LOAD // AUX: badvaddr
#define HWACHA_CAUSE_FAULT_STORE CAUSE_FAULT_STORE // AUX: badvaddr
 
#endif
/riscv-tests/ma_addr.S
0,0 → 1,106
# See LICENSE for license details.
 
#*****************************************************************************
# ma_addr.S
#-----------------------------------------------------------------------------
#
# Test misaligned ld/st trap.
#
 
#include "riscv_test.h"
#include "test_macros.h"
 
#include "riscv_test.h"
#undef RVTEST_RV64S
#define RVTEST_RV64S RVTEST_RV32M
#define __MACHINE_MODE
 
RVTEST_RV32M
RVTEST_CODE_BEGIN
 
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
#define sepc mepc
#define stvec_handler mtvec_handler
 
la s0, stvec_handler
 
# indicate it's a load test
li s1, 0
 
#define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
li TESTNUM, testnum; \
insn x0, offset(base); \
j fail \
 
MISALIGNED_LDST_TEST(2, lh, s0, 1)
MISALIGNED_LDST_TEST(3, lhu, s0, 1)
MISALIGNED_LDST_TEST(4, lw, s0, 1)
MISALIGNED_LDST_TEST(5, lw, s0, 2)
MISALIGNED_LDST_TEST(6, lw, s0, 3)
 
#ifdef __riscv64
MISALIGNED_LDST_TEST(7, lwu, s0, 1)
MISALIGNED_LDST_TEST(8, lwu, s0, 2)
MISALIGNED_LDST_TEST(9, lwu, s0, 3)
 
MISALIGNED_LDST_TEST(10, ld, s0, 1)
MISALIGNED_LDST_TEST(11, ld, s0, 2)
MISALIGNED_LDST_TEST(12, ld, s0, 3)
MISALIGNED_LDST_TEST(13, ld, s0, 4)
MISALIGNED_LDST_TEST(14, ld, s0, 5)
MISALIGNED_LDST_TEST(15, ld, s0, 6)
MISALIGNED_LDST_TEST(16, ld, s0, 7)
#endif
 
# indicate it's a store test
li s1, 1
 
MISALIGNED_LDST_TEST(22, sh, s0, 1)
MISALIGNED_LDST_TEST(23, sw, s0, 1)
MISALIGNED_LDST_TEST(24, sw, s0, 2)
MISALIGNED_LDST_TEST(25, sw, s0, 3)
 
#ifdef __riscv64
MISALIGNED_LDST_TEST(26, sd, s0, 1)
MISALIGNED_LDST_TEST(27, sd, s0, 2)
MISALIGNED_LDST_TEST(28, sd, s0, 3)
MISALIGNED_LDST_TEST(29, sd, s0, 4)
MISALIGNED_LDST_TEST(30, sd, s0, 5)
MISALIGNED_LDST_TEST(31, sd, s0, 6)
MISALIGNED_LDST_TEST(32, sd, s0, 7)
#endif
 
TEST_PASSFAIL
 
.align 3
stvec_handler:
bnez s1, test_store
 
test_load:
li t1, CAUSE_MISALIGNED_LOAD
csrr t0, scause
bne t0, t1, fail
csrr t0, sepc
addi t0, t0, 8
csrw sepc, t0
sret
 
test_store:
li t1, CAUSE_MISALIGNED_STORE
csrr t0, scause
bne t0, t1, fail
csrr t0, sepc
addi t0, t0, 8
csrw sepc, t0
sret
 
RVTEST_CODE_END
 
.data
RVTEST_DATA_BEGIN
 
TEST_DATA
 
RVTEST_DATA_END
/riscv-tests/riscv_test.h
4,7 → 4,7
#define _ENV_PHYSICAL_SINGLE_CORE_H
 
#include "encoding.h"
//#include "../hwacha_xcpt.h"
#include "hwacha_xcpt.h"
 
//-----------------------------------------------------------------------
// Begin Macro
27,48 → 27,72
 
#define RVTEST_RV32U \
.macro init; \
RVTEST_32_ENABLE; \
.endm
 
#define RVTEST_RV32UF \
.macro init; \
RVTEST_32_ENABLE; \
RVTEST_FP_ENABLE; \
.endm
 
#define RVTEST_RV32UV \
.macro init; \
RVTEST_32_ENABLE; \
RVTEST_FP_ENABLE; \
RVTEST_VEC_ENABLE; \
.endm
 
#define RVTEST_RV64M \
.macro init; \
RVTEST_ENABLE_MACHINE; \
.endm
 
#define RVTEST_RV64S \
.macro init; \
RVTEST_ENABLE_SUPERVISOR; \
.endm
 
#define RVTEST_RV64SV \
.macro init; \
RVTEST_ENABLE_SUPERVISOR; \
RVTEST_VEC_ENABLE; \
.endm
 
#define RVTEST_RV32M \
.macro init; \
RVTEST_ENABLE_MACHINE; \
.endm
 
#define RVTEST_RV32S \
.macro init; \
RVTEST_32_ENABLE; \
RVTEST_ENABLE_SUPERVISOR; \
.endm
 
#define RVTEST_32_ENABLE \
li a0, SR_S64; \
csrc status, a0; \
#ifdef __riscv64
# define CHECK_XLEN csrr a0, mcpuid; bltz a0, 1f; RVTEST_PASS; 1:
#else
# define CHECK_XLEN csrr a0, mcpuid; bgez a0, 1f; RVTEST_PASS; 1:
#endif
 
#define RVTEST_ENABLE_SUPERVISOR \
li a0, MSTATUS_PRV1 & (MSTATUS_PRV1 >> 1); \
csrs mstatus, a0; \
 
#define RVTEST_ENABLE_MACHINE \
li a0, MSTATUS_PRV1; \
csrs mstatus, a0; \
 
#define RVTEST_FP_ENABLE \
li a0, SR_EF; \
csrs status, a0; \
csrr a1, status; \
and a0, a0, a1; \
bnez a0, 2f; \
RVTEST_PASS; \
2:fssr x0; \
li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \
csrs mstatus, a0; \
csrr a0, mcpuid; \
andi a0, a0, 1 << ('D' - 'A'); /* test for D extension */ \
bnez a0, 1f; \
RVTEST_PASS; /* "pass" the test if FPU not present */ \
1:csrwi fcsr, 0
 
#define RVTEST_VEC_ENABLE \
li a0, SR_EA; \
csrs status, a0; \
csrr a1, status; \
li a0, SSTATUS_XS & (SSTATUS_XS >> 1); \
csrs sstatus, a0; \
csrr a1, sstatus; \
and a0, a0, a1; \
bnez a0, 2f; \
RVTEST_PASS; \
75,21 → 99,77
2: \
 
#define RISCV_MULTICORE_DISABLE \
csrr a0, hartid; \
1: bnez a0, 1b; \
csrr a0, mhartid; \
1: bnez a0, 1b
 
#define EXTRA_TVEC_USER
#define EXTRA_TVEC_SUPERVISOR
#define EXTRA_TVEC_HYPERVISOR
#define EXTRA_TVEC_MACHINE
#define EXTRA_INIT
#define EXTRA_INIT_TIMER
 
#define RVTEST_CODE_BEGIN \
.text; \
.align 4; \
.global _start; \
.align 6; \
.weak stvec_handler; \
.weak mtvec_handler; \
tvec_user: \
EXTRA_TVEC_USER; \
/* test whether the test came from pass/fail */ \
la t5, ecall; \
csrr t6, mepc; \
beq t5, t6, write_tohost; \
/* test whether the stvec_handler target exists */ \
la t5, stvec_handler; \
bnez t5, mrts_routine; \
/* test whether the mtvec_handler target exists */ \
la t5, mtvec_handler; \
bnez t5, mtvec_handler; \
/* some other exception occurred */ \
j other_exception; \
.align 6; \
tvec_supervisor: \
EXTRA_TVEC_SUPERVISOR; \
csrr t5, mcause; \
bgez t5, tvec_user; \
mrts_routine: \
mrts; \
.align 6; \
tvec_hypervisor: \
EXTRA_TVEC_HYPERVISOR; \
/* renting some space out here */ \
other_exception: \
1: ori TESTNUM, TESTNUM, 1337; /* some other exception occurred */ \
write_tohost: \
csrw mtohost, TESTNUM; \
j write_tohost; \
.align 6; \
tvec_machine: \
EXTRA_TVEC_MACHINE; \
la t5, ecall; \
csrr t6, mepc; \
beq t5, t6, write_tohost; \
la t5, mtvec_handler; \
bnez t5, mtvec_handler; \
j other_exception; \
.align 6; \
.globl _start; \
_start: \
RISCV_MULTICORE_DISABLE; \
CHECK_XLEN; \
la t0, stvec_handler; \
csrw stvec, t0; \
li t0, MSTATUS_PRV1 | MSTATUS_PRV2 | MSTATUS_IE1 | MSTATUS_IE2; \
csrc mstatus, t0; \
init; \
EXTRA_INIT; \
EXTRA_INIT_TIMER; \
la t0, 1f; \
csrw mepc, t0; \
csrr a0, mhartid; \
eret; \
1:
 
//-----------------------------------------------------------------------
// End Macro
96,6 → 176,8
//-----------------------------------------------------------------------
 
#define RVTEST_CODE_END \
ecall: ecall; \
j ecall
 
//-----------------------------------------------------------------------
// Pass/Fail Macro
103,17 → 185,16
 
#define RVTEST_PASS \
fence; \
csrw tohost, 1; \
1: j 1b; \
li TESTNUM, 1; \
j ecall
 
#define TESTNUM x28
#define RVTEST_FAIL \
fence; \
beqz TESTNUM, 1f; \
1: beqz TESTNUM, 1b; \
sll TESTNUM, TESTNUM, 1; \
or TESTNUM, TESTNUM, 1; \
csrw tohost, TESTNUM; \
1: j 1b; \
j ecall
 
//-----------------------------------------------------------------------
// Data Section Macro
/riscv-tests/encoding.h
3,56 → 3,124
#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H
 
#define SR_S 0x00000001
#define SR_PS 0x00000002
#define SR_EI 0x00000004
#define SR_PEI 0x00000008
#define SR_EF 0x00000010
#define SR_U64 0x00000020
#define SR_S64 0x00000040
#define SR_VM 0x00000080
#define SR_EA 0x00000100
#define SR_IM 0x00FF0000
#define SR_IP 0xFF000000
#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP)
#define SR_IM_SHIFT 16
#define SR_IP_SHIFT 24
#define MSTATUS_IE 0x00000001
#define MSTATUS_PRV 0x00000006
#define MSTATUS_IE1 0x00000008
#define MSTATUS_PRV1 0x00000030
#define MSTATUS_IE2 0x00000040
#define MSTATUS_PRV2 0x00000180
#define MSTATUS_IE3 0x00000200
#define MSTATUS_PRV3 0x00000C00
#define MSTATUS_FS 0x00003000
#define MSTATUS_XS 0x0000C000
#define MSTATUS_MPRV 0x00010000
#define MSTATUS_VM 0x003E0000
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000
 
#define IRQ_COP 2
#define IRQ_IPI 5
#define IRQ_HOST 6
#define IRQ_TIMER 7
#define SSTATUS_IE 0x00000001
#define SSTATUS_PIE 0x00000008
#define SSTATUS_PS 0x00000010
#define SSTATUS_FS 0x00003000
#define SSTATUS_XS 0x0000C000
#define SSTATUS_MPRV 0x00010000
#define SSTATUS_TIE 0x01000000
#define SSTATUS32_SD 0x80000000
#define SSTATUS64_SD 0x8000000000000000
 
#define IMPL_SPIKE 1
#define IMPL_ROCKET 2
#define MIP_SSIP 0x00000002
#define MIP_HSIP 0x00000004
#define MIP_MSIP 0x00000008
#define MIP_STIP 0x00000020
#define MIP_HTIP 0x00000040
#define MIP_MTIP 0x00000080
 
#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP
 
#define PRV_U 0
#define PRV_S 1
#define PRV_H 2
#define PRV_M 3
 
#define VM_MBARE 0
#define VM_MBB 1
#define VM_MBBID 2
#define VM_SV32 8
#define VM_SV39 9
#define VM_SV48 10
 
#define UA_RV32 0
#define UA_RV64 4
#define UA_RV128 8
 
#define IRQ_SOFT 0
#define IRQ_TIMER 1
#define IRQ_HOST 2
#define IRQ_COP 3
 
#define IMPL_ROCKET 1
 
#define DEFAULT_MTVEC 0x100
 
// page table entry (PTE) fields
#define PTE_V 0x001 // Entry is a page Table descriptor
#define PTE_T 0x002 // Entry is a page Table, not a terminal node
#define PTE_G 0x004 // Global
#define PTE_UR 0x008 // User Write permission
#define PTE_UW 0x010 // User Read permission
#define PTE_UX 0x020 // User eXecute permission
#define PTE_SR 0x040 // Supervisor Read permission
#define PTE_SW 0x080 // Supervisor Write permission
#define PTE_SX 0x100 // Supervisor eXecute permission
#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
#define PTE_V 0x001 // Valid
#define PTE_TYPE 0x01E // Type
#define PTE_R 0x020 // Referenced
#define PTE_D 0x040 // Dirty
#define PTE_SOFT 0x380 // Reserved for Software
 
#define PTE_TYPE_TABLE 0x00
#define PTE_TYPE_TABLE_GLOBAL 0x02
#define PTE_TYPE_URX_SR 0x04
#define PTE_TYPE_URWX_SRW 0x06
#define PTE_TYPE_UR_SR 0x08
#define PTE_TYPE_URW_SRW 0x0A
#define PTE_TYPE_URX_SRX 0x0C
#define PTE_TYPE_URWX_SRWX 0x0E
#define PTE_TYPE_SR 0x10
#define PTE_TYPE_SRW 0x12
#define PTE_TYPE_SRX 0x14
#define PTE_TYPE_SRWX 0x16
#define PTE_TYPE_SR_GLOBAL 0x18
#define PTE_TYPE_SRW_GLOBAL 0x1A
#define PTE_TYPE_SRX_GLOBAL 0x1C
#define PTE_TYPE_SRWX_GLOBAL 0x1E
 
#define PTE_PPN_SHIFT 10
 
#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1)
#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
 
#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
 
#ifdef __riscv
 
#ifdef __riscv64
# define RISCV_PGLEVELS 3
# define RISCV_PGSHIFT 13
# define MSTATUS_SD MSTATUS64_SD
# define SSTATUS_SD SSTATUS64_SD
# define RISCV_PGLEVEL_BITS 9
#else
# define RISCV_PGLEVELS 2
# define RISCV_PGSHIFT 12
# define MSTATUS_SD MSTATUS32_SD
# define SSTATUS_SD SSTATUS32_SD
# define RISCV_PGLEVEL_BITS 10
#endif
#define RISCV_PGLEVEL_BITS 10
#define RISCV_PGSHIFT 12
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
 
#ifndef __ASSEMBLER__
 
#define read_csr(reg) ({ long __tmp; \
#ifdef __GNUC__
 
#define read_csr(reg) ({ unsigned long __tmp; \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
 
63,7 → 131,7
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
__tmp; })
 
#define set_csr(reg, bit) ({ long __tmp; \
#define set_csr(reg, bit) ({ unsigned long __tmp; \
if (__builtin_constant_p(bit) && (bit) < 32) \
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
else \
70,7 → 138,7
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
__tmp; })
 
#define clear_csr(reg, bit) ({ long __tmp; \
#define clear_csr(reg, bit) ({ unsigned long __tmp; \
if (__builtin_constant_p(bit) && (bit) < 32) \
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
else \
77,18 → 145,12
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
__tmp; })
 
#define rdtime() ({ unsigned long __tmp; \
asm volatile ("rdtime %0" : "=r"(__tmp)); \
__tmp; })
#define rdtime() read_csr(time)
#define rdcycle() read_csr(cycle)
#define rdinstret() read_csr(instret)
 
#define rdcycle() ({ unsigned long __tmp; \
asm volatile ("rdcycle %0" : "=r"(__tmp)); \
__tmp; })
#endif
 
#define rdinstret() ({ unsigned long __tmp; \
asm volatile ("rdinstret %0" : "=r"(__tmp)); \
__tmp; })
 
#endif
 
#endif
97,346 → 159,379
/* Automatically generated by parse-opcodes */
#ifndef RISCV_ENCODING_H
#define RISCV_ENCODING_H
#define MATCH_FMV_S_X 0xf0000053
#define MASK_FMV_S_X 0xfff0707f
#define MATCH_ADD 0x33
#define MASK_ADD 0xfe00707f
#define MATCH_ADDI 0x13
#define MASK_ADDI 0x707f
#define MATCH_ADDIW 0x1b
#define MASK_ADDIW 0x707f
#define MATCH_ADDW 0x3b
#define MASK_ADDW 0xfe00707f
#define MATCH_AMOADD_D 0x302f
#define MASK_AMOADD_D 0xf800707f
#define MATCH_AMOADD_W 0x202f
#define MASK_AMOADD_W 0xf800707f
#define MATCH_AMOAND_D 0x6000302f
#define MASK_AMOAND_D 0xf800707f
#define MATCH_AMOAND_W 0x6000202f
#define MASK_AMOAND_W 0xf800707f
#define MATCH_AMOMAX_D 0xa000302f
#define MASK_AMOMAX_D 0xf800707f
#define MATCH_AMOMAX_W 0xa000202f
#define MASK_AMOMAX_W 0xf800707f
#define MATCH_AMOMAXU_D 0xe000302f
#define MASK_AMOMAXU_D 0xf800707f
#define MATCH_AMOMAXU_W 0xe000202f
#define MASK_AMOMAXU_W 0xf800707f
#define MATCH_AMOMIN_D 0x8000302f
#define MASK_AMOMIN_D 0xf800707f
#define MATCH_AMOMIN_W 0x8000202f
#define MASK_AMOMIN_W 0xf800707f
#define MATCH_AMOMINU_D 0xc000302f
#define MASK_AMOMINU_D 0xf800707f
#define MATCH_AMOMINU_W 0xc000202f
#define MASK_AMOMINU_W 0xf800707f
#define MATCH_AMOOR_D 0x4000302f
#define MASK_AMOOR_D 0xf800707f
#define MATCH_AMOOR_W 0x4000202f
#define MASK_AMOOR_W 0xf800707f
#define MATCH_AMOSWAP_D 0x800302f
#define MASK_AMOSWAP_D 0xf800707f
#define MATCH_AMOSWAP_W 0x800202f
#define MASK_AMOSWAP_W 0xf800707f
#define MATCH_AMOXOR_D 0x2000302f
#define MASK_AMOXOR_D 0xf800707f
#define MATCH_AMOXOR_W 0x2000202f
#define MASK_AMOXOR_W 0xf800707f
#define MATCH_REMUW 0x200703b
#define MASK_REMUW 0xfe00707f
#define MATCH_FMIN_D 0x2a000053
#define MASK_FMIN_D 0xfe00707f
#define MATCH_AMOMAX_D 0xa000302f
#define MASK_AMOMAX_D 0xf800707f
#define MATCH_AND 0x7033
#define MASK_AND 0xfe00707f
#define MATCH_ANDI 0x7013
#define MASK_ANDI 0x707f
#define MATCH_AUIPC 0x17
#define MASK_AUIPC 0x7f
#define MATCH_BEQ 0x63
#define MASK_BEQ 0x707f
#define MATCH_BGE 0x5063
#define MASK_BGE 0x707f
#define MATCH_BGEU 0x7063
#define MASK_BGEU 0x707f
#define MATCH_BLT 0x4063
#define MASK_BLT 0x707f
#define MATCH_BLTU 0x6063
#define MASK_BLTU 0x707f
#define MATCH_FSGNJN_D 0x22001053
#define MASK_FSGNJN_D 0xfe00707f
#define MATCH_FMIN_S 0x28000053
#define MASK_FMIN_S 0xfe00707f
#define MATCH_BNE 0x1063
#define MASK_BNE 0x707f
#define MATCH_C_ADD 0x6000
#define MASK_C_ADD 0xf003
#define MATCH_C_ADDI 0x8000
#define MASK_C_ADDI 0xe003
#define MATCH_C_ADDI4 0xa000
#define MASK_C_ADDI4 0xe003
#define MATCH_C_ADDIW 0xe000
#define MASK_C_ADDIW 0xe003
#define MATCH_C_ADDW 0x7000
#define MASK_C_ADDW 0xf003
#define MATCH_C_BEQZ 0x2002
#define MASK_C_BEQZ 0xe003
#define MATCH_C_BNEZ 0x6002
#define MASK_C_BNEZ 0xe003
#define MATCH_C_J 0xa002
#define MASK_C_J 0xe003
#define MATCH_C_JALR 0x5000
#define MASK_C_JALR 0xf003
#define MATCH_C_LD 0x2001
#define MASK_C_LD 0xe003
#define MATCH_C_LDSP 0xc001
#define MASK_C_LDSP 0xe003
#define MATCH_C_LI 0x0
#define MASK_C_LI 0xe003
#define MATCH_C_LUI 0x2000
#define MASK_C_LUI 0xe003
#define MATCH_C_LW 0x1
#define MASK_C_LW 0xe003
#define MATCH_C_LWSP 0x8001
#define MASK_C_LWSP 0xe003
#define MATCH_C_MV 0x4000
#define MASK_C_MV 0xf003
#define MATCH_C_SD 0x6001
#define MASK_C_SD 0xe003
#define MATCH_C_SDSP 0xe001
#define MASK_C_SDSP 0xe003
#define MATCH_C_SLLI 0xc000
#define MASK_C_SLLI 0xe003
#define MATCH_C_SW 0x4001
#define MASK_C_SW 0xe003
#define MATCH_C_SWSP 0xa001
#define MASK_C_SWSP 0xe003
#define MATCH_CSRRC 0x3073
#define MASK_CSRRC 0x707f
#define MATCH_CSRRCI 0x7073
#define MASK_CSRRCI 0x707f
#define MATCH_CSRRS 0x2073
#define MASK_CSRRS 0x707f
#define MATCH_CSRRSI 0x6073
#define MASK_CSRRSI 0x707f
#define MATCH_CSRRW 0x1073
#define MASK_CSRRW 0x707f
#define MATCH_SLLIW 0x101b
#define MASK_SLLIW 0xfe00707f
#define MATCH_LB 0x3
#define MASK_LB 0x707f
#define MATCH_FMAX_S 0x28001053
#define MASK_FMAX_S 0xfe00707f
#define MATCH_LH 0x1003
#define MASK_LH 0x707f
#define MATCH_FCVT_D_W 0xd2000053
#define MASK_FCVT_D_W 0xfff0007f
#define MATCH_LW 0x2003
#define MASK_LW 0x707f
#define MATCH_ADD 0x33
#define MASK_ADD 0xfe00707f
#define MATCH_CSRRC 0x3073
#define MASK_CSRRC 0x707f
#define MATCH_FMAX_D 0x2a001053
#define MASK_FMAX_D 0xfe00707f
#define MATCH_BNE 0x1063
#define MASK_BNE 0x707f
#define MATCH_FCVT_S_D 0x40100053
#define MASK_FCVT_S_D 0xfff0007f
#define MATCH_BGEU 0x7063
#define MASK_BGEU 0x707f
#define MATCH_CSRRWI 0x5073
#define MASK_CSRRWI 0x707f
#define MATCH_DIV 0x2004033
#define MASK_DIV 0xfe00707f
#define MATCH_DIVU 0x2005033
#define MASK_DIVU 0xfe00707f
#define MATCH_DIVUW 0x200503b
#define MASK_DIVUW 0xfe00707f
#define MATCH_DIVW 0x200403b
#define MASK_DIVW 0xfe00707f
#define MATCH_FADD_D 0x2000053
#define MASK_FADD_D 0xfe00007f
#define MATCH_SLTIU 0x3013
#define MASK_SLTIU 0x707f
#define MATCH_FADD_S 0x53
#define MASK_FADD_S 0xfe00007f
#define MATCH_FCLASS_D 0xe2001053
#define MASK_FCLASS_D 0xfff0707f
#define MATCH_FCLASS_S 0xe0001053
#define MASK_FCLASS_S 0xfff0707f
#define MATCH_FCVT_D_L 0xd2200053
#define MASK_FCVT_D_L 0xfff0007f
#define MATCH_FCVT_D_LU 0xd2300053
#define MASK_FCVT_D_LU 0xfff0007f
#define MATCH_FCVT_D_S 0x42000053
#define MASK_FCVT_D_S 0xfff0007f
#define MATCH_FCVT_D_W 0xd2000053
#define MASK_FCVT_D_W 0xfff0007f
#define MATCH_FCVT_D_WU 0xd2100053
#define MASK_FCVT_D_WU 0xfff0007f
#define MATCH_FCVT_L_D 0xc2200053
#define MASK_FCVT_L_D 0xfff0007f
#define MATCH_FCVT_L_S 0xc0200053
#define MASK_FCVT_L_S 0xfff0007f
#define MATCH_FCVT_LU_D 0xc2300053
#define MASK_FCVT_LU_D 0xfff0007f
#define MATCH_FCVT_LU_S 0xc0300053
#define MASK_FCVT_LU_S 0xfff0007f
#define MATCH_FCVT_S_D 0x40100053
#define MASK_FCVT_S_D 0xfff0007f
#define MATCH_FCVT_S_L 0xd0200053
#define MASK_FCVT_S_L 0xfff0007f
#define MATCH_FCVT_S_LU 0xd0300053
#define MASK_FCVT_S_LU 0xfff0007f
#define MATCH_FCVT_S_W 0xd0000053
#define MASK_FCVT_S_W 0xfff0007f
#define MATCH_MUL 0x2000033
#define MASK_MUL 0xfe00707f
#define MATCH_AMOMINU_D 0xc000302f
#define MASK_AMOMINU_D 0xf800707f
#define MATCH_FCVT_S_LU 0xd0300053
#define MASK_FCVT_S_LU 0xfff0007f
#define MATCH_SRLI 0x5013
#define MASK_SRLI 0xfc00707f
#define MATCH_AMOMINU_W 0xc000202f
#define MASK_AMOMINU_W 0xf800707f
#define MATCH_DIVUW 0x200503b
#define MASK_DIVUW 0xfe00707f
#define MATCH_MULW 0x200003b
#define MASK_MULW 0xfe00707f
#define MATCH_SRLW 0x503b
#define MASK_SRLW 0xfe00707f
#define MATCH_DIV 0x2004033
#define MASK_DIV 0xfe00707f
#define MATCH_FCVT_S_WU 0xd0100053
#define MASK_FCVT_S_WU 0xfff0007f
#define MATCH_FCVT_W_D 0xc2000053
#define MASK_FCVT_W_D 0xfff0007f
#define MATCH_FCVT_W_S 0xc0000053
#define MASK_FCVT_W_S 0xfff0007f
#define MATCH_FCVT_WU_D 0xc2100053
#define MASK_FCVT_WU_D 0xfff0007f
#define MATCH_FCVT_WU_S 0xc0100053
#define MASK_FCVT_WU_S 0xfff0007f
#define MATCH_FDIV_D 0x1a000053
#define MASK_FDIV_D 0xfe00007f
#define MATCH_FDIV_S 0x18000053
#define MASK_FDIV_S 0xfe00007f
#define MATCH_FENCE 0xf
#define MASK_FENCE 0x707f
#define MATCH_FNMSUB_S 0x4b
#define MASK_FNMSUB_S 0x600007f
#define MATCH_FCVT_L_S 0xc0200053
#define MASK_FCVT_L_S 0xfff0007f
#define MATCH_SBREAK 0x100073
#define MASK_SBREAK 0xffffffff
#define MATCH_FENCE_I 0x100f
#define MASK_FENCE_I 0x707f
#define MATCH_FEQ_D 0xa2002053
#define MASK_FEQ_D 0xfe00707f
#define MATCH_FEQ_S 0xa0002053
#define MASK_FEQ_S 0xfe00707f
#define MATCH_FLD 0x3007
#define MASK_FLD 0x707f
#define MATCH_FLE_D 0xa2000053
#define MASK_FLE_D 0xfe00707f
#define MATCH_FLE_S 0xa0000053
#define MASK_FLE_S 0xfe00707f
#define MATCH_FDIV_S 0x18000053
#define MASK_FDIV_S 0xfe00007f
#define MATCH_FLE_D 0xa2000053
#define MASK_FLE_D 0xfe00707f
#define MATCH_FENCE_I 0x100f
#define MASK_FENCE_I 0x707f
#define MATCH_FNMSUB_D 0x200004b
#define MASK_FNMSUB_D 0x600007f
#define MATCH_ADDW 0x3b
#define MASK_ADDW 0xfe00707f
#define MATCH_SLL 0x1033
#define MASK_SLL 0xfe00707f
#define MATCH_XOR 0x4033
#define MASK_XOR 0xfe00707f
#define MATCH_SUB 0x40000033
#define MASK_SUB 0xfe00707f
#define MATCH_BLT 0x4063
#define MASK_BLT 0x707f
#define MATCH_SCALL 0x73
#define MASK_SCALL 0xffffffff
#define MATCH_FCLASS_S 0xe0001053
#define MASK_FCLASS_S 0xfff0707f
#define MATCH_SC_W 0x1800202f
#define MASK_SC_W 0xf800707f
#define MATCH_REM 0x2006033
#define MASK_REM 0xfe00707f
#define MATCH_SRLIW 0x501b
#define MASK_SRLIW 0xfe00707f
#define MATCH_LUI 0x37
#define MASK_LUI 0x7f
#define MATCH_CSRRCI 0x7073
#define MASK_CSRRCI 0x707f
#define MATCH_ADDI 0x13
#define MASK_ADDI 0x707f
#define MATCH_MULH 0x2001033
#define MASK_MULH 0xfe00707f
#define MATCH_FMUL_S 0x10000053
#define MASK_FMUL_S 0xfe00007f
#define MATCH_CSRRSI 0x6073
#define MASK_CSRRSI 0x707f
#define MATCH_SRAI 0x40005013
#define MASK_SRAI 0xfc00707f
#define MATCH_AMOAND_D 0x6000302f
#define MASK_AMOAND_D 0xf800707f
#define MATCH_FLT_D 0xa2001053
#define MASK_FLT_D 0xfe00707f
#define MATCH_SRAW 0x4000503b
#define MASK_SRAW 0xfe00707f
#define MATCH_FLT_S 0xa0001053
#define MASK_FLT_S 0xfe00707f
#define MATCH_FLW 0x2007
#define MASK_FLW 0x707f
#define MATCH_FMADD_D 0x2000043
#define MASK_FMADD_D 0x600007f
#define MATCH_FMADD_S 0x43
#define MASK_FMADD_S 0x600007f
#define MATCH_FMAX_D 0x2a001053
#define MASK_FMAX_D 0xfe00707f
#define MATCH_FMAX_S 0x28001053
#define MASK_FMAX_S 0xfe00707f
#define MATCH_FMIN_D 0x2a000053
#define MASK_FMIN_D 0xfe00707f
#define MATCH_FMIN_S 0x28000053
#define MASK_FMIN_S 0xfe00707f
#define MATCH_FMSUB_D 0x2000047
#define MASK_FMSUB_D 0x600007f
#define MATCH_FMSUB_S 0x47
#define MASK_FMSUB_S 0x600007f
#define MATCH_FMUL_D 0x12000053
#define MASK_FMUL_D 0xfe00007f
#define MATCH_LD 0x3003
#define MASK_LD 0x707f
#define MATCH_ORI 0x6013
#define MASK_ORI 0x707f
#define MATCH_CSRRS 0x2073
#define MASK_CSRRS 0x707f
#define MATCH_FLT_S 0xa0001053
#define MASK_FLT_S 0xfe00707f
#define MATCH_ADDIW 0x1b
#define MASK_ADDIW 0x707f
#define MATCH_AMOAND_W 0x6000202f
#define MASK_AMOAND_W 0xf800707f
#define MATCH_FEQ_S 0xa0002053
#define MASK_FEQ_S 0xfe00707f
#define MATCH_FMUL_S 0x10000053
#define MASK_FMUL_S 0xfe00007f
#define MATCH_FMV_D_X 0xf2000053
#define MASK_FMV_D_X 0xfff0707f
#define MATCH_FMV_S_X 0xf0000053
#define MASK_FMV_S_X 0xfff0707f
#define MATCH_FMV_X_D 0xe2000053
#define MASK_FMV_X_D 0xfff0707f
#define MATCH_FMV_X_S 0xe0000053
#define MASK_FMV_X_S 0xfff0707f
#define MATCH_FNMADD_D 0x200004f
#define MASK_FNMADD_D 0x600007f
#define MATCH_FNMADD_S 0x4f
#define MASK_FNMADD_S 0x600007f
#define MATCH_FNMSUB_D 0x200004b
#define MASK_FNMSUB_D 0x600007f
#define MATCH_FNMSUB_S 0x4b
#define MASK_FNMSUB_S 0x600007f
#define MATCH_FSD 0x3027
#define MASK_FSD 0x707f
#define MATCH_FSGNJ_D 0x22000053
#define MASK_FSGNJ_D 0xfe00707f
#define MATCH_FSGNJ_S 0x20000053
#define MASK_FSGNJ_S 0xfe00707f
#define MATCH_FSGNJN_D 0x22001053
#define MASK_FSGNJN_D 0xfe00707f
#define MATCH_FSGNJN_S 0x20001053
#define MASK_FSGNJN_S 0xfe00707f
#define MATCH_FSGNJX_D 0x22002053
#define MASK_FSGNJX_D 0xfe00707f
#define MATCH_SRA 0x40005033
#define MASK_SRA 0xfe00707f
#define MATCH_BGE 0x5063
#define MASK_BGE 0x707f
#define MATCH_SRAIW 0x4000501b
#define MASK_SRAIW 0xfe00707f
#define MATCH_SRL 0x5033
#define MASK_SRL 0xfe00707f
#define MATCH_FSGNJX_S 0x20002053
#define MASK_FSGNJX_S 0xfe00707f
#define MATCH_FSQRT_D 0x5a000053
#define MASK_FSQRT_D 0xfff0007f
#define MATCH_FSQRT_S 0x58000053
#define MASK_FSQRT_S 0xfff0007f
#define MATCH_FSUB_D 0xa000053
#define MASK_FSUB_D 0xfe00007f
#define MATCH_FSGNJX_S 0x20002053
#define MASK_FSGNJX_S 0xfe00707f
#define MATCH_FEQ_D 0xa2002053
#define MASK_FEQ_D 0xfe00707f
#define MATCH_FCVT_D_WU 0xd2100053
#define MASK_FCVT_D_WU 0xfff0007f
#define MATCH_OR 0x6033
#define MASK_OR 0xfe00707f
#define MATCH_FCVT_WU_D 0xc2100053
#define MASK_FCVT_WU_D 0xfff0007f
#define MATCH_SUBW 0x4000003b
#define MASK_SUBW 0xfe00707f
#define MATCH_FCVT_D_L 0xd2200053
#define MASK_FCVT_D_L 0xfff0007f
#define MATCH_AMOMAXU_D 0xe000302f
#define MASK_AMOMAXU_D 0xf800707f
#define MATCH_XORI 0x4013
#define MASK_XORI 0x707f
#define MATCH_AMOXOR_D 0x2000302f
#define MASK_AMOXOR_D 0xf800707f
#define MATCH_AMOMAXU_W 0xe000202f
#define MASK_AMOMAXU_W 0xf800707f
#define MATCH_FCVT_WU_S 0xc0100053
#define MASK_FCVT_WU_S 0xfff0007f
#define MATCH_ANDI 0x7013
#define MASK_ANDI 0x707f
#define MATCH_FMV_X_S 0xe0000053
#define MASK_FMV_X_S 0xfff0707f
#define MATCH_SRET 0x80000073
#define MASK_SRET 0xffffffff
#define MATCH_FNMADD_S 0x4f
#define MASK_FNMADD_S 0x600007f
#define MATCH_FSUB_S 0x8000053
#define MASK_FSUB_S 0xfe00007f
#define MATCH_FSW 0x2027
#define MASK_FSW 0x707f
#define MATCH_HRTS 0x20500073
#define MASK_HRTS 0xffffffff
#define MATCH_JAL 0x6f
#define MASK_JAL 0x7f
#define MATCH_JALR 0x67
#define MASK_JALR 0x707f
#define MATCH_LB 0x3
#define MASK_LB 0x707f
#define MATCH_LBU 0x4003
#define MASK_LBU 0x707f
#define MATCH_LD 0x3003
#define MASK_LD 0x707f
#define MATCH_LH 0x1003
#define MASK_LH 0x707f
#define MATCH_LHU 0x5003
#define MASK_LHU 0x707f
#define MATCH_LR_D 0x1000302f
#define MASK_LR_D 0xf9f0707f
#define MATCH_LR_W 0x1000202f
#define MASK_LR_W 0xf9f0707f
#define MATCH_LUI 0x37
#define MASK_LUI 0x7f
#define MATCH_LW 0x2003
#define MASK_LW 0x707f
#define MATCH_LWU 0x6003
#define MASK_LWU 0x707f
#define MATCH_FMV_X_D 0xe2000053
#define MASK_FMV_X_D 0xfff0707f
#define MATCH_FCVT_D_S 0x42000053
#define MASK_FCVT_D_S 0xfff0007f
#define MATCH_FNMADD_D 0x200004f
#define MASK_FNMADD_D 0x600007f
#define MATCH_AMOADD_D 0x302f
#define MASK_AMOADD_D 0xf800707f
#define MATCH_LR_D 0x1000302f
#define MASK_LR_D 0xf9f0707f
#define MATCH_FCVT_W_S 0xc0000053
#define MASK_FCVT_W_S 0xfff0007f
#define MATCH_MRTH 0x30600073
#define MASK_MRTH 0xffffffff
#define MATCH_MRTS 0x30500073
#define MASK_MRTS 0xffffffff
#define MATCH_MUL 0x2000033
#define MASK_MUL 0xfe00707f
#define MATCH_MULH 0x2001033
#define MASK_MULH 0xfe00707f
#define MATCH_MULHSU 0x2002033
#define MASK_MULHSU 0xfe00707f
#define MATCH_AMOADD_W 0x202f
#define MASK_AMOADD_W 0xf800707f
#define MATCH_FCVT_D_LU 0xd2300053
#define MASK_FCVT_D_LU 0xfff0007f
#define MATCH_LR_W 0x1000202f
#define MASK_LR_W 0xf9f0707f
#define MATCH_FCVT_W_D 0xc2000053
#define MASK_FCVT_W_D 0xfff0007f
#define MATCH_MULHU 0x2003033
#define MASK_MULHU 0xfe00707f
#define MATCH_MULW 0x200003b
#define MASK_MULW 0xfe00707f
#define MATCH_OR 0x6033
#define MASK_OR 0xfe00707f
#define MATCH_ORI 0x6013
#define MASK_ORI 0x707f
#define MATCH_REM 0x2006033
#define MASK_REM 0xfe00707f
#define MATCH_REMU 0x2007033
#define MASK_REMU 0xfe00707f
#define MATCH_REMUW 0x200703b
#define MASK_REMUW 0xfe00707f
#define MATCH_REMW 0x200603b
#define MASK_REMW 0xfe00707f
#define MATCH_SB 0x23
#define MASK_SB 0x707f
#define MATCH_SBREAK 0x100073
#define MASK_SBREAK 0xffffffff
#define MATCH_SC_D 0x1800302f
#define MASK_SC_D 0xf800707f
#define MATCH_SC_W 0x1800202f
#define MASK_SC_W 0xf800707f
#define MATCH_SCALL 0x73
#define MASK_SCALL 0xffffffff
#define MATCH_SD 0x3023
#define MASK_SD 0x707f
#define MATCH_SFENCE_VM 0x10100073
#define MASK_SFENCE_VM 0xfff07fff
#define MATCH_SH 0x1023
#define MASK_SH 0x707f
#define MATCH_SLL 0x1033
#define MASK_SLL 0xfe00707f
#define MATCH_SLLI 0x1013
#define MASK_SLLI 0xfc00707f
#define MATCH_SLLIW 0x101b
#define MASK_SLLIW 0xfe00707f
#define MATCH_SLLW 0x103b
#define MASK_SLLW 0xfe00707f
#define MATCH_SLT 0x2033
#define MASK_SLT 0xfe00707f
#define MATCH_SLLW 0x103b
#define MASK_SLLW 0xfe00707f
#define MATCH_AMOOR_D 0x4000302f
#define MASK_AMOOR_D 0xf800707f
#define MATCH_SLTI 0x2013
#define MASK_SLTI 0x707f
#define MATCH_REMU 0x2007033
#define MASK_REMU 0xfe00707f
#define MATCH_FLW 0x2007
#define MASK_FLW 0x707f
#define MATCH_REMW 0x200603b
#define MASK_REMW 0xfe00707f
#define MATCH_SLTIU 0x3013
#define MASK_SLTIU 0x707f
#define MATCH_SLTU 0x3033
#define MASK_SLTU 0xfe00707f
#define MATCH_SLLI 0x1013
#define MASK_SLLI 0xfc00707f
#define MATCH_AMOOR_W 0x4000202f
#define MASK_AMOOR_W 0xf800707f
#define MATCH_BEQ 0x63
#define MASK_BEQ 0x707f
#define MATCH_FLD 0x3007
#define MASK_FLD 0x707f
#define MATCH_FSUB_S 0x8000053
#define MASK_FSUB_S 0xfe00007f
#define MATCH_AND 0x7033
#define MASK_AND 0xfe00707f
#define MATCH_FMV_D_X 0xf2000053
#define MASK_FMV_D_X 0xfff0707f
#define MATCH_LBU 0x4003
#define MASK_LBU 0x707f
#define MATCH_FSGNJ_S 0x20000053
#define MASK_FSGNJ_S 0xfe00707f
#define MATCH_AMOMAX_W 0xa000202f
#define MASK_AMOMAX_W 0xf800707f
#define MATCH_FSGNJ_D 0x22000053
#define MASK_FSGNJ_D 0xfe00707f
#define MATCH_MULHU 0x2003033
#define MASK_MULHU 0xfe00707f
#define MATCH_FCVT_L_D 0xc2200053
#define MASK_FCVT_L_D 0xfff0007f
#define MATCH_FCVT_S_WU 0xd0100053
#define MASK_FCVT_S_WU 0xfff0007f
#define MATCH_FCVT_LU_S 0xc0300053
#define MASK_FCVT_LU_S 0xfff0007f
#define MATCH_FCVT_S_L 0xd0200053
#define MASK_FCVT_S_L 0xfff0007f
#define MATCH_AUIPC 0x17
#define MASK_AUIPC 0x7f
#define MATCH_FCVT_LU_D 0xc2300053
#define MASK_FCVT_LU_D 0xfff0007f
#define MATCH_CSRRWI 0x5073
#define MASK_CSRRWI 0x707f
#define MATCH_SC_D 0x1800302f
#define MASK_SC_D 0xf800707f
#define MATCH_FMADD_S 0x43
#define MASK_FMADD_S 0x600007f
#define MATCH_FSQRT_S 0x58000053
#define MASK_FSQRT_S 0xfff0007f
#define MATCH_AMOMIN_W 0x8000202f
#define MASK_AMOMIN_W 0xf800707f
#define MATCH_FSGNJN_S 0x20001053
#define MASK_FSGNJN_S 0xfe00707f
#define MATCH_AMOSWAP_D 0x800302f
#define MASK_AMOSWAP_D 0xf800707f
#define MATCH_FSQRT_D 0x5a000053
#define MASK_FSQRT_D 0xfff0007f
#define MATCH_FMADD_D 0x2000043
#define MASK_FMADD_D 0x600007f
#define MATCH_DIVW 0x200403b
#define MASK_DIVW 0xfe00707f
#define MATCH_AMOMIN_D 0x8000302f
#define MASK_AMOMIN_D 0xf800707f
#define MATCH_DIVU 0x2005033
#define MASK_DIVU 0xfe00707f
#define MATCH_AMOSWAP_W 0x800202f
#define MASK_AMOSWAP_W 0xf800707f
#define MATCH_JALR 0x67
#define MASK_JALR 0x707f
#define MATCH_FSD 0x3027
#define MASK_FSD 0x707f
#define MATCH_SRA 0x40005033
#define MASK_SRA 0xfe00707f
#define MATCH_SRAI 0x40005013
#define MASK_SRAI 0xfc00707f
#define MATCH_SRAIW 0x4000501b
#define MASK_SRAIW 0xfe00707f
#define MATCH_SRAW 0x4000503b
#define MASK_SRAW 0xfe00707f
#define MATCH_SRET 0x10000073
#define MASK_SRET 0xffffffff
#define MATCH_SRL 0x5033
#define MASK_SRL 0xfe00707f
#define MATCH_SRLI 0x5013
#define MASK_SRLI 0xfc00707f
#define MATCH_SRLIW 0x501b
#define MASK_SRLIW 0xfe00707f
#define MATCH_SRLW 0x503b
#define MASK_SRLW 0xfe00707f
#define MATCH_SUB 0x40000033
#define MASK_SUB 0xfe00707f
#define MATCH_SUBW 0x4000003b
#define MASK_SUBW 0xfe00707f
#define MATCH_SW 0x2023
#define MASK_SW 0x707f
#define MATCH_FMSUB_S 0x47
#define MASK_FMSUB_S 0x600007f
#define MATCH_LHU 0x5003
#define MASK_LHU 0x707f
#define MATCH_SH 0x1023
#define MASK_SH 0x707f
#define MATCH_FSW 0x2027
#define MASK_FSW 0x707f
#define MATCH_SB 0x23
#define MASK_SB 0x707f
#define MATCH_FMSUB_D 0x2000047
#define MASK_FMSUB_D 0x600007f
#define MATCH_SD 0x3023
#define MASK_SD 0x707f
#define MATCH_WFI 0x10200073
#define MASK_WFI 0xffffffff
#define MATCH_XOR 0x4033
#define MASK_XOR 0xfe00707f
#define MATCH_XORI 0x4013
#define MASK_XORI 0x707f
#define CSR_FFLAGS 0x1
#define CSR_FRM 0x2
#define CSR_FCSR 0x3
#define CSR_STATS 0xc0
#define CSR_SUP0 0x500
#define CSR_SUP1 0x501
#define CSR_EPC 0x502
#define CSR_BADVADDR 0x503
#define CSR_PTBR 0x504
#define CSR_ASID 0x505
#define CSR_COUNT 0x506
#define CSR_COMPARE 0x507
#define CSR_EVEC 0x508
#define CSR_CAUSE 0x509
#define CSR_STATUS 0x50a
#define CSR_HARTID 0x50b
#define CSR_IMPL 0x50c
#define CSR_FATC 0x50d
#define CSR_SEND_IPI 0x50e
#define CSR_CLEAR_IPI 0x50f
#define CSR_RESET 0x51d
#define CSR_TOHOST 0x51e
#define CSR_FROMHOST 0x51f
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
#define CSR_STATS 0xc0
#define CSR_UARCH0 0xcc0
#define CSR_UARCH1 0xcc1
#define CSR_UARCH2 0xcc2
453,209 → 548,255
#define CSR_UARCH13 0xccd
#define CSR_UARCH14 0xcce
#define CSR_UARCH15 0xccf
#define CSR_COUNTH 0x586
#define CSR_SSTATUS 0x100
#define CSR_STVEC 0x101
#define CSR_SIE 0x104
#define CSR_STIMECMP 0x121
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SIP 0x144
#define CSR_SPTBR 0x180
#define CSR_SASID 0x181
#define CSR_CYCLEW 0x900
#define CSR_TIMEW 0x901
#define CSR_INSTRETW 0x902
#define CSR_STIME 0xd01
#define CSR_SCAUSE 0xd42
#define CSR_SBADADDR 0xd43
#define CSR_STIMEW 0xa01
#define CSR_MSTATUS 0x300
#define CSR_MTVEC 0x301
#define CSR_MTDELEG 0x302
#define CSR_MIE 0x304
#define CSR_MTIMECMP 0x321
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MBADADDR 0x343
#define CSR_MIP 0x344
#define CSR_MTIME 0x701
#define CSR_MCPUID 0xf00
#define CSR_MIMPID 0xf01
#define CSR_MHARTID 0xf10
#define CSR_MTOHOST 0x780
#define CSR_MFROMHOST 0x781
#define CSR_MRESET 0x782
#define CSR_SEND_IPI 0x783
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
#define CSR_CYCLEHW 0x980
#define CSR_TIMEHW 0x981
#define CSR_INSTRETHW 0x982
#define CSR_STIMEH 0xd81
#define CSR_STIMEHW 0xa81
#define CSR_MTIMEH 0x741
#define CAUSE_MISALIGNED_FETCH 0x0
#define CAUSE_FAULT_FETCH 0x1
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
#define CAUSE_PRIVILEGED_INSTRUCTION 0x3
#define CAUSE_FP_DISABLED 0x4
#define CAUSE_SYSCALL 0x6
#define CAUSE_BREAKPOINT 0x7
#define CAUSE_MISALIGNED_LOAD 0x8
#define CAUSE_MISALIGNED_STORE 0x9
#define CAUSE_FAULT_LOAD 0xa
#define CAUSE_FAULT_STORE 0xb
#define CAUSE_ACCELERATOR_DISABLED 0xc
#define CAUSE_BREAKPOINT 0x3
#define CAUSE_MISALIGNED_LOAD 0x4
#define CAUSE_FAULT_LOAD 0x5
#define CAUSE_MISALIGNED_STORE 0x6
#define CAUSE_FAULT_STORE 0x7
#define CAUSE_USER_ECALL 0x8
#define CAUSE_SUPERVISOR_ECALL 0x9
#define CAUSE_HYPERVISOR_ECALL 0xa
#define CAUSE_MACHINE_ECALL 0xb
#endif
#ifdef DECLARE_INSN
DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
DECLARE_INSN(and, MATCH_AND, MASK_AND)
DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
DECLARE_INSN(c_addi4, MATCH_C_ADDI4, MASK_C_ADDI4)
DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
DECLARE_INSN(lb, MATCH_LB, MASK_LB)
DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
DECLARE_INSN(lh, MATCH_LH, MASK_LH)
DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
DECLARE_INSN(lw, MATCH_LW, MASK_LW)
DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
DECLARE_INSN(rem, MATCH_REM, MASK_REM)
DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
DECLARE_INSN(ld, MATCH_LD, MASK_LD)
DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
DECLARE_INSN(or, MATCH_OR, MASK_OR)
DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
DECLARE_INSN(hrts, MATCH_HRTS, MASK_HRTS)
DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
DECLARE_INSN(lb, MATCH_LB, MASK_LB)
DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
DECLARE_INSN(ld, MATCH_LD, MASK_LD)
DECLARE_INSN(lh, MATCH_LH, MASK_LH)
DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
DECLARE_INSN(lw, MATCH_LW, MASK_LW)
DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
DECLARE_INSN(mrth, MATCH_MRTH, MASK_MRTH)
DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS)
DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
DECLARE_INSN(or, MATCH_OR, MASK_OR)
DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
DECLARE_INSN(rem, MATCH_REM, MASK_REM)
DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
DECLARE_INSN(sb, MATCH_SB, MASK_SB)
DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
DECLARE_INSN(sd, MATCH_SD, MASK_SD)
DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
DECLARE_INSN(sh, MATCH_SH, MASK_SH)
DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
DECLARE_INSN(and, MATCH_AND, MASK_AND)
DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
DECLARE_INSN(sw, MATCH_SW, MASK_SW)
DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
DECLARE_INSN(sh, MATCH_SH, MASK_SH)
DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
DECLARE_INSN(sb, MATCH_SB, MASK_SB)
DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
DECLARE_INSN(sd, MATCH_SD, MASK_SD)
DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
#endif
#ifdef DECLARE_CSR
DECLARE_CSR(fflags, CSR_FFLAGS)
DECLARE_CSR(frm, CSR_FRM)
DECLARE_CSR(fcsr, CSR_FCSR)
DECLARE_CSR(stats, CSR_STATS)
DECLARE_CSR(sup0, CSR_SUP0)
DECLARE_CSR(sup1, CSR_SUP1)
DECLARE_CSR(epc, CSR_EPC)
DECLARE_CSR(badvaddr, CSR_BADVADDR)
DECLARE_CSR(ptbr, CSR_PTBR)
DECLARE_CSR(asid, CSR_ASID)
DECLARE_CSR(count, CSR_COUNT)
DECLARE_CSR(compare, CSR_COMPARE)
DECLARE_CSR(evec, CSR_EVEC)
DECLARE_CSR(cause, CSR_CAUSE)
DECLARE_CSR(status, CSR_STATUS)
DECLARE_CSR(hartid, CSR_HARTID)
DECLARE_CSR(impl, CSR_IMPL)
DECLARE_CSR(fatc, CSR_FATC)
DECLARE_CSR(send_ipi, CSR_SEND_IPI)
DECLARE_CSR(clear_ipi, CSR_CLEAR_IPI)
DECLARE_CSR(reset, CSR_RESET)
DECLARE_CSR(tohost, CSR_TOHOST)
DECLARE_CSR(fromhost, CSR_FROMHOST)
DECLARE_CSR(cycle, CSR_CYCLE)
DECLARE_CSR(time, CSR_TIME)
DECLARE_CSR(instret, CSR_INSTRET)
DECLARE_CSR(stats, CSR_STATS)
DECLARE_CSR(uarch0, CSR_UARCH0)
DECLARE_CSR(uarch1, CSR_UARCH1)
DECLARE_CSR(uarch2, CSR_UARCH2)
672,38 → 813,58
DECLARE_CSR(uarch13, CSR_UARCH13)
DECLARE_CSR(uarch14, CSR_UARCH14)
DECLARE_CSR(uarch15, CSR_UARCH15)
DECLARE_CSR(counth, CSR_COUNTH)
DECLARE_CSR(sstatus, CSR_SSTATUS)
DECLARE_CSR(stvec, CSR_STVEC)
DECLARE_CSR(sie, CSR_SIE)
DECLARE_CSR(stimecmp, CSR_STIMECMP)
DECLARE_CSR(sscratch, CSR_SSCRATCH)
DECLARE_CSR(sepc, CSR_SEPC)
DECLARE_CSR(sip, CSR_SIP)
DECLARE_CSR(sptbr, CSR_SPTBR)
DECLARE_CSR(sasid, CSR_SASID)
DECLARE_CSR(cyclew, CSR_CYCLEW)
DECLARE_CSR(timew, CSR_TIMEW)
DECLARE_CSR(instretw, CSR_INSTRETW)
DECLARE_CSR(stime, CSR_STIME)
DECLARE_CSR(scause, CSR_SCAUSE)
DECLARE_CSR(sbadaddr, CSR_SBADADDR)
DECLARE_CSR(stimew, CSR_STIMEW)
DECLARE_CSR(mstatus, CSR_MSTATUS)
DECLARE_CSR(mtvec, CSR_MTVEC)
DECLARE_CSR(mtdeleg, CSR_MTDELEG)
DECLARE_CSR(mie, CSR_MIE)
DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
DECLARE_CSR(mscratch, CSR_MSCRATCH)
DECLARE_CSR(mepc, CSR_MEPC)
DECLARE_CSR(mcause, CSR_MCAUSE)
DECLARE_CSR(mbadaddr, CSR_MBADADDR)
DECLARE_CSR(mip, CSR_MIP)
DECLARE_CSR(mtime, CSR_MTIME)
DECLARE_CSR(mcpuid, CSR_MCPUID)
DECLARE_CSR(mimpid, CSR_MIMPID)
DECLARE_CSR(mhartid, CSR_MHARTID)
DECLARE_CSR(mtohost, CSR_MTOHOST)
DECLARE_CSR(mfromhost, CSR_MFROMHOST)
DECLARE_CSR(mreset, CSR_MRESET)
DECLARE_CSR(send_ipi, CSR_SEND_IPI)
DECLARE_CSR(cycleh, CSR_CYCLEH)
DECLARE_CSR(timeh, CSR_TIMEH)
DECLARE_CSR(instreth, CSR_INSTRETH)
DECLARE_CSR(cyclehw, CSR_CYCLEHW)
DECLARE_CSR(timehw, CSR_TIMEHW)
DECLARE_CSR(instrethw, CSR_INSTRETHW)
DECLARE_CSR(stimeh, CSR_STIMEH)
DECLARE_CSR(stimehw, CSR_STIMEHW)
DECLARE_CSR(mtimeh, CSR_MTIMEH)
#endif
#ifdef DECLARE_CAUSE
DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
DECLARE_CAUSE("frm", CAUSE_FRM)
DECLARE_CAUSE("fcsr", CAUSE_FCSR)
DECLARE_CAUSE("stats", CAUSE_STATS)
DECLARE_CAUSE("sup0", CAUSE_SUP0)
DECLARE_CAUSE("sup1", CAUSE_SUP1)
DECLARE_CAUSE("epc", CAUSE_EPC)
DECLARE_CAUSE("badvaddr", CAUSE_BADVADDR)
DECLARE_CAUSE("ptbr", CAUSE_PTBR)
DECLARE_CAUSE("asid", CAUSE_ASID)
DECLARE_CAUSE("count", CAUSE_COUNT)
DECLARE_CAUSE("compare", CAUSE_COMPARE)
DECLARE_CAUSE("evec", CAUSE_EVEC)
DECLARE_CAUSE("cause", CAUSE_CAUSE)
DECLARE_CAUSE("status", CAUSE_STATUS)
DECLARE_CAUSE("hartid", CAUSE_HARTID)
DECLARE_CAUSE("impl", CAUSE_IMPL)
DECLARE_CAUSE("fatc", CAUSE_FATC)
DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
DECLARE_CAUSE("clear_ipi", CAUSE_CLEAR_IPI)
DECLARE_CAUSE("reset", CAUSE_RESET)
DECLARE_CAUSE("tohost", CAUSE_TOHOST)
DECLARE_CAUSE("fromhost", CAUSE_FROMHOST)
DECLARE_CAUSE("cycle", CAUSE_CYCLE)
DECLARE_CAUSE("time", CAUSE_TIME)
DECLARE_CAUSE("instret", CAUSE_INSTRET)
DECLARE_CAUSE("stats", CAUSE_STATS)
DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
720,8 → 881,47
DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
DECLARE_CAUSE("counth", CAUSE_COUNTH)
DECLARE_CAUSE("sstatus", CAUSE_SSTATUS)
DECLARE_CAUSE("stvec", CAUSE_STVEC)
DECLARE_CAUSE("sie", CAUSE_SIE)
DECLARE_CAUSE("stimecmp", CAUSE_STIMECMP)
DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH)
DECLARE_CAUSE("sepc", CAUSE_SEPC)
DECLARE_CAUSE("sip", CAUSE_SIP)
DECLARE_CAUSE("sptbr", CAUSE_SPTBR)
DECLARE_CAUSE("sasid", CAUSE_SASID)
DECLARE_CAUSE("cyclew", CAUSE_CYCLEW)
DECLARE_CAUSE("timew", CAUSE_TIMEW)
DECLARE_CAUSE("instretw", CAUSE_INSTRETW)
DECLARE_CAUSE("stime", CAUSE_STIME)
DECLARE_CAUSE("scause", CAUSE_SCAUSE)
DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR)
DECLARE_CAUSE("stimew", CAUSE_STIMEW)
DECLARE_CAUSE("mstatus", CAUSE_MSTATUS)
DECLARE_CAUSE("mtvec", CAUSE_MTVEC)
DECLARE_CAUSE("mtdeleg", CAUSE_MTDELEG)
DECLARE_CAUSE("mie", CAUSE_MIE)
DECLARE_CAUSE("mtimecmp", CAUSE_MTIMECMP)
DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH)
DECLARE_CAUSE("mepc", CAUSE_MEPC)
DECLARE_CAUSE("mcause", CAUSE_MCAUSE)
DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR)
DECLARE_CAUSE("mip", CAUSE_MIP)
DECLARE_CAUSE("mtime", CAUSE_MTIME)
DECLARE_CAUSE("mcpuid", CAUSE_MCPUID)
DECLARE_CAUSE("mimpid", CAUSE_MIMPID)
DECLARE_CAUSE("mhartid", CAUSE_MHARTID)
DECLARE_CAUSE("mtohost", CAUSE_MTOHOST)
DECLARE_CAUSE("mfromhost", CAUSE_MFROMHOST)
DECLARE_CAUSE("mreset", CAUSE_MRESET)
DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
DECLARE_CAUSE("timeh", CAUSE_TIMEH)
DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
DECLARE_CAUSE("cyclehw", CAUSE_CYCLEHW)
DECLARE_CAUSE("timehw", CAUSE_TIMEHW)
DECLARE_CAUSE("instrethw", CAUSE_INSTRETHW)
DECLARE_CAUSE("stimeh", CAUSE_STIMEH)
DECLARE_CAUSE("stimehw", CAUSE_STIMEHW)
DECLARE_CAUSE("mtimeh", CAUSE_MTIMEH)
#endif
/riscv-tests/lui.S
0,0 → 1,36
# See LICENSE for license details.
 
#*****************************************************************************
# lui.S
#-----------------------------------------------------------------------------
#
# Test lui instruction.
#
 
#include "riscv_test.h"
#include "test_macros.h"
 
RVTEST_RV32U
RVTEST_CODE_BEGIN
 
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
 
TEST_CASE( 2, x1, 0x00000000, lui x1, 0x00000 );
TEST_CASE( 3, x1, 0xfffff800, lui x1, 0xfffff;sra x1,x1,1);
TEST_CASE( 4, x1, 0x000007ff, lui x1, 0x7ffff;sra x1,x1,20);
TEST_CASE( 5, x1, 0xfffff800, lui x1, 0x80000;sra x1,x1,20);
 
TEST_CASE( 6, x0, 0, lui x0, 0x80000 );
 
TEST_PASSFAIL
 
RVTEST_CODE_END
 
.data
RVTEST_DATA_BEGIN
 
TEST_DATA
 
RVTEST_DATA_END
/riscv-tests/README
1,5 → 1,6
# RISC-V ISA Tests
 
This directory contains a mirror of the tests from the riscv-tests repository
(https://github.com/riscv/riscv-tests) that are used in the Potato processor.
This directory contains a mirror of various tests from the riscv-tests repository
(https://github.com/riscv/riscv-tests) that are used to verify the correct operation
of the Potato processor.
 
/riscv-tests/scall.S
0,0 → 1,49
# See LICENSE for license details.
 
#*****************************************************************************
# scall.S
#-----------------------------------------------------------------------------
#
# Test syscall trap.
#
 
#include "riscv_test.h"
#include "test_macros.h"
 
RVTEST_RV32M
RVTEST_CODE_BEGIN
 
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
#define sepc mepc
#define stvec_handler mtvec_handler
 
#undef CAUSE_SUPERVISOR_ECALL
#define CAUSE_SUPERVISOR_ECALL CAUSE_MACHINE_ECALL
 
li TESTNUM, 2
scall
j fail
 
j pass
 
TEST_PASSFAIL
 
stvec_handler:
li t1, CAUSE_SUPERVISOR_ECALL
csrr t0, scause
bne t0, t1, fail
csrr t0, sepc
addi t0, t0, 8
csrw sepc, t0
sret
 
RVTEST_CODE_END
 
.data
RVTEST_DATA_BEGIN
 
TEST_DATA
 
RVTEST_DATA_END
/riscv-tests/sbreak.S
0,0 → 1,46
# See LICENSE for license details.
 
#*****************************************************************************
# scall.S
#-----------------------------------------------------------------------------
#
# Test syscall trap.
#
 
#include "riscv_test.h"
#include "test_macros.h"
 
RVTEST_RV32M
RVTEST_CODE_BEGIN
 
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
#define sepc mepc
#define stvec_handler mtvec_handler
 
li TESTNUM, 2
sbreak
j fail
 
j pass
 
TEST_PASSFAIL
 
stvec_handler:
li t1, CAUSE_BREAKPOINT
csrr t0, scause
bne t0, t1, fail
csrr t0, sepc
addi t0, t0, 8
csrw sepc, t0
sret
 
RVTEST_CODE_END
 
.data
RVTEST_DATA_BEGIN
 
TEST_DATA
 
RVTEST_DATA_END
/riscv-tests/test_macros.h
492,12 → 492,12
TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
 
#define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
inst f3, f0; fmv.x.s a0, f3)
 
#define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
inst f3, f0; fmv.x.d a0, f3)
 
#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
570,9 → 570,8
#-----------------------------------------------------------------------
 
#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
csrs status, SR_EI; \
la a0, handler ## testnum; \
csrw evec, a0; \
csrw stvec, a0; \
vsetcfg nxreg, nfreg; \
li a0, 4; \
vsetvl a0, a0; \
597,10 → 596,10
handler ## testnum: \
vxcptkill; \
li TESTNUM,2; \
vxcptcause a0; \
csrr a0, scause; \
li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
bne a0,a1,fail; \
vxcptaux a0; \
csrr a0, sbadaddr; \
la a1, illegal ## testnum; \
lw a2, 0(a1); \
bne a0, a2, fail; \
631,9 → 630,8
bne a1,a2,fail; \
 
#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
csrs status, SR_EI; \
la a0, handler ## testnum; \
csrw evec, a0; \
csrw stvec, a0; \
vsetcfg nxreg, nfreg; \
li a0, 4; \
vsetvl a0, a0; \
657,10 → 655,10
handler ## testnum: \
vxcptkill; \
li TESTNUM,2; \
vxcptcause a0; \
csrr a0, scause; \
li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
bne a0,a1,fail; \
vxcptaux a0; \
csrr a0, sbadaddr; \
la a1,illegal ## testnum; \
bne a0,a1,fail; \
vsetcfg 32,0; \
696,7 → 694,7
#define TEST_PASSFAIL \
bne x0, TESTNUM, pass; \
fail: \
RVTEST_FAIL \
RVTEST_FAIL; \
pass: \
RVTEST_PASS \
 
/src/pp_execute.vhd
17,8 → 17,9
 
stall, flush : in std_logic;
 
-- IRQ input:
-- Interrupt inputs:
irq : in std_logic_vector(7 downto 0);
software_interrupt, timer_interrupt : in std_logic;
 
-- Data memory outputs:
dmem_address : out std_logic_vector(31 downto 0);
77,9 → 78,11
count_instruction_out : out std_logic;
 
-- Exception control registers:
status_in : in csr_status_register;
evec_in : in std_logic_vector(31 downto 0);
evec_out : out std_logic_vector(31 downto 0);
ie_in, ie1_in : in std_logic;
mie_in : in std_logic_vector(31 downto 0);
mtvec_in : in std_logic_vector(31 downto 0);
mtvec_out : out std_logic_vector(31 downto 0);
--mepc_in : in std_logic_vector(31 downto 0);
 
-- Exception signals:
decode_exception_in : in std_logic;
143,8 → 146,8
signal do_jump : std_logic;
signal jump_target : std_logic_vector(31 downto 0);
 
signal sr : csr_status_register;
signal evec, evec_forwarded : std_logic_vector(31 downto 0);
signal mtvec, mtvec_forwarded : std_logic_vector(31 downto 0);
signal mie, mie_forwarded : std_logic_vector(31 downto 0);
 
signal csr_write : csr_write_mode;
signal csr_addr : csr_address;
158,7 → 161,7
 
signal exception_taken : std_logic;
signal exception_cause : csr_exception_cause;
signal exception_vaddr : std_logic_vector(31 downto 0);
signal exception_addr : std_logic_vector(31 downto 0);
 
signal exception_context_forwarded : csr_exception_context;
 
185,9 → 188,10
 
exception_out <= exception_taken;
exception_context_out <= (
status => exception_context_forwarded.status,
ie => exception_context_forwarded.ie,
ie1 => exception_context_forwarded.ie1,
cause => exception_cause,
badvaddr => exception_vaddr
badaddr => exception_addr
) when exception_taken = '1' else exception_context_forwarded;
 
do_jump <= (to_std_logic(branch = BRANCH_JUMP or branch = BRANCH_JUMP_INDIRECT)
196,19 → 200,19
jump_out <= do_jump;
jump_target_out <= jump_target;
 
evec_out <= evec_forwarded;
exception_taken <= (decode_exception or to_std_logic(exception_cause /= CSR_CAUSE_NONE) or irq_asserted) and not stall;
mtvec_out <= std_logic_vector(unsigned(mtvec_forwarded) + CSR_MTVEC_M_OFFSET);
exception_taken <= not stall and (decode_exception or to_std_logic(exception_cause /= CSR_CAUSE_NONE));
 
irq_asserted <= to_std_logic(exception_context_forwarded.status.ei = '1' and
(irq and exception_context_forwarded.status.im) /= x"00");
irq_asserted <= to_std_logic(exception_context_forwarded.ie = '1' and (irq and mie_forwarded(31 downto 24)) /= x"00");
 
rs1_data <= rs1_data_in;
rs2_data <= rs2_data_in;
 
dmem_address <= alu_result;
dmem_address <= alu_result when (mem_op /= MEMOP_TYPE_NONE and mem_op /= MEMOP_TYPE_INVALID) and exception_taken = '0'
else (others => '0');
dmem_data_out <= rs2_forwarded;
dmem_write_req <= '1' when mem_op = MEMOP_TYPE_STORE else '0';
dmem_read_req <= '1' when memop_is_load(mem_op) else '0';
dmem_write_req <= '1' when mem_op = MEMOP_TYPE_STORE and exception_taken = '0' else '0';
dmem_read_req <= '1' when memop_is_load(mem_op) and exception_taken = '0' else '0';
 
pipeline_register: process(clk)
begin
251,11 → 255,9
csr_use_immediate <= csr_use_immediate_in;
csr_writeable <= csr_writeable_in;
 
-- Status register;
sr <= status_in;
 
-- Exception vector base:
evec <= evec_in;
mtvec <= mtvec_in;
mie <= mie_in;
 
-- Instruction decoder exceptions:
decode_exception <= decode_exception_in;
278,13 → 280,13
end case;
end process set_data_size;
 
get_irq_num: process(irq, exception_context_forwarded)
get_irq_num: process(irq, exception_context_forwarded, mie_forwarded)
variable temp : std_logic_vector(3 downto 0);
begin
temp := (others => '0');
 
for i in 0 to 7 loop
if irq(i) = '1' and exception_context_forwarded.status.im(i) = '1' then
if irq(i) = '1' and mie_forwarded(24 + i) = '1' then
temp := std_logic_vector(to_unsigned(i, temp'length));
exit;
end if;
323,10 → 325,15
end process instr_misalign_check;
 
find_exception_cause: process(decode_exception, decode_exception_cause, mem_op,
data_misaligned, instr_misaligned, irq_asserted, irq_asserted_num)
data_misaligned, instr_misaligned, irq_asserted, irq_asserted_num, mie_forwarded,
software_interrupt, timer_interrupt, exception_context_forwarded)
begin
if irq_asserted = '1' then
exception_cause <= std_logic_vector(unsigned(CSR_CAUSE_IRQ_BASE) + unsigned(irq_asserted_num));
elsif software_interrupt = '1' and mie_forwarded(CSR_MIE_MSIE) = '1' and exception_context_forwarded.ie = '1' then
exception_cause <= CSR_CAUSE_SOFTWARE_INT;
elsif timer_interrupt = '1' and mie_forwarded(CSR_MIE_MTIE) = '1' and exception_context_forwarded.ie = '1' then
exception_cause <= CSR_CAUSE_TIMER_INT;
elsif decode_exception = '1' then
exception_cause <= decode_exception_cause;
elsif mem_op = MEMOP_TYPE_INVALID then
342,16 → 349,16
end if;
end process find_exception_cause;
 
find_exception_vaddr: process(instr_misaligned, data_misaligned, jump_target, alu_result)
find_exception_addr: process(instr_misaligned, data_misaligned, jump_target, alu_result)
begin
if instr_misaligned = '1' then
exception_vaddr <= jump_target;
exception_addr <= jump_target;
elsif data_misaligned = '1' then
exception_vaddr <= alu_result;
exception_addr <= alu_result;
else
exception_vaddr <= (others => '0');
exception_addr <= (others => '0');
end if;
end process find_exception_vaddr;
end process find_exception_addr;
 
calc_jump_tgt: process(branch, pc, rs1_forwarded, immediate, csr_value_forwarded)
begin
361,7 → 368,7
when BRANCH_JUMP_INDIRECT =>
jump_target <= std_logic_vector(unsigned(rs1_forwarded) + unsigned(immediate));
when BRANCH_SRET =>
jump_target <= csr_value_forwarded; -- Will be the EPC value in the case of SRET
jump_target <= csr_value_forwarded;
when others =>
jump_target <= (others => '0');
end case;
417,20 → 424,20
csr_value, mem_csr_value, wb_csr_value, csr_writeable, mem_exception, wb_exception,
mem_exception_context, wb_exception_context)
begin
if csr_addr = CSR_CAUSE and mem_exception = '1' then
if csr_addr = CSR_MCAUSE and mem_exception = '1' then
csr_value_forwarded <= to_std_logic_vector(mem_exception_context.cause);
elsif csr_addr = CSR_STATUS and mem_exception = '1' then
csr_value_forwarded <= to_std_logic_vector(mem_exception_context.status);
elsif csr_addr = CSR_BADVADDR and mem_exception = '1' then
csr_value_forwarded <= mem_exception_context.badvaddr;
elsif csr_addr = CSR_MSTATUS and mem_exception = '1' then
csr_value_forwarded <= csr_make_mstatus(mem_exception_context.ie, mem_exception_context.ie1);
elsif csr_addr = CSR_MBADADDR and mem_exception = '1' then
csr_value_forwarded <= mem_exception_context.badaddr;
elsif mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = csr_addr and csr_writeable then
csr_value_forwarded <= mem_csr_value;
elsif csr_addr = CSR_CAUSE and wb_exception = '1' then
elsif csr_addr = CSR_MCAUSE and wb_exception = '1' then
csr_value_forwarded <= to_std_logic_vector(wb_exception_context.cause);
elsif csr_addr = CSR_STATUS and wb_exception = '1' then
csr_value_forwarded <= to_std_logic_vector(wb_exception_context.status);
elsif csr_addr = CSR_BADVADDR and wb_exception = '1' then
csr_value_forwarded <= wb_exception_context.badvaddr;
elsif csr_addr = CSR_MSTATUS and wb_exception = '1' then
csr_value_forwarded <= csr_make_mstatus(wb_exception_context.ie, wb_exception_context.ie1);
elsif csr_addr = CSR_MBADADDR and wb_exception = '1' then
csr_value_forwarded <= wb_exception_context.badaddr;
elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = csr_addr and csr_writeable then
csr_value_forwarded <= wb_csr_value;
else
438,40 → 445,55
end if;
end process csr_forward;
 
evec_forward: process(mem_csr_write, mem_csr_addr, mem_csr_value,
wb_csr_write, wb_csr_addr, wb_csr_value, evec)
mtvec_forward: process(mem_csr_write, mem_csr_addr, mem_csr_value,
wb_csr_write, wb_csr_addr, wb_csr_value, mtvec)
begin
if mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_EVEC then
evec_forwarded <= mem_csr_value;
elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_EVEC then
evec_forwarded <= wb_csr_value;
if mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MTVEC then
mtvec_forwarded <= mem_csr_value;
elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MTVEC then
mtvec_forwarded <= wb_csr_value;
else
evec_forwarded <= evec;
mtvec_forwarded <= mtvec;
end if;
end process evec_forward;
end process mtvec_forward;
 
mie_forward: process(mem_csr_write, mem_csr_addr, mem_csr_value,
wb_csr_write, wb_csr_addr, wb_csr_value, mie)
begin
if mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MIE then
mie_forwarded <= mem_csr_value;
elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MIE then
mie_forwarded <= wb_csr_value;
else
mie_forwarded <= mie;
end if;
end process mie_forward;
 
exception_ctx_forward: process(mem_exception, wb_exception, mem_exception_context, wb_exception_context,
exception_cause, exception_vaddr, mem_csr_write, mem_csr_addr, mem_csr_value,
wb_csr_write, wb_csr_addr, wb_csr_value, sr)
exception_cause, exception_addr, mem_csr_write, mem_csr_addr, mem_csr_value,
wb_csr_write, wb_csr_addr, wb_csr_value, ie_in, ie1_in)
begin
if mem_exception = '1' then
exception_context_forwarded <= mem_exception_context;
elsif mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_STATUS then
elsif mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MSTATUS then
exception_context_forwarded <= (
status => to_csr_status_register(mem_csr_value),
cause => mem_exception_context.cause,
badvaddr => mem_exception_context.badvaddr);
ie => mem_csr_value(CSR_SR_IE),
ie1 => mem_csr_value(CSR_SR_IE1),
cause => exception_cause,
badaddr => exception_addr);
elsif wb_exception = '1' then
exception_context_forwarded <= wb_exception_context;
elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_STATUS then
elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MSTATUS then
exception_context_forwarded <= (
status => to_csr_status_register(wb_csr_value),
cause => wb_exception_context.cause,
badvaddr => wb_exception_context.badvaddr);
ie => wb_csr_value(CSR_SR_IE),
ie1 => wb_csr_value(CSR_SR_IE1),
cause => exception_cause,
badaddr => exception_addr);
else
exception_context_forwarded.status <= sr;
exception_context_forwarded.ie <= ie_in;
exception_context_forwarded.ie1 <= ie1_in;
exception_context_forwarded.cause <= exception_cause;
exception_context_forwarded.badvaddr <= exception_vaddr;
exception_context_forwarded.badaddr <= exception_addr;
end if;
end process exception_ctx_forward;
 
/src/pp_potato.vhd
12,11 → 12,12
entity pp_potato is
generic(
PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000" --! Address of the first instruction to execute.
RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000200" --! Address of the first instruction to execute.
);
port(
clk : in std_logic;
reset : in std_logic;
clk : in std_logic;
timer_clk : in std_logic;
reset : in std_logic;
 
-- Interrupts:
irq : in std_logic_vector(7 downto 0);
68,7 → 69,7
) port map(
clk => clk,
reset => reset,
timer_clk => clk,
timer_clk => timer_clk,
imem_address => imem_address,
imem_data_in => imem_data,
imem_req => imem_req,
/src/pp_memory.vhd
84,7 → 84,7
mem_op <= MEMOP_TYPE_NONE;
rd_write_out <= '0';
csr_write_out <= CSR_WRITE_REPLACE;
csr_addr_out <= CSR_EPC;
csr_addr_out <= CSR_MEPC;
csr_data_out <= pc;
count_instr_out <= '0';
else
108,27 → 108,20
exception_out <= exception_in or to_std_logic(branch = BRANCH_SRET);
 
if exception_in = '1' then
exception_context_out.status <= (
pim => exception_context_in.status.im,
im => (others => '0'),
pei => exception_context_in.status.ei,
ei => '0'
);
exception_context_out.ie <= '0';
exception_context_out.ie1 <= exception_context_in.ie;
exception_context_out.cause <= exception_context_in.cause;
exception_context_out.badvaddr <= exception_context_in.badvaddr;
exception_context_out.badaddr <= exception_context_in.badaddr;
elsif branch = BRANCH_SRET then
exception_context_out.status <= (
pim => exception_context_in.status.pim,
im => exception_context_in.status.pim,
pei => exception_context_in.status.pei,
ei => exception_context_in.status.pei
);
exception_context_out.ie <= exception_context_in.ie1;
exception_context_out.ie1 <= exception_context_in.ie;
exception_context_out.cause <= CSR_CAUSE_NONE;
exception_context_out.badvaddr <= (others => '0');
exception_context_out.badaddr <= (others => '0');
else
exception_context_out.status <= exception_context_in.status;
exception_context_out.ie <= exception_context_in.ie;
exception_context_out.ie1 <= exception_context_in.ie1;
exception_context_out.cause <= CSR_CAUSE_NONE;
exception_context_out.badvaddr <= (others => '0');
exception_context_out.badaddr <= (others => '0');
end if;
end if;
end if;
/src/pp_control_unit.vhd
25,7 → 25,7
 
-- Exception signals:
decode_exception : out std_logic;
decode_exception_cause : out std_logic_vector(4 downto 0);
decode_exception_cause : out csr_exception_cause;
 
-- Control register signals:
csr_write : out csr_write_mode;
45,7 → 45,7
 
architecture behaviour of pp_control_unit is
signal exception : std_logic;
signal exception_cause : std_logic_vector(4 downto 0);
signal exception_cause : csr_exception_cause;
signal alu_op_temp : alu_operation;
begin
 
125,13 → 125,13
 
if funct12 = x"000" then
exception <= '1';
exception_cause <= CSR_CAUSE_SYSCALL;
exception_cause <= CSR_CAUSE_ECALL;
branch <= BRANCH_NONE;
elsif funct12 = x"001" then
exception <= '1';
exception_cause <= CSR_CAUSE_BREAKPOINT;
branch <= BRANCH_NONE;
elsif funct12 = x"800" then
elsif funct12 = CSR_EPC_ERET then
exception <= '0';
exception_cause <= CSR_CAUSE_NONE;
branch <= BRANCH_SRET;
/src/pp_decode.vhd
111,8 → 111,8
 
decode_csr_addr: process(immediate_value)
begin
if immediate_value(11 downto 0) = CSR_EPC_SRET then
csr_addr <= CSR_EPC;
if immediate_value(11 downto 0) = CSR_EPC_ERET then
csr_addr <= CSR_MEPC;
else
csr_addr <= immediate_value(11 downto 0);
end if;
/src/pp_csr_unit.vhd
7,6 → 7,7
use ieee.numeric_std.all;
 
use work.pp_csr.all;
use work.pp_utilities.all;
 
entity pp_csr_unit is
generic(
16,6 → 17,9
clk, timer_clk : in std_logic;
reset : in std_logic;
 
-- IRQ signals:
irq : in std_logic_vector(7 downto 0);
 
-- Count retired instruction:
count_instruction : in std_logic;
 
39,35 → 43,58
exception_context : in csr_exception_context;
exception_context_write : in std_logic;
 
-- Interrupts originating from this unit:
software_interrupt_out : out std_logic;
timer_interrupt_out : out std_logic;
 
-- Registers needed for exception handling, always read:
status_out : out csr_status_register;
evec_out : out std_logic_vector(31 downto 0)
mie_out : out std_logic_vector(31 downto 0);
mtvec_out : out std_logic_vector(31 downto 0);
ie_out, ie1_out : out std_logic
);
end entity pp_csr_unit;
 
architecture behaviour of pp_csr_unit is
 
-- Implemented counters:
-- Counters:
signal counter_time : std_logic_vector(63 downto 0);
signal counter_cycle : std_logic_vector(63 downto 0);
signal counter_instret : std_logic_vector(63 downto 0);
 
-- Implemented registers:
signal sup0, sup1 : std_logic_vector(31 downto 0) := (others => '0');
signal epc, evec : std_logic_vector(31 downto 0) := (others => '0');
signal badvaddr : std_logic_vector(31 downto 0) := (others => '0');
signal cause : csr_exception_cause;
-- Machine time counter:
signal counter_mtime : std_logic_vector(31 downto 0);
signal mtime_compare : std_logic_vector(31 downto 0);
 
-- Machine-mode registers:
signal mcause : csr_exception_cause;
signal mbadaddr : std_logic_vector(31 downto 0);
signal mscratch : std_logic_vector(31 downto 0);
signal mepc : std_logic_vector(31 downto 0);
signal mtvec : std_logic_vector(31 downto 0) := x"00000100";
signal mie : std_logic_vector(31 downto 0) := (others => '0');
 
-- Interrupt enable bits:
signal ie, ie1 : std_logic;
 
-- HTIF FROMHOST register:
signal fromhost: std_logic_vector(31 downto 0);
 
-- Status register:
signal status_register : csr_status_register;
-- Interrupt signals:
signal timer_interrupt : std_logic;
signal software_interrupt : std_logic;
 
begin
 
read_writeable <= csr_is_writeable(read_address);
-- Interrupt signals:
software_interrupt_out <= software_interrupt;
timer_interrupt_out <= timer_interrupt;
ie_out <= ie;
ie1_out <= ie1;
mie_out <= mie;
 
-- The two upper bits of the CSR address encodes the accessibility of the CSR:
read_writeable <= read_address(11 downto 10) /= b"11";
 
--! Updates the FROMHOST register when new data is available.
htif_fromhost: process(clk)
begin
86,7 → 113,7
tohost_data <= (others => '0');
tohost_updated <= '0';
else
if write_mode /= CSR_WRITE_NONE and write_address = CSR_TOHOST then
if write_mode /= CSR_WRITE_NONE and write_address = CSR_MTOHOST then
tohost_data <= write_data_in;
tohost_updated <= '1';
else
96,32 → 123,67
end if;
end process htif_tohost;
 
mtime_counter: process(timer_clk, reset)
begin
if reset = '1' then -- Asynchronous reset because timer_clk is slower than clk
counter_mtime <= (others => '0');
elsif rising_edge(timer_clk) then
counter_mtime <= std_logic_vector(unsigned(counter_mtime) + 1);
end if;
end process mtime_counter;
 
mtime_interrupt: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
timer_interrupt <= '0';
else
if write_mode /= CSR_WRITE_NONE and write_address = CSR_MTIMECMP then
timer_interrupt <= '0';
elsif counter_mtime = mtime_compare then
timer_interrupt <= '1';
end if;
end if;
end if;
end process mtime_interrupt;
 
write: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
status_register <= CSR_SR_DEFAULT;
software_interrupt <= '0';
mtvec <= x"00000100";
mepc <= x"00000100";
mie <= (others => '0');
ie <= '0';
ie1 <= '0';
else
if exception_context_write = '1' then
status_register <= exception_context.status;
cause <= exception_context.cause;
badvaddr <= exception_context.badvaddr;
ie <= exception_context.ie;
ie1 <= exception_context.ie1;
mcause <= exception_context.cause;
mbadaddr <= exception_context.badaddr;
end if;
 
if write_mode /= CSR_WRITE_NONE then
case write_address is
when CSR_STATUS =>
if exception_context_write = '0' then
status_register <= to_csr_status_register(write_data_in);
end if;
when CSR_EPC =>
epc <= write_data_in;
when CSR_EVEC =>
evec <= write_data_in;
when CSR_SUP0 =>
sup0 <= write_data_in;
when CSR_SUP1 =>
sup1 <= write_data_in;
when CSR_MSTATUS => -- Status register
ie1 <= write_data_in(CSR_SR_IE1);
ie <= write_data_in(CSR_SR_IE);
when CSR_MSCRATCH => -- Scratch register
mscratch <= write_data_in;
when CSR_MEPC => -- Exception return address
mepc <= write_data_in;
--when CSR_MCAUSE => -- Exception cause
-- mcause <= write_data_in(31) & write_data_in(4 downto 0);
when CSR_MTVEC => -- Exception vector address
mtvec <= write_data_in;
when CSR_MTIMECMP => -- Time compare register
mtime_compare <= write_data_in;
when CSR_MIE => -- Interrupt enable register:
mie <= write_data_in;
when CSR_MIP => -- Interrupt pending register:
software_interrupt <= write_data_in(CSR_MIP_MSIP);
when others =>
-- Ignore writes to invalid or read-only registers
end case;
130,21 → 192,14
end if;
end process write;
 
status_out <= exception_context.status when exception_context_write = '1' else status_register;
 
read: process(clk)
begin
if rising_edge(clk) then
--if exception_context_write = '1' then
-- status_out <= exception_context.status;
--else
-- status_out <= status_register;
--end if;
 
if write_mode /= CSR_WRITE_NONE and write_address = CSR_EVEC then
evec_out <= write_data_in;
if write_mode /= CSR_WRITE_NONE and write_address = CSR_MTVEC then
mtvec_out <= write_data_in;
else
evec_out <= evec;
mtvec_out <= mtvec;
end if;
 
if write_mode /= CSR_WRITE_NONE and write_address = read_address then
151,30 → 206,46
read_data_out <= write_data_in;
else
case read_address is
-- Status and control registers:
when CSR_STATUS => -- Status register
read_data_out <= to_std_logic_vector(status_register);
when CSR_HARTID => -- Processor ID
 
-- Machine mode registers:
when CSR_MCPUID => -- CPU features register
read_data_out <= (
8 => '1', -- Set the bit corresponding to I
others => '0');
when CSR_MIMPID => -- Implementation/Implementor ID
read_data_out <= (31 downto 16 => '0') & x"8000";
-- The anonymous source ID, 0x8000 is used until an open-source implementation ID
-- is available for use.
when CSR_MHARTID => -- Hardware thread ID
read_data_out <= PROCESSOR_ID;
when CSR_FROMHOST => -- Fromhost data
when CSR_MFROMHOST => -- Data from a host environment
read_data_out <= fromhost;
when CSR_EPC | CSR_EPC_SRET => -- Exception PC value
read_data_out <= epc;
when CSR_EVEC => -- Exception handler address
read_data_out <= evec;
when CSR_CAUSE => -- Exception cause
read_data_out <= to_std_logic_vector(cause);
when CSR_BADVADDR => -- Load/store address responsible for the exception
read_data_out <= badvaddr;
when CSR_MSTATUS => -- Status register
read_data_out <= csr_make_mstatus(ie, ie1);
when CSR_MSCRATCH => -- Scratch register
read_data_out <= mscratch;
when CSR_MEPC => -- Exception PC value
read_data_out <= mepc;
when CSR_MTVEC => -- Exception vector address
read_data_out <= mtvec;
when CSR_MTDELEG => -- Exception vector delegation register, unsupported
read_data_out <= (others => '0');
when CSR_MIP => -- Interrupt pending
read_data_out <= irq & (CSR_MIP_MTIP => timer_interrupt, CSR_MIP_MSIP => software_interrupt,
23 downto 8 => '0', 6 downto 4 => '0', 2 downto 0 => '0');
when CSR_MIE => -- Interrupt enable register
read_data_out <= mie;
when CSR_MBADADDR => -- Bad memory address
read_data_out <= mbadaddr;
when CSR_MCAUSE => -- Exception cause
read_data_out <= mcause(5) & (30 downto 5 => '0') & mcause(4 downto 0); --to_std_logic_vector(mcause);
-- Supporting registers:
when CSR_SUP0 =>
read_data_out <= sup0;
when CSR_SUP1 =>
read_data_out <= sup1;
-- Timers and counters:
when CSR_MTIME => -- Machine time counter register
read_data_out <= counter_mtime;
when CSR_MTIMECMP => -- Machine time compare register
read_data_out <= mtime_compare;
 
when CSR_TIME =>
read_data_out <= counter_time(31 downto 0);
when CSR_TIMEH =>
/src/pp_csr.vhd
12,8 → 12,9
subtype csr_address is std_logic_vector(11 downto 0);
 
--! Type used for exception cause values.
subtype csr_exception_cause is std_logic_vector(4 downto 0);
subtype csr_exception_cause is std_logic_vector(5 downto 0); -- Upper bit is the interrupt bit
 
--! Converts an exception cause to a std_logic_vector.
function to_std_logic_vector(input : in csr_exception_cause) return std_logic_vector;
 
--! Control/status register write mode:
22,28 → 23,22
);
 
-- Exception cause values:
constant CSR_CAUSE_INSTR_MISALIGN : csr_exception_cause := b"00000";
constant CSR_CAUSE_INSTR_FETCH : csr_exception_cause := b"00001";
constant CSR_CAUSE_INVALID_INSTR : csr_exception_cause := b"00010";
constant CSR_CAUSE_SYSCALL : csr_exception_cause := b"00110";
constant CSR_CAUSE_BREAKPOINT : csr_exception_cause := b"00111";
constant CSR_CAUSE_LOAD_MISALIGN : csr_exception_cause := b"01000";
constant CSR_CAUSE_STORE_MISALIGN : csr_exception_cause := b"01001";
constant CSR_CAUSE_LOAD_ERROR : csr_exception_cause := b"01010";
constant CSR_CAUSE_STORE_ERROR : csr_exception_cause := b"01011";
constant CSR_CAUSE_FROMHOST : csr_exception_cause := b"11110";
constant CSR_CAUSE_NONE : csr_exception_cause := b"11111";
constant CSR_CAUSE_INSTR_MISALIGN : csr_exception_cause := b"000000";
constant CSR_CAUSE_INSTR_FETCH : csr_exception_cause := b"000001";
constant CSR_CAUSE_INVALID_INSTR : csr_exception_cause := b"000010";
constant CSR_CAUSE_BREAKPOINT : csr_exception_cause := b"000011";
constant CSR_CAUSE_LOAD_MISALIGN : csr_exception_cause := b"000100";
constant CSR_CAUSE_LOAD_ERROR : csr_exception_cause := b"000101";
constant CSR_CAUSE_STORE_MISALIGN : csr_exception_cause := b"000110";
constant CSR_CAUSE_STORE_ERROR : csr_exception_cause := b"000111";
constant CSR_CAUSE_ECALL : csr_exception_cause := b"001011";
constant CSR_CAUSE_NONE : csr_exception_cause := b"011111";
 
constant CSR_CAUSE_IRQ_BASE : csr_exception_cause := b"10000";
constant CSR_CAUSE_SOFTWARE_INT : csr_exception_cause := b"100000";
constant CSR_CAUSE_TIMER_INT : csr_exception_cause := b"100001";
constant CSR_CAUSE_IRQ_BASE : csr_exception_cause := b"110000";
 
-- Control register IDs, specified in the immediate of csr* instructions:
constant CSR_STATUS : csr_address := x"50a";
constant CSR_HARTID : csr_address := x"50b";
constant CSR_SUP0 : csr_address := x"500";
constant CSR_SUP1 : csr_address := x"501";
constant CSR_BADVADDR : csr_address := x"503";
constant CSR_TOHOST : csr_address := x"51e";
constant CSR_FROMHOST : csr_address := x"51f";
-- Control register IDs, specified in the immediate field of csr* instructions:
constant CSR_CYCLE : csr_address := x"c00";
constant CSR_CYCLEH : csr_address := x"c80";
constant CSR_TIME : csr_address := x"c01";
50,57 → 45,61
constant CSR_TIMEH : csr_address := x"c81";
constant CSR_INSTRET : csr_address := x"c02";
constant CSR_INSTRETH : csr_address := x"c82";
constant CSR_EPC : csr_address := x"502";
constant CSR_EVEC : csr_address := x"508";
constant CSR_CAUSE : csr_address := x"509";
 
-- Values used as control register IDs in SRET, SCALL and SBREAK:
constant CSR_EPC_SRET : csr_address := x"800";
constant CSR_MCPUID : csr_address := x"f00";
constant CSR_MIMPID : csr_address := x"f01";
constant CSR_MHARTID : csr_address := x"f10";
 
constant CSR_MSTATUS : csr_address := x"300";
constant CSR_MTVEC : csr_address := x"301";
constant CSR_MTDELEG : csr_address := x"302";
constant CSR_MIE : csr_address := x"304";
 
constant CSR_MTIMECMP : csr_address := x"321";
constant CSR_MTIME : csr_address := x"701";
 
constant CSR_MSCRATCH : csr_address := x"340";
constant CSR_MEPC : csr_address := x"341";
constant CSR_MCAUSE : csr_address := x"342";
constant CSR_MBADADDR : csr_address := x"343";
constant CSR_MIP : csr_address := x"344";
 
constant CSR_MTOHOST : csr_address := x"780";
constant CSR_MFROMHOST : csr_address := x"781";
 
-- Values used as control register IDs in ERET:
constant CSR_EPC_ERET : csr_address := x"100";
 
-- Offset into the exception vector for handling machine-mode exceptions:
constant CSR_MTVEC_M_OFFSET : natural := 192;
 
-- Additional CSRs from supervisor mode that aliases machine mode registers
-- in this implementation:
--constant CSR_STVEC : csr_address := x"101";
--constant CSR_SEPC : csr_address := x"141";
 
-- Status register bit indices:
constant CSR_SR_S : natural := 0;
constant CSR_SR_PS : natural := 1;
constant CSR_SR_EI : natural := 2;
constant CSR_SR_PEI : natural := 3;
constant CSR_SR_IE : natural := 0;
constant CSR_SR_IE1 : natural := 3;
 
-- Status register in Potato:
-- * Bit 0, S: Supervisor mode, always 1
-- * Bit 1, PS: Previous supervisor mode bit, always 1
-- * Bit 2, EI: Enable interrupts bit
-- * Bit 3, PEI: Previous enable interrupts bit
-- * Bits 23 downto 16, IM: Interrupt mask
-- * Bits 31 downto 24, PIM: Previous interrupt mask
-- MIE and MIP register bit indices:
constant CSR_MIE_MSIE : natural := 3;
constant CSR_MIE_MTIE : natural := 7;
constant CSR_MIP_MSIP : natural := CSR_MIE_MSIE;
constant CSR_MIP_MTIP : natural := CSR_MIE_MTIE;
 
-- Status register record:
type csr_status_register is
record
ei, pei : std_logic;
im, pim : std_logic_vector(7 downto 0);
end record;
 
-- Exception context; this record contains all state that is stored
-- Exception context; this record contains all state that can be manipulated
-- when an exception is taken.
type csr_exception_context is
record
status : csr_status_register;
cause : csr_exception_cause;
badvaddr : std_logic_vector(31 downto 0);
ie, ie1 : std_logic; -- Enable Interrupt bits
cause : csr_exception_cause;
badaddr : std_logic_vector(31 downto 0);
end record;
 
-- Reset value of the status register:
constant CSR_SR_DEFAULT : csr_status_register := (ei => '0', pei => '0', im => x"00", pim => x"00");
--! Creates the value of the mstatus registe from the EI and EI1 bits.
function csr_make_mstatus(ie, ie1 : in std_logic) return std_logic_vector;
 
-- Converts a status register record into an std_logic_vector:
function to_std_logic_vector(input : in csr_status_register)
return std_logic_vector;
 
-- Converts an std_logic_vector into a status register record:
function to_csr_status_register(input : in std_logic_vector(31 downto 0))
return csr_status_register;
 
--! Checks if a control register is writeable.
function csr_is_writeable(csr : in csr_address) return boolean;
 
end package pp_csr;
 
package body pp_csr is
108,37 → 107,21
function to_std_logic_vector(input : in csr_exception_cause)
return std_logic_vector is
begin
return (31 downto 5 => '0') & input;
return (31 => input(5), 30 downto 5 => '0') & input(4 downto 0);
end function to_std_logic_vector;
 
function to_std_logic_vector(input : in csr_status_register)
return std_logic_vector is
function csr_make_mstatus(ie, ie1 : in std_logic) return std_logic_vector is
variable retval : std_logic_vector(31 downto 0);
begin
return input.pim & input.im & (15 downto 4 => '0') & input.pei & input.ei & '1' & '1';
end function to_std_logic_vector;
 
function to_csr_status_register(input : in std_logic_vector(31 downto 0))
return csr_status_register
is
variable retval : csr_status_register;
begin
retval.ei := input(CSR_SR_EI);
retval.pei := input(CSR_SR_PEI);
retval.im := input(23 downto 16);
retval.pim := input(31 downto 24);
retval := (
11 downto 10 => '1', -- PRV3
8 downto 7 => '1', -- PRV2
5 downto 4 => '1', -- PRV1
CSR_SR_IE1 => ie1, -- IE1
2 downto 1 => '1', -- PRV
CSR_SR_IE => ie, -- IE
others => '0');
return retval;
end function to_csr_status_register;
end function csr_make_mstatus;
 
function csr_is_writeable(csr : in csr_address) return boolean is
begin
case csr is
when CSR_FROMHOST | CSR_CYCLE | CSR_CYCLEH | CSR_HARTID
| CSR_TIME | CSR_TIMEH | CSR_INSTRET | CSR_INSTRETH
| CSR_CAUSE | CSR_BADVADDR =>
return false;
when others =>
return true;
end case;
end function csr_is_writeable;
 
end package body pp_csr;
/src/pp_core.vhd
19,7 → 19,7
entity pp_core is
generic(
PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000" --! Address of the first instruction to execute.
RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000200" --! Address of the first instruction to execute.
);
port(
-- Control inputs:
67,7 → 67,7
-- by the instret counter:
signal if_count_instruction, id_count_instruction : std_logic;
signal ex_count_instruction, mem_count_instruction : std_logic;
signal wb_count_instruction : std_logic;
signal wb_count_instruction : std_logic;
 
-- CSR read port signals:
signal csr_read_data : std_logic_vector(31 downto 0);
75,9 → 75,13
signal csr_read_address, csr_read_address_p : csr_address;
 
-- Status register outputs:
signal status : csr_status_register;
signal evec : std_logic_vector(31 downto 0);
signal mtvec : std_logic_vector(31 downto 0);
signal mie : std_logic_vector(31 downto 0);
signal ie, ie1 : std_logic;
 
-- Internal interrupt signals:
signal software_interrupt, timer_interrupt : std_logic;
 
-- Load hazard detected in the execute stage:
signal load_hazard_detected : std_logic;
 
182,6 → 186,7
clk => clk,
reset => reset,
timer_clk => timer_clk,
irq => irq,
count_instruction => wb_count_instruction,
fromhost_data => fromhost_data,
fromhost_updated => fromhost_write_en,
195,12 → 200,15
write_mode => wb_csr_write,
exception_context => wb_exception_context,
exception_context_write => wb_exception,
status_out => status,
evec_out => evec
mie_out => mie,
mtvec_out => mtvec,
ie_out => ie,
ie1_out => ie1,
software_interrupt_out => software_interrupt,
timer_interrupt_out => timer_interrupt
);
 
csr_read_address <= id_csr_address when stall_ex = '0' else csr_read_address_p;
 
store_previous_csr_addr: process(clk, stall_ex)
begin
if rising_edge(clk) and stall_ex = '0' then
299,6 → 307,8
stall => stall_ex,
flush => flush_ex,
irq => irq,
software_interrupt => software_interrupt,
timer_interrupt => timer_interrupt,
dmem_address => ex_dmem_address,
dmem_data_size => ex_dmem_data_size,
dmem_data_out => ex_dmem_data_out,
337,9 → 347,11
mem_size_out => ex_mem_size,
count_instruction_in => id_count_instruction,
count_instruction_out => ex_count_instruction,
status_in => status,
evec_in => evec,
evec_out => exception_target,
ie_in => ie,
ie1_in => ie1,
mie_in => mie,
mtvec_in => mtvec,
mtvec_out => exception_target,
decode_exception_in => id_exception,
decode_exception_cause_in => id_exception_cause,
exception_out => exception_taken,
/src/pp_fetch.vhd
11,7 → 11,7
--! @brief Instruction fetch unit.
entity pp_fetch is
generic(
RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000"
RESET_ADDRESS : std_logic_vector(31 downto 0)
);
port(
clk : in std_logic;
/testbenches/tb_processor.vhd
12,54 → 12,25
 
entity tb_processor is
generic(
IMEM_SIZE : natural := 2048; --! Size of the instruction memory in bytes.
DMEM_SIZE : natural := 2048; --! Size of the data memory in bytes.
IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
IMEM_SIZE : natural := 4096; --! Size of the instruction memory in bytes.
DMEM_SIZE : natural := 4096; --! Size of the data memory in bytes.
RESET_ADDRESS : std_logic_vector := x"00000200"; --! Processor reset address
IMEM_START_ADDR : std_logic_vector := x"00000100"; --! Instruction memory start address
IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
);
end entity tb_processor;
 
architecture testbench of tb_processor is
 
-- Processor component prototype:
component pp_core is
port(
-- Common inputs:
clk : in std_logic; --! Processor clock
reset : in std_logic; --! Reset signal
timer_clk : in std_logic; --! Timer clock input
-- Instruction memory interface:
imem_address : out std_logic_vector(31 downto 0); --! Address of the next instruction
imem_data_in : in std_logic_vector(31 downto 0); --! Instruction input
imem_req : out std_logic;
imem_ack : in std_logic;
 
-- Data memory interface:
dmem_address : out std_logic_vector(31 downto 0); --! Data address
dmem_data_in : in std_logic_vector(31 downto 0); --! Input from the data memory
dmem_data_out : out std_logic_vector(31 downto 0); --! Ouptut to the data memory
dmem_data_size : out std_logic_vector( 1 downto 0); --! Size of the data, 1 = 8 bits, 2 = 16 bits, 0 = 32 bits.
dmem_read_req : out std_logic; --! Data memory read request
dmem_read_ack : in std_logic; --! Data memory read acknowledge
dmem_write_req : out std_logic; --! Data memory write request
dmem_write_ack : in std_logic; --! Data memory write acknowledge
 
-- Tohost/fromhost interface:
fromhost_data : in std_logic_vector(31 downto 0); --! Data from the host/simulator.
fromhost_write_en : in std_logic; --! Write enable signal from the host/simulator.
tohost_data : out std_logic_vector(31 downto 0); --! Data to the host/simulator.
tohost_write_en : out std_logic; --! Write enable signal to the host/simulator.
 
-- External interrupt input:
irq : in std_logic_vector(7 downto 0) --! IRQ input
);
end component pp_core;
 
-- Clock signal:
signal clk : std_logic := '0';
constant clk_period : time := 10 ns;
 
-- Timer clock signal:
signal timer_clk : std_logic := '0';
constant timer_clk_period : time := 100 ns;
 
-- Common inputs:
signal reset : std_logic := '1';
 
92,9 → 63,9
-- Memory array type:
type memory_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant IMEM_BASE : natural := 0;
constant IMEM_END : natural := IMEM_SIZE - 1;
constant DMEM_BASE : natural := IMEM_SIZE;
constant DMEM_END : natural := IMEM_SIZE + DMEM_SIZE - 1;
constant IMEM_END : natural := IMEM_BASE + IMEM_SIZE - 1;
constant DMEM_BASE : natural := IMEM_END + 1;
constant DMEM_END : natural := IMEM_END + DMEM_SIZE;
 
-- Memories:
signal imem_memory : memory_array(IMEM_BASE to IMEM_END);
104,11 → 75,13
 
begin
 
uut: pp_core
port map(
uut: entity work.pp_core
generic map(
RESET_ADDRESS => RESET_ADDRESS
) port map(
clk => clk,
reset => reset,
timer_clk => clk,
timer_clk => timer_clk,
imem_address => imem_address,
imem_data_in => imem_data_in,
imem_req => imem_req,
140,6 → 113,18
end if;
end process clock;
 
timer_clock: process
begin
timer_clk <= '0';
wait for timer_clk_period / 2;
timer_clk <= '1';
wait for timer_clk_period / 2;
 
if simulation_finished then
wait;
end if;
end process timer_clock;
 
--! Initializes the instruction memory from file.
imem_init: process
file imem_file : text open READ_MODE is IMEM_FILENAME;
147,7 → 132,8
variable input_index : natural;
variable input_value : std_logic_vector(31 downto 0);
begin
for i in IMEM_BASE / 4 to IMEM_END / 4 loop
for i in to_integer(unsigned(IMEM_START_ADDR)) / 4 to IMEM_END / 4 loop
--for i in IMEM_BASE / 4 to IMEM_END / 4 loop
if not endfile(imem_file) then
readline(imem_file, input_line);
hread(input_line, input_value);
211,7 → 197,7
when b"10" => -- 16 bits
dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out( 7 downto 0);
dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
when others => -- Reserved for possible future 64 bit support
when others =>
end case;
dmem_write_ack <= '1';
end if;
259,7 → 245,7
dmem_data_in( 7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)) + 0);
when b"01" => -- 8 bits
dmem_data_in(7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)));
when others => -- Reserved for possible future 64 bit support
when others =>
end case;
dmem_read_ack <= '1';
end if;
/testbenches/tb_soc.vhd
14,10 → 14,12
--! @brief Testbench providing a full SoC architecture connected with a Wishbone bus.
entity tb_soc is
generic(
IMEM_SIZE : natural := 2048; --! Size of the instruction memory in bytes.
DMEM_SIZE : natural := 2048; --! Size of the data memory in bytes.
IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
IMEM_SIZE : natural := 4096; --! Size of the instruction memory in bytes.
DMEM_SIZE : natural := 4096; --! Size of the data memory in bytes.
RESET_ADDRESS : std_logic_vector := x"00000200"; --! Processor reset address
IMEM_START_ADDR : std_logic_vector := x"00000100"; --! Instruction memory start address
IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
);
end entity tb_soc;
 
27,6 → 29,9
signal clk : std_logic;
constant clk_period : time := 10 ns;
 
signal timer_clk : std_logic;
constant timer_clk_period : time := 100 ns;
 
-- Reset:
signal reset : std_logic := '1';
 
93,9 → 98,12
begin
 
processor: entity work.pp_potato
port map(
generic map(
RESET_ADDRESS => RESET_ADDRESS
) port map(
clk => clk,
reset => processor_reset,
timer_clk => timer_clk,
irq => irq,
fromhost_data => fromhost_data,
fromhost_updated => fromhost_updated,
200,17 → 208,18
variable input_value : std_logic_vector(31 downto 0);
variable temp : std_logic_vector(31 downto 0);
constant DMEM_START : natural := IMEM_SIZE;
constant DMEM_START_ADDR : natural := IMEM_SIZE;
begin
if not initialized then
-- Read the instruction memory file:
for i in 0 to IMEM_SIZE loop
for i in 0 to (IMEM_SIZE / 4) - 1 loop
exit when endfile(imem_file);
 
readline(imem_file, input_line);
hread(input_line, input_value);
 
init_adr_out <= std_logic_vector(to_unsigned(i * 4, init_adr_out'length));
init_adr_out <= std_logic_vector(to_unsigned(to_integer(unsigned(IMEM_START_ADDR)) + (i * 4),
init_adr_out'length));
init_dat_out <= input_value;
init_cyc_out <= '1';
init_stb_out <= '1';
226,13 → 235,12
wait for clk_period;
 
-- Read the data memory file:
for i in 0 to DMEM_SIZE loop
for i in 0 to (DMEM_SIZE / 4) - 1 loop
exit when endfile(dmem_file);
readline(dmem_file, input_line);
hread(input_line, input_value);
 
 
-- Swap endianness, TODO: prevent this, fix scripts/extract_hex.sh
temp(7 downto 0) := input_value(31 downto 24);
temp(15 downto 8) := input_value(23 downto 16);
241,7 → 249,7
 
input_value := temp;
 
init_adr_out <= std_logic_vector(to_unsigned(DMEM_START + (i * 4), init_adr_out'length));
init_adr_out <= std_logic_vector(to_unsigned(DMEM_START_ADDR + (i * 4), init_adr_out'length));
init_dat_out <= input_value;
init_cyc_out <= '1';
init_stb_out <= '1';
273,6 → 281,18
end if;
end process clock;
 
timer_clock: process
begin
timer_clk <= '1';
wait for timer_clk_period / 2;
timer_clk <= '0';
wait for timer_clk_period / 2;
 
if simulation_finished then
wait;
end if;
end process timer_clock;
 
stimulus: process
begin
wait for clk_period * 2;
/docs/manual.tex File deleted
/docs/opencores.png Cannot display: file marked as a binary type. svn:mime-type = image/png
/docs/opencores.png
docs/opencores.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +image/png \ No newline at end of property Index: docs/datasheet.tex =================================================================== --- docs/datasheet.tex (nonexistent) +++ docs/datasheet.tex (revision 58) @@ -0,0 +1,136 @@ +% The Potato Processor - Processor Datasheet +% (c) Kristian Klomsten Skordal 2015 +% Report bugs and issues on + +\documentclass[10pt,a4paper]{article} + +\usepackage[pdftitle={The Potato Processor Datasheet}, + pdfauthor={Kristian Klomsten Skordal}]{hyperref} +\usepackage{graphicx} +\usepackage{multicol} +\usepackage{enumitem} +\usepackage{titlesec} +\usepackage{tabularx} +\usepackage[margin=2.0cm,includefoot,footskip=10pt]{geometry} +\usepackage[british]{babel} + +\renewcommand{\familydefault}{\sfdefault} + +\titleformat{\section}[block]{}{}{0pt}{\normalfont\large\bfseries} +\pagestyle{empty} + +\setlength{\parindent}{0pt} +\setlist[itemize]{leftmargin=*,nosep} + +\begin{document} + +\begin{minipage}{0.5\textwidth} +\raggedright +\includegraphics[width=0.6\textwidth]{opencores.png} +\end{minipage} +\begin{minipage}{0.5\textwidth} +\raggedleft\Large\bf +\textsf{The Potato Processor\\Datasheet} +\end{minipage} + +\vspace{0.5em} +\noindent\rule{\linewidth}{1pt}\\ + +\begin{minipage}[t]{0.48\textwidth} + +\section{Architecture} +\includegraphics[width=\textwidth]{diagram.png} + +\section{Features} + +\begin{itemize} +\item Supports the complete 32-bit RISC-V base integer ISA (RV32I) version 2.0 +\item Supports machine mode as defined by the RISC-V supervisor extensions version 1.7 +\item Includes a hardware timer with microsecond resolution and compare interrupt +\item 8 IRQ inputs that can be invidually enabled +\item Classic 5-stage RISC pipeline +\item Instruction cache +\item Wishbone interface +\item Automatic test suite +\end{itemize} + +\section{Interface} + +The processor includes a wishbone interface conforming to the B4 revision of the +wishbone specification.\\ + +\begin{tabularx}{\textwidth}{|l|X|} +\hline +Interface type & Master \\ +Address port width & 32 bits \\ +Data port width & 32 bits \\ +Data port granularity & 8 bits \\ +Maximum operand size & 32 bits \\ +Endianess & Little \\ +Sequence of data transfer & In-order \\ +\hline +\end{tabularx} + +\section{Programming} + +Tools for writing programmes for the RISC-V architecture are available from the +RISC-V project, at:\\[1em] +\url{https://github.com/riscv/riscv-tools}\\ + +Use the \texttt{new\_privileged\_isa} branch to get tools that work with the +current supervisor extensions. + +\end{minipage}\hfill +\begin{minipage}[t]{0.48\textwidth} + +\section{Application} +\includegraphics[width=\textwidth]{example.png} + +\section{Signals} + +The processor is provided by a VHDL module named \texttt{pp\_potato}. The signals of +the module are all active high and are as follows:\\ + +\begin{tabularx}{\textwidth}{|l|l|X|} +\hline +\textbf{Name} & \textbf{Width} & \textbf{Description} \\ +\hline +\texttt{clk} & 1 & Processor clock \\ +\texttt{timer\_clk} & 1 & 10~MHz timer clock \\ +\texttt{reset} & 1 & Reset signal \\ +\hline +\texttt{irq} & 8 & IRQ inputs \\ +\hline +\texttt{wb\_adr\_out} & 32 & Wishbone address \\ +\texttt{wb\_sel\_out} & 4 & Wishbone byte select \\ +\texttt{wb\_cyc\_out} & 1 & Wishbone cycle \\ +\texttt{wb\_stb\_out} & 1 & Wishbone strobe \\ +\texttt{wb\_we\_out} & 1 & Wishbone write enable \\ +\texttt{wb\_dat\_out} & 32 & Wishbone data output \\ +\texttt{wb\_dat\_in} & 32 & Wishbone data input \\ +\texttt{wb\_ack\_in} & 1 & Wishbone acknowledge \\ +\hline +\end{tabularx}\\ + +Additional signals are used to implement a host-target interface used in the automatic testing +environment. These signals have names starting with \texttt{fromhost} and \texttt{tohost} and +should be left unconnected for normal use.\\ + +\section{Specifications} + +The base RISC-V instruction set and the privileged extensions are available in the +specifications published at:\\ + +\url{http://riscv.org/download.html}. + +\end{minipage} + +\vfill +\noindent\rule{\linewidth}{1pt} +{\small +Project page: \url{http://opencores.org/project,potato}\\ +Report bugs and issues on \url{http://opencores.org/project,potato,bugtracker}} + +\end{document} + + Index: docs/diagram.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = image/png Index: docs/diagram.png =================================================================== --- docs/diagram.png (nonexistent) +++ docs/diagram.png (revision 58)
docs/diagram.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +image/png \ No newline at end of property Index: docs/datasheet.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/pdf Index: docs/datasheet.pdf =================================================================== --- docs/datasheet.pdf (nonexistent) +++ docs/datasheet.pdf (revision 58)
docs/datasheet.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/pdf \ No newline at end of property Index: docs/example.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = image/png Index: docs/example.png =================================================================== --- docs/example.png (nonexistent) +++ docs/example.png (revision 58)
docs/example.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +image/png \ No newline at end of property Index: example/toplevel.vhd =================================================================== --- example/toplevel.vhd (revision 45) +++ example/toplevel.vhd (revision 58) @@ -131,6 +131,7 @@ processor: entity work.pp_potato port map( clk => system_clk, + timer_clk => timer_clk, reset => reset, irq => irq, fromhost_data => (others => '0'), Index: Makefile =================================================================== --- Makefile (revision 45) +++ Makefile (revision 58) @@ -69,16 +69,19 @@ sw \ xor \ xori \ + lui \ lb \ lbu \ lh \ lhu \ - lw + lw \ + ma_addr \ + sbreak \ + scall # Local tests to run: LOCAL_TESTS ?= \ - scall \ - sbreak \ + timer \ sw-jal all: potato.prj run-tests
/benchmarks/benchmark.ld
13,9 → 13,9
 
SECTIONS
{
.text 0x0 :
.text 0x100 :
{
*(.init*)
*(.init)
*(.text*)
__text_end = .;
}
/benchmarks/sha256/main.c
24,7 → 24,7
// registers with regbase[0] = x1 and upwards.
void exception_handler(uint32_t cause, void * epc, void * regbase)
{
if(cause == (CAUSE_IRQ_BASE + 5)) // Timer interrupt
if(cause == ((1 << CAUSE_INTERRUPT_BIT) | (CAUSE_IRQ_BASE + 5))) // Timer interrupt
{
uart_puts(IO_ADDRESS(UART_BASE), "Hashes per second: ");
uart_puth(IO_ADDRESS(UART_BASE), hashes_per_second);
/benchmarks/sha256/Makefile
29,6 → 29,7
sha256.coe: sha256.bin
echo "memory_initialization_radix=16;" > sha256.coe
echo "memory_initialization_vector=" >> sha256.coe
for i in $$(seq 0 63); do echo 00000013 >> sha256.coe; done
$(HEXDUMP) -v -e '1/4 "%08x\n"' sha256.bin >> sha256.coe
echo ";" >> sha256.coe
 
/benchmarks/potato.h
5,58 → 5,36
#ifndef POTATO_H
#define POTATO_H
 
// This file contains various defines neccessary for using the Potato processor
// with current RISC-V compilers. It also makes sure that applications keep
// working even though the supervisor extension specification should change.
 
// Control and status registers:
#define CSR_SUP0 0x500
#define CSR_SUP1 0x501
#define CSR_EPC 0x502
#define CSR_BADVADDR 0x503
#define CSR_EVEC 0x508
#define CSR_CAUSE 0x509
#define CSR_STATUS 0x50a
#define CSR_HARTID 0x50b
#define CSR_TOHOST 0x51e
#define CSR_FROMHOST 0x51f
#define CSR_CYCLE 0xc00
#define CSR_CYCLEH 0xc80
#define CSR_TIME 0xc01
#define CSR_TIMEH 0xc81
#define CSR_INSTRET 0xc02
#define CSR_INSTRETH 0xc82
 
// Exception cause values:
#define CAUSE_INSTR_MISALIGN 0x00
#define CAUSE_INSTR_FETCH 0x01
#define CAUSE_INVALID_INSTR 0x02
#define CAUSE_SYSCALL 0x06
#define CAUSE_BREAKPOINT 0x07
#define CAUSE_LOAD_MISALIGN 0x08
#define CAUSE_STORE_MISALIGN 0x09
#define CAUSE_LOAD_ERROR 0x0a
#define CAUSE_STORE_ERROR 0x0b
#define CAUSE_FROMHOST 0x1e
#define CAUSE_BREAKPOINT 0x03
#define CAUSE_LOAD_MISALIGN 0x04
#define CAUSE_LOAD_ERROR 0x05
#define CAUSE_STORE_MISALIGN 0x06
#define CAUSE_STORE_ERROR 0x07
#define CAUSE_ECALL 0x0b
 
#define CAUSE_IRQ_BASE 0x10
 
// Interrupt bit in the cause register:
#define CAUSE_INTERRUPT_BIT 31
 
// Status register bit indices:
#define STATUS_EI 2 // Enable Interrupts
#define STATUS_PEI 3 // Previous value of Enable Interrupts
#define STATUS_IM_MASK 0x00ff0000 // Interrupt Mask
#define STATUS_PIM_MASK 0xff000000 // Previous Interrupt Mask
#define STATUS_IE 0 // Enable Interrupts
#define STATUS_IE1 3 // Previous value of Enable Interrupts
 
#define potato_enable_interrupts() asm volatile("csrsi %[status], 1 << %[ei_bit]\n" \
:: [status] "i" (CSR_STATUS), [ei_bit] "i" (STATUS_EI))
#define potato_disable_interrupts() asm volatile("csrci %[status], 1 << %[ei_bit] | 1 << %[pei_bit]\n" \
:: [status] "i" (CSR_STATUS), [ei_bit] "i" (STATUS_EI), [pei_bit] "i" (STATUS_PEI))
#define potato_enable_interrupts() asm volatile("csrsi mstatus, 1 << %[ie_bit]\n" \
:: [ie_bit] "i" (STATUS_IE))
#define potato_disable_interrupts() asm volatile("csrci mstatus, 1 << %[ie_bit] | 1 << %[ie1_bit]\n" \
:: [ie_bit] "i" (STATUS_IE), [ie1_bit] "i" (STATUS_IE1))
 
#define potato_write_host(data) \
do { \
register uint32_t temp = data; \
asm volatile("csrw %[tohost], %[temp]\n" \
:: [tohost] "i" (CSR_TOHOST), [temp] "r" (temp)); \
asm volatile("csrw mtohost, %[temp]\n" \
:: [temp] "r" (temp)); \
} while(0);
 
#define potato_enable_irq(n) \
64,8 → 42,8
register uint32_t temp = 0; \
asm volatile( \
"li %[temp], 1 << %[shift]\n" \
"csrs %[status], %[temp]\n" \
:: [temp] "r" (temp), [shift] "i" (n + 16), [status] "i" (CSR_STATUS)); \
"csrs mie, %[temp]\n" \
:: [temp] "r" (temp), [shift] "i" (n + 24)); \
} while(0)
 
#define potato_disable_irq(n) \
73,16 → 51,16
register uint32_t temp = 0; \
asm volatile( \
"li %[temp], 1 << %[shift]\n" \
"csrc %[status], %[temp]\n" \
:: [temp] "r" (temp), [shift] "i" (n + 24), [status] "i" (CSR_STATUS)); \
"csrc mie, %[temp]\n" \
:: [temp] "r" (temp), [shift] "i" (n + 24);) \
} while(0)
 
#define potato_get_badvaddr(n) \
#define potato_get_badaddr(n) \
do { \
register uint32_t __temp = 0; \
asm volatile ( \
"csrr %[temp], %[badvaddr]\n" \
: [temp] "=r" (__temp) : [badvaddr] "i" (CSR_BADVADDR)); \
"csrr %[temp], mbadaddr\n" \
: [temp] "=r" (__temp)); \
n = __temp; \
} while(0)
 
/benchmarks/start.S
10,6 → 10,20
 
.section .init
 
.align 6
tvec_user: // User mode is not supported by Potato
j tvec_machine
.align 6
tvec_supervisor: // Supervisor mode is not supported by Potato
j tvec_machine
.align 6
tvec_hypervisor: // Hypervisor mode is not supported by Potato
j tvec_machine
.align 6
tvec_machine:
j exception_handler_wrapper
 
.align 6
.global _start
_start:
 
44,17 → 58,11
 
2:
 
.hidden set_evec
set_evec:
// Set up an exception handler:
la x1, exception_handler_wrapper
csrw evec, x1
 
.hidden call_main
call_main:
la sp, __stack_top
jal main
csrw tohost, a0
csrw mtohost, a0
1:
j 1b
 
97,8 → 105,8
sw x30, 116(sp)
sw x31, 120(sp)
 
csrr a0, cause
csrr a1, epc
csrr a0, mcause
csrr a1, mepc
mv a2, sp
jal exception_handler
 
138,5 → 146,5
lw x31, 120(sp)
addi sp, sp, 124
 
sret
eret
 
/.
. Property changes : Modified: svn:mergeinfo ## -0,0 +0,2 ## Merged /potato/branches/new-priviledged-isa:r48 Merged /potato/branches/new-privileged-isa:r49-57

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.