URL
https://opencores.org/ocsvn/potato/potato/trunk
Subversion Repositories potato
Compare Revisions
- This comparison shows the changes necessary to convert path
/potato/trunk
- from Rev 64 to Rev 65
- ↔ Reverse comparison
Rev 64 → Rev 65
/benchmarks/sha256/main.c
73,7 → 73,7
uart_puts(IO_ADDRESS(UART_BASE), "The Potato Processor SHA256 Benchmark\n\r\n\r"); |
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// Enable interrupts: |
potato_enable_irq(TIMER_IRQ); |
potato_enable_irq(IRQ_TIMER); |
potato_enable_interrupts(); |
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struct sha256_context context; |
/benchmarks/sha256/uart.c
17,8 → 17,8
void uart_putc(volatile uint32_t * base, char c) |
{ |
// Wait until there is room in the transmit buffer: |
while(base[UART_STATUS >> 2] & (1 << 3)); |
base[UART_TX >> 2] = c & 0x000000ff; |
while(base[UART_STATUS >> 2] & (1 << UART_STATUS_TXBUF_FULL)); |
base[UART_TX >> 2] = c & 0xff; |
} |
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void uart_puth(volatile uint32_t * base, uint32_t n) |
/benchmarks/platform.h
24,8 → 24,10
#define SEG7_BASE 0x00006000 |
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// IRQs: |
#define EXTERNAL_IRQ 0 |
#define TIMER_IRQ 5 |
#define IRQ_EXTERNAL 0 |
#define IRQ_UART_RTS 1 |
#define IRQ_UART_RECV 2 |
#define IRQ_TIMER 5 |
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// GPIO register offsets: |
#define GPIO_INPUT 0 |
37,6 → 39,12
#define UART_RX 4 |
#define UART_STATUS 8 |
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// UART status register bits: |
#define UART_STATUS_RXBUF_EMPTY 0 |
#define UART_STATUS_TXBUF_EMPTY 1 |
#define UART_STATUS_RXBUF_FULL 2 |
#define UART_STATUS_TXBUF_FULL 3 |
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// Timer register offsets: |
#define TIMER_CTRL 0 |
#define TIMER_COMPARE 4 |
/benchmarks/potato.h
5,6 → 5,12
#ifndef POTATO_H |
#define POTATO_H |
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// Number of IRQs supported: |
#define POTATO_NUM_IRQS 8 |
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// Implementation-specific CSRs: |
#define CSR_PP_CACHECTRL 0x790 |
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// Exception cause values: |
#define CAUSE_INSTR_MISALIGN 0x00 |
#define CAUSE_INSTR_FETCH 0x01 |
25,6 → 31,9
#define STATUS_IE 0 // Enable Interrupts |
#define STATUS_IE1 3 // Previous value of Enable Interrupts |
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// Cache control register bit indices: |
#define CSR_PP_CACHECTRL_ICACHE_EN 0 |
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#define potato_enable_interrupts() asm volatile("csrsi mstatus, 1 << %[ie_bit]\n" \ |
:: [ie_bit] "i" (STATUS_IE)) |
#define potato_disable_interrupts() asm volatile("csrci mstatus, 1 << %[ie_bit] | 1 << %[ie1_bit]\n" \ |
/benchmarks/start.S
58,6 → 58,11
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2: |
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.hidden enable_caches |
enable_caches: |
csrsi CSR_PP_CACHECTRL, 1 << CSR_PP_CACHECTRL_ICACHE_EN |
fence.i |
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.hidden call_main |
call_main: |
la sp, __stack_top |