URL
https://opencores.org/ocsvn/potato/potato/trunk
Subversion Repositories potato
Compare Revisions
- This comparison shows the changes necessary to convert path
/potato
- from Rev 53 to Rev 54
- ↔ Reverse comparison
Rev 53 → Rev 54
/branches/new-privileged-isa/benchmarks/benchmark.ld
13,9 → 13,9
|
SECTIONS |
{ |
.text 0x0 : |
.text 0x100 : |
{ |
*(.init*) |
*(.init) |
*(.text*) |
__text_end = .; |
} |
/branches/new-privileged-isa/benchmarks/sha256/main.c
24,7 → 24,7
// registers with regbase[0] = x1 and upwards. |
void exception_handler(uint32_t cause, void * epc, void * regbase) |
{ |
if(cause == (CAUSE_IRQ_BASE + 5)) // Timer interrupt |
if(cause == ((1 << CAUSE_INTERRUPT_BIT) | (CAUSE_IRQ_BASE + 5))) // Timer interrupt |
{ |
uart_puts(IO_ADDRESS(UART_BASE), "Hashes per second: "); |
uart_puth(IO_ADDRESS(UART_BASE), hashes_per_second); |
/branches/new-privileged-isa/benchmarks/sha256/Makefile
29,6 → 29,7
sha256.coe: sha256.bin |
echo "memory_initialization_radix=16;" > sha256.coe |
echo "memory_initialization_vector=" >> sha256.coe |
for i in $$(seq 0 63); do echo 00000013 >> sha256.coe; done |
$(HEXDUMP) -v -e '1/4 "%08x\n"' sha256.bin >> sha256.coe |
echo ";" >> sha256.coe |
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/branches/new-privileged-isa/benchmarks/potato.h
5,58 → 5,36
#ifndef POTATO_H |
#define POTATO_H |
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// This file contains various defines neccessary for using the Potato processor |
// with current RISC-V compilers. It also makes sure that applications keep |
// working even though the supervisor extension specification should change. |
|
// Control and status registers: |
#define CSR_SUP0 0x500 |
#define CSR_SUP1 0x501 |
#define CSR_EPC 0x502 |
#define CSR_BADVADDR 0x503 |
#define CSR_EVEC 0x508 |
#define CSR_CAUSE 0x509 |
#define CSR_STATUS 0x50a |
#define CSR_HARTID 0x50b |
#define CSR_TOHOST 0x51e |
#define CSR_FROMHOST 0x51f |
#define CSR_CYCLE 0xc00 |
#define CSR_CYCLEH 0xc80 |
#define CSR_TIME 0xc01 |
#define CSR_TIMEH 0xc81 |
#define CSR_INSTRET 0xc02 |
#define CSR_INSTRETH 0xc82 |
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// Exception cause values: |
#define CAUSE_INSTR_MISALIGN 0x00 |
#define CAUSE_INSTR_FETCH 0x01 |
#define CAUSE_INVALID_INSTR 0x02 |
#define CAUSE_SYSCALL 0x06 |
#define CAUSE_BREAKPOINT 0x07 |
#define CAUSE_LOAD_MISALIGN 0x08 |
#define CAUSE_STORE_MISALIGN 0x09 |
#define CAUSE_LOAD_ERROR 0x0a |
#define CAUSE_STORE_ERROR 0x0b |
#define CAUSE_FROMHOST 0x1e |
#define CAUSE_BREAKPOINT 0x03 |
#define CAUSE_LOAD_MISALIGN 0x04 |
#define CAUSE_LOAD_ERROR 0x05 |
#define CAUSE_STORE_MISALIGN 0x06 |
#define CAUSE_STORE_ERROR 0x07 |
#define CAUSE_ECALL 0x0b |
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#define CAUSE_IRQ_BASE 0x10 |
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// Interrupt bit in the cause register: |
#define CAUSE_INTERRUPT_BIT 31 |
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// Status register bit indices: |
#define STATUS_EI 2 // Enable Interrupts |
#define STATUS_PEI 3 // Previous value of Enable Interrupts |
#define STATUS_IM_MASK 0x00ff0000 // Interrupt Mask |
#define STATUS_PIM_MASK 0xff000000 // Previous Interrupt Mask |
#define STATUS_IE 0 // Enable Interrupts |
#define STATUS_IE1 3 // Previous value of Enable Interrupts |
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#define potato_enable_interrupts() asm volatile("csrsi %[status], 1 << %[ei_bit]\n" \ |
:: [status] "i" (CSR_STATUS), [ei_bit] "i" (STATUS_EI)) |
#define potato_disable_interrupts() asm volatile("csrci %[status], 1 << %[ei_bit] | 1 << %[pei_bit]\n" \ |
:: [status] "i" (CSR_STATUS), [ei_bit] "i" (STATUS_EI), [pei_bit] "i" (STATUS_PEI)) |
#define potato_enable_interrupts() asm volatile("csrsi mstatus, 1 << %[ie_bit]\n" \ |
:: [ie_bit] "i" (STATUS_IE)) |
#define potato_disable_interrupts() asm volatile("csrci mstatus, 1 << %[ie_bit] | 1 << %[ie1_bit]\n" \ |
:: [ie_bit] "i" (STATUS_IE), [ie1_bit] "i" (STATUS_IE1)) |
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#define potato_write_host(data) \ |
do { \ |
register uint32_t temp = data; \ |
asm volatile("csrw %[tohost], %[temp]\n" \ |
:: [tohost] "i" (CSR_TOHOST), [temp] "r" (temp)); \ |
asm volatile("csrw mtohost, %[temp]\n" \ |
:: [temp] "r" (temp)); \ |
} while(0); |
|
#define potato_enable_irq(n) \ |
64,8 → 42,8
register uint32_t temp = 0; \ |
asm volatile( \ |
"li %[temp], 1 << %[shift]\n" \ |
"csrs %[status], %[temp]\n" \ |
:: [temp] "r" (temp), [shift] "i" (n + 16), [status] "i" (CSR_STATUS)); \ |
"csrs mie, %[temp]\n" \ |
:: [temp] "r" (temp), [shift] "i" (n + 24)); \ |
} while(0) |
|
#define potato_disable_irq(n) \ |
73,16 → 51,16
register uint32_t temp = 0; \ |
asm volatile( \ |
"li %[temp], 1 << %[shift]\n" \ |
"csrc %[status], %[temp]\n" \ |
:: [temp] "r" (temp), [shift] "i" (n + 24), [status] "i" (CSR_STATUS)); \ |
"csrc mie, %[temp]\n" \ |
:: [temp] "r" (temp), [shift] "i" (n + 24);) \ |
} while(0) |
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#define potato_get_badvaddr(n) \ |
#define potato_get_badaddr(n) \ |
do { \ |
register uint32_t __temp = 0; \ |
asm volatile ( \ |
"csrr %[temp], %[badvaddr]\n" \ |
: [temp] "=r" (__temp) : [badvaddr] "i" (CSR_BADVADDR)); \ |
"csrr %[temp], mbadaddr\n" \ |
: [temp] "=r" (__temp)); \ |
n = __temp; \ |
} while(0) |
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/branches/new-privileged-isa/benchmarks/start.S
10,6 → 10,20
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.section .init |
|
.align 6 |
tvec_user: // User mode is not supported by Potato |
j tvec_machine |
.align 6 |
tvec_supervisor: // Supervisor mode is not supported by Potato |
j tvec_machine |
.align 6 |
tvec_hypervisor: // Hypervisor mode is not supported by Potato |
j tvec_machine |
.align 6 |
tvec_machine: |
j exception_handler_wrapper |
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.align 6 |
.global _start |
_start: |
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44,17 → 58,11
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2: |
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.hidden set_evec |
set_evec: |
// Set up an exception handler: |
la x1, exception_handler_wrapper |
csrw evec, x1 |
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.hidden call_main |
call_main: |
la sp, __stack_top |
jal main |
csrw tohost, a0 |
csrw mtohost, a0 |
1: |
j 1b |
|
97,8 → 105,8
sw x30, 116(sp) |
sw x31, 120(sp) |
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csrr a0, cause |
csrr a1, epc |
csrr a0, mcause |
csrr a1, mepc |
mv a2, sp |
jal exception_handler |
|
138,5 → 146,5
lw x31, 120(sp) |
addi sp, sp, 124 |
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sret |
eret |
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