URL
https://opencores.org/ocsvn/ppx16/ppx16/trunk
Subversion Repositories ppx16
Compare Revisions
- This comparison shows the changes necessary to convert path
/ppx16/trunk/syn/xilinx/bin
- from Rev 16 to Rev 22
- ↔ Reverse comparison
Rev 16 → Rev 22
/p16c55.tcl
0,0 → 1,44
set process "5" |
set part "2s200pq208" |
set tristate_map "FALSE" |
set opt_auto_mode "TRUE" |
set opt_best_result "29223.458000" |
set dont_lock_lcells "auto" |
set input2output "20.000000" |
set input2register "20.000000" |
set register2output "20.000000" |
set register2register "20.000000" |
set wire_table "xis215-5_avg" |
set encoding "auto" |
set edifin_ground_port_names "GND" |
set edifin_power_port_names "VCC" |
set edif_array_range_extraction_style "%s\[%d:%d\]" |
|
set_xilinx_eqn |
|
load_library xis2 |
|
read -technology xis2 { |
../../../rtl/vhdl/PPX_Pack.vhd |
../../../rtl/vhdl/PPX_ALU.vhd |
../../../rtl/vhdl/PPX_Ctrl.vhd |
../../../rtl/vhdl/PPX_PCS.vhd |
../../../rtl/vhdl/PPX16.vhd |
../../../rtl/vhdl/PPX_RAM.vhd |
../../../rtl/vhdl/PPX_Port.vhd |
../../../rtl/vhdl/PPX_TMR.vhd |
../src/ROM55_Test_leo.vhd |
../../../rtl/vhdl/P16C55.vhd |
} |
|
pre_optimize |
|
optimize -hierarchy=auto -delay -pass 1 -pass 2 -pass 3 -pass 4 |
|
optimize_timing |
|
report_area |
|
report_delay |
|
write p16c55_leo.edf |
/p16c55_leo.pin
0,0 → 1,7
#NET "clk" TNM_NET = "clk"; |
#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; |
|
NET "Clk" LOC = "P77"; |
NET "Reset_n" LOC = "P133"; |
NET "Port_A(0)" LOC = "P96"; |
NET "Port_A(1)" LOC = "P98"; |
/p16c55.pin
0,0 → 1,7
#NET "clk" TNM_NET = "clk"; |
#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; |
|
NET "clk" LOC = "P77"; |
NET "reset_n" LOC = "P133"; |
NET "port_a<0>" LOC = "P96"; |
NET "port_a<1>" LOC = "P98"; |
/p16f84.tcl
0,0 → 1,44
set process "5" |
set part "2s200pq208" |
set tristate_map "FALSE" |
set opt_auto_mode "TRUE" |
set opt_best_result "29223.458000" |
set dont_lock_lcells "auto" |
set input2output "20.000000" |
set input2register "20.000000" |
set register2output "20.000000" |
set register2register "20.000000" |
set wire_table "xis215-5_avg" |
set encoding "auto" |
set edifin_ground_port_names "GND" |
set edifin_power_port_names "VCC" |
set edif_array_range_extraction_style "%s\[%d:%d\]" |
|
set_xilinx_eqn |
|
load_library xis2 |
|
read -technology xis2 { |
../../../rtl/vhdl/PPX_Pack.vhd |
../../../rtl/vhdl/PPX_ALU.vhd |
../../../rtl/vhdl/PPX_Ctrl.vhd |
../../../rtl/vhdl/PPX_PCS.vhd |
../../../rtl/vhdl/PPX16.vhd |
../../../rtl/vhdl/PPX_RAM.vhd |
../../../rtl/vhdl/PPX_Port.vhd |
../../../rtl/vhdl/PPX_TMR.vhd |
../src/ROM84_Test_leo.vhd |
../../../rtl/vhdl/P16F84.vhd |
} |
|
pre_optimize |
|
optimize -hierarchy=auto -delay -pass 1 -pass 2 -pass 3 -pass 4 |
|
optimize_timing |
|
report_area |
|
report_delay |
|
write p16f84_leo.edf |
/p16f84_leo.pin
0,0 → 1,13
NET "clk" TNM_NET = "clk"; |
TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; |
|
NET "Clk" LOC = "P77"; |
NET "Reset_n" LOC = "P133"; |
NET "Port_B(0)" LOC = "P29"; |
NET "Port_B(1)" LOC = "P31"; |
NET "Port_B(2)" LOC = "P34"; |
NET "Port_B(3)" LOC = "P36"; |
NET "Port_B(4)" LOC = "P41"; |
NET "Port_B(5)" LOC = "P43"; |
NET "Port_B(6)" LOC = "P45"; |
NET "Port_B(7)" LOC = "P47"; |
/p16f84.pin
0,0 → 1,13
NET "clk" TNM_NET = "clk"; |
TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; |
|
NET "clk" LOC = "P77"; |
NET "reset_n" LOC = "P133"; |
NET "port_b<0>" LOC = "P29"; |
NET "port_b<1>" LOC = "P31"; |
NET "port_b<2>" LOC = "P34"; |
NET "port_b<3>" LOC = "P36"; |
NET "port_b<4>" LOC = "P41"; |
NET "port_b<5>" LOC = "P43"; |
NET "port_b<6>" LOC = "P45"; |
NET "port_b<7>" LOC = "P47"; |
/p16f84.prj
0,0 → 1,10
../../../rtl/vhdl/PPX_Pack.vhd |
../../../rtl/vhdl/PPX_ALU.vhd |
../../../rtl/vhdl/PPX_Ctrl.vhd |
../../../rtl/vhdl/PPX_PCS.vhd |
../../../rtl/vhdl/PPX16.vhd |
../../../rtl/vhdl/PPX_RAM.vhd |
../../../rtl/vhdl/PPX_Port.vhd |
../../../rtl/vhdl/PPX_TMR.vhd |
../src/ROM84_Test.vhd |
../../../rtl/vhdl/P16F84.vhd |
/p16c55.scr
0,0 → 1,7
run |
-ifn ../bin/p16c55.prj |
-ifmt VHDL |
-ofn ../out/p16c55.ngc |
-ofmt NGC -p xc2s200-pq208-5 |
-opt_mode Speed |
-opt_level 2 |
/p16c55.prj
0,0 → 1,10
../../../rtl/vhdl/PPX_Pack.vhd |
../../../rtl/vhdl/PPX_ALU.vhd |
../../../rtl/vhdl/PPX_Ctrl.vhd |
../../../rtl/vhdl/PPX_PCS.vhd |
../../../rtl/vhdl/PPX16.vhd |
../../../rtl/vhdl/PPX_RAM.vhd |
../../../rtl/vhdl/PPX_Port.vhd |
../../../rtl/vhdl/PPX_TMR.vhd |
../src/ROM55_Test.vhd |
../../../rtl/vhdl/P16C55.vhd |
/p16f84.scr
0,0 → 1,7
run |
-ifn ../bin/p16f84.prj |
-ifmt VHDL |
-ofn ../out/p16f84.ngc |
-ofmt NGC -p xc2s200-pq208-5 |
-opt_mode Speed |
-opt_level 2 |