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URL https://opencores.org/ocsvn/present/present/trunk

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    /present/trunk/32BitIO
    from Rev 3 to Rev 4
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Rev 3 → Rev 4

/PresentEnc.vhd File deleted
/keyupdTB.vhd File deleted \ No newline at end of file
/sLayerTB.vhd File deleted \ No newline at end of file
/mux80.vhd File deleted
/pLayer.vhd File deleted \ No newline at end of file
/txt_util.vhd File deleted
/PresentStateMachine.vhd File deleted
/keyupd.vhd File deleted \ No newline at end of file
/PresentEncTB.vhd File deleted \ No newline at end of file
/slayer.vhd File deleted \ No newline at end of file
/counter.vhd File deleted
/mux64.vhd File deleted
/kody.vhd File deleted \ No newline at end of file
/outputRegister.vhd File deleted
/bench/vhdl/sLayerTB.vhd
0,0 → 1,111
-----------------------------------------------------------------------
---- ----
---- Present - a lightweight block cipher project ----
---- ----
---- This file is part of the Present - a lightweight block ----
---- cipher project ----
---- http://www.http://opencores.org/project,present ----
---- ----
---- Description: ----
---- Substitution layer test bench of Present encoder. ----
---- Nothing special. ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY sLayerTB IS
END sLayerTB;
ARCHITECTURE behavior OF sLayerTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT slayer
PORT(
input : IN std_logic_vector(3 downto 0);
output : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
 
--BiDirs
signal input : std_logic_vector(3 downto 0);
signal output : std_logic_vector(3 downto 0);
 
-- Clock period definitions
constant clk_period : time := 1ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: slayer PORT MAP (
input => input,
output => output
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
reset <= '1';
wait for 100ns;
reset <= '0';
wait for clk_period;
input <= x"0";
wait for clk_period;
input <= x"A";
wait for clk_period;
input <= x"F";
wait for clk_period;
-- insert stimulus here
assert false severity failure;
end process;
 
END;
/bench/vhdl/keyupdTB.vhd
0,0 → 1,122
-----------------------------------------------------------------------
---- ----
---- Present - a lightweight block cipher project ----
---- ----
---- This file is part of the Present - a lightweight block ----
---- cipher project ----
---- http://www.http://opencores.org/project,present ----
---- ----
---- Description: ----
---- Key update test bench. It was much more used during ----
---- inverse so data below are the same. ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY keyupdTB IS
END keyupdTB;
ARCHITECTURE behavior OF keyupdTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT keyupd
PORT(
key : IN std_logic_vector(79 downto 0);
num : IN std_logic_vector(4 downto 0);
keyout : OUT std_logic_vector(79 downto 0)--;
--clk, reset : std_logic
);
END COMPONENT;
 
--Inputs
signal key : std_logic_vector(79 downto 0) := (others => '0');
signal num : std_logic_vector(4 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
 
--Outputs
signal keyout : std_logic_vector(79 downto 0);
constant clk_period : time := 1ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: keyupd PORT MAP (
key => key,
num => num,
keyout => keyout--,
--clk => clk,
--reset => reset
);
-- No clocks detected in port list. Replace clk below with
-- appropriate port name
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
reset <= '1';
wait for 100ns;
reset <='0';
wait for clk_period;
key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
num <= "00001";
wait for clk_period;
key <= x"c0000000000000008000";
num <= "00010";
wait for clk_period;
key <= x"50001800000000010000";
num <= "00011";
wait for clk_period;
key <= x"8ba27a0eb8783ac96d59";
num <= "11111";
wait for clk_period;
assert false severity failure;
end process;
END;
/bench/vhdl/PresentEncTB.vhd
0,0 → 1,275
-----------------------------------------------------------------------
---- ----
---- Present - a lightweight block cipher project ----
---- ----
---- This file is part of the Present - a lightweight block ----
---- cipher project ----
---- http://www.http://opencores.org/project,present ----
---- ----
---- Description: ----
---- Test bench of Present encoder with 32 bit IO. ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE std.textio.all;
USE work.txt_util.all;
USE ieee.std_logic_textio.all;
use work.kody.ALL;
ENTITY PresentEncTB IS
END PresentEncTB;
ARCHITECTURE behavior OF PresentEncTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PresentEnc
PORT(
input : IN std_logic_vector(31 downto 0);
output : OUT std_logic_vector(31 downto 0);
ctrl : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
reset : IN std_logic;
ready : out std_logic
);
END COMPONENT;
-- Clock period definitions
constant clk_period : time := 1ns;
constant p10 : time := clk_period/10;
constant edge : time := clk_period-p10;
 
--Inputs
signal input : std_logic_vector(31 downto 0) := (others => '0');
signal ctrl : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal strobe : std_logic;
 
--Outputs
signal output : std_logic_vector(31 downto 0);
signal ready : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PresentEnc PORT MAP (
input => input,
output => output,
ctrl => ctrl,
clk => clk,
reset => reset,
ready => ready
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
file infile :text is in "wejscie.txt";
variable line_in :line;
variable bytes : std_logic_vector(32 downto 0);
variable bytes2 : std_logic_vector(3 downto 0);
variable xbit : std_logic;
begin
-- hold reset state for 100ms.
wait for 100ns;
reset <= '1';
wait for 10ns;
reset <= '0';
wait for 10ns;
-- insert stimulus here
while not (endfile(infile)) loop
readline(infile, line_in); --2
hread(line_in, bytes2);
ctrl <= bytes2;
wait for clk_period;
readline(infile, line_in); -- 1
hread(line_in, bytes2);
ctrl <= bytes2;
readline(infile, line_in);
read(line_in, xbit);
input <= (others => xbit);
wait for clk_period;
readline(infile, line_in);
hread(line_in, bytes2);
ctrl <= bytes2;
readline(infile, line_in);
read(line_in, xbit);
input <= (others => xbit);
wait for clk_period;
readline(infile, line_in);
hread(line_in, bytes2);
ctrl <= bytes2;
readline(infile, line_in);
read(line_in, xbit);
input <= (others => xbit);
wait for clk_period;
readline(infile, line_in);
hread(line_in, bytes2);
ctrl <= bytes2;
readline(infile, line_in);
read(line_in, xbit);
input <= (others => xbit);
wait for clk_period;
readline(infile, line_in);
hread(line_in, bytes2);
ctrl <= bytes2;
readline(infile, line_in);
read(line_in, xbit);
input <= (others => xbit);
wait for clk_period;
readline(infile, line_in);
hread(line_in, bytes2);
ctrl <= bytes2;
wait for clk_period*33;
readline(infile, line_in);
hread(line_in, bytes2);
ctrl <= bytes2;
wait for clk_period;
readline(infile, line_in);
hread(line_in, bytes2);
ctrl <= bytes2;
wait for clk_period*2;
end loop;
assert false severity failure;
end process;
strobe <= TRANSPORT clk AFTER edge;
outs: PROCESS (strobe)
variable str :string(1 to 29);
variable lineout :line;
variable init_file :std_logic := '1';
file outfile :text is out "wyjscie.txt";
-------- funkcja konwersji: std_logic_vector => character --------
function conv_to_hex_char (sig: std_logic_vector(3 downto 0)) RETURN character IS
begin
case sig is
when "0000" => return '0';
when "0001" => return '1';
when "0010" => return '2';
when "0011" => return '3';
when "0100" => return '4';
when "0101" => return '5';
when "0110" => return '6';
when "0111" => return '7';
when "1000" => return '8';
when "1001" => return '9';
when "1010" => return 'A';
when "1011" => return 'B';
when "1100" => return 'C';
when "1101" => return 'D';
when "1110" => return 'E';
when others => return 'F';
end case;
end conv_to_hex_char;
-------- funkcja konwersji: std_logic => character --------
function conv_to_char (sig: std_logic) RETURN character IS
begin
case sig is
when '1' => return '1';
when '0' => return '0';
when 'Z' => return 'Z';
when others => return 'X';
end case;
end conv_to_char;
-------- funkcja konwersji: std_logic_vector => string --------
function conv_to_string (inp: std_logic_vector; length: integer) RETURN string IS
variable x : integer := length/4;
variable s : string(1 to x);
begin
for i in 0 to (x-1) loop
s(x-i) := conv_to_hex_char(inp(4*i+3 downto 4*i));
end loop;
return s;
end conv_to_string;
-------------------------------------
begin
 
if init_file = '1' then
str:="clk ";
write(lineout,str); writeline(outfile,lineout);
str:="| reset ";
write(lineout,str); writeline(outfile,lineout);
str:="| | ready ";
write(lineout,str); writeline(outfile,lineout);
str:="| | | ctrl ";
write(lineout,str); writeline(outfile,lineout);
str:="| | | | input ";
write(lineout,str); writeline(outfile,lineout);
str:="| | | | | output ";
write(lineout,str); writeline(outfile,lineout);
str:="| | | | | | ";
write(lineout,str); writeline(outfile,lineout);
init_file := '0';
end if;
 
if (strobe'EVENT and strobe='0') then
str := (others => ' ');
str(1) := conv_to_char(clk);
str(2) := '|';
str(3) := conv_to_char(reset);
str(4) := '|';
str(5) := conv_to_char(ready);
str(6) := '|';
str(7) := conv_to_hex_char(ctrl);
str(8) := '|';
str(9 to 16) := conv_to_string(input,32);
str(17) := '|';
str(18 to 25) := conv_to_string(output,32);
str(26) := '|';
write(lineout,str);
writeline(outfile,lineout);
end if;
end process outs;
end;
/bench/vhdl/txt_util.vhd
0,0 → 1,586
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
 
 
package txt_util is
 
-- prints a message to the screen
procedure print(text: string);
 
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
 
-- converts std_logic into a character
function chr(sl: std_logic) return character;
 
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
 
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
 
-- converts boolean into a string
function str(b: boolean) return string;
 
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
 
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
 
-- converts integer to string, using base 10
function str(int: integer) return string;
 
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
 
 
-- functions to manipulate strings
-----------------------------------
 
-- convert a character to upper case
function to_upper(c: character) return character;
 
-- convert a character to lower case
function to_lower(c: character) return character;
 
-- convert a string to upper case
function to_upper(s: string) return string;
 
-- convert a string to lower case
function to_lower(s: string) return string;
 
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
 
 
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
 
 
 
 
package body txt_util is
 
 
 
 
-- prints text to the screen
 
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
 
 
 
 
-- prints text to the screen when active
 
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
 
 
-- converts std_logic into a character
 
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
 
 
 
-- converts std_logic into a string (1 to 1)
 
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
 
 
 
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
 
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
 
 
function str(b: boolean) return string is
 
begin
if b then
return "true";
else
return "false";
end if;
end str;
 
 
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
 
 
 
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
function str(int: integer; base: integer) return string is
 
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
 
begin
 
-- bug fix for negative numbers
abs_int := abs(int);
 
num := abs_int;
 
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
 
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
 
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
 
end str;
 
 
-- convert integer to string, using base 10
function str(int: integer) return string is
 
begin
 
return str(int, 10) ;
 
end str;
 
 
 
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
 
 
 
-- functions to manipulate strings
-----------------------------------
 
 
-- convert a character to upper case
 
function to_upper(c: character) return character is
 
variable u: character;
 
begin
 
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
 
return u;
 
end to_upper;
 
 
-- convert a character to lower case
 
function to_lower(c: character) return character is
 
variable l: character;
 
begin
 
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
 
return l;
 
end to_lower;
 
 
 
-- convert a string to upper case
 
function to_upper(s: string) return string is
 
variable uppercase: string (s'range);
 
begin
 
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
 
end to_upper;
 
 
 
-- convert a string to lower case
 
function to_lower(s: string) return string is
 
variable lowercase: string (s'range);
 
begin
 
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
 
end to_lower;
 
 
 
-- functions to convert strings into other types
 
 
-- converts a character into a std_logic
 
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
 
 
-- converts a string into std_logic_vector
 
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
 
 
 
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
 
 
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
 
 
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
 
 
 
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
 
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
 
 
 
 
end txt_util;
 
 
 
 
/bench/vhdl
bench/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: bench =================================================================== --- bench (nonexistent) +++ bench (revision 4)
bench Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: rtl/vhdl/counter.vhd =================================================================== --- rtl/vhdl/counter.vhd (nonexistent) +++ rtl/vhdl/counter.vhd (revision 4) @@ -0,0 +1,86 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- A little modified counter construction - it additionally ---- +---- control another one signal. It contains "built-in" reset if ---- +---- it is not counting. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_2 : integer := 2; + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + info : out std_logic_vector (w_2-1 downto 0); + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + begin + licznik : process (clk, reset) + variable cnt : unsigned(w_5-1 downto 0); + begin + if (reset = '1') then + cnt := (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt := cnt + 1; + if (std_logic_vector(cnt) = "00001") then + info <= "01"; + elsif (std_logic_vector(cnt) = "00000") then + info <= "00"; + else + info <= "11"; + end if; + else + cnt := (others => '0'); + end if; + end if; + num <= std_logic_vector(cnt); + end process licznik; + end Behavioral; + Index: rtl/vhdl/slayer.vhd =================================================================== --- rtl/vhdl/slayer.vhd (nonexistent) +++ rtl/vhdl/slayer.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer of Present cipher. Simple logic. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: rtl/vhdl/keyupd.vhd =================================================================== --- rtl/vhdl/keyupd.vhd (nonexistent) +++ rtl/vhdl/keyupd.vhd (revision 4) @@ -0,0 +1,86 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update module for present cipher it is 'signal ---- +---- mixing' made by rotation left by 61 bits, using one s-box, ---- +---- and output of the counter. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: rtl/vhdl/mux80.vhd =================================================================== --- rtl/vhdl/mux80.vhd (nonexistent) +++ rtl/vhdl/mux80.vhd (revision 4) @@ -0,0 +1,103 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This is not "strict" implementation of multiplexer but ---- +---- contains its functionality. There are two inputs. One - ---- +---- 32 bit input, and one 80 bit input - because of way, in which ---- +---- Present is working. For more information see below ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity mux80 is + generic ( + w_2 : integer := 2; + w_32 : integer := 32; + w_80 : integer := 80 + ); + port( + i0ctrl : in std_logic_vector (w_2-1 downto 0); + input0 : in std_logic_vector(w_32-1 downto 0); + input1 : in std_logic_vector(w_80-1 downto 0); + output : inout std_logic_vector(w_80-1 downto 0); + ctrl, clk, reset : in std_logic + ); +end mux80; + +architecture Behavioral of mux80 is + +begin + inne : process (clk, reset) + begin + if (reset = '1') then + output <= (others => '0'); + elsif (clk'Event and clk = '1') then + if ctrl = '0' then + -- load least significant 32 bits of output from input0 (32 bit wide) + if (i0ctrl = in_ld_reg_L ) then + output <= output(80-1 downto 32) & input0; + -- load "middle" significant 32 bits of output from input0 (32 bit wide) + elsif (i0ctrl = in_ld_reg_H) then + output <= output(79 downto 64) & input0 & output(31 downto 0); + -- load most significant 16 bits of output from input0 (16 bit wide) + elsif (i0ctrl = in_ld_reg_HH) then + output <= input0(15 downto 0) & output(63 downto 0); + else + -- do nothing + output <= output; + end if; + -- on output goes data from 80 bit input + else + output <= input1; + end if; + end if; + end process inne; +end Behavioral; + Index: rtl/vhdl/mux64.vhd =================================================================== --- rtl/vhdl/mux64.vhd (nonexistent) +++ rtl/vhdl/mux64.vhd (revision 4) @@ -0,0 +1,100 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This is not "strict" implementation of multiplexer but ---- +---- contains its functionality. There are two inputs. One - ---- +---- 32 bit input, and one 64 bit input - because of way, in which ---- +---- Present is working. For more information see below ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity mux64 is + generic ( + w_2 : integer := 2; + w_32 : integer := 32; + w_64 : integer := 64 + ); + port( + i0ctrl : in std_logic_vector (w_2-1 downto 0); + input0 : in std_logic_vector(w_32-1 downto 0); + input1 : in std_logic_vector(w_64-1 downto 0); + ctrl, clk, reset : in std_logic; + output : inout std_logic_vector(w_64-1 downto 0) + ); +end mux64; + +architecture Behavioral of mux64 is + +begin + inne : process (clk, reset) + begin + if (reset = '1') then + output <= (others => '0'); + elsif (clk'Event and clk = '1') then + if ctrl = '0' then + -- load least significant 32 bits of output from input0 (32 bit wide) + if (i0ctrl = in_ld_reg_L ) then + output <= output(w_64-1 downto 32) & input0; + -- load most significant 32 bits of output from input0 (32 bit wide) + elsif (i0ctrl = in_ld_reg_H) then + output <= input0 & output(31 downto 0); + else + -- do nothing + output <= output; + end if; + -- on output goes data from 64 bit input + else + output <= input1; + end if; + end if; + end process inne; +end Behavioral; + Index: rtl/vhdl/outputRegister.vhd =================================================================== --- rtl/vhdl/outputRegister.vhd (nonexistent) +++ rtl/vhdl/outputRegister.vhd (revision 4) @@ -0,0 +1,93 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Not "pure" registers. Main function of this component is ---- +---- to convert 64 bit input to 32 bit output. For more see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +entity outputRegister is + generic ( + w_2 : integer := 2; + w_32: integer := 32; + w_64: integer := 64 + ); + port( + rst, clk, rd : in std_logic; + ctrl : in std_logic_vector(w_2-1 downto 0); + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_32-1 downto 0); + ready : out std_logic + ); +end outputRegister; + +architecture Behavioral of outputRegister is + signal reg : std_logic_vector(w_64-1 downto 0); + begin + process( rst, clk, ctrl, input) + begin + if (rst = '1') then + output <= (others=>'Z'); + elsif(clk'event and clk = '1') then + -- loading internal signal + if(ctrl = out_ld_reg) then + reg <= input; + output <= (others=>'Z'); + ---- leas significant 32 bits to output + elsif (ctrl = out_reg_L) then + output <= reg(w_32-1 downto 0); + ---- most significant 32 bits to output + elsif (ctrl = out_reg_H) then + output <= reg(w_64-1 downto w_32); + ---- this should not happen + else + output <= (others=>'Z'); + end if; + end if; + end process; + ready <= rd; + end Behavioral; + Index: rtl/vhdl/PresentEnc.vhd =================================================================== --- rtl/vhdl/PresentEnc.vhd (nonexistent) +++ rtl/vhdl/PresentEnc.vhd (revision 4) @@ -0,0 +1,224 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level of present encoder with 32 bit IO. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEnc is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + ctrl : in std_logic_vector(w_4-1 downto 0); + input : in std_logic_vector(w_32-1 downto 0); + output : out std_logic_vector(w_32-1 downto 0); + clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEnc; + +architecture Behavioral of PresentEnc is + + component PresentStateMachine is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port ( + info : in std_logic_vector (w_2-1 downto 0); + ctrl : in std_logic_vector (w_4-1 downto 0); + key_ctrl: out std_logic_vector (w_2-1 downto 0); + plain_ctrl: out std_logic_vector (w_2-1 downto 0); + outReg : out std_logic_vector (w_2-1 downto 0); + reset, clk : in std_logic; + ready, cnt_res, ctrl_mux64, ctrl_mux80 : out std_logic + ); + end component; + + -- substitution layer for decoding + component slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + -- permutation layer for decoding + component pLayer is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + -- key update for decoding + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + -- 'register' for 32 bit output and 64 bit input + component outputRegister is + generic ( + w_2 : integer := 2; + w_32: integer := 32; + w_64: integer := 64 + ); + port( + ctrl : in std_logic_vector(w_2-1 downto 0); + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_32-1 downto 0); + rst, clk, rd : in std_logic; + ready : out std_logic + ); + end component; + + -- counter for decoding. It is counting up!!! + component counter is + generic ( + w_2 : integer := 2; + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + info : out std_logic_vector(w_2-1 downto 0); + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- 'multiplexer' for 32/64 bit input and 64 bit output + component mux64 is + generic ( + w_2 : integer := 2; + w_32 : integer := 32; + w_64 : integer := 64 + ); + port( + i0ctrl : in std_logic_vector (w_2-1 downto 0); + input0 : in std_logic_vector(w_32-1 downto 0); + input1 : in std_logic_vector(w_64-1 downto 0); + output : inout std_logic_vector(w_64-1 downto 0); + ctrl, clk, reset : in std_logic + ); + end component; + + -- 'multiplexer' for 32/80 bit input and 80 bit output + component mux80 is + generic ( + w_2 : integer := 2; + w_32 : integer := 32; + w_80 : integer := 80 + ); + port( + i0ctrl : in std_logic_vector (w_2-1 downto 0); + input0 : in std_logic_vector(w_32-1 downto 0); + input1 : in std_logic_vector(w_80-1 downto 0); + output : inout std_logic_vector(w_80-1 downto 0); + ctrl, clk, reset : in std_logic + ); + end component; + + component xorModule is + generic( + w : positive + ); + port( + inputA, inputB : in std_logic_vector( w-1 downto 0 ); + output : out std_logic_vector ( w-1 downto 0 ) + ); + end component; + + -- signals + + signal ro32ctrl, key_ctrl, plain_ctrl, info : std_logic_vector(w_2-1 downto 0); + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciphertext, P, Pout : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux64ctrl, mux80ctrl, cnt_res : std_logic; + + begin + + -- connections + + mux_64: mux64 port map( + input0 => input, input1 => Pout, output => toXor, ctrl => mux64ctrl, + i0ctrl => plain_ctrl, clk => clk, reset => reset); + mux_80: mux80 port map( + input0 => input, input1 => kupd, output => keyfout, ctrl => mux80ctrl, + i0ctrl => key_ctrl, clk => clk, reset => reset); + slayers : for N in 15 downto 0 generate + s_x: slayer port map(input => ciphertext(4*N+3 downto 4*N), output => P(4*N+3 downto 4*N)); + end generate slayers; + p1: pLayer port map(input => P, output => Pout); + mixer: keyupd port map(key => keyfout, num => keynum, keyout => kupd); + output_reg: outputRegister port map(rst => reset, clk => clk, rd => ready_sig, ctrl => ro32ctrl, + input => ciphertext, output => output, ready => ready); + SM: PresentStateMachine port map(ctrl => ctrl, outReg => ro32ctrl, reset => reset, + ready => ready_sig, cnt_res => cnt_res, ctrl_mux64 => mux64ctrl, ctrl_mux80 => mux80ctrl, + clk => clk, key_ctrl => key_ctrl, plain_ctrl => plain_ctrl, info => info + ); + count: counter port map( clk => clk, reset => reset, cnt_res => cnt_res, info => info, num => keynum); + ciphertext <= toXor xor keyfout(79 downto 16); +end Behavioral; Index: rtl/vhdl/PresentStateMachine.vhd =================================================================== --- rtl/vhdl/PresentStateMachine.vhd (nonexistent) +++ rtl/vhdl/PresentStateMachine.vhd (revision 4) @@ -0,0 +1,203 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present encoder with 32 bit IO. For more---- +---- informations ---- +---- see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_2 : integer := 2; + w_4 : integer := 4; + w_5 : integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port ( + clk, reset : in std_logic; + info : in std_logic_vector (w_2-1 downto 0); + ctrl : in std_logic_vector (w_4-1 downto 0); + key_ctrl: out std_logic_vector (w_2-1 downto 0); + plain_ctrl: out std_logic_vector (w_2-1 downto 0); + outReg : out std_logic_vector (w_2-1 downto 0); + ready, cnt_res, ctrl_mux64, ctrl_mux80: out std_logic + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal stan : stany; + signal stan_nast : stany; + + begin + States : process(stan, ctrl, info) + begin + stan_nast<= stan; + case stan is + -- waiting for start + when NOP => + ready <= '0'; + outReg <= out_reg_Z; + cnt_res <= '0'; + ctrl_mux64 <= '0'; + ctrl_mux80 <= '0'; + -- read first 32 bits of key + if (ctrl = crdk1) then + key_ctrl <= in_ld_reg_L; + stan_nast <= RDK1; + else + stan_nast <= NOP; + end if; + when RDK1 => + -- read second 32 bits of key + if (ctrl = crdk2) then + key_ctrl <= in_ld_reg_H; + stan_nast <= RDK2; + -- wait for next 32 bits of key + elsif (ctrl = crdk1) then + key_ctrl <= in_ld_reg_L; + else + stan_nast <= NOP; + end if; + when RDK2 => + -- read last 16 bits of key + if (ctrl = crdk3) then + key_ctrl <= in_ld_reg_HH; + stan_nast <= RDK3; + -- wait for next 16 bits of key + elsif (ctrl = crdk2) then + key_ctrl <= in_ld_reg_H; + else + stan_nast <= NOP; + end if; + when RDK3 => + -- read first 32 bits of text + if (ctrl = crdt1) then + key_ctrl <= in_reg_Z; + plain_ctrl <= in_ld_reg_L; + stan_nast <= RDT1; + -- wait for first 32 bits of text + elsif (ctrl = crdk3) then + key_ctrl <= in_ld_reg_HH; + else + stan_nast <= NOP; + end if; + when RDT1 => + -- read second 32 bits of text + if (ctrl = crdt2) then + plain_ctrl <= in_ld_reg_H; + stan_nast <= RDT2; + -- wait for second 32 bits of text + elsif (ctrl = crdt1) then + plain_ctrl <= in_ld_reg_L; + else + stan_nast <= NOP; + end if; + when RDT2 => + --- Encode data + if (ctrl = ccod) then + plain_ctrl <= in_reg_Z; + stan_nast <= COD; + cnt_res <= '1'; + -- Wait for encode + elsif (ctrl = crdt2) then + plain_ctrl <= in_ld_reg_H; + else + stan_nast <= NOP; + end if; + when COD => + -- Encode data + if (ctrl = ccod) then + -- Ready + if (info = "00") then + stan_nast <= CTO1; + outReg <= out_ld_reg; + ready <= '1'; + cnt_res <= '0'; + ready <= '1'; + -- encoding + elsif (info = "01") then + ctrl_mux64 <= '1'; + ctrl_mux80 <= '1'; + end if; + else + stan_nast <= NOP; + end if; + when CTO1 => + -- send first 32 bits of data + if (ctrl = ccto2) then + stan_nast <= CTO2; + outReg <= out_reg_L; + -- wait for sending second 32 bits of data + elsif ((ctrl = ccto1) or (ctrl = ccod)) then + outReg <= out_reg_L; + else + stan_nast <= NOP; + end if; + when CTO2 => + -- send second 32 bits of data + if (ctrl = ccto2) then + stan_nast <= CTO2; + outReg <= out_reg_H; + else + stan_nast <= NOP; + end if; + end case; + end process States; + + inne : process (clk, reset) + begin + if (reset = '1') then + stan <= NOP; + elsif (clk'Event and clk = '1') then + stan <= stan_nast; + end if; + end process inne; + + end Behavioral; + Index: rtl/vhdl/kody.vhd =================================================================== --- rtl/vhdl/kody.vhd (nonexistent) +++ rtl/vhdl/kody.vhd (revision 4) @@ -0,0 +1,77 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This file contains types and constant used by this ---- +---- implementation of Present project ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, RDK1, RDK2, RDK3, RDT1, RDT2, COD, CTO1, CTO2); + -- constant as control command from input -- + constant cnop : std_logic_vector(3 downto 0) := "0000"; --0 no operations + constant cdec : std_logic_vector(3 downto 0) := "0001"; --1 decode text + constant crdk1 : std_logic_vector(3 downto 0) := "0010"; --2 read key part 1 + constant crdk2 : std_logic_vector(3 downto 0) := "0011"; --3 read key part 2 + constant crdk3 : std_logic_vector(3 downto 0) := "0100"; --4 read key part 3 + constant cmkd : std_logic_vector(3 downto 0) := "0101"; --5 make decrypt key + constant ccod : std_logic_vector(3 downto 0) := "0110"; --6 code text + constant crdt1 : std_logic_vector(3 downto 0) := "0111"; --7 read text part 1 + constant crdt2 : std_logic_vector(3 downto 0) := "1000"; --8 read text part 2 + constant ccto1 : std_logic_vector(3 downto 0) := "1001"; --9 ciphertext output part 1 (LSW) + constant ccto2 : std_logic_vector(3 downto 0) := "1010"; --A ciphertext output part 2 (MSW) + -- For input registers (early version, now for mux's) -- + constant in_ld_reg_L : std_logic_vector(1 downto 0) := "00"; -- Load low part of the register (64 & 80 bit) + constant in_ld_reg_H : std_logic_vector(1 downto 0) := "01"; -- Load high part of the register (64 & 80 bit) + constant in_ld_reg_HH : std_logic_vector(1 downto 0) := "10"; -- Load highest part of the register (80 bit only) + constant in_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) + -- For output register -- + constant out_ld_reg : std_logic_vector(1 downto 0) := "00"; -- Load the output register + constant out_reg_L : std_logic_vector(1 downto 0) := "01"; -- send low part of the register to the output + constant out_reg_H : std_logic_vector(1 downto 0) := "10"; -- senf high part of the register to the output + constant out_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) +end kody; \ No newline at end of file Index: rtl/vhdl/pLayer.vhd =================================================================== --- rtl/vhdl/pLayer.vhd (nonexistent) +++ rtl/vhdl/pLayer.vhd (revision 4) @@ -0,0 +1,125 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Permutation layer of Present cipher. Simple signal mixing.---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer; + +architecture Behavioral of pLayer is +begin + output(0) <= input(0); + output(16) <= input(1); + output(32) <= input(2); + output(48) <= input(3); + output(1) <= input(4); + output(17) <= input(5); + output(33) <= input(6); + output(49) <= input(7); + output(2) <= input(8); + output(18) <= input(9); + output(34) <= input(10); + output(50) <= input(11); + output(3) <= input(12); + output(19) <= input(13); + output(35) <= input(14); + output(51) <= input(15); + output(4) <= input(16); + output(20) <= input(17); + output(36) <= input(18); + output(52) <= input(19); + output(5) <= input(20); + output(21) <= input(21); + output(37) <= input(22); + output(53) <= input(23); + output(6) <= input(24); + output(22) <= input(25); + output(38) <= input(26); + output(54) <= input(27); + output(7) <= input(28); + output(23) <= input(29); + output(39) <= input(30); + output(55) <= input(31); + output(8) <= input(32); + output(24) <= input(33); + output(40) <= input(34); + output(56) <= input(35); + output(9) <= input(36); + output(25) <= input(37); + output(41) <= input(38); + output(57) <= input(39); + output(10) <= input(40); + output(26) <= input(41); + output(42) <= input(42); + output(58) <= input(43); + output(11) <= input(44); + output(27) <= input(45); + output(43) <= input(46); + output(59) <= input(47); + output(12) <= input(48); + output(28) <= input(49); + output(44) <= input(50); + output(60) <= input(51); + output(13) <= input(52); + output(29) <= input(53); + output(45) <= input(54); + output(61) <= input(55); + output(14) <= input(56); + output(30) <= input(57); + output(46) <= input(58); + output(62) <= input(59); + output(15) <= input(60); + output(31) <= input(61); + output(47) <= input(62); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: rtl/vhdl =================================================================== --- rtl/vhdl (nonexistent) +++ rtl/vhdl (revision 4)
rtl/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: rtl =================================================================== --- rtl (nonexistent) +++ rtl (revision 4)
rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: doc/src =================================================================== --- doc/src (nonexistent) +++ doc/src (revision 4)
doc/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: doc =================================================================== --- doc (nonexistent) +++ doc (revision 4)
doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sim =================================================================== --- sim (nonexistent) +++ sim (revision 4)
sim Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw =================================================================== --- sw (nonexistent) +++ sw (revision 4)
sw Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: syn/XC3ES500 =================================================================== --- syn/XC3ES500 (nonexistent) +++ syn/XC3ES500 (revision 4)
syn/XC3ES500 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: syn =================================================================== --- syn (nonexistent) +++ syn (revision 4)
syn Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property

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