Subversion Repositories present

/keyupd_invTB.vhd File deleted \ No newline at end of file

/PresentEncKeyGen.vhd File deleted

/pLayer_inv.vhd File deleted \ No newline at end of file

/Reg.vhd File deleted

/PresentDecStateMachine.vhd File deleted

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/PresentDec.vhd File deleted

/PresentStateMachine.vhd File deleted

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/counter.vhd File deleted

/counter_inv.vhd File deleted

/PresentFullDecoder.vhd File deleted

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/PresentDecTB.vhd File deleted

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/keyupd.vhd File deleted \ No newline at end of file

/PresentKeyGenTB.vhd File deleted

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/kody.vhd File deleted \ No newline at end of file

/bench/vhdl/PresentFullDecoderTB.vhd

/bench/vhdl/sLayer_invTB.vhd

/bench/vhdl/PresentDecTB.vhd

/bench/vhdl/keyupd_invTB.vhd

/bench/vhdl/PresentKeyGenTB.vhd

/bench/vhdl/txt_util.vhd

/bench/vhdl

bench/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: bench =================================================================== --- bench (nonexistent) +++ bench (revision 4)

bench Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: rtl/vhdl/slayer.vhd =================================================================== --- rtl/vhdl/slayer.vhd (nonexistent) +++ rtl/vhdl/slayer.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer of Present cipher. Simple logic. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: rtl/vhdl/keyupd.vhd =================================================================== --- rtl/vhdl/keyupd.vhd (nonexistent) +++ rtl/vhdl/keyupd.vhd (revision 4) @@ -0,0 +1,86 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update module for present cipher it is 'signal ---- +---- mixing' made by rotation left by 61 bits, using one s-box, ---- +---- and output of the counter. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: rtl/vhdl/PresentStateMachine.vhd =================================================================== --- rtl/vhdl/PresentStateMachine.vhd (nonexistent) +++ rtl/vhdl/PresentStateMachine.vhd (revision 4) @@ -0,0 +1,130 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present encoder. For more informations ---- +---- see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + ---- Waiting for start + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + RegEn <= '0'; + if (start = '1') then + next_state <= SM_START; + else + next_state <= NOP; + end if; + -- Decoding + when SM_START => + ready <= '0'; + RegEn <= '1'; + cnt_res <= '1'; + if (start = '1') then + -- control during first start + if (num = "00000") then + ctrl_mux <= '0'; + next_state <= SM_START; + -- last iteration + elsif (num = "11111") then + ctrl_mux <= '1'; + next_state <= SM_READY; + -- rest iterations + else + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + -- Decoding end + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: rtl/vhdl/kody.vhd =================================================================== --- rtl/vhdl/kody.vhd (nonexistent) +++ rtl/vhdl/kody.vhd (revision 4) @@ -0,0 +1,56 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This file contains types and constant used by this ---- +---- implementation of Present project ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, SM_START, SM_READY); + type decode_states is (NOP, KG_START, DEC_START, DEC_READY); +end kody; \ No newline at end of file Index: rtl/vhdl/AsyncMux.vhd =================================================================== --- rtl/vhdl/AsyncMux.vhd (nonexistent) +++ rtl/vhdl/AsyncMux.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Simple construction of multiplexer. Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); +end AsyncMux; + +architecture Behavioral of AsyncMux is + +begin + output <= input0 when (ctrl = '0') else + input1; +end Behavioral; + Index: rtl/vhdl/pLayer_inv.vhd =================================================================== --- rtl/vhdl/pLayer_inv.vhd (nonexistent) +++ rtl/vhdl/pLayer_inv.vhd (revision 4) @@ -0,0 +1,125 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Permutation layer of Present decoder. Simple signal ---- +---- mixing, but in inverse way as cipher. For more information see---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer_inv is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer_inv; + +architecture Behavioral of pLayer_inv is +begin + output(0) <= input(0); + output(1) <= input(16); + output(2) <= input(32); + output(3) <= input(48); + output(4) <= input(1); + output(5) <= input(17); + output(6) <= input(33); + output(7) <= input(49); + output(8) <= input(2); + output(9) <= input(18); + output(10) <= input(34); + output(11) <= input(50); + output(12) <= input(3); + output(13) <= input(19); + output(14) <= input(35); + output(15) <= input(51); + output(16) <= input(4); + output(17) <= input(20); + output(18) <= input(36); + output(19) <= input(52); + output(20) <= input(5); + output(21) <= input(21); + output(22) <= input(37); + output(23) <= input(53); + output(24) <= input(6); + output(25) <= input(22); + output(26) <= input(38); + output(27) <= input(54); + output(28) <= input(7); + output(29) <= input(23); + output(30) <= input(39); + output(31) <= input(55); + output(32) <= input(8); + output(33) <= input(24); + output(34) <= input(40); + output(35) <= input(56); + output(36) <= input(9); + output(37) <= input(25); + output(38) <= input(41); + output(39) <= input(57); + output(40) <= input(10); + output(41) <= input(26); + output(42) <= input(42); + output(43) <= input(58); + output(44) <= input(11); + output(45) <= input(27); + output(46) <= input(43); + output(47) <= input(59); + output(48) <= input(12); + output(49) <= input(28); + output(50) <= input(44); + output(51) <= input(60); + output(52) <= input(13); + output(53) <= input(29); + output(54) <= input(45); + output(55) <= input(61); + output(56) <= input(14); + output(57) <= input(30); + output(58) <= input(46); + output(59) <= input(62); + output(60) <= input(15); + output(61) <= input(31); + output(62) <= input(47); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: rtl/vhdl/PresentEncKeyGen.vhd =================================================================== --- rtl/vhdl/PresentEncKeyGen.vhd (nonexistent) +++ rtl/vhdl/PresentEncKeyGen.vhd (revision 4) @@ -0,0 +1,170 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key generator of Present encoder. It is only those part ---- +---- which is needed for key and cipher decoding by Present ---- +---- decoder. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEncKeyGen is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_80: integer := 80 + ); + port( + key : in std_logic_vector(w_80 - 1 downto 0); + key_end : out std_logic_vector(w_80 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEncKeyGen; + +architecture Behavioral of PresentEncKeyGen is + + component Reg is + generic(width : integer := w_80); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 80 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- signals + + signal keynum : std_logic_vector (w_5-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + + -- connections + + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + mixer: keyupd port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + key_end <= keyfout; + ready <= ready_sig; +end Behavioral; Index: rtl/vhdl/slayer_inv.vhd =================================================================== --- rtl/vhdl/slayer_inv.vhd (nonexistent) +++ rtl/vhdl/slayer_inv.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Inverse substitution layer of Present decoder. Simple ---- +---- logic. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer_inv is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer_inv; + +architecture Behavioral of slayer_inv is + + begin + output <= x"0" when input = x"C" else + x"1" when input = x"5" else + x"2" when input = x"6" else + x"3" when input = x"B" else + x"4" when input = x"9" else + x"5" when input = x"0" else + x"6" when input = x"A" else + x"7" when input = x"D" else + x"8" when input = x"3" else + x"9" when input = x"E" else + x"A" when input = x"F" else + x"B" when input = x"8" else + x"C" when input = x"4" else + x"D" when input = x"7" else + x"E" when input = x"1" else + x"F" when input = x"2" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: rtl/vhdl/Reg.vhd =================================================================== --- rtl/vhdl/Reg.vhd (nonexistent) +++ rtl/vhdl/Reg.vhd (revision 4) @@ -0,0 +1,83 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Register - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg is + generic(width : integer := 64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end Reg; + +architecture Behavioral of Reg is + +signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); + +begin + clock : process(clk, reset) + begin + if (reset = '1') then + reg <= (others => '0'); + elsif (clk = '1' and clk'Event) then + if (enable = '1') then + reg <= input; + end if; + end if; + end process clock; + output <= reg; +end Behavioral; + Index: rtl/vhdl/keyupd_inv.vhd =================================================================== --- rtl/vhdl/keyupd_inv.vhd (nonexistent) +++ rtl/vhdl/keyupd_inv.vhd (revision 4) @@ -0,0 +1,88 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Inverse Key update module for present cipher decoding ---- +---- it is 'signal mixing' made by rotation right by 61 bits, ---- +---- using one s-box, and output of the counter. Note, that order ---- +---- of this operatins must be inverse in comparison with key_upd. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd_inv is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd_inv; + +architecture Behavioral of keyupd_inv is + + component slayer_inv is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer_inv port map(input => changin, output => changed); + changin <= key(79 downto 76); + keytemp(79 downto 76)<= changed; + keytemp(75 downto 20) <= key(75 downto 20); + keytemp(19 downto 15)<= key(19 downto 15) xor num; + keytemp(14 downto 0) <= key(14 downto 0); + keyout <= keytemp(60 downto 0) & keytemp(79 downto 61); + end Behavioral; \ No newline at end of file Index: rtl/vhdl/counter.vhd =================================================================== --- rtl/vhdl/counter.vhd (nonexistent) +++ rtl/vhdl/counter.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Typical construction of 5bit counter. It is counting up. ---- +---- Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt + 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: rtl/vhdl/PresentDecStateMachine.vhd =================================================================== --- rtl/vhdl/PresentDecStateMachine.vhd (nonexistent) +++ rtl/vhdl/PresentDecStateMachine.vhd (revision 4) @@ -0,0 +1,135 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present decoder. It is only part of ---- +---- "inverse Present", not key gen. For more informations see ---- +---- below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentDecStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentDecStateMachine; + +architecture Behavioral of PresentDecStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + ---- Waiting for start + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + if (start = '1') then + RegEn <= '1'; + next_state <= SM_START; + else + RegEn <= '0'; + next_state <= NOP; + end if; + -- Decoding + when SM_START => + ready <= '0'; + cnt_res <= '1'; + if (start = '1') then + -- control during first start + if (num = "11111") then + RegEn <= '1'; + ctrl_mux <= '1'; + next_state <= SM_START; + -- last iteration + elsif (num = "00000") then + RegEn <= '0'; + ctrl_mux <= '1'; + next_state <= SM_READY; + -- rest iterations + else + RegEn <= '1'; + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + RegEn <= '0'; + ctrl_mux <= '0'; + next_state <= NOP; + end if; + -- Decoding end + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: rtl/vhdl/FullDecoderSM.vhd =================================================================== --- rtl/vhdl/FullDecoderSM.vhd (nonexistent) +++ rtl/vhdl/FullDecoderSM.vhd (revision 4) @@ -0,0 +1,134 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present decoder. It controls entire ---- +---- environment for decoding. We can feature 2 'steady states' ---- +---- and 2 'running states'. For more informations see below ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FullDecoderSM is + port( + key_gen_start : out std_logic; + key_gen_ready : in std_logic; + decode_start : out std_logic; + decode_ready : in std_logic; + full_decoder_start :in std_logic; + full_decoder_ready : out std_logic; + clk, reset :in std_logic + ); +end FullDecoderSM; + +architecture Behavioral of FullDecoderSM is + + signal state : decode_states; + signal next_state : decode_states; + +begin + + states : process(state, full_decoder_start, key_gen_ready, decode_ready) + begin + case state is + ---- It is No operation - waiting for proper data in the input ---- + when NOP => + key_gen_start <= '0'; + decode_start <= '0'; + full_decoder_ready <= '0'; + if (full_decoder_start = '1') then + next_state <= KG_START; + else + next_state <= NOP; + end if; + ---- It is running key generator for decoding + when KG_START => + key_gen_start <= '1'; + decode_start <= '0'; + full_decoder_ready <= '0'; + if (key_gen_ready = '1') then + next_state <= DEC_START; + else + next_state <= KG_START; + end if; + ---- enerated key for decoding is ready. Now we are decoding ---- + when DEC_START => + key_gen_start <= '1'; + decode_start <= '1'; + full_decoder_ready <= '0'; + if (decode_ready = '1') then + next_state <= DEC_READY; + else + next_state <= DEC_START; + end if; + ---- Decoding was ended. Waiting for user retrieving data ---- + ---- and give information about new operation ---- + when DEC_READY => + key_gen_start <= '1'; + decode_start <= '1'; + full_decoder_ready <= '1'; + if (full_decoder_start = '1') then + next_state <= DEC_READY; + else + next_state <= NOP; + end if; + end case; + end process states; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + +end Behavioral; + Index: rtl/vhdl/PresentFullDecoder.vhd =================================================================== --- rtl/vhdl/PresentFullDecoder.vhd (nonexistent) +++ rtl/vhdl/PresentFullDecoder.vhd (revision 4) @@ -0,0 +1,170 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Present decoder with suitable key generator for decoding ---- +---- (basing on given encode key). ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentFullDecoder is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + ciphertext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + plaintext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentFullDecoder; + +architecture Behavioral of PresentFullDecoder is + +-- Key generator component +component PresentEncKeyGen is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_80: integer := 80 + ); + port( + key : in std_logic_vector(w_80 - 1 downto 0); + key_end : out std_logic_vector(w_80 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentEncKeyGen; + +-- 'pure' Present decoder +component PresentDec is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentDec; + +component FullDecoderSM is + port( + key_gen_start : out std_logic; + key_gen_ready : in std_logic; + decode_start : out std_logic; + decode_ready : in std_logic; + full_decoder_start :in std_logic; + full_decoder_ready : out std_logic; + clk, reset :in std_logic + ); +end component FullDecoderSM; + +-- signals + +signal key_gen_output : std_logic_vector(w_80 - 1 downto 0); + +signal key_gen_start : std_logic; +signal key_gen_ready : std_logic; + +signal decode_start : std_logic; +signal decode_ready : std_logic; + +begin + + -- connections + + keyGen : PresentEncKeyGen + port map( + key => key, + key_end => key_gen_output, + start => key_gen_start, + clk => clk, + reset => reset, + ready => key_gen_ready + ); + + decoder : PresentDec + port map( + plaintext => ciphertext, + key => key_gen_output, + ciphertext => plaintext, + start => decode_start, + clk => clk, + reset => reset, + ready => decode_ready + ); + + SM : FullDecoderSM + port map( + key_gen_start => key_gen_start, + key_gen_ready => key_gen_ready, + decode_start => decode_start, + decode_ready => decode_ready, + full_decoder_start => start, + full_decoder_ready => ready, + clk => clk, + reset => reset + ); + +end Behavioral; Index: rtl/vhdl/counter_inv.vhd =================================================================== --- rtl/vhdl/counter_inv.vhd (nonexistent) +++ rtl/vhdl/counter_inv.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Typical construction of 5bit counter. It is counting ---- +---- down. Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter_inv is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter_inv; + +architecture Behavioral of counter_inv is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '1'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt - 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: rtl/vhdl/PresentDec.vhd =================================================================== --- rtl/vhdl/PresentDec.vhd (nonexistent) +++ rtl/vhdl/PresentDec.vhd (revision 4) @@ -0,0 +1,220 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level of present decoder. It contains 'Key generator' ---- +---- from encoder and 'inverse Present' for decoding the cipher. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentDec is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentDec; + +architecture Behavioral of PresentDec is + + component Reg is + generic(width : integer := w_64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentDecStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- INVERSE substitution layer for decoding + component slayer_inv is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + -- INVERSE permutation layer for decoding + component pLayer_inv is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + -- INVERSE key update for decoding + component keyupd_inv is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + -- INVERSE counter for decoding. It is counting down!!! + component counter_inv is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- signals + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + + -- connections + mux_64: AsyncMux generic map(width => w_64) port map( + input0 => plaintext, + input1 => Pout, + ctrl => mux_ctrl, + output => textToReg + ); + regText : Reg generic map(width => w_64) port map( + input => textToReg, + output => toXor, + enable => RegEn, + clk => clk, + reset => reset + ); + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + slayers_inv : for N in 15 downto 0 generate + s_x: slayer_inv port map( + input => P(4*N+3 downto 4*N), + output => Pout(4*N+3 downto 4*N) + ); + end generate slayers_inv; + p1: pLayer_inv port map( + input => ciph, + output => P + ); + mixer: keyupd_inv port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentDecStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter_inv port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + ciph <= toXor xor keyfout(79 downto 16); + ciphertext <= ciph; + ready <= ready_sig; +end Behavioral; Index: rtl/vhdl =================================================================== --- rtl/vhdl (nonexistent) +++ rtl/vhdl (revision 4)

rtl/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: rtl =================================================================== --- rtl (nonexistent) +++ rtl (revision 4)

rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: doc/src =================================================================== --- doc/src (nonexistent) +++ doc/src (revision 4)

doc/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: doc =================================================================== --- doc (nonexistent) +++ doc (revision 4)

doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sim =================================================================== --- sim (nonexistent) +++ sim (revision 4)

sim Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw =================================================================== --- sw (nonexistent) +++ sw (revision 4)

sw Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: syn/XC3ES500 =================================================================== --- syn/XC3ES500 (nonexistent) +++ syn/XC3ES500 (revision 4)

syn/XC3ES500 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: syn =================================================================== --- syn (nonexistent) +++ syn (revision 4)

syn Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property