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URL https://opencores.org/ocsvn/present/present/trunk

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  • This comparison shows the changes necessary to convert path 
    /present/trunk/DecodeTesting/bench
    from Rev 7 to Rev 11
    ↔ Reverse comparison
  •

Rev 7 → Rev 11

/vhdl/PresentFullDecoderTB.vhd
110,6 → 110,12
stim_proc: process
begin
---- Preparation for test case 1 -----------------
-- ciphertext <= x"5579c1387b228445";
-- key <= x"00000000000000000000";
-- expected_plaintext <= x"0000000000000000";
--------------------------------------------------
reset <= '1';
start <= '0';
ciphertext <= x"5579c1387b228445";
120,7 → 126,21
ciphertext <= x"5579c1387b228445";
key <= (others => '0');
start <= '1';
wait for clk_period*80;
wait until ready = '1';
 
if plaintext /= x"0000000000000000" then
report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
assert false severity failure;
else
report "Test case 1 successful" severity note;
end if;
 
---- Preparation for test case 2 -----------------
-- ciphertext <= x"e72c46c0f5945049";
-- key <= x"ffffffffffffffffffff";
-- expected_plaintext <= x"0000000000000000";
--------------------------------------------------
start <= '0';
wait for clk_period;
127,7 → 147,21
ciphertext <= x"e72c46c0f5945049";
key <= (others => '1');
start <= '1';
wait for clk_period*80;
wait until ready = '1';
 
if plaintext /= x"0000000000000000" then
report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
assert false severity failure;
else
report "Test case 2 successful" severity note;
end if;
 
---- Preparation for test case 3 -----------------
-- ciphertext <= x"a112ffc72f68417b";
-- key <= x"00000000000000000000";
-- expected_plaintext <= x"ffffffffffffffff";
--------------------------------------------------
start <= '0';
wait for clk_period;
134,7 → 168,21
ciphertext <= x"a112ffc72f68417b";
key <= (others => '0');
start <= '1';
wait for clk_period*80;
wait until ready = '1';
if plaintext /= x"ffffffffffffffff" then
report "RESULT MISMATCH! Test case 3 failed" severity ERROR;
assert false severity failure;
else
report "Test case 3 successful" severity note;
end if;
 
---- Preparation for test case 4 -----------------
-- ciphertext <= x"3333dcd3213210d2";
-- key <= x"ffffffffffffffffffff";
-- expected_plaintext <= x"ffffffffffffffff";
--------------------------------------------------
start <= '0';
wait for clk_period;
141,10 → 189,18
ciphertext <= x"3333dcd3213210d2";
key <= (others => '1');
start <= '1';
wait for clk_period*80;
wait until ready = '1';
start <= '0';
wait for clk_period;
if plaintext /= x"ffffffffffffffff" then
report "RESULT MISMATCH! Test case 4 failed" severity ERROR;
assert false severity failure;
else
report "Test case 4 successful" severity note;
end if;
assert false severity failure;
 
end process;
/vhdl/ShiftRegTB.vhd
121,14 → 121,41
wait for 100 ns;
reset <= '1';
wait for clk_period*10;
reset <= '0';
en <= '1';
wait for clk_period*1;
en <= '0';
wait for clk_period*1;
 
------------- Test case 1 ------------------------
-- expected_output <= x"aa00000000000000";
--------------------------------------------------
if output /= x"aa00000000000000" then
report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
assert false severity failure;
else
report "Test case 1 successful" severity note;
end if;
shift <= '1';
wait for clk_period*10;
assert false severity failure;
------------- Test case 2 ------------------------
-- expected_output <= x"002a800000000000";
--------------------------------------------------
if output /= x"002a800000000000" then
report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
assert false severity failure;
else
report "Test case 2 successful" severity note;
end if;
assert false severity failure;
end process;
 
END;
/vhdl/sLayer_invTB.vhd
89,7 → 89,6
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
98,13 → 97,52
wait for 100ns;
reset <= '0';
wait for clk_period;
 
------------- Test case 1 ------------------------
-- input <= x"0";
-- expected_output <= x"5";
--------------------------------------------------
 
input <= x"0";
wait for clk_period;
if output /= x"5" then
report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
assert false severity failure;
else
report "Test case 1 successful" severity note;
end if;
------------- Test case 2 ------------------------
-- input <= x"A";
-- expected_output <= x"6";
--------------------------------------------------
input <= x"A";
wait for clk_period;
if output /= x"6" then
report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
assert false severity failure;
else
report "Test case 2 successful" severity note;
end if;
 
------------- Test case 3 ------------------------
-- input <= x"F";
-- expected_output <= x"A";
--------------------------------------------------
input <= x"F";
wait for clk_period;
-- insert stimulus here
if output /= x"A" then
report "RESULT MISMATCH! Test case 3 failed" severity ERROR;
assert false severity failure;
else
report "Test case 3 successful" severity note;
end if;
 
assert false severity failure;
end process;
 
/vhdl/PresentDecTB.vhd
110,6 → 110,12
stim_proc: process
begin
 
---- Preparation for test case 1 -----------------
-- plaintext <= x"5579c1387b228445";
-- key <= x"6dab31744f41d7008759";
-- expected_ciphertext <= x"0000000000000000";
--------------------------------------------------
 
reset <= '1';
start <= '0';
plaintext <= x"5579c1387b228445";
120,7 → 126,21
plaintext <= x"5579c1387b228445";
key <= x"6dab31744f41d7008759";
start <= '1';
wait for clk_period*40;
wait until ready = '1';
if ciphertext /= x"0000000000000000" then
report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
assert false severity failure;
else
report "Test case 1 successful" severity note;
end if;
 
---- Preparation for test case 2 -----------------
-- plaintext <= x"e72c46c0f5945049";
-- key <= x"fe7a548fb60eb167c511";
-- expected_ciphertext <= x"0000000000000000";
--------------------------------------------------
start <= '0';
wait for clk_period;
127,7 → 147,21
plaintext <= x"e72c46c0f5945049";
key <= x"fe7a548fb60eb167c511";
start <= '1';
wait for clk_period*40;
wait until ready = '1';
if ciphertext /= x"0000000000000000" then
report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
assert false severity failure;
else
report "Test case 2 successful" severity note;
end if;
 
---- Preparation for test case 3 -----------------
-- plaintext <= x"a112ffc72f68417b";
-- key <= x"6dab31744f41d7008759";
-- expected_ciphertext <= x"ffffffffffffffff";
--------------------------------------------------
 
start <= '0';
wait for clk_period;
134,7 → 168,21
plaintext <= x"a112ffc72f68417b";
key <= x"6dab31744f41d7008759";
start <= '1';
wait for clk_period*40;
wait until ready = '1';
if ciphertext /= x"ffffffffffffffff" then
report "RESULT MISMATCH! Test case 3 failed" severity ERROR;
assert false severity failure;
else
report "Test case 3 successful" severity note;
end if;
 
---- Preparation for test case 4 -----------------
-- plaintext <= x"3333dcd3213210d2";
-- key <= x"fe7a548fb60eb167c511";
-- expected_ciphertext <= x"ffffffffffffffff";
--------------------------------------------------
 
start <= '0';
wait for clk_period;
141,10 → 189,15
plaintext <= x"3333dcd3213210d2";
key <= x"fe7a548fb60eb167c511";
start <= '1';
wait for clk_period*40;
start <= '0';
wait for clk_period;
wait until ready = '1';
if ciphertext /= x"ffffffffffffffff" then
report "RESULT MISMATCH! Test case 4 failed" severity ERROR;
assert false severity failure;
else
report "Test case 4 successful" severity note;
end if;
assert false severity failure;
 
end process;
/vhdl/keyupd_invTB.vhd
106,18 → 106,71
wait for 100ns;
reset <='0';
wait for clk_period;
key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
------------- Test case 1 ------------------------
-- key <= x"00000000000000000000";
-- expected_keyout <= x"c0000000000000008000";
--------------------------------------------------
key <= x"c0000000000000008000";
num <= "00001";
wait for clk_period;
key <= x"c0000000000000008000";
if keyout /= x"00000000000000000000" then
report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
assert false severity failure;
else
report "Test case 1 successful" severity note;
end if;
------------- Test case 2 ------------------------
-- key <= x"c0000000000000008000";
-- expected_keyout <= x"50001800000000010000";
--------------------------------------------------
key <= x"50001800000000010000";
num <= "00010";
wait for clk_period;
key <= x"50001800000000010000";
if keyout /= x"c0000000000000008000" then
report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
assert false severity failure;
else
report "Test case 2 successful" severity note;
end if;
------------- Test case 3 ------------------------
-- key <= x"60000a00030000018000";
-- expected_keyout <= x"50001800000000010000";
--------------------------------------------------
key <= x"60000a00030000018000";
num <= "00011";
wait for clk_period;
key <= x"8ba27a0eb8783ac96d59";
if keyout /= x"50001800000000010000" then
report "RESULT MISMATCH! Test case 3 failed" severity ERROR;
assert false severity failure;
else
report "Test case 3 successful" severity note;
end if;
------------- Test case 4 ------------------------
-- key <= x"8ba27a0eb8783ac96d59";
-- expected_keyout <= x"8ba27a0eb8783ac96d59";
--------------------------------------------------
key <= x"6dab31744f41d7008759";
num <= "11111";
wait for clk_period;
if keyout /= x"8ba27a0eb8783ac96d59" then
report "RESULT MISMATCH! Test case 4 failed" severity ERROR;
assert false severity failure;
else
report "Test case 4 successful" severity note;
end if;
assert false severity failure;
end process;
END;
/vhdl/PresentDecodeCommTB.vhd
124,6 → 124,8
wait for CLK_period*10;
 
-- All data are sent in direction from LSB to MSB
 
-- Reading first 'data' file each "segment" is one bit of serial data
while not (endfile(txt)) loop
readline(txt, line_in); -- info line
180,7 → 182,7
DATA_RXD <= data; -- parity bit
wait for 8.75 us;
report "Koniec bajtu";
report "End of byte";
DATA_RXD <= '1'; -- stop bit
wait for 100 us;
end loop;
239,7 → 241,7
DATA_RXD <= data; -- parity bit
wait for 8.75 us;
report "Koniec bajtu";
report "End of byte";
DATA_RXD <= '1'; -- stop bit
wait for 100 us;
end loop;
301,7 → 303,7
DATA_RXD <= data; -- parity bit
wait for 8.75 us;
report "Koniec bajtu";
report "End of byte";
DATA_RXD <= '1'; -- stop bit
wait for 100 us;
end loop;
360,7 → 362,7
DATA_RXD <= data; -- parity bit
wait for 8.75 us;
report "Koniec bajtu";
report "End of byte";
DATA_RXD <= '1'; -- stop bit
wait for 100 us;
end loop;
/vhdl/PresentKeyGenTB.vhd
105,6 → 105,11
stim_proc: process
begin
 
---- Preparation for test case 1 -----------------
-- key <= x"00000000000000000000";
-- expected_key_end <= x"6dab31744f41d7008759";
--------------------------------------------------
 
reset <= '1';
start <= '0';
wait for 100 ns;
112,27 → 117,72
key <= (others => '0');
start <= '1';
wait for clk_period*40;
wait until ready = '1';
if key_end /= x"6dab31744f41d7008759" then
report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
assert false severity failure;
else
report "Test case 1 successful" severity note;
end if;
 
---- Preparation for test case 2 -----------------
-- key <= x"ffffffffffffffffffff";
-- expected_key_end <= x"fe7a548fb60eb167c511";
--------------------------------------------------
 
start <= '0';
wait for clk_period;
key <= (others => '1');
start <= '1';
wait for clk_period*40;
wait until ready = '1';
if key_end /= x"fe7a548fb60eb167c511" then
report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
assert false severity failure;
else
report "Test case 2 successful" severity note;
end if;
 
---- Preparation for test case 3 -----------------
-- key <= x"00000000000000000000";
-- expected_key_end <= x"6dab31744f41d7008759";
-- same as test case 1
--------------------------------------------------
start <= '0';
wait for clk_period;
 
key <= (others => '0');
start <= '1';
wait for clk_period*40;
wait until ready = '1';
if key_end /= x"6dab31744f41d7008759" then
report "RESULT MISMATCH! Test case 3 failed" severity ERROR;
assert false severity failure;
else
report "Test case 3 successful" severity note;
end if;
 
---- Preparation for test case 4 -----------------
-- key <= x"ffffffffffffffffffff";
-- expected_key_end <= x"fe7a548fb60eb167c511";
--------------------------------------------------
start <= '0';
wait for clk_period;
key <= (others => '1');
start <= '1';
wait for clk_period*40;
start <= '0';
wait for clk_period;
wait until ready = '1';
 
if key_end /= x"fe7a548fb60eb167c511" then
report "RESULT MISMATCH! Test case 4 failed" severity ERROR;
assert false severity failure;
else
report "Test case 4 successful" severity note;
end if;
assert false severity failure;
 

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