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/present_decode_testing.tex
7,7 → 7,7
%%%%%%%%%%%%%%%%%
\docDate{ \today }
\docID{Present Decoder ("Decode Testing") - with communication channel with PC}
\docRevision{0.1}
\docRevision{0.2}
\docStatus{Draft}
\docTitle{\mbox{Present Decoder ("Decode Testing") -} \mbox{with communication channel with PC}}
\docTitleShort{Present Decoder ("Decode Testing")...}
18,6 → 18,7
 
\revisionList{
0.1 & all & 2014/05/25 & First draft & K. Gajewski \\
0.2 & all & 2014/09/16 & Some small corrections with the text, typos, etc. & K. Gajewski \\
}
 
\begin{document}
54,18 → 55,18
\end{center}
\end{figure}
 
In subprojects \texttt{Pure} and \texttt{PureTesting} Present coder components was presented. In this project Present decoder was presented. It was attached by shifting registers to RS-232 core developed by Digilent\textsuperscript{\textregistered} to enable communication with PC. Decoding key is firstly generated, basing on the key used for data coding. Next, input data are decoded (taking into account "inverse" direction to the presented in Fig. \ref{pAlgorithm}), and at last feeds the output. This core works with 80 bit key. Target was Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E \cite{Spartan} on Spartan 3E Starter Board \cite{Digilent} made by Digilent\textsuperscript{\textregistered}.
In subprojects \texttt{Pure} and \texttt{PureTesting} Present encoder components was presented. In this project Present decoder was presented. It was attached by shifting registers to RS-232 core developed by Digilent\textsuperscript{\textregistered} to enable communication with PC. Decoding key is firstly generated, basing on the key used for data coding. Next, input data are decoded (taking into account "inverse" direction to the presented in Fig. \ref{pAlgorithm}), and at last feeds the output. This core works with 80 bit key. Target was Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E \cite{Spartan} on Spartan 3E Starter Board \cite{Digilent} made by Digilent\textsuperscript{\textregistered}.
 
\newpage
 
\section{Interface}
 
Top level component of Present Decode Testing was shown in Fig. \ref{pdectest}. The number of inputs and outputs was limited due to RS-232 component in communication interface. All inputs and outputs are synchronous except \texttt{reset} signal in state machines and sampled at rising edge of clock. All signals are \texttt{STD\_LOGIC}.
Top level component of Present Decode Testing was shown in Fig. \ref{pdectest}. The number of inputs and outputs was limited due to RS-232 component in communication interface. All inputs and outputs are synchronous except \texttt{reset} signal and sampled at rising edge of the clock. All signals are \texttt{STD\_LOGIC}.
\begin{figure}[!ht]%
\begin{center}
\includegraphics[width=0.5\textwidth]{img/PresentDecodeTesting.png}
\caption{%
Top level component of Present Decode Testing
Top level component of the Present Decode Testing
}%
\label{pdectest}
\end{center}
73,19 → 74,19
 
\begin{tabularx}{\textwidth}{|p{30mm}|p{11mm}|p{11mm}|X|}
\hline \bf{Signal name} & \bf{Width} & \bf{In/Out} & \bf{Description}\\
\hline \texttt{clk} & 1 & in & Clock signal for the component. \\
\hline \texttt{DATA\_RXD} & 1 & in & Input data signal. \\
\hline \texttt{reset} & 1 & in & \emph{Asynchronous} / \emph{Synchronous} reset signal.\\
\hline \texttt{DATA\_TXD} & 1 & out & Output data signal. \\
\hline \texttt{clk} & 1 & in & clock signal for the component. \\
\hline \texttt{DATA\_RXD} & 1 & in & input data signal. \\
\hline \texttt{reset} & 1 & in & \emph{asynchronous} reset signal.\\
\hline \texttt{DATA\_TXD} & 1 & out & output data signal. \\
\hline
\end{tabularx}
\captionof{table}{Input/Output signals of Present Decode Testing component}
\captionof{table}{Input/Output signals of the Present Decode Testing component}
 
\newpage
 
\section{Internal structure and state machine workflow}
 
Internal datapath between components was shown in fig. \ref{pdecinside}. All control signals, \texttt{clk} and \texttt{reset} was omitted for clearance. In these schamatic \texttt{keyReg}, \texttt{textReg} and \texttt{outReg} are shift registers enabling conversion of the input/output serial data into parallel data. They are respectively:
Internal datapath between components was shown in Fig. \ref{pdecinside}. All control signals, \texttt{clk} and \texttt{reset} was omitted for clearance. In these schamatic \texttt{keyReg}, \texttt{textReg} and \texttt{outReg} are shift registers enabling conversion of the input/output serial data into parallel data. They are respectively:
\begin{itemize}
\item \texttt{keyReg} - shift register for the key used during decoding,
\item \texttt{textReg} - shift register for the text to be decoded (to be more clearly \texttt{ciphertext}),
98,19 → 99,19
\begin{center}
\includegraphics[width=0.95\textwidth]{img/PresentDecodeCommInside.png}
\caption{%
Internal structure of Present Decode core with communication environment.
Internal structure of the Present Decode Testing core with communication environment.
}%
\label{pdecinside}
\end{center}
\end{figure}
 
State machine states and transition between them was shown in fig. \ref{presentDecodeCommSM}.
State machine states and transition between them was shown in Fig. \ref{presentDecodeCommSM}.
 
\begin{figure}[!ht]%
\begin{center}
\includegraphics[width=0.95\textwidth]{img/presentDecodeCommSM.png}
\caption{%
State machine of the Present Decode cipher with added communication component
State machine of the Present Decode Testing decipher with added communication component
}%
\label{presentDecodeCommSM}
\end{center}
117,12 → 118,12
\end{figure}
 
 
In fact it is the same State machine as in Present \texttt{Pure Testing} subproject, but due to its length, will be reminded. State machine consist of following states:
In fact it is the same state machine as in \texttt{Present Pure Testing} subproject, but due to its length, will be reminded. State machine consist of following states:
 
\begin{itemize}
\item \texttt{NOP} - this is initial state of the state machine. It is set up after resetting the system. If any data appear in the RS-232 input (\texttt{RDAsig = '1'}), this state will be changed.
\item \texttt{READ\_DATA\_TEXT} / \texttt{READ\_DATA\_KEY} - This state informs the RS-232 component that input data was read (by write enable in \texttt{keyReg} register).
\item \texttt{DECODE\_READ\_TEXT} / \texttt{DECODE\_READ\_KEY}- In this state the number of performed data reading iterations are checked. Because one RS-232 packet was set to 8 bytes - 8 iterations need to be performed for reading full 64 bit text data input (10 iterations for reading full 80 bit key data input).
\item \texttt{NOP} - this is the initial state of the state machine. It is set up after resetting the system. If any data appear in the RS-232 input (\texttt{RDAsig = '1'}), this state will be changed.
\item \texttt{READ\_DATA\_TEXT} / \texttt{READ\_DATA\_KEY} - These states inform the RS-232 component that input data was read (by write enable in \texttt{keyReg} register).
\item \texttt{DECODE\_READ\_TEXT} / \texttt{DECODE\_READ\_KEY}- In these states the number of performed data reading iterations are checked. Because one RS-232 packet was set to 8 bytes - 8 iterations need to be performed for reading full 64 bit text data input (10 iterations for reading full 80 bit key data input).
\item \texttt{TEMP\_STATE} / \texttt{TEMP2\_STATE} / \texttt{TEMP\_OUT} - Here the counter is prepared for key reading / decoding / next "decoding session".
\item \texttt{MOVE\_TEXT} / \texttt{MOVE\_KEY} / - Due to serial data in RS-232 component are stored in 8 bit register, they need to be shifted in appropriate place in given shift registers. It is performed by 8 shifts made in 8 clock cycles.
\item \texttt{NOP\_FOR\_KEY} - Kind of \texttt{NOP} or wait state until 'key' data will arrive.
136,7 → 137,7
 
\section{FPGA implementations}
 
The component has been verified on a Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E FPGA in FG320 package and synthesized with Xilinx ISE 14.2. It was also implemented and practically tested on Spartan 3E Starter Board made by Digilent\textsuperscript{\textregistered}. Appropriate setup files was prepared with use of ISE Project Navigator, but Makefile scripts was also written. Suitable files was stored in \texttt{./DecodeTesting/syn/XC3ES500/} directory.
The component has been verified on a Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E FPGA in FG320 package and synthesized with Xilinx ISE 14.2. It was also implemented and practically tested on Spartan 3E Starter Board made by Digilent\textsuperscript{\textregistered}. Appropriate setup files was prepared with the use of ISE Project Navigator, but Makefile scripts was also written. Suitable files was stored in \texttt{./DecodeTesting/syn/XC3ES500/} directory.
Makefile was tested in Windows 8 with use of Cygwin for 64-bit Windows.
 
Synthesis results was given in Fig. \ref{SynResults}
159,13 → 160,13
Possible change in used FPGA device may be possible in steps given below\footnotemark[1]:
\begin{enumerate}
\item Copy \texttt{./DecodeTesting/syn/XC3ES500/} directory to another one like \\ \texttt{./DecodeTesting/syn/YOUR\_FPGA\_SYMBOL/}
\item Go to \texttt{./DecodeTesting/syn/XC3ES500/} directory.
\item In \texttt{PresentDecodeComm.xst} file modify the line \texttt{-p xc3s500e-5-fg320} to \texttt{-p YOUR\_FPGA\_SYMBOL}
\item In \texttt{Makefile} file modify the line \texttt{PLATFORM=xc3s500e-fg320-5} to \texttt{PLATFORM=YOUR\_FPGA\_SYMBOL}
\item Go to \texttt{./DecodeTesting/syn/YOUR\_FPGA\_SYMBOL/} directory.
\item In \texttt{PresentDecodeComm.xst} file modify the line \texttt{-p xc3s500e-5-fg320} to \texttt{-p YOUR\_FPGA\_CODE}
\item In \texttt{Makefile} file modify the line \texttt{PLATFORM=xc3s500e-fg320-5} to \texttt{PLATFORM=YOUR\_FPGA\_CODE}
\end{enumerate}
 
\textbf{WARNING!!!}
With this core there exist one issue related to communication process. It was observed, that every \textbf{first} decoding process after resetting the core, returns incorrect data. Resending data and performing new calculations fix that. So, using this core it is desirable to force performing first "dummy" calculations after every reset.
With this core there exist one issue related to communication process. It was observed, that every \textbf{first} decoding process after resetting the core, returns incorrect data (not observed during testing in ISE environment). Resending data and performing new calculations fix that. So, using this core it is desirable to force performing first "dummy" calculations after every reset.
 
\footnotetext[1]{This solution was not tested and is based on my own observations. Additional care should be taken with *.UCF files - this supplied with this project should be appropriate only for Spartan 3E Starter Board made by Digilent\textsuperscript{\textregistered}. You can make this modifications on your own risk}
 

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