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bench/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: bench =================================================================== --- bench (nonexistent) +++ bench (revision 4)

bench Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: rtl/vhdl/slayer.vhd =================================================================== --- rtl/vhdl/slayer.vhd (nonexistent) +++ rtl/vhdl/slayer.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer of Present cipher. Simple logic. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: rtl/vhdl/PresentDecodeComm.vhd =================================================================== --- rtl/vhdl/PresentDecodeComm.vhd (nonexistent) +++ rtl/vhdl/PresentDecodeComm.vhd (revision 4) @@ -0,0 +1,273 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level part of 'pure' Present decode with RS-232 ---- +---- communication with PC. It contains all suitable components ---- +---- with links between each others. For more informations see ---- +---- below and http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentDecodeComm is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_64: integer := 64; + w_80: integer := 80 + ); + port ( + DATA_RXD : in STD_LOGIC; + CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + DATA_TXD : out STD_LOGIC + ); +end PresentDecodeComm; + +architecture Behavioral of PresentDecodeComm is + +-- Shift register is used for translation 8 bit input of RS-232 data (both RXD and TXD) +-- 64 bit and 80 bit data in dependence of the data type (key, text, result). SM ocntrols it +-- If data are not fully retrieved, last received data are shifted by 8 bits. This is repeated +-- 8 times for text and output value (8 x 8 bits) or 10 times (10 x 8 bits) for key. +-- Width of the word is fully configurable. +component ShiftReg is + generic ( + length_1 : integer := 8; + length_2 : integer := w_64; + internal_data : integer := w_64 + ); + port ( + input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); + output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end component ShiftReg; + +-- Component given by Digilent in Eval board for RS-232 communication +component Rs232RefComp is + Port ( + TXD : out std_logic := '1'; + RXD : in std_logic; + CLK : in std_logic; --Master Clock + DBIN : in std_logic_vector (7 downto 0); --Data Bus in + DBOUT : out std_logic_vector (7 downto 0); --Data Bus out + RDA : inout std_logic; --Read Data Available + TBE : inout std_logic := '1'; --Transfer Bus Empty + RD : in std_logic; --Read Strobe + WR : in std_logic; --Write Strobe + PE : out std_logic; --Parity Error Flag + FE : out std_logic; --Frame Error Flag + OE : out std_logic; --Overwrite Error Flag + RST : in std_logic := '0'); --Master Reset +end component Rs232RefComp; + +-- Present decoder - nothing special +component PresentFullDecoder is + generic ( + w_64: integer := 64; + w_80: integer := 80 + ); + port( + ciphertext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + plaintext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentFullDecoder; + +-- State machine +component PresentDecodeCommSM is + port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + RDAsig : in STD_LOGIC; + TBEsig : in STD_LOGIC; + RDsig : out STD_LOGIC; + WRsig : out STD_LOGIC; + textDataEn : out STD_LOGIC; + textDataShift : out STD_LOGIC; + keyDataEn : out STD_LOGIC; + keyDataShift : out STD_LOGIC; + ciphDataEn : out STD_LOGIC; + ciphDataShift : out STD_LOGIC; + startSig : out STD_LOGIC; + readySig : in STD_LOGIC + ); +end component PresentDecodeCommSM; + +--Signals +signal keyText : STD_LOGIC_VECTOR(w_80 - 1 downto 0); +signal plaintext : STD_LOGIC_VECTOR(w_64 - 1 downto 0); +signal ciphertext : STD_LOGIC_VECTOR(w_64 - 1 downto 0); + +signal dataTXD : STD_LOGIC_VECTOR(7 downto 0); +signal dataRXD : STD_LOGIC_VECTOR(7 downto 0); +signal RDAsig : STD_LOGIC; +signal TBEsig : STD_LOGIC; +signal RDsig : STD_LOGIC; +signal WRsig : STD_LOGIC; +signal PEsig : STD_LOGIC; +signal FEsig : STD_LOGIC; +signal OEsig : STD_LOGIC; + +signal keyDataEn : STD_LOGIC; +signal keyDataShift : STD_LOGIC; + +signal textDataEn : STD_LOGIC; +signal textDataShift : STD_LOGIC; + +signal ciphDataEn : STD_LOGIC; +signal ciphDataShift : STD_LOGIC; + +signal startSig : STD_LOGIC; +signal readySig : STD_LOGIC; + +begin + + -- Connections + RS232 : Rs232RefComp + Port map( + TXD => DATA_TXD, + RXD => DATA_RXD, + CLK => clk, + DBIN => dataTXD, + DBOUT => dataRXD, + RDA => RDAsig, + TBE => TBEsig, + RD => RDsig, + WR => WRsig, + PE => PEsig, + FE => FEsig, + OE => OEsig, + RST => reset + ); + + textReg : ShiftReg + generic map( + length_1 => 8, + length_2 => w_64, + internal_data => w_64 + ) + port map( + input => dataRXD, + output => plaintext, + en => textDataEn, + shift => textDataShift, + clk => clk, + reset => reset + ); + + keyReg : ShiftReg + generic map( + length_1 => 8, + length_2 => w_80, + internal_data => w_80 + ) + port map( + input => dataRXD, + output => keyText, + en => keyDataEn, + shift => keyDataShift, + clk => clk, + reset => reset + ); + + present :PresentFullDecoder + port map( + ciphertext => plaintext, + key => keyText, + plaintext => ciphertext, + start => startSig, + clk => clk, + reset => reset, + ready => readySig + ); + + outReg : ShiftReg + generic map( + length_1 => w_64, + length_2 => 8, + internal_data => w_64 + ) + port map( + input => ciphertext, + output => dataTXD, + en => ciphDataEn, + shift => ciphDataShift, + clk => clk, + reset => reset + ); + + SM : PresentDecodeCommSM + port map( + clk => clk, + reset => reset, + RDAsig => RDAsig, + TBEsig => TBEsig, + RDsig => RDsig, + WRsig => WRsig, + textDataEn => textDataEn, + textDataShift => textDataShift, + keyDataEn => keyDataEn, + keyDataShift => keyDataShift, + ciphDataEn => ciphDataEn, + ciphDataShift => ciphDataShift, + startSig => startSig, + readySig => readySig + ); + +end Behavioral; + Index: rtl/vhdl/PresentDecodeCommSM.vhd =================================================================== --- rtl/vhdl/PresentDecodeCommSM.vhd (nonexistent) +++ rtl/vhdl/PresentDecodeCommSM.vhd (revision 4) @@ -0,0 +1,426 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine of 'pure' Present decoder with RS-232 ---- +---- communication with PC. Some names can be unclear because of ---- +---- the same type used as in PresentCommSM (in fact the same cycle---- +---- For more informations see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentDecodeCommSM is + port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + RDAsig : in STD_LOGIC; + TBEsig : in STD_LOGIC; + RDsig : out STD_LOGIC; + WRsig : out STD_LOGIC; + textDataEn : out STD_LOGIC; + textDataShift : out STD_LOGIC; + keyDataEn : out STD_LOGIC; + keyDataShift : out STD_LOGIC; + ciphDataEn : out STD_LOGIC; + ciphDataShift : out STD_LOGIC; + startSig : out STD_LOGIC; + readySig : in STD_LOGIC + ); +end PresentDecodeCommSM; + +architecture Behavioral of PresentDecodeCommSM is + +-- counter used for determine number of readed/sended data (key, cipher, result) +component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end component counter; + +-- signals + +signal state : stany_comm := NOP; +signal next_state : stany_comm := NOP; + +-- modify for variable key size +signal serialDataCtrCt : STD_LOGIC; +signal serialDataCtrOut : STD_LOGIC_VECTOR(3 downto 0); +signal serialDataCtrReset : STD_LOGIC; +signal ctrReset : STD_LOGIC; +-- DO NOT MODIFY!!! +signal shiftDataCtrCt : STD_LOGIC; +signal shiftDataCtrOut : STD_LOGIC_VECTOR(2 downto 0); + +begin + ctrReset <= serialDataCtrReset or reset; + SM : process(state, RDAsig, TBEsig, shiftDataCtrOut, serialDataCtrOut, readySig) + begin + case state is + -- No operation - waiting for incoming data + when NOP => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- data has come + if (RDAsig = '1') then + next_state <= READ_DATA_TEXT; + else + next_state <= NOP; + end if; + -- Cipher data enable and read data + when READ_DATA_TEXT => + RDsig <= '1'; + WRsig <= '0'; + textDataEn <= '1'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + -- counter of retrieved bytes + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= DECODE_READ_TEXT; + -- Cipher data readed, stop counter and check if proper number of byte + -- was readed + when DECODE_READ_TEXT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + -- 8 bytes should be readed + if (serialDataCtrOut(3 downto 0) = "1000") then + -- 8 bytes was readed + next_state <= TEMP_STATE; + else + -- 8 bytes was not readed + next_state <= MOVE_TEXT; + end if; + -- Reset counter for next reading + when TEMP_STATE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= NOP_FOR_KEY; + -- Here data are shfted in shift register - another shift counter are used + when MOVE_TEXT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '1'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut(2 downto 0) = "111") then + next_state <= NOP; + else + next_state <= MOVE_TEXT; + end if; + -- "No operation 2" waiting for data - it could be optimized in way, + -- that waiting for key and text could be the same state, but it was + -- intentionally separated. + when NOP_FOR_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- data has come + if (RDAsig = '1') then + next_state <= READ_DATA_KEY; + else + next_state <= NOP_FOR_KEY; + end if; + -- Key data enable and read data + when READ_DATA_KEY => + RDsig <= '1'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '1'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + -- counter of retrieved bytes + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= DECODE_READ_KEY; + -- Data readed, stop counter and check if proper number of byte + -- was readed + when DECODE_READ_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- 10 bytes should be readed + if (serialDataCtrOut(3 downto 0) = "1010") then + -- 10 bytes was readed + next_state <= TEMP2_STATE; + else + -- 10 bytes was not readed + next_state <= MOVE_KEY; + end if; + -- Reset counter for next reading + when TEMP2_STATE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= PRESENT_ENCODE; + -- Here data are shfted in shift register - another shift counter are used + when MOVE_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '1'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut(2 downto 0) = "111") then + next_state <= NOP_FOR_KEY; + else + next_state <= MOVE_KEY; + end if; + -- All suitable data was readed Present encode start + when PRESENT_ENCODE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- change state if Present result ready + if (readySig = '1') then + ciphDataEn <= '1'; + next_state <= WRITE_OUT; + else + ciphDataEn <= '0'; + next_state <= PRESENT_ENCODE; + end if; + -- similar control of writing result as during reading + when WRITE_OUT => + RDsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + if (serialDataCtrOut = "1000") then + WRsig <= '0'; + next_state <= TEMP_OUT; + else + WRsig <= '1'; + next_state <= MOVE_OUT; + end if; + -- all data was sended - start new Present encode cycle + when TEMP_OUT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= NOP; + when MOVE_OUT => + if (TBEsig = '0') then + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= MOVE_OUT; + else + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '1'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut = "111") then + next_state <= WRITE_OUT; + else + next_state <= MOVE_OUT; + end if; + end if; + end case; + end process SM; + + state_modifier : process (clk, reset) + begin + if (clk = '1' and clk'Event) then + if (reset = '1') then + state <= NOP; + else + state <= next_state; + end if; + end if; + end process state_modifier; + + -- counter for controling number of bytes of readed data + dataCounter : counter + generic map( + w_5 => 4 + ) + port map ( + cnt_res => serialDataCtrCt, + num => serialDataCtrOut, + clk => clk, + reset => ctrReset + ); + + -- counter for controling number of shifted bits of readed data + shiftCounter : counter + generic map( + w_5 => 3 + ) + port map ( + cnt_res => shiftDataCtrCt, + num => shiftDataCtrOut, + clk => clk, + reset => reset + ); + +end Behavioral; + Index: rtl/vhdl/keyupd.vhd =================================================================== --- rtl/vhdl/keyupd.vhd (nonexistent) +++ rtl/vhdl/keyupd.vhd (revision 4) @@ -0,0 +1,86 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update module for present cipher it is 'signal ---- +---- mixing' made by rotation left by 61 bits, using one s-box, ---- +---- and output of the counter. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: rtl/vhdl/kody.vhd =================================================================== --- rtl/vhdl/kody.vhd (nonexistent) +++ rtl/vhdl/kody.vhd (revision 4) @@ -0,0 +1,59 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This file contains types and constant used by this ---- +---- implementation of Present project ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, SM_START, SM_READY); + type decode_states is (NOP, KG_START, DEC_START, DEC_READY); + type stany_comm is (NOP, READ_DATA_KEY, DECODE_READ_KEY, MOVE_KEY, TEMP_STATE, TEMP2_STATE, TEMP_OUT, + NOP_FOR_KEY, READ_DATA_TEXT, DECODE_READ_TEXT, MOVE_TEXT, + PRESENT_ENCODE, WRITE_OUT, MOVE_OUT); +end kody; \ No newline at end of file Index: rtl/vhdl/PresentStateMachine.vhd =================================================================== --- rtl/vhdl/PresentStateMachine.vhd (nonexistent) +++ rtl/vhdl/PresentStateMachine.vhd (revision 4) @@ -0,0 +1,130 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present encoder. For more informations ---- +---- see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + ---- Waiting for start + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + RegEn <= '0'; + if (start = '1') then + next_state <= SM_START; + else + next_state <= NOP; + end if; + -- Decoding + when SM_START => + ready <= '0'; + RegEn <= '1'; + cnt_res <= '1'; + if (start = '1') then + -- control during first start + if (num = "00000") then + ctrl_mux <= '0'; + next_state <= SM_START; + -- last iteration + elsif (num = "11111") then + ctrl_mux <= '1'; + next_state <= SM_READY; + -- rest iterations + else + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + -- Decoding end + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: rtl/vhdl/AsyncMux.vhd =================================================================== --- rtl/vhdl/AsyncMux.vhd (nonexistent) +++ rtl/vhdl/AsyncMux.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Simple construction of multiplexer. Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); +end AsyncMux; + +architecture Behavioral of AsyncMux is + +begin + output <= input0 when (ctrl = '0') else + input1; +end Behavioral; + Index: rtl/vhdl/pLayer_inv.vhd =================================================================== --- rtl/vhdl/pLayer_inv.vhd (nonexistent) +++ rtl/vhdl/pLayer_inv.vhd (revision 4) @@ -0,0 +1,125 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Permutation layer of Present decoder. Simple signal ---- +---- mixing, but in inverse way as cipher. For more information see---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer_inv is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer_inv; + +architecture Behavioral of pLayer_inv is +begin + output(0) <= input(0); + output(1) <= input(16); + output(2) <= input(32); + output(3) <= input(48); + output(4) <= input(1); + output(5) <= input(17); + output(6) <= input(33); + output(7) <= input(49); + output(8) <= input(2); + output(9) <= input(18); + output(10) <= input(34); + output(11) <= input(50); + output(12) <= input(3); + output(13) <= input(19); + output(14) <= input(35); + output(15) <= input(51); + output(16) <= input(4); + output(17) <= input(20); + output(18) <= input(36); + output(19) <= input(52); + output(20) <= input(5); + output(21) <= input(21); + output(22) <= input(37); + output(23) <= input(53); + output(24) <= input(6); + output(25) <= input(22); + output(26) <= input(38); + output(27) <= input(54); + output(28) <= input(7); + output(29) <= input(23); + output(30) <= input(39); + output(31) <= input(55); + output(32) <= input(8); + output(33) <= input(24); + output(34) <= input(40); + output(35) <= input(56); + output(36) <= input(9); + output(37) <= input(25); + output(38) <= input(41); + output(39) <= input(57); + output(40) <= input(10); + output(41) <= input(26); + output(42) <= input(42); + output(43) <= input(58); + output(44) <= input(11); + output(45) <= input(27); + output(46) <= input(43); + output(47) <= input(59); + output(48) <= input(12); + output(49) <= input(28); + output(50) <= input(44); + output(51) <= input(60); + output(52) <= input(13); + output(53) <= input(29); + output(54) <= input(45); + output(55) <= input(61); + output(56) <= input(14); + output(57) <= input(30); + output(58) <= input(46); + output(59) <= input(62); + output(60) <= input(15); + output(61) <= input(31); + output(62) <= input(47); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: rtl/vhdl/PresentEncKeyGen.vhd =================================================================== --- rtl/vhdl/PresentEncKeyGen.vhd (nonexistent) +++ rtl/vhdl/PresentEncKeyGen.vhd (revision 4) @@ -0,0 +1,170 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key generator of Present encoder. It is only those part ---- +---- which is needed for key and cipher decoding by Present ---- +---- decoder. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEncKeyGen is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_80: integer := 80 + ); + port( + key : in std_logic_vector(w_80 - 1 downto 0); + key_end : out std_logic_vector(w_80 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEncKeyGen; + +architecture Behavioral of PresentEncKeyGen is + + component Reg is + generic(width : integer := w_80); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 80 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- signals + + signal keynum : std_logic_vector (w_5-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + + -- connections + + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + mixer: keyupd port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + key_end <= keyfout; + ready <= ready_sig; +end Behavioral; Index: rtl/vhdl/slayer_inv.vhd =================================================================== --- rtl/vhdl/slayer_inv.vhd (nonexistent) +++ rtl/vhdl/slayer_inv.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Inverse substitution layer of Present decoder. Simple ---- +---- logic. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer_inv is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer_inv; + +architecture Behavioral of slayer_inv is + + begin + output <= x"0" when input = x"C" else + x"1" when input = x"5" else + x"2" when input = x"6" else + x"3" when input = x"B" else + x"4" when input = x"9" else + x"5" when input = x"0" else + x"6" when input = x"A" else + x"7" when input = x"D" else + x"8" when input = x"3" else + x"9" when input = x"E" else + x"A" when input = x"F" else + x"B" when input = x"8" else + x"C" when input = x"4" else + x"D" when input = x"7" else + x"E" when input = x"1" else + x"F" when input = x"2" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: rtl/vhdl/ShiftReg.vhd =================================================================== --- rtl/vhdl/ShiftReg.vhd (nonexistent) +++ rtl/vhdl/ShiftReg.vhd (revision 4) @@ -0,0 +1,95 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Shift register with parallel input/output. Nothing special---- +---- except configuration - it enables wider input than output and ---- +---- inverse config. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ShiftReg is + generic ( + length_1 : integer := 8; + length_2 : integer := 64; + internal_data : integer := 64 + ); + port ( + input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); + output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end ShiftReg; + +architecture Behavioral of ShiftReg is + +signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0); + +begin + reg : process (clk, reset, data) + begin + if (clk'event and clk = '1') then + if (reset = '1') then + data <= (others => '0'); + elsif (en = '1') then + data(internal_data - 1 downto internal_data - length_1) <= input; + else + if (shift = '1') then + data <= '0' & data(internal_data - 1 downto 1); + end if; + end if; + end if; + output <= data(length_2 - 1 downto 0); + end process reg; + +end Behavioral; + Index: rtl/vhdl/keyupd_inv.vhd =================================================================== --- rtl/vhdl/keyupd_inv.vhd (nonexistent) +++ rtl/vhdl/keyupd_inv.vhd (revision 4) @@ -0,0 +1,88 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Inverse Key update module for present cipher decoding ---- +---- it is 'signal mixing' made by rotation right by 61 bits, ---- +---- using one s-box, and output of the counter. Note, that order ---- +---- of this operatins must be inverse in comparison with key_upd. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd_inv is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd_inv; + +architecture Behavioral of keyupd_inv is + + component slayer_inv is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer_inv port map(input => changin, output => changed); + changin <= key(79 downto 76); + keytemp(79 downto 76)<= changed; + keytemp(75 downto 20) <= key(75 downto 20); + keytemp(19 downto 15)<= key(19 downto 15) xor num; + keytemp(14 downto 0) <= key(14 downto 0); + keyout <= keytemp(60 downto 0) & keytemp(79 downto 61); + end Behavioral; \ No newline at end of file Index: rtl/vhdl/Reg.vhd =================================================================== --- rtl/vhdl/Reg.vhd (nonexistent) +++ rtl/vhdl/Reg.vhd (revision 4) @@ -0,0 +1,83 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Register - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg is + generic(width : integer := 64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end Reg; + +architecture Behavioral of Reg is + +signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); + +begin + clock : process(clk, reset) + begin + if (reset = '1') then + reg <= (others => '0'); + elsif (clk = '1' and clk'Event) then + if (enable = '1') then + reg <= input; + end if; + end if; + end process clock; + output <= reg; +end Behavioral; + Index: rtl/vhdl/PresentDecodeCommImpl.ucf =================================================================== --- rtl/vhdl/PresentDecodeCommImpl.ucf (nonexistent) +++ rtl/vhdl/PresentDecodeCommImpl.ucf (revision 4) @@ -0,0 +1,7 @@ +NET "DATA_RXD" LOC= "R7" | IOSTANDARD= LVTTL | SLEW= FAST ; +NET "DATA_TXD" LOC= "M14" | IOSTANDARD= LVTTL | DRIVE= 8 | SLEW= FAST ; +NET "CLK" LOC= "C9" | IOSTANDARD= LVCMOS33 | SLEW= FAST ; +NET "CLK" TNM_NET = "clk_group"; +TIMESPEC "TS_CLK" = PERIOD "clk_group" 20 ns HIGH 40%; +NET "RESET" LOC= "K17" | IOSTANDARD= LVTTL | PULLDOWN; +SYSTEM_JITTER = 1 ns; \ No newline at end of file Index: rtl/vhdl/counter.vhd =================================================================== --- rtl/vhdl/counter.vhd (nonexistent) +++ rtl/vhdl/counter.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Typical construction of 5bit counter. It is counting up. ---- +---- Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt + 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: rtl/vhdl/PresentDecStateMachine.vhd =================================================================== --- rtl/vhdl/PresentDecStateMachine.vhd (nonexistent) +++ rtl/vhdl/PresentDecStateMachine.vhd (revision 4) @@ -0,0 +1,135 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present decoder. It is only part of ---- +---- "inverse Present", not key gen. For more informations see ---- +---- below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentDecStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentDecStateMachine; + +architecture Behavioral of PresentDecStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + ---- Waiting for start + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + if (start = '1') then + RegEn <= '1'; + next_state <= SM_START; + else + RegEn <= '0'; + next_state <= NOP; + end if; + -- Decoding + when SM_START => + ready <= '0'; + cnt_res <= '1'; + if (start = '1') then + -- control during first start + if (num = "11111") then + RegEn <= '1'; + ctrl_mux <= '1'; + next_state <= SM_START; + -- last iteration + elsif (num = "00000") then + RegEn <= '0'; + ctrl_mux <= '1'; + next_state <= SM_READY; + -- rest iterations + else + RegEn <= '1'; + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + RegEn <= '0'; + ctrl_mux <= '0'; + next_state <= NOP; + end if; + -- Decoding end + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: rtl/vhdl/RS232RefComp.vhd =================================================================== --- rtl/vhdl/RS232RefComp.vhd (nonexistent) +++ rtl/vhdl/RS232RefComp.vhd (revision 4) @@ -0,0 +1,406 @@ +------------------------------------------------------------------------ +-- RS232RefCom.vhd +------------------------------------------------------------------------ +-- Author: Dan Pederson +-- Copyright 2004 Digilent, Inc. +------------------------------------------------------------------------ +-- Description: This file defines a UART which tranfers data from +-- serial form to parallel form and vice versa. +------------------------------------------------------------------------ +-- Revision History: +-- 07/15/04 (Created) DanP +-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant +-- in the Clock Dividing Processes +------------------------------------------------------------------------ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Rs232RefComp is + Port ( + TXD : out std_logic := '1'; + RXD : in std_logic; + CLK : in std_logic; --Master Clock + DBIN : in std_logic_vector (7 downto 0); --Data Bus in + DBOUT : out std_logic_vector (7 downto 0); --Data Bus out + RDA : inout std_logic; --Read Data Available + TBE : inout std_logic := '1'; --Transfer Bus Empty + RD : in std_logic; --Read Strobe + WR : in std_logic; --Write Strobe + PE : out std_logic; --Parity Error Flag + FE : out std_logic; --Frame Error Flag + OE : out std_logic; --Overwrite Error Flag + RST : in std_logic := '0'); --Master Reset +end Rs232RefComp; + +architecture Behavioral of Rs232RefComp is +------------------------------------------------------------------------ +-- Component Declarations +------------------------------------------------------------------------ + +------------------------------------------------------------------------ +-- Local Type Declarations +------------------------------------------------------------------------ + --Receive state machine + type rstate is ( + strIdle, --Idle state + strEightDelay, --Delays for 8 clock cycles + strGetData, --Shifts in the 8 data bits, and checks parity + strCheckStop --Sets framing error flag if Stop bit is wrong + ); + + type tstate is ( + sttIdle, --Idle state + sttTransfer, --Move data into shift register + sttShift --Shift out data + ); + + type TBEstate is ( + stbeIdle, + stbeSetTBE, + stbeWaitLoad, + stbeWaitWrite + ); + + +------------------------------------------------------------------------ +-- Signal Declarations +------------------------------------------------------------------------ + constant baudDivide : std_logic_vector(7 downto 0) := "00001101"; --Baud Rate dividor, set now for a rate of 9600. + --Found by dividing 50MHz by 9600 and 16. + signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register + signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register + signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register + signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register + signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk + signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk + signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times + signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer + signal rClk : std_logic := '0'; --Receiving Clock + signal tClk : std_logic; --Transfering Clock + signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits + signal parError: std_logic; --Parity error bit + signal frameError: std_logic; --Frame error bit + signal CE : std_logic; --Clock enable for the latch + signal ctRst : std_logic := '0'; + signal load : std_logic := '0'; + signal shift : std_logic := '0'; + signal par : std_logic; + signal tClkRST : std_logic := '0'; + signal rShift : std_logic := '0'; + signal dataRST : std_logic := '0'; + signal dataIncr: std_logic := '0'; + + signal strCur : rstate := strIdle; --Current state in the Receive state machine + signal strNext : rstate; --Next state in the Receive state machine + signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine + signal sttNext : tstate; --Next state in the Transfer staet machine + signal stbeCur : TBEstate := stbeIdle; + signal stbeNext: TBEstate; + +------------------------------------------------------------------------ +-- Module Implementation +------------------------------------------------------------------------ + +begin + frameError <= not rdSReg(9); + parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) ); + DBOUT <= rdReg; + tfReg <= DBIN; + par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) ); + +--Clock Dividing Functions-- + + process (CLK, clkDiv) --set up clock divide for rClk + begin + if (Clk = '1' and Clk'event) then + if (clkDiv = baudDivide) then + clkDiv <= "000000000"; + else + clkDiv <= clkDiv +1; + end if; + end if; + end process; + + process (clkDiv, rClk, CLK) --Define rClk + begin + if CLK = '1' and CLK'Event then + if clkDiv = baudDivide then + rClk <= not rClk; + else + rClk <= rClk; + end if; + end if; + end process; + + process (rClk) --set up clock divide for tClk + begin + if (rClk = '1' and rClk'event) then + rClkDiv <= rClkDiv +1; + end if; + end process; + + tClk <= rClkDiv(3); --define tClk + + process (rClk, ctRst) --set up a counter based on rClk + begin + if rClk = '1' and rClk'Event then + if ctRst = '1' then + ctr <= "0000"; + else + ctr <= ctr +1; + end if; + end if; + end process; + + process (tClk, tClkRST) --set up a counter based on tClk + begin + if (tClk = '1' and tClk'event) then + if tClkRST = '1' then + tfCtr <= "0000"; + else + tfCtr <= tfCtr +1; + end if; + end if; + end process; + + --This process controls the error flags-- + process (rClk, RST, RD, CE) + begin + if RD = '1' or RST = '1' then + FE <= '0'; + OE <= '0'; + RDA <= '0'; + PE <= '0'; + elsif rClk = '1' and rClk'event then + if CE = '1' then + FE <= frameError; + OE <= RDA; + RDA <= '1'; + PE <= parError; + rdReg(7 downto 0) <= rdSReg (7 downto 0); + end if; + end if; + end process; + + --This process controls the receiving shift register-- + process (rClk, rShift) + begin + if rClk = '1' and rClk'Event then + if rShift = '1' then + rdSReg <= (RXD & rdSReg(9 downto 1)); + end if; + end if; + end process; + + --This process controls the dataCtr to keep track of shifted values-- + process (rClk, dataRST) + begin + if (rClk = '1' and rClk'event) then + if dataRST = '1' then + dataCtr <= "0000"; + elsif dataIncr = '1' then + dataCtr <= dataCtr +1; + end if; + end if; + end process; + + --Receiving State Machine-- + process (rClk, RST) + begin + if rClk = '1' and rClk'Event then + if RST = '1' then + strCur <= strIdle; + else + strCur <= strNext; + end if; + end if; + end process; + + --This process generates the sequence of steps needed receive the data + + process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA) + begin + case strCur is + + when strIdle => + dataIncr <= '0'; + rShift <= '0'; + dataRst <= '0'; + + CE <= '0'; + if RXD = '0' then + ctRst <= '1'; + strNext <= strEightDelay; + else + ctRst <= '0'; + strNext <= strIdle; + end if; + + when strEightDelay => + dataIncr <= '0'; + rShift <= '0'; + CE <= '0'; + + if ctr(2 downto 0) = "111" then + ctRst <= '1'; + dataRST <= '1'; + strNext <= strGetData; + else + ctRst <= '0'; + dataRST <= '0'; + strNext <= strEightDelay; + end if; + + when strGetData => + CE <= '0'; + dataRst <= '0'; + if ctr(3 downto 0) = "1111" then + ctRst <= '1'; + dataIncr <= '1'; + rShift <= '1'; + else + ctRst <= '0'; + dataIncr <= '0'; + rShift <= '0'; + end if; + + if dataCtr = "1010" then + strNext <= strCheckStop; + else + strNext <= strGetData; + end if; + + when strCheckStop => + dataIncr <= '0'; + rShift <= '0'; + dataRst <= '0'; + ctRst <= '0'; + + CE <= '1'; + strNext <= strIdle; + + end case; + + end process; + + --TBE State Machine-- + process (CLK, RST) + begin + if CLK = '1' and CLK'Event then + if RST = '1' then + stbeCur <= stbeIdle; + else + stbeCur <= stbeNext; + end if; + end if; + end process; + + --This process gererates the sequence of events needed to control the TBE flag-- + process (stbeCur, CLK, WR, DBIN, load) + begin + + case stbeCur is + + when stbeIdle => + TBE <= '1'; + if WR = '1' then + stbeNext <= stbeSetTBE; + else + stbeNext <= stbeIdle; + end if; + + when stbeSetTBE => + TBE <= '0'; + if load = '1' then + stbeNext <= stbeWaitLoad; + else + stbeNext <= stbeSetTBE; + end if; + + when stbeWaitLoad => + if load = '0' then + stbeNext <= stbeWaitWrite; + else + stbeNext <= stbeWaitLoad; + end if; + + when stbeWaitWrite => + if WR = '0' then + stbeNext <= stbeIdle; + else + stbeNext <= stbeWaitWrite; + end if; + end case; + end process; + + --This process loads and shifts out the transfer shift register-- + process (load, shift, tClk, tfSReg) + begin + TXD <= tfsReg(0); + if tClk = '1' and tClk'Event then + if load = '1' then + tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0'); + end if; + if shift = '1' then + + tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1)); + end if; + end if; + end process; + + -- Transfer State Machine-- + process (tClk, RST) + begin + if (tClk = '1' and tClk'Event) then + if RST = '1' then + sttCur <= sttIdle; + else + sttCur <= sttNext; + end if; + end if; + end process; + + -- This process generates the sequence of steps needed transfer the data-- + process (sttCur, tfCtr, tfReg, TBE, tclk) + begin + + case sttCur is + + when sttIdle => + tClkRST <= '0'; + shift <= '0'; + load <= '0'; + if TBE = '1' then + sttNext <= sttIdle; + else + sttNext <= sttTransfer; + end if; + + when sttTransfer => + shift <= '0'; + load <= '1'; + tClkRST <= '1'; + sttNext <= sttShift; + + + when sttShift => + shift <= '1'; + load <= '0'; + tClkRST <= '0'; + if tfCtr = "1100" then + sttNext <= sttIdle; + else + sttNext <= sttShift; + end if; + end case; + end process; + +end Behavioral; \ No newline at end of file Index: rtl/vhdl/FullDecoderSM.vhd =================================================================== --- rtl/vhdl/FullDecoderSM.vhd (nonexistent) +++ rtl/vhdl/FullDecoderSM.vhd (revision 4) @@ -0,0 +1,134 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present decoder. It controls entire ---- +---- environment for decoding. We can feature 2 'steady states' ---- +---- and 2 'running states'. For more informations see below ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FullDecoderSM is + port( + key_gen_start : out std_logic; + key_gen_ready : in std_logic; + decode_start : out std_logic; + decode_ready : in std_logic; + full_decoder_start :in std_logic; + full_decoder_ready : out std_logic; + clk, reset :in std_logic + ); +end FullDecoderSM; + +architecture Behavioral of FullDecoderSM is + + signal state : decode_states; + signal next_state : decode_states; + +begin + + states : process(state, full_decoder_start, key_gen_ready, decode_ready) + begin + case state is + ---- It is No operation - waiting for proper data in the input ---- + when NOP => + key_gen_start <= '0'; + decode_start <= '0'; + full_decoder_ready <= '0'; + if (full_decoder_start = '1') then + next_state <= KG_START; + else + next_state <= NOP; + end if; + ---- It is running key generator for decoding + when KG_START => + key_gen_start <= '1'; + decode_start <= '0'; + full_decoder_ready <= '0'; + if (key_gen_ready = '1') then + next_state <= DEC_START; + else + next_state <= KG_START; + end if; + ---- enerated key for decoding is ready. Now we are decoding ---- + when DEC_START => + key_gen_start <= '1'; + decode_start <= '1'; + full_decoder_ready <= '0'; + if (decode_ready = '1') then + next_state <= DEC_READY; + else + next_state <= DEC_START; + end if; + ---- Decoding was ended. Waiting for user retrieving data ---- + ---- and give information about new operation ---- + when DEC_READY => + key_gen_start <= '1'; + decode_start <= '1'; + full_decoder_ready <= '1'; + if (full_decoder_start = '1') then + next_state <= DEC_READY; + else + next_state <= NOP; + end if; + end case; + end process states; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + +end Behavioral; + Index: rtl/vhdl/PresentFullDecoder.vhd =================================================================== --- rtl/vhdl/PresentFullDecoder.vhd (nonexistent) +++ rtl/vhdl/PresentFullDecoder.vhd (revision 4) @@ -0,0 +1,170 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Present decoder with suitable key generator for decoding ---- +---- (basing on given encode key). ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentFullDecoder is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + ciphertext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + plaintext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentFullDecoder; + +architecture Behavioral of PresentFullDecoder is + +-- Key generator component +component PresentEncKeyGen is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_80: integer := 80 + ); + port( + key : in std_logic_vector(w_80 - 1 downto 0); + key_end : out std_logic_vector(w_80 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentEncKeyGen; + +-- 'pure' Present decoder +component PresentDec is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentDec; + +component FullDecoderSM is + port( + key_gen_start : out std_logic; + key_gen_ready : in std_logic; + decode_start : out std_logic; + decode_ready : in std_logic; + full_decoder_start :in std_logic; + full_decoder_ready : out std_logic; + clk, reset :in std_logic + ); +end component FullDecoderSM; + +-- signals + +signal key_gen_output : std_logic_vector(w_80 - 1 downto 0); + +signal key_gen_start : std_logic; +signal key_gen_ready : std_logic; + +signal decode_start : std_logic; +signal decode_ready : std_logic; + +begin + + -- connections + + keyGen : PresentEncKeyGen + port map( + key => key, + key_end => key_gen_output, + start => key_gen_start, + clk => clk, + reset => reset, + ready => key_gen_ready + ); + + decoder : PresentDec + port map( + plaintext => ciphertext, + key => key_gen_output, + ciphertext => plaintext, + start => decode_start, + clk => clk, + reset => reset, + ready => decode_ready + ); + + SM : FullDecoderSM + port map( + key_gen_start => key_gen_start, + key_gen_ready => key_gen_ready, + decode_start => decode_start, + decode_ready => decode_ready, + full_decoder_start => start, + full_decoder_ready => ready, + clk => clk, + reset => reset + ); + +end Behavioral; Index: rtl/vhdl/counter_inv.vhd =================================================================== --- rtl/vhdl/counter_inv.vhd (nonexistent) +++ rtl/vhdl/counter_inv.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Typical construction of 5bit counter. It is counting ---- +---- down. Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter_inv is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter_inv; + +architecture Behavioral of counter_inv is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '1'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt - 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: rtl/vhdl/PresentDec.vhd =================================================================== --- rtl/vhdl/PresentDec.vhd (nonexistent) +++ rtl/vhdl/PresentDec.vhd (revision 4) @@ -0,0 +1,220 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level of present decoder. It contains 'Key generator' ---- +---- from encoder and 'inverse Present' for decoding the cipher. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentDec is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentDec; + +architecture Behavioral of PresentDec is + + component Reg is + generic(width : integer := w_64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentDecStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- INVERSE substitution layer for decoding + component slayer_inv is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + -- INVERSE permutation layer for decoding + component pLayer_inv is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + -- INVERSE key update for decoding + component keyupd_inv is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + -- INVERSE counter for decoding. It is counting down!!! + component counter_inv is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- signals + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + + -- connections + mux_64: AsyncMux generic map(width => w_64) port map( + input0 => plaintext, + input1 => Pout, + ctrl => mux_ctrl, + output => textToReg + ); + regText : Reg generic map(width => w_64) port map( + input => textToReg, + output => toXor, + enable => RegEn, + clk => clk, + reset => reset + ); + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + slayers_inv : for N in 15 downto 0 generate + s_x: slayer_inv port map( + input => P(4*N+3 downto 4*N), + output => Pout(4*N+3 downto 4*N) + ); + end generate slayers_inv; + p1: pLayer_inv port map( + input => ciph, + output => P + ); + mixer: keyupd_inv port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentDecStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter_inv port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + ciph <= toXor xor keyfout(79 downto 16); + ciphertext <= ciph; + ready <= ready_sig; +end Behavioral; Index: rtl/vhdl =================================================================== --- rtl/vhdl (nonexistent) +++ rtl/vhdl (revision 4)

rtl/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: rtl =================================================================== --- rtl (nonexistent) +++ rtl (revision 4)

rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: doc/src =================================================================== --- doc/src (nonexistent) +++ doc/src (revision 4)

doc/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: doc =================================================================== --- doc (nonexistent) +++ doc (revision 4)

doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sim =================================================================== --- sim (nonexistent) +++ sim (revision 4)

sim Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/rxtxSerial.dll =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sw/JavaTests/PresentCommTesting/rxtxSerial.dll =================================================================== --- sw/JavaTests/PresentCommTesting/rxtxSerial.dll (nonexistent) +++ sw/JavaTests/PresentCommTesting/rxtxSerial.dll (revision 4)

sw/JavaTests/PresentCommTesting/rxtxSerial.dll Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/.classpath =================================================================== --- sw/JavaTests/PresentCommTesting/.classpath (nonexistent) +++ sw/JavaTests/PresentCommTesting/.classpath (revision 4) @@ -0,0 +1,9 @@ + + + + + + + + + Index: sw/JavaTests/PresentCommTesting/.project =================================================================== --- sw/JavaTests/PresentCommTesting/.project (nonexistent) +++ sw/JavaTests/PresentCommTesting/.project (revision 4) @@ -0,0 +1,17 @@ + + + PresentCommTesting + + + + + + org.eclipse.jdt.core.javabuilder + + + + + + org.eclipse.jdt.core.javanature + + Index: sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar =================================================================== --- sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar (nonexistent) +++ sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar (revision 4)

sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar =================================================================== --- sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar (nonexistent) +++ sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar (revision 4)

sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/lib =================================================================== --- sw/JavaTests/PresentCommTesting/lib (nonexistent) +++ sw/JavaTests/PresentCommTesting/lib (revision 4)

sw/JavaTests/PresentCommTesting/lib Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java =================================================================== --- sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java (nonexistent) +++ sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java (revision 4) @@ -0,0 +1,90 @@ +package pl.com.kgajewski.serialcomm.datagen; +import java.io.BufferedWriter; +import java.io.File; +import java.io.FileWriter; +import java.io.IOException; + +import org.apache.commons.lang3.StringUtils; + + +public class PresentDataGenerator { + public static void main(String[] args) { + String drive = "e:\\"; + String data = "a112ffc72f68417b"; + String key = "00000000000000000000"; + + String data2 = "3333dcd3213210d2"; + String key2 = "ffffffffffffffffffff"; + + try { + System.out.println("key"); + File f1 = new File(drive + "key.txt"); + f1.createNewFile(); + formatDataFromHex(key, f1); + + System.out.println("data"); + File f2 = new File(drive + "data.txt"); + f1.createNewFile(); + formatDataFromHex(data, f2); + + System.out.println("key2"); + File f3 = new File(drive + "key2.txt"); + f3.createNewFile(); + formatDataFromHex(key2, f3); + + System.out.println("data2"); + File f4 = new File(drive + "data2.txt"); + f4.createNewFile(); + formatDataFromHex(data2, f4); + + } catch (IOException e1) { + // TODO Auto-generated catch block + e1.printStackTrace(); + } + + } + + private static void formatDataFromHex(String str, File f) throws IOException { + BufferedWriter bfw = new BufferedWriter(new FileWriter(f)); + for (int i = str.length(); i > 0; i -= 2) { + String substr = str.substring(i - 2, i); + + parseByteStringHex(bfw, substr); + } + bfw.close(); + } + + private static void parseByteStringHex(BufferedWriter bfw, String str) + throws IOException { + Integer i = Integer.valueOf(str, 16); + String s = Integer.toString(i, 2); + String tmp = ""; + for (int j = 8 - s.length(); j > 0; j--) { + tmp = tmp.concat("0"); + } + parseByteString(bfw, tmp + s); + } + + private static void parseByteString(BufferedWriter bfw, String str) + throws IOException { + int ones = 0; + bfw.write(str); + bfw.write("\n"); + str = StringUtils.reverse(str); + + for (int j = 0; j < str.length(); j++) { + bfw.write(str.charAt(j)); + bfw.write("\n"); + if (str.charAt(j) == '1') { + ones++; + } + } + if (ones % 2 == 1) { + bfw.write("0"); + } else { + bfw.write("1"); + } + bfw.write("\n"); + } + +} Index: sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen =================================================================== --- sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen (nonexistent) +++ sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen (revision 4)

sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java =================================================================== --- sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java (nonexistent) +++ sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java (revision 4) @@ -0,0 +1,261 @@ +package pl.com.kgajewski.serialcomm.gui; + +import gnu.io.CommPort; +import gnu.io.CommPortIdentifier; +import gnu.io.PortInUseException; +import gnu.io.SerialPort; +import gnu.io.SerialPortEvent; +import gnu.io.SerialPortEventListener; + +import java.io.IOException; +import java.io.InputStream; +import java.io.OutputStream; +import java.math.BigInteger; +import java.util.Enumeration; +import java.util.HashMap; +import java.util.TooManyListenersException; + +import org.apache.commons.lang3.ArrayUtils; +import org.apache.commons.lang3.StringUtils; +import org.eclipse.swt.graphics.Color; + +public class Communication implements SerialPortEventListener { + + //passed from main GUI + Window window = null; + + // just a boolean flag that i use for enabling + // and disabling buttons depending on whether the program + // is connected to a serial port or not + private boolean bConnected = false; + + // the timeout value for connecting with the port + final static int TIMEOUT = 2000; + + // for containing the ports that will be found + private Enumeration ports = null; + // map the port names to CommPortIdentifiers + private HashMap portMap = new HashMap(); + + // this is the object that contains the opened port + private CommPortIdentifier selectedPortIdentifier = null; + private SerialPort serialPort = null; + + // input and output streams for sending and receiving data + private InputStream input = null; + private OutputStream output = null; + + public Communication(Window window) { + this.window = window; + } + + // a string for recording what goes on in the program + // this string is written to the GUI + String logText = ""; + + // search for all the serial ports + // pre style="font-size: 11px;": none + // post: adds all the found ports to a combo box on the GUI + public void searchForPorts() { + ports = CommPortIdentifier.getPortIdentifiers(); + + while (ports.hasMoreElements()) { + CommPortIdentifier curPort = (CommPortIdentifier) ports + .nextElement(); + + // get only serial ports + if (curPort.getPortType() == CommPortIdentifier.PORT_SERIAL) { + window.combo.add(curPort.getName()); + portMap.put(curPort.getName(), curPort); + } + } + } + + // connect to the selected port in the combo box + // pre style="font-size: 11px;": ports are already found by using the + // searchForPorts + // method + // post: the connected comm port is stored in commPort, otherwise, + // an exception is generated + public void connect() { + if (window.combo.getSelectionIndex() >= 0) { + String selectedPort = (String) window.combo.getItem(window.combo.getSelectionIndex()); + selectedPortIdentifier = (CommPortIdentifier) portMap + .get(selectedPort); + + CommPort commPort = null; + + try { + // the method below returns an object of type CommPort + commPort = selectedPortIdentifier.open("pl.com.kgajewski.cerialcomm", + TIMEOUT); + // the CommPort object can be casted to a SerialPort object + serialPort = (SerialPort) commPort; + serialPort.setSerialPortParams(115200,SerialPort.DATABITS_8,SerialPort.STOPBITS_1,SerialPort.PARITY_ODD); + + // for controlling GUI elements + setConnected(true); + + // logging + logText = selectedPort + " opened successfully."; + window.text.setForeground(new Color(window.shell.getDisplay(), 0, 0, 0)); + window.appendText(logText + "\n"); + + // CODE ON SETTING BAUD RATE ETC OMITTED + // XBEE PAIR ASSUMED TO HAVE SAME SETTINGS ALREADY + + // enables the controls on the GUI if a successful connection is + // made + window.toggleControls(); + + } catch (PortInUseException e) { + logText = selectedPort + " is in use. (" + e.toString() + ")"; + + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } catch (Exception e) { + logText = "Failed to open " + selectedPort + "(" + e.toString() + + ")"; + window.appendText(logText + "\n"); + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + } + } + } + // open the input and output streams + // pre style="font-size: 11px;": an open port + // post: initialized input and output streams for use to communicate data + public boolean initIOStream() { + // return value for whether opening the streams is successful or not + boolean successful = false; + + try { + // + input = serialPort.getInputStream(); + output = serialPort.getOutputStream(); + + successful = true; + return successful; + } catch (IOException e) { + logText = "I/O Streams failed to open. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + return successful; + } + } + + // starts the event listener that knows whenever data is available to be + // read + // pre style="font-size: 11px;": an open serial port + // post: an event listener for the serial port that knows when data is + // received + public void initListener() { + try { + serialPort.addEventListener(this); + serialPort.notifyOnDataAvailable(true); + } catch (TooManyListenersException e) { + logText = "Too many listeners. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + //disconnect the serial port + //pre style="font-size: 11px;": an open serial port + //post: closed serial port + public void disconnect() + { + //close the serial port + try + { + serialPort.removeEventListener(); + serialPort.close(); + input.close(); + output.close(); + setConnected(false); + window.toggleControls(); + + logText = "Disconnected."; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + catch (Exception e) + { + logText = "Failed to close " + serialPort.getName() + + "(" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + //what happens when data is received + //pre style="font-size: 11px;": serial event is triggered + //post: processing on the data it reads + public void serialEvent(SerialPortEvent evt) { + if (evt.getEventType() == SerialPortEvent.DATA_AVAILABLE) + { + try + { + byte [] buffer = new byte[10]; + int n = input.read(buffer); + if (n > 0) + { + if (n == 1) { + BigInteger command = new BigInteger(new byte []{0, buffer[0]}); + final String s = "Command = " + command.toString(16) + "\n"; + window.appendText(s); + } else { + buffer = ArrayUtils.subarray(buffer, 0, buffer.length - 2); + buffer = ArrayUtils.add(buffer, (byte)0); + ArrayUtils.reverse(buffer); + BigInteger data = new BigInteger(buffer); + window.appendText(data.toString(16) + "\n"); + } + } + else + { + window.appendText("\n"); + } + } + catch (Exception e) + { + logText = "Failed to read data. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + } + + //method that can be called to send data + //pre style="font-size: 11px;": open serial port + //post: data sent to the other device + public void writeData(String str) + { + try + { + for (int i = str.length()-1; i > 0; i -= 2) { + String s = str.substring(i-1, i+1); + byte b = (byte)(Integer.parseInt(s, 16) & 0xFF); + output.write(b); + Thread.sleep(1); + } + } + catch (Exception e) + { + logText = "Failed to write data. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + final public boolean getConnected() + { + return bConnected; + } + + public void setConnected(boolean bConnected) + { + this.bConnected = bConnected; + } + + +} Index: sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java =================================================================== --- sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java (nonexistent) +++ sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java (revision 4) @@ -0,0 +1,159 @@ +package pl.com.kgajewski.serialcomm.gui; + +import org.eclipse.swt.SWT; +import org.eclipse.swt.events.MouseAdapter; +import org.eclipse.swt.events.MouseEvent; +import org.eclipse.swt.widgets.Button; +import org.eclipse.swt.widgets.Combo; +import org.eclipse.swt.widgets.Composite; +import org.eclipse.swt.widgets.Display; +import org.eclipse.swt.widgets.Label; +import org.eclipse.swt.widgets.Shell; +import org.eclipse.swt.widgets.Text; + +public class Window { + + //Communicator object + Communication communication = null; + public Display display; + protected Shell shell; + public Text text; + private Text data; + private Text key; + public Combo combo; + private Button btnConnect; + private Button btnDisconnect; + private Button btnSendData; + + public void toggleControls() + { + if (communication.getConnected() == true) + { + btnDisconnect.setEnabled(true); + btnConnect.setEnabled(false); + btnSendData.setEnabled(true); + } + else + { + btnDisconnect.setEnabled(false); + btnConnect.setEnabled(true); + btnSendData.setEnabled(false); + } + } + + /** + * Launch the application. + * + * @param args + */ + public static void main(String[] args) { + try { + Window window = new Window(); + window.open(); + } catch (Exception e) { + e.printStackTrace(); + } + } + + /** + * Open the window. + */ + public void open() { + display = Display.getDefault(); + createContents(); + communication = new Communication(this); + communication.searchForPorts(); + toggleControls(); + shell.open(); + shell.layout(); + while (!shell.isDisposed()) { + if (!display.readAndDispatch()) { + display.sleep(); + } + } + } + + /** + * Create contents of the window. + */ + protected void createContents() { + shell = new Shell(); + shell.setSize(470, 274); + shell.setText("SWT Application"); + shell.setLayout(null); + + Composite composite = new Composite(shell, SWT.NONE); + composite.setBounds(0, 0, 444, 236); + + text = new Text(composite, SWT.BORDER | SWT.MULTI); + this.text.setBounds(107, 126, 327, 105); + + combo = new Combo(composite, SWT.NONE); + combo.setBounds(10, 10, 91, 23); + + btnConnect = new Button(composite, SWT.NONE); + btnConnect.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.connect(); + if (communication.getConnected() == true) + { + if (communication.initIOStream() == true) + { + communication.initListener(); + } + } + } + }); + btnConnect.setBounds(107, 10, 75, 25); + btnConnect.setText("Connect"); + + btnDisconnect = new Button(composite, SWT.NONE); + btnDisconnect.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.disconnect(); + } + }); + btnDisconnect.setBounds(188, 10, 75, 25); + btnDisconnect.setText("Disconnect"); + + Label lblLog = new Label(composite, SWT.NONE); + lblLog.setBounds(107, 105, 186, 15); + lblLog.setText("Log"); + + data = new Text(composite, SWT.BORDER); + data.setBounds(45, 39, 248, 21); + + key = new Text(composite, SWT.BORDER); + key.setBounds(45, 66, 248, 21); + + btnSendData = new Button(composite, SWT.NONE); + btnSendData.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.writeData(data.getText()); + communication.writeData(key.getText()); + } + }); + btnSendData.setBounds(10, 100, 75, 25); + btnSendData.setText("Send"); + + Label lblData = new Label(composite, SWT.NONE); + lblData.setBounds(10, 39, 29, 15); + lblData.setText("Data"); + + Label lblKey = new Label(composite, SWT.NONE); + lblKey.setBounds(10, 66, 55, 15); + lblKey.setText("Key"); + } + + public void appendText(final String s) { + display.syncExec(new Runnable() { + public void run() { + text.append(s); + } + }); + + } +} Index: sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui =================================================================== --- sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui (nonexistent) +++ sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui (revision 4)

sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm =================================================================== --- sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm (nonexistent) +++ sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm (revision 4)

sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski =================================================================== --- sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski (nonexistent) +++ sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski (revision 4)

sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/src/pl/com =================================================================== --- sw/JavaTests/PresentCommTesting/src/pl/com (nonexistent) +++ sw/JavaTests/PresentCommTesting/src/pl/com (revision 4)

sw/JavaTests/PresentCommTesting/src/pl/com Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/src/pl =================================================================== --- sw/JavaTests/PresentCommTesting/src/pl (nonexistent) +++ sw/JavaTests/PresentCommTesting/src/pl (revision 4)

sw/JavaTests/PresentCommTesting/src/pl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/src =================================================================== --- sw/JavaTests/PresentCommTesting/src (nonexistent) +++ sw/JavaTests/PresentCommTesting/src (revision 4)

sw/JavaTests/PresentCommTesting/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/bin =================================================================== --- sw/JavaTests/PresentCommTesting/bin (nonexistent) +++ sw/JavaTests/PresentCommTesting/bin (revision 4)

sw/JavaTests/PresentCommTesting/bin Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/rxtxParallel.dll =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sw/JavaTests/PresentCommTesting/rxtxParallel.dll =================================================================== --- sw/JavaTests/PresentCommTesting/rxtxParallel.dll (nonexistent) +++ sw/JavaTests/PresentCommTesting/rxtxParallel.dll (revision 4)

sw/JavaTests/PresentCommTesting/rxtxParallel.dll Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sw/JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs =================================================================== --- sw/JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs (nonexistent) +++ sw/JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs (revision 4) @@ -0,0 +1,11 @@ +eclipse.preferences.version=1 +org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled +org.eclipse.jdt.core.compiler.codegen.targetPlatform=1.6 +org.eclipse.jdt.core.compiler.codegen.unusedLocal=preserve +org.eclipse.jdt.core.compiler.compliance=1.6 +org.eclipse.jdt.core.compiler.debug.lineNumber=generate +org.eclipse.jdt.core.compiler.debug.localVariable=generate +org.eclipse.jdt.core.compiler.debug.sourceFile=generate +org.eclipse.jdt.core.compiler.problem.assertIdentifier=error +org.eclipse.jdt.core.compiler.problem.enumIdentifier=error +org.eclipse.jdt.core.compiler.source=1.6 Index: sw/JavaTests/PresentCommTesting/.settings =================================================================== --- sw/JavaTests/PresentCommTesting/.settings (nonexistent) +++ sw/JavaTests/PresentCommTesting/.settings (revision 4)

sw/JavaTests/PresentCommTesting/.settings Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests/PresentCommTesting =================================================================== --- sw/JavaTests/PresentCommTesting (nonexistent) +++ sw/JavaTests/PresentCommTesting (revision 4)

sw/JavaTests/PresentCommTesting Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw/JavaTests =================================================================== --- sw/JavaTests (nonexistent) +++ sw/JavaTests (revision 4)

sw/JavaTests Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: sw =================================================================== --- sw (nonexistent) +++ sw (revision 4)

sw Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: syn/XC3ES500 =================================================================== --- syn/XC3ES500 (nonexistent) +++ syn/XC3ES500 (revision 4)

syn/XC3ES500 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: syn =================================================================== --- syn (nonexistent) +++ syn (revision 4)

syn Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property