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/doc/present_pure.pdf
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/doc/src/present_pure.tex
7,7 → 7,7
%%%%%%%%%%%%%%%%% |
\docDate{ \today } |
\docID{Present cipher} |
\docRevision{0.1} |
\docRevision{0.2} |
\docStatus{Draft} |
\docTitle{\mbox{Present Cipher}} |
\authorName{\mbox{Krzysztof Gajewski} \\ and opencores.org} |
17,6 → 17,7
|
\revisionList{ |
0.1 & all & 2014/02/01 & First draft & K. Gajewski \\ |
0.2 & all & 2014/09/16 & Some small corrections with the text, typos, etc. & K. Gajewski \\ |
} |
|
\begin{document} |
38,11 → 39,11
This cipher consists of 32 rounds, during which: |
\begin{itemize} |
\item round key is added to plaintext |
\item plaintext goues through sBoxes (substitution boxes) |
\item plaintext goes through sBoxes (substitution boxes) |
\item plaintext after sBoxes goes through pLayer (permutation layer) |
\item round key is updated |
\end{itemize} |
After that, ciphertext feeds out the output. Briefly algorithm was shown in Fig. \ref{pAlgorithm} |
After that, ciphertext feeds out the output. Briefly algorithm was shown in Fig. \ref{pAlgorithm}. |
\begin{figure}[!ht]% |
\begin{center} |
\includegraphics[width=0.66\textwidth]{img/presentAlgorithm.png} |
58,12 → 59,12
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\section{Interface} |
|
Top level component of present was shown in Fig. \ref{penc}. All inputs and outputs are synchronous except \texttt{reset} signal and sampled at rising edge of the clock. Type for all signals is \texttt{STD\_LOGIC} or \texttt{STD\_LOGIC\_VECTOR}. |
Top level component of the Present encoder was shown in Fig. \ref{penc}. All inputs and outputs are synchronous except \texttt{reset} signal and sampled at rising edge of the clock. Type for all signals is \texttt{STD\_LOGIC} or \texttt{STD\_LOGIC\_VECTOR}. |
\begin{figure}[!ht]% |
\begin{center} |
\includegraphics[width=0.5\textwidth]{img/PresentEnc.png} |
\caption{% |
Top level component of Present component |
Top level component of the Present encoder |
}% |
\label{penc} |
\end{center} |
74,19 → 75,19
\hline \texttt{key} & 80 & in & secret key used for input data encoding. \\ |
\hline \texttt{plaintext} & 64 & in & input data which have to be encoded. \\ |
\hline \texttt{clk} & 1 & in & clock signal for the component\\ |
\hline \texttt{reset} & 1 & in & \emph{Asynchronous} reset signal. \\ |
\hline \texttt{reset} & 1 & in & \emph{asynchronous} reset signal. \\ |
\hline \texttt{start} & 1 & in & signal which starts encoding process. \\ |
\hline \texttt{ciphertext} & 64 & out & encoded text output. \\ |
\hline \texttt{ready} & 1 & out & signal informing about end of encoding process. \newline "0" - wait until end of data encoding. \newline "1" - data at the \texttt{ciphertext} output are valid, you can read them. \\ |
\hline |
\end{tabularx} |
\captionof{table}{Input/Output signals of Present component} |
\captionof{table}{Input/Output signals of the Present encoder } |
|
\newpage |
|
\section{State machine workflow} |
|
Overall internal structure of Present component is similar to the structure shown in \cite{PRESENT}. Suitable control logic was added in state machine added |
Overall internal structure of the Present component is similar to the structure shown in \cite{PRESENT}. Suitable control logic was added in state machine added |
to the core. It was shown in Fig. \ref{presentSM}. |
|
\begin{figure}[!ht]% |
101,15 → 102,15
|
State machine consist of three states \texttt{NOP}, \texttt{SM\_START} and \texttt{READY}. Some control signal of used multiplexers, registers and counter was omitted. \texttt{NOP} is default state after resetting the core. This state is active as long as \texttt{START} = '0'. |
|
When \texttt{START} = '1' encoding process starts. Proper \texttt{key} and \texttt{plaintext} must fed the input before start encoding. \texttt{SM\_START} state is active as long as \texttt{START} = '1'. Change of this signal to '0' automatically stops encoding process. |
When \texttt{START} = '1' encoding process starts. Proper \texttt{key} and \texttt{plaintext} must feed the input before start encoding. \texttt{SM\_START} state is active as long as \texttt{START} = '1'. Change of this signal to '0' automatically stops encoding process. |
|
After 32 clock cycles (counter reach \texttt{'11111'} value), when encoding process is ended, state machine automatically change its state to \texttt{READY}. This informs user by setting \texttt{READY} output to '1'. Then \texttt{ciphertext} output contains proper data, which can be readed by user. This state are active as long as \texttt{START} = '1'. Change this signal to '0', change state machine to \texttt{NOP} state. Core is ready for next data encoding. |
After 32 clock cycles (counter reach \texttt{'11111'} value), when the encoding process is ends, state machine automatically change its state to \texttt{READY}. This informs user by setting \texttt{READY} output to '1'. Then \texttt{ciphertext} output contains proper data, which can be read by user. This state is active as long as \texttt{START} = '1'. Change this signal to '0', turns the state machine to \texttt{NOP} state. Core is ready for the next data encoding. |
|
\newpage |
|
\section{FPGA implementations} |
|
The component has only been verified on a Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E FPGA in FG320 package and synthesized with Xilinx ISE 14.2. Appropriate setup files was prepared with use of ISE Project Navigator, but Makefile scripts was also written. Suitable files was stored in \texttt{./Pure/syn/XC3ES500/} directory. |
The component has only been verified on a Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E FPGA in FG320 package and synthesized with Xilinx ISE 14.2. Appropriate setup files was prepared with the use of ISE Project Navigator, but Makefile scripts was also written. Suitable files was stored in \texttt{./Pure/syn/XC3ES500/} directory. |
Implementation in FPGA device was done in another subproject called \texttt{PureTesting}. |
Makefile was tested in Windows 8 with use of Cygwin for 64-bit Windows. |
|
133,12 → 134,12
Possible change in used FPGA device may be possible in steps given below\footnotemark[1]: |
\begin{enumerate} |
\item Copy \texttt{./Pure/syn/XC3ES500/} directory to another one like \texttt{./Pure/syn/YOUR\_FPGA\_SYMBOL/} |
\item Go to \texttt{./Pure/syn/XC3ES500/} directory. |
\item In \texttt{PresentEnc.xst} file modify the line \texttt{-p xc3s500e-5-fg320} to \texttt{-p YOUR\_FPGA\_SYMBOL} |
\item In \texttt{Makefile} file modify the line \texttt{PLATFORM=xc3s500e-fg320-5} to \texttt{PLATFORM=YOUR\_FPGA\_SYMBOL} |
\item Go to \texttt{./Pure/syn/YOUR\_FPGA\_SYMBOL/} directory. |
\item In \texttt{PresentEnc.xst} file modify the line \texttt{-p xc3s500e-5-fg320} to \texttt{-p YOUR\_FPGA\_CODE} |
\item In \texttt{Makefile} file modify the line \texttt{PLATFORM=xc3s500e-fg320-5} to \texttt{PLATFORM=YOUR\_FPGA\_CODE} |
\end{enumerate} |
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\footnotetext[1]{This solution was not tested and is based on my own observations. Additional care should be taken with *.UCF files. You can make this modifications on your own risk} |
\footnotetext[1]{This solution was not tested and is based on my own observations.} |
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\newpage |