URL
https://opencores.org/ocsvn/present/present/trunk
Subversion Repositories present
Compare Revisions
- This comparison shows the changes necessary to convert path
/present/trunk/PureTesting/sim
- from Rev 4 to Rev 8
- ↔ Reverse comparison
Rev 4 → Rev 8
/rtl_sim/bin/test/key.txt
0,0 → 1,100
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
/rtl_sim/bin/test/data.txt
0,0 → 1,80
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
/rtl_sim/bin/test/key2.txt
0,0 → 1,100
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
/rtl_sim/bin/test/data2.txt
0,0 → 1,80
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
rtl_sim/bin/test
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: rtl_sim/bin/PresentTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: rtl_sim/bin/PresentTB_isim_beh.wdb
===================================================================
--- rtl_sim/bin/PresentTB_isim_beh.wdb (nonexistent)
+++ rtl_sim/bin/PresentTB_isim_beh.wdb (revision 8)
rtl_sim/bin/PresentTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: rtl_sim/bin/PresentCommTB_stx_beh.prj
===================================================================
--- rtl_sim/bin/PresentCommTB_stx_beh.prj (nonexistent)
+++ rtl_sim/bin/PresentCommTB_stx_beh.prj (revision 8)
@@ -0,0 +1,15 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/kody.vhd"
+vhdl isim_temp "../../../rtl/vhdl/Reg.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl isim_temp "../../../rtl/vhdl/pLayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/keyupd.vhd"
+vhdl isim_temp "../../../rtl/vhdl/counter.vhd"
+vhdl isim_temp "../../../rtl/vhdl/AsyncMux.vhd"
+vhdl isim_temp "../../../rtl/vhdl/ShiftReg.vhd"
+vhdl isim_temp "../../../rtl/vhdl/RS232RefComp.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentEnc.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentCommSM.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentComm.vhd"
+vhdl isim_temp "../../../bench/vhdl/txt_util.vhd"
+vhdl isim_temp "../../../bench/vhdl/PresentCommTB.vhd"
Index: rtl_sim/bin/PresentCommTB_beh.prj
===================================================================
--- rtl_sim/bin/PresentCommTB_beh.prj (nonexistent)
+++ rtl_sim/bin/PresentCommTB_beh.prj (revision 8)
@@ -0,0 +1,15 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../rtl/vhdl/kody.vhd"
+vhdl work "../../../rtl/vhdl/Reg.vhd"
+vhdl work "../../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl work "../../../rtl/vhdl/pLayer.vhd"
+vhdl work "../../../rtl/vhdl/keyupd.vhd"
+vhdl work "../../../rtl/vhdl/counter.vhd"
+vhdl work "../../../rtl/vhdl/AsyncMux.vhd"
+vhdl work "../../../rtl/vhdl/ShiftReg.vhd"
+vhdl work "../../../rtl/vhdl/RS232RefComp.vhd"
+vhdl work "../../../rtl/vhdl/PresentEnc.vhd"
+vhdl work "../../../rtl/vhdl/PresentCommSM.vhd"
+vhdl work "../../../rtl/vhdl/PresentComm.vhd"
+vhdl work "../../../bench/vhdl/txt_util.vhd"
+vhdl work "../../../bench/vhdl/PresentCommTB.vhd"
Index: rtl_sim/bin/sLayerTB_stx_beh.prj
===================================================================
--- rtl_sim/bin/sLayerTB_stx_beh.prj (nonexistent)
+++ rtl_sim/bin/sLayerTB_stx_beh.prj (revision 8)
@@ -0,0 +1,2 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../bench/vhdl/sLayerTB.vhd"
Index: rtl_sim/bin/PresentCommTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: rtl_sim/bin/PresentCommTB_isim_beh.wdb
===================================================================
--- rtl_sim/bin/PresentCommTB_isim_beh.wdb (nonexistent)
+++ rtl_sim/bin/PresentCommTB_isim_beh.wdb (revision 8)
rtl_sim/bin/PresentCommTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: rtl_sim/bin/sLayerTB_beh.prj
===================================================================
--- rtl_sim/bin/sLayerTB_beh.prj (nonexistent)
+++ rtl_sim/bin/sLayerTB_beh.prj (revision 8)
@@ -0,0 +1,2 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../bench/vhdl/sLayerTB.vhd"
Index: rtl_sim/bin/keyupdTB_stx_beh.prj
===================================================================
--- rtl_sim/bin/keyupdTB_stx_beh.prj (nonexistent)
+++ rtl_sim/bin/keyupdTB_stx_beh.prj (revision 8)
@@ -0,0 +1,3 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/keyupd.vhd"
+vhdl isim_temp "../../../bench/vhdl/keyupdTB.vhd"
Index: rtl_sim/bin/keyupdTB_beh.prj
===================================================================
--- rtl_sim/bin/keyupdTB_beh.prj (nonexistent)
+++ rtl_sim/bin/keyupdTB_beh.prj (revision 8)
@@ -0,0 +1,3 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../rtl/vhdl/keyupd.vhd"
+vhdl work "../../../bench/vhdl/keyupdTB.vhd"
Index: rtl_sim/bin/sLayerTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: rtl_sim/bin/sLayerTB_isim_beh.wdb
===================================================================
--- rtl_sim/bin/sLayerTB_isim_beh.wdb (nonexistent)
+++ rtl_sim/bin/sLayerTB_isim_beh.wdb (revision 8)
rtl_sim/bin/sLayerTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: rtl_sim/bin/keyupdTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: rtl_sim/bin/keyupdTB_isim_beh.wdb
===================================================================
--- rtl_sim/bin/keyupdTB_isim_beh.wdb (nonexistent)
+++ rtl_sim/bin/keyupdTB_isim_beh.wdb (revision 8)
rtl_sim/bin/keyupdTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: rtl_sim/bin/isim.cmd
===================================================================
--- rtl_sim/bin/isim.cmd (nonexistent)
+++ rtl_sim/bin/isim.cmd (revision 8)
@@ -0,0 +1,3 @@
+onerror {resume}
+wave add /
+run 1000 ns;
Index: rtl_sim/bin/ShiftRegTB_stx_beh.prj
===================================================================
--- rtl_sim/bin/ShiftRegTB_stx_beh.prj (nonexistent)
+++ rtl_sim/bin/ShiftRegTB_stx_beh.prj (revision 8)
@@ -0,0 +1,2 @@
+vhdl isim_temp "../../../rtl/vhdl/ShiftReg.vhd"
+vhdl isim_temp "../../../bench/vhdl/ShiftRegTB.vhd"
Index: rtl_sim/bin/ShiftRegTB_beh.prj
===================================================================
--- rtl_sim/bin/ShiftRegTB_beh.prj (nonexistent)
+++ rtl_sim/bin/ShiftRegTB_beh.prj (revision 8)
@@ -0,0 +1,2 @@
+vhdl work "../../../rtl/vhdl/ShiftReg.vhd"
+vhdl work "../../../bench/vhdl/ShiftRegTB.vhd"
Index: rtl_sim/bin/ShiftRegTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: rtl_sim/bin/ShiftRegTB_isim_beh.wdb
===================================================================
--- rtl_sim/bin/ShiftRegTB_isim_beh.wdb (nonexistent)
+++ rtl_sim/bin/ShiftRegTB_isim_beh.wdb (revision 8)
rtl_sim/bin/ShiftRegTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: rtl_sim/bin/PresentTB_stx_beh.prj
===================================================================
--- rtl_sim/bin/PresentTB_stx_beh.prj (nonexistent)
+++ rtl_sim/bin/PresentTB_stx_beh.prj (revision 8)
@@ -0,0 +1,10 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/kody.vhd"
+vhdl isim_temp "../../../rtl/vhdl/Reg.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl isim_temp "../../../rtl/vhdl/pLayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/keyupd.vhd"
+vhdl isim_temp "../../../rtl/vhdl/counter.vhd"
+vhdl isim_temp "../../../rtl/vhdl/AsyncMux.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentEnc.vhd"
+vhdl isim_temp "../../../bench/vhdl/PresentTB.vhd"
Index: rtl_sim/bin/Makefile
===================================================================
--- rtl_sim/bin/Makefile (nonexistent)
+++ rtl_sim/bin/Makefile (revision 8)
@@ -0,0 +1,59 @@
+PROJECT=present-pure-testing
+
+RM=rm -rf
+
+PLATFORM=xc3s500e-fg320-5
+
+XILINX_DIR="D:/Programy/Xilinx/14.2/ISE_DS/ISE/bin/nt64/"
+FUSE=$(XILINX_DIR)"fuse.exe"
+VHPCOMP=$(XILINX_DIR)"vhpcomp.exe"
+
+clean:
+ $(RM) ./isim
+ $(RM) ./isim.wdb
+ $(RM) *.log
+ $(RM) *.xmsgs
+ $(RM) ./fuseRelaunch.cmd
+ $(RM) *.exe
+
+exports:
+ export DISPLAY=:0
+ export XILINX=D:/Programy/Xilinx/14.2/ISE_DS/ISE
+ export SYSOP=nt64
+ export PATH=${XILINX}/bin/${SYSOP}
+ export LD_LIBRARY_PATH=${XILINX}/lib/${SYSOP}
+
+PresentCommTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./PresentCommTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o PresentCommTB_isim_beh.exe -prj ./PresentCommTB_beh.prj work.PresentCommTB
+
+run_PresentCommTB: exports PresentCommTB
+ "./PresentCommTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "PresentCommTB_isim_beh.wdb"
+
+PresentTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./PresentTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o PresentTB_isim_beh.exe -prj ./PresentTB_beh.prj work.PresentTB
+
+run_PresentTB: exports PresentTB
+ "./PresentTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "PresentTB_isim_beh.wdb"
+
+keyupdTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./keyupdTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o keyupdTB_isim_beh.exe -prj ./keyupdTB_beh.prj work.keyupdTB
+
+run_keyupdTB: exports keyupdTB
+ "./keyupdTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "keyupdTB_isim_beh.wdb"
+
+ShiftRegTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./ShiftRegTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o ShiftRegTB_isim_beh.exe -prj ./ShiftRegTB_beh.prj work.ShiftRegTB
+
+run_ShiftRegTB: exports ShiftRegTB
+ "./ShiftRegTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "ShiftRegTB_isim_beh.wdb"
+
+sLayerTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./sLayerTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o sLayerTB_isim_beh.exe -prj ./sLayerTB_beh.prj work.sLayerTB
+
+run_sLayerTB: exports sLayerTB
+ "./sLayerTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "sLayerTB_isim_beh.wdb"
\ No newline at end of file
Index: rtl_sim/bin/PresentTB_beh.prj
===================================================================
--- rtl_sim/bin/PresentTB_beh.prj (nonexistent)
+++ rtl_sim/bin/PresentTB_beh.prj (revision 8)
@@ -0,0 +1,10 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../rtl/vhdl/kody.vhd"
+vhdl work "../../../rtl/vhdl/Reg.vhd"
+vhdl work "../../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl work "../../../rtl/vhdl/pLayer.vhd"
+vhdl work "../../../rtl/vhdl/keyupd.vhd"
+vhdl work "../../../rtl/vhdl/counter.vhd"
+vhdl work "../../../rtl/vhdl/AsyncMux.vhd"
+vhdl work "../../../rtl/vhdl/PresentEnc.vhd"
+vhdl work "../../../bench/vhdl/PresentTB.vhd"
Index: rtl_sim/bin
===================================================================
--- rtl_sim/bin (nonexistent)
+++ rtl_sim/bin (revision 8)
rtl_sim/bin
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: rtl_sim
===================================================================
--- rtl_sim (nonexistent)
+++ rtl_sim (revision 8)
rtl_sim
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property