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    /present/trunk/PureTesting
    from Rev 19 to Rev 20
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Rev 19 → Rev 20

/rtl/vhdl/ShiftReg.vhd
77,10 → 77,10
begin
reg : process (clk, reset, data)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
data <= (others => '0');
elsif (en = '1') then
if (reset = '1') then
data <= (others => '0');
elsif (clk'event and clk = '1') then
if (en = '1') then
data(internal_data - 1 downto internal_data - length_1) <= input;
else
if (shift = '1') then
/rtl/vhdl/PresentCommSM.vhd
390,12 → 390,10
 
state_modifier : process (clk, reset)
begin
if (clk = '1' and clk'Event) then
if (reset = '1') then
state <= NOP;
else
state <= next_state;
end if;
if (reset = '1') then
state <= NOP;
elsif (clk = '1' and clk'Event) then
state <= next_state;
end if;
end process state_modifier;
/doc/present_pure_testing.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/src/present_pure_testing.tex
7,7 → 7,7
%%%%%%%%%%%%%%%%%
\docDate{ \today }
\docID{Present Cipher ("Pure Testing") - with communication channel with PC}
\docRevision{0.1}
\docRevision{0.2}
\docStatus{Draft}
\docTitle{\mbox{Present Cipher ("Pure Testing") -} \mbox{with communication channel with PC}}
\docTitleShort{Present Cipher ("Pure Testing")...}
18,6 → 18,7
 
\revisionList{
0.1 & all & 2014/05/01 & First draft & K. Gajewski \\
0.2 & all & 2014/09/16 & Some small corrections with the text, typos, etc. & K. Gajewski \\
}
 
\begin{document}
43,7 → 44,7
\item plaintext after sBoxes goes through pLayer (permutation layer)
\item round key is updated
\end{itemize}
After that, ciphertext feeds out the output. Briefly algorithm was shown in Fig. \ref{pAlgorithm}
After that, ciphertext feeds out the output. Briefly algorithm was shown in Fig. \ref{pAlgorithm}.
\begin{figure}[!ht]%
\begin{center}
\includegraphics[width=0.66\textwidth]{img/presentAlgorithm.png}
60,12 → 61,12
 
\section{Interface}
 
Top level component of Present Pure Testing was shown in Fig. \ref{ptest}. The number of inputs and outputs was limited due to RS-232 component in communication interface. All inputs and outputs are synchronous except \texttt{reset} signal in Present State Machine ("internal" part of the core) and sampled at rising edge of clock. All signals are \texttt{STD\_LOGIC}.
Top level component of the Present Pure Testing was shown in Fig. \ref{ptest}. The number of inputs and outputs was limited due to RS-232 component in communication interface. All inputs and outputs are synchronous except \texttt{reset} signal and sampled at rising edge of clock. All signals are \texttt{STD\_LOGIC}.
\begin{figure}[!ht]%
\begin{center}
\includegraphics[width=0.5\textwidth]{img/PresentPureTesting.png}
\caption{%
Top level component of Present Pure Testing
Top level component of the Present Pure Testing
}%
\label{ptest}
\end{center}
73,19 → 74,19
 
\begin{tabularx}{\textwidth}{|p{30mm}|p{11mm}|p{11mm}|X|}
\hline \bf{Signal name} & \bf{Width} & \bf{In/Out} & \bf{Description}\\
\hline \texttt{clk} & 1 & in & Clock signal for the component. \\
\hline \texttt{DATA\_RXD} & 1 & in & Input data signal. \\
\hline \texttt{reset} & 1 & in & \emph{Asynchronous} / \emph{Synchronous} reset signal.\\
\hline \texttt{DATA\_TXD} & 1 & out & Output data signal. \\
\hline \texttt{clk} & 1 & in & clock signal for the component. \\
\hline \texttt{DATA\_RXD} & 1 & in & input data signal. \\
\hline \texttt{reset} & 1 & in & \emph{asynchronous} reset signal.\\
\hline \texttt{DATA\_TXD} & 1 & out & output data signal. \\
\hline
\end{tabularx}
\captionof{table}{Input/Output signals of Present component}
\captionof{table}{Input/Output signals of the Present component}
 
\newpage
 
\section{Internal structure and state machine workflow}
 
Internal datapath between components was shown in fig. \ref{pinside}. All control signals, \texttt{clk} and \texttt{reset} was omitted for clearance. In these schamatic \texttt{keyReg}, \texttt{textReg} and \texttt{outReg} are shift registers enabling conversion of the input/output serial data into parallel data. They are respectively:
Internal datapath between components was shown in fig. \ref{pinside}. All control signals, \texttt{clk} and \texttt{reset} was omitted for clearance. In these schamatic \texttt{keyReg}, \texttt{textReg} and \texttt{outReg} are shift registers enabling conversion of the serial input/output data into parallel data. They are respectively:
\begin{itemize}
\item \texttt{keyReg} - shift register for the key,
\item \texttt{textReg} - shift register for the text to be encoded,
98,7 → 99,7
\begin{center}
\includegraphics[width=0.95\textwidth]{img/PresentCommInside.png}
\caption{%
Internal structure of Present core with communication environment.
Internal structure of the Present core with communication environment.
}%
\label{pinside}
\end{center}
120,14 → 121,14
State machine consist of following states, which are briefly explained:
 
\begin{itemize}
\item \texttt{NOP} - this is initial state of the state machine. It is set up after resetting the system. If any data appear in the RS-232 input (\texttt{RDAsig = '1'}), this state will be changed.
\item \texttt{READ\_DATA\_TEXT} / \texttt{READ\_DATA\_KEY} - This state informs the RS-232 component that input data was readed (by write enable in \texttt{keyReg} register).
\item \texttt{DECODE\_READ\_TEXT} / \texttt{DECODE\_READ\_KEY}- In this state the number of performed data reading iterations are checked. Because one RS-232 packet was set to 8 bytes - 8 iterations need to be ferformed for reading full 64 bit text data input (10 iterations for reading full 80 bit key data input).
\item \texttt{NOP} - this is the initial state of the state machine. It is set up after resetting the system. If any data appear in the RS-232 input (\texttt{RDAsig = '1'}), this state will be changed.
\item \texttt{READ\_DATA\_TEXT} / \texttt{READ\_DATA\_KEY} - These states inform the RS-232 component that input data was read (by write enable in \texttt{keyReg} register).
\item \texttt{DECODE\_READ\_TEXT} / \texttt{DECODE\_READ\_KEY}- In these states the number of performed data reading iterations are checked. Because one RS-232 packet was set to 8 bytes - 8 iterations need to be ferformed for reading full 64 bit text data input (10 iterations for reading full 80 bit key data input).
\item \texttt{TEMP\_STATE} / \texttt{TEMP2\_STATE} / \texttt{TEMP\_OUT} - Here the counter is prepared for key reading / encoding / next "encoding session".
\item \texttt{MOVE\_TEXT} / \texttt{MOVE\_KEY} / - Due to serial data in RS-232 component are stored in 8 bit register, they need to be shifted in appropriate place in given shift registers. It is performed by 8 shifts made in 8 clock cycles.
\item \texttt{NOP\_FOR\_KEY} - Kind of \texttt{NOP} or wait state until 'key' data will arrive.
\item \texttt{PRESENT\_ENCODE} - In this state Present encoding is performed. This state is active until Present component informs about ending of the encoding process (\texttt{readySig = '1'}).
\item \texttt{WRITE\_OUT} - state responsible for immediate sending encoded data. It is performed as many number as 64 bits of encoded data wil be sended by the RS-232 component to the PC (similarly to "\texttt{DECODE...}" states).
\item \texttt{WRITE\_OUT} - state responsible for immediate sending encoded data. It is performed as many number as 64 bits of encoded data will be sent by the RS-232 component to the PC (similarly to "\texttt{DECODE...}" states).
\item \texttt{MOVE\_OUT} - it is similar state to the previous \texttt{MOVE...} states, but here additionally state machine must wait until output data buffer will be prepared for next data which have to be sended.
\end{itemize}
No "lost data" checking, and data correction protocol was performed. It was assumed "ideal channel" for communication. Some states could be "merged" into one state but it will involve more expanded control logic.
136,7 → 137,7
 
\section{FPGA implementations}
 
The component has been verified on a Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E FPGA in FG320 package and synthesized with Xilinx ISE 14.2. It was also implemented and practically tested on Spartan 3E Starter Board made by Digilent\textsuperscript{\textregistered}. Appropriate setup files was prepared with use of ISE Project Navigator, but Makefile scripts was also written. Suitable files was stored in \texttt{./PureTesting/syn/XC3ES500/} directory.
The component has been verified on a Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E FPGA in FG320 package and synthesized with Xilinx ISE 14.2. It was also implemented and practically tested on Spartan 3E Starter Board made by Digilent\textsuperscript{\textregistered}. Appropriate setup files was prepared with the use of ISE Project Navigator, but Makefile scripts was also written. Suitable files was stored in \texttt{./PureTesting/syn/XC3ES500/} directory.
Makefile was tested in Windows 8 with use of Cygwin for 64-bit Windows.
 
Synthesis results was given in Fig. \ref{SynResults}
159,9 → 160,9
Possible change in used FPGA device may be possible in steps given below\footnotemark[1]:
\begin{enumerate}
\item Copy \texttt{./PureTesting/syn/XC3ES500/} directory to another one like \\ \texttt{./PureTesting/syn/YOUR\_FPGA\_SYMBOL/}
\item Go to \texttt{./PureTesting/syn/XC3ES500/} directory.
\item In \texttt{PresentEnc.xst} file modify the line \texttt{-p xc3s500e-5-fg320} to \texttt{-p YOUR\_FPGA\_SYMBOL}
\item In \texttt{Makefile} file modify the line \texttt{PLATFORM=xc3s500e-fg320-5} to \texttt{PLATFORM=YOUR\_FPGA\_SYMBOL}
\item Go to \texttt{./PureTesting/syn/YOUR\_FPGA\_SYMBOL/} directory.
\item In \texttt{PresentComm.xst} file modify the line \texttt{-p xc3s500e-5-fg320} to \texttt{-p YOUR\_FPGA\_CODE}
\item In \texttt{Makefile} file modify the line \texttt{PLATFORM=xc3s500e-fg320-5} to \texttt{PLATFORM=YOUR\_FPGA\_CODE}
\end{enumerate}
 
\footnotetext[1]{This solution was not tested and is based on my own observations. Additional care should be taken with *.UCF files - this supplied with this project should be appropriate only for Spartan 3E Starter Board made by Digilent\textsuperscript{\textregistered}. You can make this modifications on your own risk}

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