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Rev 2 → Rev 3

/DecodeTesting/slayer.vhd
0,0 → 1,55
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:48:15 05/13/2010
-- Design Name:
-- Module Name: permutation - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity slayer is
generic (
w_4 : integer := 4
);
port (
input : in std_logic_vector(w_4-1 downto 0);
output : out std_logic_vector(w_4-1 downto 0)
);
end slayer;
 
architecture Behavioral of slayer is
 
begin
output <= x"C" when input = x"0" else
x"5" when input = x"1" else
x"6" when input = x"2" else
x"B" when input = x"3" else
x"9" when input = x"4" else
x"0" when input = x"5" else
x"A" when input = x"6" else
x"D" when input = x"7" else
x"3" when input = x"8" else
x"E" when input = x"9" else
x"F" when input = x"A" else
x"8" when input = x"B" else
x"4" when input = x"C" else
x"7" when input = x"D" else
x"1" when input = x"E" else
x"2" when input = x"F" else
"ZZZZ";
end Behavioral;
/DecodeTesting/PresentDecodeComm.vhd
0,0 → 1,236
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:01:00 06/26/2013
-- Design Name:
-- Module Name: PresentComm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity PresentDecodeComm is
generic (
w_2: integer := 2;
w_4: integer := 4;
w_5: integer := 5;
w_64: integer := 64;
w_80: integer := 80
);
port (
DATA_RXD : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
DATA_TXD : out STD_LOGIC
);
end PresentDecodeComm;
 
architecture Behavioral of PresentDecodeComm is
 
component ShiftReg is
generic (
length_1 : integer := 8;
length_2 : integer := w_64;
internal_data : integer := w_64
);
port (
input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);
output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
en : in STD_LOGIC;
shift : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component ShiftReg;
 
component Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end component Rs232RefComp;
 
component PresentFullDecoder is
generic (
w_64: integer := 64;
w_80: integer := 80
);
port(
ciphertext : in std_logic_vector(w_64 - 1 downto 0);
key : in std_logic_vector(w_80 - 1 downto 0);
plaintext : out std_logic_vector(w_64 - 1 downto 0);
start, clk, reset : in std_logic;
ready : out std_logic
);
end component PresentFullDecoder;
 
component PresentDecodeCommSM is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
RDAsig : in STD_LOGIC;
TBEsig : in STD_LOGIC;
RDsig : out STD_LOGIC;
WRsig : out STD_LOGIC;
textDataEn : out STD_LOGIC;
textDataShift : out STD_LOGIC;
keyDataEn : out STD_LOGIC;
keyDataShift : out STD_LOGIC;
ciphDataEn : out STD_LOGIC;
ciphDataShift : out STD_LOGIC;
startSig : out STD_LOGIC;
readySig : in STD_LOGIC
);
end component PresentDecodeCommSM;
 
signal keyText : STD_LOGIC_VECTOR(w_80 - 1 downto 0);
signal plaintext : STD_LOGIC_VECTOR(w_64 - 1 downto 0);
signal ciphertext : STD_LOGIC_VECTOR(w_64 - 1 downto 0);
 
signal dataTXD : STD_LOGIC_VECTOR(7 downto 0);
signal dataRXD : STD_LOGIC_VECTOR(7 downto 0);
signal RDAsig : STD_LOGIC;
signal TBEsig : STD_LOGIC;
signal RDsig : STD_LOGIC;
signal WRsig : STD_LOGIC;
signal PEsig : STD_LOGIC;
signal FEsig : STD_LOGIC;
signal OEsig : STD_LOGIC;
 
signal keyDataEn : STD_LOGIC;
signal keyDataShift : STD_LOGIC;
 
signal textDataEn : STD_LOGIC;
signal textDataShift : STD_LOGIC;
 
signal ciphDataEn : STD_LOGIC;
signal ciphDataShift : STD_LOGIC;
 
signal startSig : STD_LOGIC;
signal readySig : STD_LOGIC;
 
begin
 
RS232 : Rs232RefComp
Port map(
TXD => DATA_TXD,
RXD => DATA_RXD,
CLK => clk,
DBIN => dataTXD,
DBOUT => dataRXD,
RDA => RDAsig,
TBE => TBEsig,
RD => RDsig,
WR => WRsig,
PE => PEsig,
FE => FEsig,
OE => OEsig,
RST => reset
);
 
textReg : ShiftReg
generic map(
length_1 => 8,
length_2 => w_64,
internal_data => w_64
)
port map(
input => dataRXD,
output => plaintext,
en => textDataEn,
shift => textDataShift,
clk => clk,
reset => reset
);
 
keyReg : ShiftReg
generic map(
length_1 => 8,
length_2 => w_80,
internal_data => w_80
)
port map(
input => dataRXD,
output => keyText,
en => keyDataEn,
shift => keyDataShift,
clk => clk,
reset => reset
);
 
present :PresentFullDecoder
port map(
ciphertext => plaintext,
key => keyText,
plaintext => ciphertext,
start => startSig,
clk => clk,
reset => reset,
ready => readySig
);
 
outReg : ShiftReg
generic map(
length_1 => w_64,
length_2 => 8,
internal_data => w_64
)
port map(
input => ciphertext,
output => dataTXD,
en => ciphDataEn,
shift => ciphDataShift,
clk => clk,
reset => reset
);
 
SM : PresentDecodeCommSM
port map(
clk => clk,
reset => reset,
RDAsig => RDAsig,
TBEsig => TBEsig,
RDsig => RDsig,
WRsig => WRsig,
textDataEn => textDataEn,
textDataShift => textDataShift,
keyDataEn => keyDataEn,
keyDataShift => keyDataShift,
ciphDataEn => ciphDataEn,
ciphDataShift => ciphDataShift,
startSig => startSig,
readySig => readySig
);
 
end Behavioral;
 
/DecodeTesting/PresentDecodeCommSM.vhd
0,0 → 1,367
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:49:35 06/26/2013
-- Design Name:
-- Module Name: PresentCommSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.kody.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity PresentDecodeCommSM is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
RDAsig : in STD_LOGIC;
TBEsig : in STD_LOGIC;
RDsig : out STD_LOGIC;
WRsig : out STD_LOGIC;
textDataEn : out STD_LOGIC;
textDataShift : out STD_LOGIC;
keyDataEn : out STD_LOGIC;
keyDataShift : out STD_LOGIC;
ciphDataEn : out STD_LOGIC;
ciphDataShift : out STD_LOGIC;
startSig : out STD_LOGIC;
readySig : in STD_LOGIC
);
end PresentDecodeCommSM;
 
architecture Behavioral of PresentDecodeCommSM is
 
component counter is
generic (
w_5 : integer := 5
);
port (
clk, reset, cnt_res : in std_logic;
num : out std_logic_vector (w_5-1 downto 0)
);
end component counter;
 
signal state : stany_comm := NOP;
signal next_state : stany_comm := NOP;
 
-- modify for variable key size
signal serialDataCtrCt : STD_LOGIC;
signal serialDataCtrOut : STD_LOGIC_VECTOR(3 downto 0);
signal serialDataCtrReset : STD_LOGIC;
signal ctrReset : STD_LOGIC;
-- DO NOT MODIFY!!!
signal shiftDataCtrCt : STD_LOGIC;
signal shiftDataCtrOut : STD_LOGIC_VECTOR(2 downto 0);
 
begin
ctrReset <= serialDataCtrReset or reset;
SM : process(state, RDAsig, TBEsig, shiftDataCtrOut, serialDataCtrOut, readySig)
begin
case state is
when NOP =>
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '0';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '0';
if (RDAsig = '1') then
next_state <= READ_DATA_TEXT;
else
next_state <= NOP;
end if;
when READ_DATA_TEXT =>
RDsig <= '1';
WRsig <= '0';
textDataEn <= '1';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '0';
serialDataCtrCt <= '1';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '0';
next_state <= DECODE_READ_TEXT;
when DECODE_READ_TEXT =>
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '0';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '0';
if (serialDataCtrOut(3 downto 0) = "1000") then
next_state <= TEMP_STATE;
else
next_state <= MOVE_TEXT;
end if;
when TEMP_STATE =>
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '0';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '1';
next_state <= NOP_FOR_KEY;
when MOVE_TEXT =>
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '1';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '0';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '1';
serialDataCtrReset <= '0';
if (shiftDataCtrOut(2 downto 0) = "111") then
next_state <= NOP;
else
next_state <= MOVE_TEXT;
end if;
when NOP_FOR_KEY =>
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '0';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '0';
if (RDAsig = '1') then
next_state <= READ_DATA_KEY;
else
next_state <= NOP_FOR_KEY;
end if;
when READ_DATA_KEY =>
RDsig <= '1';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '1';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '0';
serialDataCtrCt <= '1';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '0';
next_state <= DECODE_READ_KEY;
when DECODE_READ_KEY =>
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '0';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '0';
if (serialDataCtrOut(3 downto 0) = "1010") then
next_state <= TEMP2_STATE;
else
next_state <= MOVE_KEY;
end if;
when TEMP2_STATE =>
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '0';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '1';
next_state <= PRESENT_ENCODE;
when MOVE_KEY =>
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '1';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '0';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '1';
serialDataCtrReset <= '0';
if (shiftDataCtrOut(2 downto 0) = "111") then
next_state <= NOP_FOR_KEY;
else
next_state <= MOVE_KEY;
end if;
when PRESENT_ENCODE =>
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataShift <= '0';
startSig <= '1';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '0';
if (readySig = '1') then
ciphDataEn <= '1';
next_state <= WRITE_OUT;
else
ciphDataEn <= '0';
next_state <= PRESENT_ENCODE;
end if;
when WRITE_OUT =>
RDsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '1';
serialDataCtrCt <= '1';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '0';
if (serialDataCtrOut = "1000") then
WRsig <= '0';
next_state <= TEMP_OUT;
else
WRsig <= '1';
next_state <= MOVE_OUT;
end if;
when TEMP_OUT =>
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '1';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '1';
next_state <= NOP;
when MOVE_OUT =>
if (TBEsig = '0') then
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '0';
startSig <= '1';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '0';
serialDataCtrReset <= '0';
next_state <= MOVE_OUT;
else
RDsig <= '0';
WRsig <= '0';
textDataEn <= '0';
textDataShift <= '0';
keyDataEn <= '0';
keyDataShift <= '0';
ciphDataEn <= '0';
ciphDataShift <= '1';
startSig <= '1';
serialDataCtrCt <= '0';
shiftDataCtrCt <= '1';
serialDataCtrReset <= '0';
if (shiftDataCtrOut = "111") then
next_state <= WRITE_OUT;
else
next_state <= MOVE_OUT;
end if;
end if;
end case;
end process SM;
 
state_modifier : process (clk, reset)
begin
if (clk = '1' and clk'Event) then
if (reset = '1') then
state <= NOP;
else
state <= next_state;
end if;
end if;
end process state_modifier;
dataCounter : counter
generic map(
w_5 => 4
)
port map (
cnt_res => serialDataCtrCt,
num => serialDataCtrOut,
clk => clk,
reset => ctrReset
);
 
shiftCounter : counter
generic map(
w_5 => 3
)
port map (
cnt_res => shiftDataCtrCt,
num => shiftDataCtrOut,
clk => clk,
reset => reset
);
 
end Behavioral;
 
/DecodeTesting/keyupd.vhd
0,0 → 1,59
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:45:36 05/13/2010
-- Design Name:
-- Module Name: keyupd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity keyupd is
generic(
w_80: integer := 80;
w_5 : integer := 5;
w_4 : integer := 4);
port(
key : in std_logic_vector(w_80-1 downto 0);
num : in std_logic_vector(w_5-1 downto 0);
keyout : out std_logic_vector(w_80-1 downto 0)
);
end keyupd;
 
architecture Behavioral of keyupd is
 
component slayer is
generic(w_4: integer := 4);
port(
input : in std_logic_vector(w_4-1 downto 0);
output : out std_logic_vector(w_4-1 downto 0)
);
end component;
 
signal changed : std_logic_vector(w_4-1 downto 0);
signal changin : std_logic_vector(w_4-1 downto 0);
signal keytemp : std_logic_vector(w_80-1 downto 0);
 
begin
s1: slayer port map(input => changin, output => changed);
changin <= keytemp(79 downto 76);
keytemp <= key(18 downto 0) & key(79 downto 19);
keyout(79 downto 76)<= changed;
keyout(75 downto 20) <= keytemp(75 downto 20);
keyout(19 downto 15)<= keytemp(19 downto 15) xor num;
keyout(14 downto 0) <= keytemp(14 downto 0);
end Behavioral;
/DecodeTesting/ShiftRegTB.vhd
0,0 → 1,119
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:11:18 10/08/2012
-- Design Name:
-- Module Name: E:/spent i praca/OpenCores/mRSAKeyFinalizer/ShiftRegTB.vhd
-- Project Name: mRSAKeyFinalizer
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ShiftReg
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.RSAFinalizerProperties.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ShiftRegTB IS
END ShiftRegTB;
ARCHITECTURE behavior OF ShiftRegTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ShiftReg
-- generic (length_1 : integer := WORD_LENGTH;
-- length_2 : integer := BYTE
GENERIC (
length_1 : integer := BYTE;
length_2 : integer := WORD_LENGTH
);
PORT(
input : in STD_LOGIC_VECTOR(7 downto 0);
--input : IN std_logic_vector(63 downto 0);
output : out STD_LOGIC_VECTOR(63 downto 0);
--output : OUT std_logic_vector(7 downto 0);
en : in STD_LOGIC;
shift : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
END COMPONENT;
 
--Inputs
signal input : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
--signal input : std_logic_vector(63 downto 0) := (others => '0');
signal en : STD_LOGIC := '0';
signal shift : STD_LOGIC := '0';
signal clk : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
 
--Outputs
signal output : STD_LOGIC_VECTOR(63 downto 0);
--signal output : std_logic_vector(7 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ShiftReg PORT MAP (
input => input,
output => output,
en => en,
shift => shift,
clk => clk,
reset => reset
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
reset <= '0';
shift <= '0';
input <= "10101010";
--input <= "1111000011110000111100001111000011110000111100001111000011110000";
wait for 100 ns;
reset <= '1';
wait for clk_period*10;
en <= '1';
wait for clk_period*1;
en <= '0';
wait for clk_period*1;
shift <= '1';
wait for clk_period*10;
assert false severity failure;
end process;
 
END;
/DecodeTesting/sLayer_invTB.vhd
0,0 → 1,95
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:11:33 05/16/2010
-- Design Name:
-- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/sLayerTB.vhd
-- Project Name: szyfrator
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: slayer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY sLayerTB IS
END sLayerTB;
ARCHITECTURE behavior OF sLayer_invTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT slayer_inv
PORT(
input : IN std_logic_vector(3 downto 0);
output : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
 
--BiDirs
signal input : std_logic_vector(3 downto 0);
signal output : std_logic_vector(3 downto 0);
 
-- Clock period definitions
constant clk_period : time := 1ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: slayer_inv PORT MAP (
input => input,
output => output
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
reset <= '1';
wait for 100ns;
reset <= '0';
wait for clk_period;
input <= x"0";
wait for clk_period;
input <= x"A";
wait for clk_period;
input <= x"F";
wait for clk_period;
-- insert stimulus here
assert false severity failure;
end process;
 
END;
/DecodeTesting/keyupd_invTB.vhd
0,0 → 1,106
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:00:18 05/16/2010
-- Design Name:
-- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/keyupdTB.vhd
-- Project Name: szyfrator
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: keyupd
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY keyupd_invTB IS
END keyupd_invTB;
ARCHITECTURE behavior OF keyupd_invTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT keyupd_inv
PORT(
key : IN std_logic_vector(79 downto 0);
num : IN std_logic_vector(4 downto 0);
keyout : OUT std_logic_vector(79 downto 0)--;
--clk, reset : std_logic
);
END COMPONENT;
 
--Inputs
signal key : std_logic_vector(79 downto 0) := (others => '0');
signal num : std_logic_vector(4 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
 
--Outputs
signal keyout : std_logic_vector(79 downto 0);
constant clk_period : time := 1ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: keyupd_inv PORT MAP (
key => key,
num => num,
keyout => keyout--,
--clk => clk,
--reset => reset
);
-- No clocks detected in port list. Replace clk below with
-- appropriate port name
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
reset <= '1';
wait for 100ns;
reset <='0';
wait for clk_period;
key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
num <= "00001";
wait for clk_period;
key <= x"c0000000000000008000";
num <= "00010";
wait for clk_period;
key <= x"50001800000000010000";
num <= "00011";
wait for clk_period;
key <= x"8ba27a0eb8783ac96d59";
num <= "11111";
wait for clk_period;
assert false severity failure;
end process;
END;
/DecodeTesting/kody.vhd
0,0 → 1,38
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package kody is
-- type for PresentStateMachine to control the datapath & circuit --
type stany is (NOP, SM_START, SM_READY);
type decode_states is (NOP, KG_START, DEC_START, DEC_READY);
type stany_comm is (NOP, READ_DATA_KEY, DECODE_READ_KEY, MOVE_KEY, TEMP_STATE, TEMP2_STATE, TEMP_OUT,
NOP_FOR_KEY, READ_DATA_TEXT, DECODE_READ_TEXT, MOVE_TEXT,
PRESENT_ENCODE, WRITE_OUT, MOVE_OUT);
-- constant as control command from input --
constant cnop : std_logic_vector(3 downto 0) := "0000"; --0 no operations
constant cdec : std_logic_vector(3 downto 0) := "0001"; --1 decode text
constant crdk1 : std_logic_vector(3 downto 0) := "0010"; --2 read key part 1
constant crdk2 : std_logic_vector(3 downto 0) := "0011"; --3 read key part 2
constant crdk3 : std_logic_vector(3 downto 0) := "0100"; --4 read key part 3
constant cmkd : std_logic_vector(3 downto 0) := "0101"; --5 make decrypt key
constant ccod : std_logic_vector(3 downto 0) := "0110"; --6 code text
constant crdt1 : std_logic_vector(3 downto 0) := "0111"; --7 read text part 1
constant crdt2 : std_logic_vector(3 downto 0) := "1000"; --8 read text part 2
constant ccto1 : std_logic_vector(3 downto 0) := "1001"; --9 ciphertext output part 1 (LSW)
constant ccto2 : std_logic_vector(3 downto 0) := "1010"; --A ciphertext output part 2 (MSW)
-- For input registers (early version, now for mux's) --
constant in_ld_reg_L : std_logic_vector(1 downto 0) := "00"; -- Load low part of the register (64 & 80 bit)
constant in_ld_reg_H : std_logic_vector(1 downto 0) := "01"; -- Load high part of the register (64 & 80 bit)
constant in_ld_reg_HH : std_logic_vector(1 downto 0) := "10"; -- Load highest part of the register (80 bit only)
constant in_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input)
-- For output register --
constant out_ld_reg : std_logic_vector(1 downto 0) := "00"; -- Load the output register
constant out_reg_L : std_logic_vector(1 downto 0) := "01"; -- send low part of the register to the output
constant out_reg_H : std_logic_vector(1 downto 0) := "10"; -- senf high part of the register to the output
constant out_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input)
end kody;
/DecodeTesting/PresentStateMachine.vhd
0,0 → 1,100
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:17:10 04/02/2011
-- Design Name:
-- Module Name: PresentStateMachine - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.kody.ALL;
 
entity PresentStateMachine is
generic (
w_5 : integer := 5
);
port (
clk, reset, start : in std_logic;
ready, cnt_res, ctrl_mux, RegEn: out std_logic;
num : in std_logic_vector (w_5-1 downto 0)
);
end PresentStateMachine;
 
architecture Behavioral of PresentStateMachine is
signal state : stany;
signal next_state : stany;
begin
States : process(state, start, num)
begin
case state is
when NOP =>
ready <= '0';
cnt_res <= '0';
ctrl_mux <= '0';
RegEn <= '0';
if (start = '1') then
next_state <= SM_START;
else
next_state <= NOP;
end if;
when SM_START =>
ready <= '0';
RegEn <= '1';
cnt_res <= '1';
if (start = '1') then
if (num = "00000") then
ctrl_mux <= '0';
next_state <= SM_START;
elsif (num = "11111") then
ctrl_mux <= '1';
next_state <= SM_READY;
else
ctrl_mux <= '1';
next_state <= SM_START;
end if;
else
ctrl_mux <= '0';
next_state <= NOP;
end if;
when SM_READY =>
cnt_res <= '0';
RegEn <= '0';
ready <= '1';
if (start = '1') then
ctrl_mux <= '1';
next_state <= SM_READY;
else
ctrl_mux <= '0';
next_state <= NOP;
end if;
end case;
end process States;
SM : process (clk, reset)
begin
if (reset = '1') then
state <= NOP;
elsif (clk'Event and clk = '1') then
state <= next_state;
end if;
end process SM;
 
end Behavioral;
 
/DecodeTesting/AsyncMux.vhd
0,0 → 1,50
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:24:35 06/24/2013
-- Design Name:
-- Module Name: AsyncMux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity AsyncMux is
generic (
width : integer := 64
);
port (
input0 : in STD_LOGIC_VECTOR(width - 1 downto 0);
input1 : in STD_LOGIC_VECTOR(width - 1 downto 0);
ctrl : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(width - 1 downto 0)
);
end AsyncMux;
 
architecture Behavioral of AsyncMux is
 
begin
output <= input0 when (ctrl = '0') else
input1;
end Behavioral;
 
/DecodeTesting/pLayer_inv.vhd
0,0 → 1,99
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:06:24 05/13/2010
-- Design Name:
-- Module Name: pLayer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity pLayer_inv is
generic(w_64 : integer := 64);
port (
input : in std_logic_vector(w_64-1 downto 0);
output : out std_logic_vector(w_64-1 downto 0)
);
end pLayer_inv;
 
architecture Behavioral of pLayer_inv is
begin
output(0) <= input(0);
output(1) <= input(16);
output(2) <= input(32);
output(3) <= input(48);
output(4) <= input(1);
output(5) <= input(17);
output(6) <= input(33);
output(7) <= input(49);
output(8) <= input(2);
output(9) <= input(18);
output(10) <= input(34);
output(11) <= input(50);
output(12) <= input(3);
output(13) <= input(19);
output(14) <= input(35);
output(15) <= input(51);
output(16) <= input(4);
output(17) <= input(20);
output(18) <= input(36);
output(19) <= input(52);
output(20) <= input(5);
output(21) <= input(21);
output(22) <= input(37);
output(23) <= input(53);
output(24) <= input(6);
output(25) <= input(22);
output(26) <= input(38);
output(27) <= input(54);
output(28) <= input(7);
output(29) <= input(23);
output(30) <= input(39);
output(31) <= input(55);
output(32) <= input(8);
output(33) <= input(24);
output(34) <= input(40);
output(35) <= input(56);
output(36) <= input(9);
output(37) <= input(25);
output(38) <= input(41);
output(39) <= input(57);
output(40) <= input(10);
output(41) <= input(26);
output(42) <= input(42);
output(43) <= input(58);
output(44) <= input(11);
output(45) <= input(27);
output(46) <= input(43);
output(47) <= input(59);
output(48) <= input(12);
output(49) <= input(28);
output(50) <= input(44);
output(51) <= input(60);
output(52) <= input(13);
output(53) <= input(29);
output(54) <= input(45);
output(55) <= input(61);
output(56) <= input(14);
output(57) <= input(30);
output(58) <= input(46);
output(59) <= input(62);
output(60) <= input(15);
output(61) <= input(31);
output(62) <= input(47);
output(63) <= input(63);
end Behavioral;
/DecodeTesting/PresentKeyGenTB.vhd
0,0 → 1,126
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:14 06/25/2013
-- Design Name:
-- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Pure/PresentTB.vhd
-- Project Name: Present_Pure
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PresentEnc
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY PresentKeyGenTB IS
END PresentKeyGenTB;
ARCHITECTURE behavior OF PresentKeyGenTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PresentEncKeyGen
PORT(
key : IN std_logic_vector(79 downto 0);
key_end : OUT std_logic_vector(79 downto 0);
start : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
ready : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal key : std_logic_vector(79 downto 0) := (others => '0');
signal start : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
 
--Outputs
signal key_end : std_logic_vector(79 downto 0);
signal ready : std_logic;
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PresentEncKeyGen PORT MAP (
key => key,
key_end => key_end,
start => start,
clk => clk,
reset => reset,
ready => ready
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
 
reset <= '1';
start <= '0';
wait for 100 ns;
reset <= '0';
key <= (others => '0');
start <= '1';
wait for clk_period*40;
start <= '0';
wait for clk_period;
key <= (others => '1');
start <= '1';
wait for clk_period*40;
start <= '0';
wait for clk_period;
key <= (others => '0');
start <= '1';
wait for clk_period*40;
start <= '0';
wait for clk_period;
key <= (others => '1');
start <= '1';
wait for clk_period*40;
start <= '0';
wait for clk_period;
assert false severity failure;
 
end process;
 
END;
/DecodeTesting/PresentEncKeyGen.vhd
0,0 → 1,140
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:02:34 05/15/2010
-- Design Name:
-- Module Name: PresentEnc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity PresentEncKeyGen is
generic (
w_2: integer := 2;
w_4: integer := 4;
w_5: integer := 5;
w_80: integer := 80
);
port(
key : in std_logic_vector(w_80 - 1 downto 0);
key_end : out std_logic_vector(w_80 - 1 downto 0);
start, clk, reset : in std_logic;
ready : out std_logic
);
end PresentEncKeyGen;
 
architecture Behavioral of PresentEncKeyGen is
 
component Reg is
generic(width : integer := w_80);
port(
input : in STD_LOGIC_VECTOR(width - 1 downto 0);
output : out STD_LOGIC_VECTOR(width - 1 downto 0);
enable : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component Reg;
component AsyncMux is
generic (
width : integer := 80
);
port (
input0 : in STD_LOGIC_VECTOR(width - 1 downto 0);
input1 : in STD_LOGIC_VECTOR(width - 1 downto 0);
ctrl : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(width - 1 downto 0)
);
end component AsyncMux;
 
component PresentStateMachine is
generic (
w_5 : integer := 5
);
port (
clk, reset, start : in std_logic;
ready, cnt_res, ctrl_mux, RegEn: out std_logic;
num : in std_logic_vector (w_5-1 downto 0)
);
end component;
 
component keyupd is
generic(
w_5 : integer := 5;
w_80: integer := 80
);
port(
num : in std_logic_vector(w_5-1 downto 0);
key : in std_logic_vector(w_80-1 downto 0);
keyout : out std_logic_vector(w_80-1 downto 0)
);
end component;
 
component counter is
generic (
w_5 : integer := 5
);
port (
clk, reset, cnt_res : in std_logic;
num : out std_logic_vector (w_5-1 downto 0)
);
end component;
signal keynum : std_logic_vector (w_5-1 downto 0);
signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0);
signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic;
begin
mux_80: AsyncMux generic map(width => w_80) port map(
input0 => key,
input1 => kupd,
ctrl => mux_ctrl,
output => keyToReg
);
regKey : Reg generic map(width => w_80) port map(
input => keyToReg,
output => keyfout,
enable => RegEn,
clk => clk,
reset => reset
);
mixer: keyupd port map(
key => keyfout,
num => keynum,
keyout => kupd
);
SM: PresentStateMachine port map(
start => start,
reset => reset,
ready => ready_sig,
cnt_res => cnt_res,
ctrl_mux => mux_ctrl,
clk => clk,
num => keynum,
RegEn => RegEn
);
count: counter port map(
clk => clk,
reset => reset,
cnt_res => cnt_res,
num => keynum
);
key_end <= keyfout;
ready <= ready_sig;
end Behavioral;
/DecodeTesting/slayer_inv.vhd
0,0 → 1,55
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:48:15 05/13/2010
-- Design Name:
-- Module Name: permutation - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity slayer_inv is
generic (
w_4 : integer := 4
);
port (
input : in std_logic_vector(w_4-1 downto 0);
output : out std_logic_vector(w_4-1 downto 0)
);
end slayer_inv;
 
architecture Behavioral of slayer_inv is
 
begin
output <= x"0" when input = x"C" else
x"1" when input = x"5" else
x"2" when input = x"6" else
x"3" when input = x"B" else
x"4" when input = x"9" else
x"5" when input = x"0" else
x"6" when input = x"A" else
x"7" when input = x"D" else
x"8" when input = x"3" else
x"9" when input = x"E" else
x"A" when input = x"F" else
x"B" when input = x"8" else
x"C" when input = x"4" else
x"D" when input = x"7" else
x"E" when input = x"1" else
x"F" when input = x"2" else
"ZZZZ";
end Behavioral;
/DecodeTesting/ShiftReg.vhd
0,0 → 1,70
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:39:23 10/08/2012
-- Design Name:
-- Module Name: ShiftReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ShiftReg is
generic (
length_1 : integer := 8;
length_2 : integer := 64;
internal_data : integer := 64
);
port (
input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);
output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
en : in STD_LOGIC;
shift : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end ShiftReg;
 
architecture Behavioral of ShiftReg is
 
signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0);
 
begin
reg : process (clk, reset, data)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
data <= (others => '0');
elsif (en = '1') then
data(internal_data - 1 downto internal_data - length_1) <= input;
else
if (shift = '1') then
data <= '0' & data(internal_data - 1 downto 1);
end if;
end if;
end if;
output <= data(length_2 - 1 downto 0);
end process reg;
 
end Behavioral;
 
/DecodeTesting/txt_util.vhd
0,0 → 1,586
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
 
 
package txt_util is
 
-- prints a message to the screen
procedure print(text: string);
 
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
 
-- converts std_logic into a character
function chr(sl: std_logic) return character;
 
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
 
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
 
-- converts boolean into a string
function str(b: boolean) return string;
 
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
 
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
 
-- converts integer to string, using base 10
function str(int: integer) return string;
 
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
 
 
-- functions to manipulate strings
-----------------------------------
 
-- convert a character to upper case
function to_upper(c: character) return character;
 
-- convert a character to lower case
function to_lower(c: character) return character;
 
-- convert a string to upper case
function to_upper(s: string) return string;
 
-- convert a string to lower case
function to_lower(s: string) return string;
 
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
 
 
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
 
 
 
 
package body txt_util is
 
 
 
 
-- prints text to the screen
 
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
 
 
 
 
-- prints text to the screen when active
 
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
 
 
-- converts std_logic into a character
 
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
 
 
 
-- converts std_logic into a string (1 to 1)
 
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
 
 
 
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
 
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
 
 
function str(b: boolean) return string is
 
begin
if b then
return "true";
else
return "false";
end if;
end str;
 
 
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
 
 
 
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
function str(int: integer; base: integer) return string is
 
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
 
begin
 
-- bug fix for negative numbers
abs_int := abs(int);
 
num := abs_int;
 
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
 
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
 
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
 
end str;
 
 
-- convert integer to string, using base 10
function str(int: integer) return string is
 
begin
 
return str(int, 10) ;
 
end str;
 
 
 
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
 
 
 
-- functions to manipulate strings
-----------------------------------
 
 
-- convert a character to upper case
 
function to_upper(c: character) return character is
 
variable u: character;
 
begin
 
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
 
return u;
 
end to_upper;
 
 
-- convert a character to lower case
 
function to_lower(c: character) return character is
 
variable l: character;
 
begin
 
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
 
return l;
 
end to_lower;
 
 
 
-- convert a string to upper case
 
function to_upper(s: string) return string is
 
variable uppercase: string (s'range);
 
begin
 
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
 
end to_upper;
 
 
 
-- convert a string to lower case
 
function to_lower(s: string) return string is
 
variable lowercase: string (s'range);
 
begin
 
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
 
end to_lower;
 
 
 
-- functions to convert strings into other types
 
 
-- converts a character into a std_logic
 
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
 
 
-- converts a string into std_logic_vector
 
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
 
 
 
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
 
 
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
 
 
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
 
 
 
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
 
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
 
 
 
 
end txt_util;
 
 
 
 
/DecodeTesting/keyupd_inv.vhd
0,0 → 1,59
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:45:36 05/13/2010
-- Design Name:
-- Module Name: keyupd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity keyupd_inv is
generic(
w_80: integer := 80;
w_5 : integer := 5;
w_4 : integer := 4);
port(
key : in std_logic_vector(w_80-1 downto 0);
num : in std_logic_vector(w_5-1 downto 0);
keyout : out std_logic_vector(w_80-1 downto 0)
);
end keyupd_inv;
 
architecture Behavioral of keyupd_inv is
 
component slayer_inv is
generic(w_4: integer := 4);
port(
input : in std_logic_vector(w_4-1 downto 0);
output : out std_logic_vector(w_4-1 downto 0)
);
end component;
 
signal changed : std_logic_vector(w_4-1 downto 0);
signal changin : std_logic_vector(w_4-1 downto 0);
signal keytemp : std_logic_vector(w_80-1 downto 0);
 
begin
s1: slayer_inv port map(input => changin, output => changed);
changin <= key(79 downto 76);
keytemp(79 downto 76)<= changed;
keytemp(75 downto 20) <= key(75 downto 20);
keytemp(19 downto 15)<= key(19 downto 15) xor num;
keytemp(14 downto 0) <= key(14 downto 0);
keyout <= keytemp(60 downto 0) & keytemp(79 downto 61);
end Behavioral;
/DecodeTesting/Reg.vhd
0,0 → 1,60
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:41:41 06/24/2013
-- Design Name:
-- Module Name: Reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Reg is
generic(width : integer := 64);
port(
input : in STD_LOGIC_VECTOR(width - 1 downto 0);
output : out STD_LOGIC_VECTOR(width - 1 downto 0);
enable : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end Reg;
 
architecture Behavioral of Reg is
 
signal reg : STD_LOGIC_VECTOR(width - 1 downto 0);
 
begin
clock : process(clk, reset)
begin
if (reset = '1') then
reg <= (others => '0');
elsif (clk = '1' and clk'Event) then
if (enable = '1') then
reg <= input;
end if;
end if;
end process clock;
output <= reg;
end Behavioral;
 
/DecodeTesting/PresentDecodeCommImpl.ucf
0,0 → 1,7
NET "DATA_RXD" LOC= "R7" | IOSTANDARD= LVTTL | SLEW= FAST ;
NET "DATA_TXD" LOC= "M14" | IOSTANDARD= LVTTL | DRIVE= 8 | SLEW= FAST ;
NET "CLK" LOC= "C9" | IOSTANDARD= LVCMOS33 | SLEW= FAST ;
NET "CLK" TNM_NET = "clk_group";
TIMESPEC "TS_CLK" = PERIOD "clk_group" 20 ns HIGH 40%;
NET "RESET" LOC= "K17" | IOSTANDARD= LVTTL | PULLDOWN;
SYSTEM_JITTER = 1 ns;
/DecodeTesting/counter.vhd
0,0 → 1,49
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:47:04 04/02/2011
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity counter is
generic (
w_5 : integer := 5
);
port (
clk, reset, cnt_res : in std_logic;
num : out std_logic_vector (w_5-1 downto 0)
);
end counter;
 
architecture Behavioral of counter is
signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0');
begin
licznik : process (clk, reset, cnt)
begin
if (reset = '1') then
cnt <= (others => '0');
elsif (clk'Event and clk = '1') then
if (cnt_res = '1') then
cnt <= cnt + 1;
end if;
end if;
end process licznik;
num <= cnt;
end Behavioral;
 
/DecodeTesting/PresentFullDecoderTB.vhd
0,0 → 1,135
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:12:57 07/14/2013
-- Design Name:
-- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Decode/PresentFullDecoderTB.vhd
-- Project Name: PresentDecode
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PresentFullDecoder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY PresentFullDecoderTB IS
END PresentFullDecoderTB;
ARCHITECTURE behavior OF PresentFullDecoderTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PresentFullDecoder
PORT(
ciphertext : IN std_logic_vector(63 downto 0);
key : IN std_logic_vector(79 downto 0);
plaintext : OUT std_logic_vector(63 downto 0);
start : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
ready : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal ciphertext : std_logic_vector(63 downto 0) := (others => '0');
signal key : std_logic_vector(79 downto 0) := (others => '0');
signal start : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
 
--Outputs
signal plaintext : std_logic_vector(63 downto 0);
signal ready : std_logic;
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PresentFullDecoder PORT MAP (
ciphertext => ciphertext,
key => key,
plaintext => plaintext,
start => start,
clk => clk,
reset => reset,
ready => ready
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
reset <= '1';
start <= '0';
ciphertext <= x"5579c1387b228445";
key <= (others => '0');
wait for 100 ns;
reset <= '0';
ciphertext <= x"5579c1387b228445";
key <= (others => '0');
start <= '1';
wait for clk_period*80;
start <= '0';
wait for clk_period;
ciphertext <= x"e72c46c0f5945049";
key <= (others => '1');
start <= '1';
wait for clk_period*80;
start <= '0';
wait for clk_period;
ciphertext <= x"a112ffc72f68417b";
key <= (others => '0');
start <= '1';
wait for clk_period*80;
start <= '0';
wait for clk_period;
ciphertext <= x"3333dcd3213210d2";
key <= (others => '1');
start <= '1';
wait for clk_period*80;
start <= '0';
wait for clk_period;
assert false severity failure;
 
end process;
 
END;
/DecodeTesting/PresentDecStateMachine.vhd
0,0 → 1,104
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:17:10 04/02/2011
-- Design Name:
-- Module Name: PresentStateMachine - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.kody.ALL;
 
entity PresentDecStateMachine is
generic (
w_5 : integer := 5
);
port (
clk, reset, start : in std_logic;
ready, cnt_res, ctrl_mux, RegEn: out std_logic;
num : in std_logic_vector (w_5-1 downto 0)
);
end PresentDecStateMachine;
 
architecture Behavioral of PresentDecStateMachine is
signal state : stany;
signal next_state : stany;
begin
States : process(state, start, num)
begin
case state is
when NOP =>
ready <= '0';
cnt_res <= '0';
ctrl_mux <= '0';
if (start = '1') then
RegEn <= '1';
next_state <= SM_START;
else
RegEn <= '0';
next_state <= NOP;
end if;
when SM_START =>
ready <= '0';
cnt_res <= '1';
if (start = '1') then
if (num = "11111") then
RegEn <= '1';
ctrl_mux <= '1';
next_state <= SM_START;
elsif (num = "00000") then
RegEn <= '0';
ctrl_mux <= '1';
next_state <= SM_READY;
else
RegEn <= '1';
ctrl_mux <= '1';
next_state <= SM_START;
end if;
else
RegEn <= '0';
ctrl_mux <= '0';
next_state <= NOP;
end if;
when SM_READY =>
cnt_res <= '0';
RegEn <= '0';
ready <= '1';
if (start = '1') then
ctrl_mux <= '1';
next_state <= SM_READY;
else
ctrl_mux <= '0';
next_state <= NOP;
end if;
end case;
end process States;
SM : process (clk, reset)
begin
if (reset = '1') then
state <= NOP;
elsif (clk'Event and clk = '1') then
state <= next_state;
end if;
end process SM;
 
end Behavioral;
 
/DecodeTesting/PresentDecTB.vhd
0,0 → 1,135
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:14 06/25/2013
-- Design Name:
-- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Pure/PresentTB.vhd
-- Project Name: Present_Pure
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PresentEnc
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY PresentDecTB IS
END PresentDecTB;
ARCHITECTURE behavior OF PresentDecTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PresentDec
PORT(
plaintext : IN std_logic_vector(63 downto 0);
key : IN std_logic_vector(79 downto 0);
ciphertext : OUT std_logic_vector(63 downto 0);
start : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
ready : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal plaintext : std_logic_vector(63 downto 0) := (others => '0');
signal key : std_logic_vector(79 downto 0) := (others => '0');
signal start : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
 
--Outputs
signal ciphertext : std_logic_vector(63 downto 0);
signal ready : std_logic;
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PresentDec PORT MAP (
plaintext => plaintext,
key => key,
ciphertext => ciphertext,
start => start,
clk => clk,
reset => reset,
ready => ready
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
 
reset <= '1';
start <= '0';
plaintext <= x"5579c1387b228445";
key <= x"6dab31744f41d7008759";
wait for 100 ns;
reset <= '0';
plaintext <= x"5579c1387b228445";
key <= x"6dab31744f41d7008759";
start <= '1';
wait for clk_period*40;
start <= '0';
wait for clk_period;
plaintext <= x"e72c46c0f5945049";
key <= x"fe7a548fb60eb167c511";
start <= '1';
wait for clk_period*40;
start <= '0';
wait for clk_period;
plaintext <= x"a112ffc72f68417b";
key <= x"6dab31744f41d7008759";
start <= '1';
wait for clk_period*40;
start <= '0';
wait for clk_period;
plaintext <= x"3333dcd3213210d2";
key <= x"fe7a548fb60eb167c511";
start <= '1';
wait for clk_period*40;
start <= '0';
wait for clk_period;
assert false severity failure;
 
end process;
 
END;
/DecodeTesting/PresentDecodeCommTB.vhd
0,0 → 1,346
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:26:35 07/05/2013
-- Design Name:
-- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Testing/VHDL/PresentCommTB.vhd
-- Project Name: PresentComm
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PresentComm
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.all;
USE work.txt_util.all;
USE ieee.std_logic_textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY PresentDecodeCommTB IS
END PresentDecodeCommTB;
ARCHITECTURE behavior OF PresentDecodeCommTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PresentDecodeComm
PORT(
DATA_RXD : IN std_logic;
CLK : IN std_logic;
RESET : IN std_logic;
DATA_TXD : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal DATA_RXD : std_logic := '0';
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
 
--Outputs
signal DATA_TXD : std_logic;
 
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PresentDecodeComm PORT MAP (
DATA_RXD => DATA_RXD,
CLK => CLK,
RESET => RESET,
DATA_TXD => DATA_TXD
);
 
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
 
-- Stimulus process
stim_proc: process
file txt :text is in "test/data.txt";
file key :text is in "test/key.txt";
file txt2 :text is in "test/data2.txt";
file key2 :text is in "test/key2.txt";
variable line_in : line;
variable line_content : string(1 to 8);
variable data : STD_LOGIC;
begin
DATA_RXD <= '1';
RESET <= '1';
wait for 1000 ns;
RESET <= '0';
wait for CLK_period*10;
 
while not (endfile(txt)) loop
readline(txt, line_in); -- info line
read(line_in, line_content);
report line_content;
DATA_RXD <= '0'; -- start bit
wait for 8.75 us;
readline(txt, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt, line_in);
read(line_in, data);
DATA_RXD <= data; -- parity bit
wait for 8.75 us;
report "Koniec bajtu";
DATA_RXD <= '1'; -- stop bit
wait for 100 us;
end loop;
 
while not (endfile(key)) loop
readline(key, line_in); -- info line
read(line_in, line_content);
report line_content;
DATA_RXD <= '0'; -- start bit
wait for 8.75 us;
readline(key, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key, line_in);
read(line_in, data);
DATA_RXD <= data; -- parity bit
wait for 8.75 us;
report "Koniec bajtu";
DATA_RXD <= '1'; -- stop bit
wait for 100 us;
end loop;
 
wait for 2000 us;
while not (endfile(txt2)) loop
readline(txt2, line_in); -- info line
read(line_in, line_content);
report line_content;
DATA_RXD <= '0'; -- start bit
wait for 8.75 us;
readline(txt2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(txt2, line_in);
read(line_in, data);
DATA_RXD <= data; -- parity bit
wait for 8.75 us;
report "Koniec bajtu";
DATA_RXD <= '1'; -- stop bit
wait for 100 us;
end loop;
 
while not (endfile(key2)) loop
readline(key2, line_in); -- info line
read(line_in, line_content);
report line_content;
DATA_RXD <= '0'; -- start bit
wait for 8.75 us;
readline(key2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key2, line_in);
read(line_in, data);
DATA_RXD <= data;
wait for 8.75 us;
readline(key2, line_in);
read(line_in, data);
DATA_RXD <= data; -- parity bit
wait for 8.75 us;
report "Koniec bajtu";
DATA_RXD <= '1'; -- stop bit
wait for 100 us;
end loop;
wait for 2000 us;
assert false severity failure;
end process;
 
END;
/DecodeTesting/RS232RefComp.vhd
0,0 → 1,406
------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
 
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
 
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
 
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
 
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
 
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "00001101"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
 
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
 
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
 
--Clock Dividing Functions--
 
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
 
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
 
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
 
tClk <= rClkDiv(3); --define tClk
 
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
 
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
 
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
 
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
 
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
 
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
 
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
 
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
 
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
 
CE <= '1';
strNext <= strIdle;
end case;
end process;
 
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
 
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
 
case stbeCur is
 
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
 
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
 
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
 
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
 
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
 
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
 
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral;
/DecodeTesting/FullDecoderSM.vhd
0,0 → 1,104
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:24:13 07/14/2013
-- Design Name:
-- Module Name: FullDecoderSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.kody.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity FullDecoderSM is
port(
key_gen_start : out std_logic;
key_gen_ready : in std_logic;
decode_start : out std_logic;
decode_ready : in std_logic;
full_decoder_start :in std_logic;
full_decoder_ready : out std_logic;
clk, reset :in std_logic
);
end FullDecoderSM;
 
architecture Behavioral of FullDecoderSM is
 
signal state : decode_states;
signal next_state : decode_states;
 
begin
 
states : process(state, full_decoder_start, key_gen_ready, decode_ready)
begin
case state is
when NOP =>
key_gen_start <= '0';
decode_start <= '0';
full_decoder_ready <= '0';
if (full_decoder_start = '1') then
next_state <= KG_START;
else
next_state <= NOP;
end if;
when KG_START =>
key_gen_start <= '1';
decode_start <= '0';
full_decoder_ready <= '0';
if (key_gen_ready = '1') then
next_state <= DEC_START;
else
next_state <= KG_START;
end if;
when DEC_START =>
key_gen_start <= '1';
decode_start <= '1';
full_decoder_ready <= '0';
if (decode_ready = '1') then
next_state <= DEC_READY;
else
next_state <= DEC_START;
end if;
when DEC_READY =>
key_gen_start <= '1';
decode_start <= '1';
full_decoder_ready <= '1';
if (full_decoder_start = '1') then
next_state <= DEC_READY;
else
next_state <= NOP;
end if;
end case;
end process states;
 
SM : process (clk, reset)
begin
if (reset = '1') then
state <= NOP;
elsif (clk'Event and clk = '1') then
state <= next_state;
end if;
end process SM;
 
end Behavioral;
 
/DecodeTesting/PresentFullDecoder.vhd
0,0 → 1,141
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:14:34 07/14/2013
-- Design Name:
-- Module Name: PresentFullDecoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity PresentFullDecoder is
generic (
w_2: integer := 2;
w_4: integer := 4;
w_5: integer := 5;
w_32: integer := 32;
w_64: integer := 64;
w_80: integer := 80
);
port(
ciphertext : in std_logic_vector(w_64 - 1 downto 0);
key : in std_logic_vector(w_80 - 1 downto 0);
plaintext : out std_logic_vector(w_64 - 1 downto 0);
start, clk, reset : in std_logic;
ready : out std_logic
);
end PresentFullDecoder;
 
architecture Behavioral of PresentFullDecoder is
 
component PresentEncKeyGen is
generic (
w_2: integer := 2;
w_4: integer := 4;
w_5: integer := 5;
w_80: integer := 80
);
port(
key : in std_logic_vector(w_80 - 1 downto 0);
key_end : out std_logic_vector(w_80 - 1 downto 0);
start, clk, reset : in std_logic;
ready : out std_logic
);
end component PresentEncKeyGen;
 
component PresentDec is
generic (
w_2: integer := 2;
w_4: integer := 4;
w_5: integer := 5;
w_32: integer := 32;
w_64: integer := 64;
w_80: integer := 80
);
port(
plaintext : in std_logic_vector(w_64 - 1 downto 0);
key : in std_logic_vector(w_80 - 1 downto 0);
ciphertext : out std_logic_vector(w_64 - 1 downto 0);
start, clk, reset : in std_logic;
ready : out std_logic
);
end component PresentDec;
 
component FullDecoderSM is
port(
key_gen_start : out std_logic;
key_gen_ready : in std_logic;
decode_start : out std_logic;
decode_ready : in std_logic;
full_decoder_start :in std_logic;
full_decoder_ready : out std_logic;
clk, reset :in std_logic
);
end component FullDecoderSM;
 
signal key_gen_output : std_logic_vector(w_80 - 1 downto 0);
 
signal key_gen_start : std_logic;
signal key_gen_ready : std_logic;
 
signal decode_start : std_logic;
signal decode_ready : std_logic;
 
begin
 
keyGen : PresentEncKeyGen
port map(
key => key,
key_end => key_gen_output,
start => key_gen_start,
clk => clk,
reset => reset,
ready => key_gen_ready
);
 
decoder : PresentDec
port map(
plaintext => ciphertext,
key => key_gen_output,
ciphertext => plaintext,
start => decode_start,
clk => clk,
reset => reset,
ready => decode_ready
);
 
SM : FullDecoderSM
port map(
key_gen_start => key_gen_start,
key_gen_ready => key_gen_ready,
decode_start => decode_start,
decode_ready => decode_ready,
full_decoder_start => start,
full_decoder_ready => ready,
clk => clk,
reset => reset
);
 
end Behavioral;
 
/DecodeTesting/counter_inv.vhd
0,0 → 1,49
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:47:04 04/02/2011
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity counter_inv is
generic (
w_5 : integer := 5
);
port (
clk, reset, cnt_res : in std_logic;
num : out std_logic_vector (w_5-1 downto 0)
);
end counter_inv;
 
architecture Behavioral of counter_inv is
signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0');
begin
licznik : process (clk, reset, cnt)
begin
if (reset = '1') then
cnt <= (others => '1');
elsif (clk'Event and clk = '1') then
if (cnt_res = '1') then
cnt <= cnt - 1;
end if;
end if;
end process licznik;
num <= cnt;
end Behavioral;
 
/DecodeTesting/PresentDec.vhd
0,0 → 1,186
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:02:34 05/15/2010
-- Design Name:
-- Module Name: PresentEnc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity PresentDec is
generic (
w_2: integer := 2;
w_4: integer := 4;
w_5: integer := 5;
w_32: integer := 32;
w_64: integer := 64;
w_80: integer := 80
);
port(
plaintext : in std_logic_vector(w_64 - 1 downto 0);
key : in std_logic_vector(w_80 - 1 downto 0);
ciphertext : out std_logic_vector(w_64 - 1 downto 0);
start, clk, reset : in std_logic;
ready : out std_logic
);
end PresentDec;
 
architecture Behavioral of PresentDec is
 
component Reg is
generic(width : integer := w_64);
port(
input : in STD_LOGIC_VECTOR(width - 1 downto 0);
output : out STD_LOGIC_VECTOR(width - 1 downto 0);
enable : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component Reg;
component AsyncMux is
generic (
width : integer := 64
);
port (
input0 : in STD_LOGIC_VECTOR(width - 1 downto 0);
input1 : in STD_LOGIC_VECTOR(width - 1 downto 0);
ctrl : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(width - 1 downto 0)
);
end component AsyncMux;
 
component PresentDecStateMachine is
generic (
w_5 : integer := 5
);
port (
clk, reset, start : in std_logic;
ready, cnt_res, ctrl_mux, RegEn: out std_logic;
num : in std_logic_vector (w_5-1 downto 0)
);
end component;
 
component slayer_inv is
generic (
w_4 : integer := 4
);
port (
input : in std_logic_vector(w_4-1 downto 0);
output : out std_logic_vector(w_4-1 downto 0)
);
end component;
 
component pLayer_inv is
generic(w_64 : integer := 64);
port(
input : in std_logic_vector(w_64-1 downto 0);
output : out std_logic_vector(w_64-1 downto 0)
);
end component;
 
component keyupd_inv is
generic(
w_5 : integer := 5;
w_80: integer := 80
);
port(
num : in std_logic_vector(w_5-1 downto 0);
key : in std_logic_vector(w_80-1 downto 0);
keyout : out std_logic_vector(w_80-1 downto 0)
);
end component;
 
component counter_inv is
generic (
w_5 : integer := 5
);
port (
clk, reset, cnt_res : in std_logic;
num : out std_logic_vector (w_5-1 downto 0)
);
end component;
signal keynum : std_logic_vector (w_5-1 downto 0);
signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0);
signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0);
signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic;
begin
mux_64: AsyncMux generic map(width => w_64) port map(
input0 => plaintext,
input1 => Pout,
ctrl => mux_ctrl,
output => textToReg
);
regText : Reg generic map(width => w_64) port map(
input => textToReg,
output => toXor,
enable => RegEn,
clk => clk,
reset => reset
);
mux_80: AsyncMux generic map(width => w_80) port map(
input0 => key,
input1 => kupd,
ctrl => mux_ctrl,
output => keyToReg
);
regKey : Reg generic map(width => w_80) port map(
input => keyToReg,
output => keyfout,
enable => RegEn,
clk => clk,
reset => reset
);
slayers_inv : for N in 15 downto 0 generate
s_x: slayer_inv port map(
input => P(4*N+3 downto 4*N),
output => Pout(4*N+3 downto 4*N)
);
end generate slayers_inv;
p1: pLayer_inv port map(
input => ciph,
output => P
);
mixer: keyupd_inv port map(
key => keyfout,
num => keynum,
keyout => kupd
);
SM: PresentDecStateMachine port map(
start => start,
reset => reset,
ready => ready_sig,
cnt_res => cnt_res,
ctrl_mux => mux_ctrl,
clk => clk,
num => keynum,
RegEn => RegEn
);
count: counter_inv port map(
clk => clk,
reset => reset,
cnt_res => cnt_res,
num => keynum
);
ciph <= toXor xor keyfout(79 downto 16);
ciphertext <= ciph;
ready <= ready_sig;
end Behavioral;
/DecodeTesting
DecodeTesting Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/slayer.vhd =================================================================== --- Decode/slayer.vhd (nonexistent) +++ Decode/slayer.vhd (revision 3) @@ -0,0 +1,55 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:48:15 05/13/2010 +-- Design Name: +-- Module Name: permutation - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: Decode/sLayer_invTB.vhd =================================================================== --- Decode/sLayer_invTB.vhd (nonexistent) +++ Decode/sLayer_invTB.vhd (revision 3) @@ -0,0 +1,95 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:11:33 05/16/2010 +-- Design Name: +-- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/sLayerTB.vhd +-- Project Name: szyfrator +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: slayer +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY sLayerTB IS +END sLayerTB; + +ARCHITECTURE behavior OF sLayer_invTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT slayer_inv + PORT( + input : IN std_logic_vector(3 downto 0); + output : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --BiDirs + signal input : std_logic_vector(3 downto 0); + signal output : std_logic_vector(3 downto 0); + + -- Clock period definitions + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: slayer_inv PORT MAP ( + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <= '0'; + wait for clk_period; + input <= x"0"; + wait for clk_period; + input <= x"A"; + wait for clk_period; + input <= x"F"; + wait for clk_period; + -- insert stimulus here + assert false severity failure; + end process; + +END; \ No newline at end of file Index: Decode/keyupd.vhd =================================================================== --- Decode/keyupd.vhd (nonexistent) +++ Decode/keyupd.vhd (revision 3) @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:45:36 05/13/2010 +-- Design Name: +-- Module Name: keyupd - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: Decode/keyupd_invTB.vhd =================================================================== --- Decode/keyupd_invTB.vhd (nonexistent) +++ Decode/keyupd_invTB.vhd (revision 3) @@ -0,0 +1,106 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:00:18 05/16/2010 +-- Design Name: +-- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/keyupdTB.vhd +-- Project Name: szyfrator +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: keyupd +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY keyupd_invTB IS +END keyupd_invTB; + +ARCHITECTURE behavior OF keyupd_invTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT keyupd_inv + PORT( + key : IN std_logic_vector(79 downto 0); + num : IN std_logic_vector(4 downto 0); + keyout : OUT std_logic_vector(79 downto 0)--; + --clk, reset : std_logic + ); + END COMPONENT; + + + --Inputs + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal num : std_logic_vector(4 downto 0) := (others => '0'); + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal keyout : std_logic_vector(79 downto 0); + + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: keyupd_inv PORT MAP ( + key => key, + num => num, + keyout => keyout--, + --clk => clk, + --reset => reset + ); + + -- No clocks detected in port list. Replace clk below with + -- appropriate port name + + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <='0'; + wait for clk_period; + key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + num <= "00001"; + wait for clk_period; + key <= x"c0000000000000008000"; + num <= "00010"; + wait for clk_period; + key <= x"50001800000000010000"; + num <= "00011"; + wait for clk_period; + key <= x"8ba27a0eb8783ac96d59"; + num <= "11111"; + wait for clk_period; + assert false severity failure; + end process; +END; \ No newline at end of file Index: Decode/PresentStateMachine.vhd =================================================================== --- Decode/PresentStateMachine.vhd (nonexistent) +++ Decode/PresentStateMachine.vhd (revision 3) @@ -0,0 +1,100 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:17:10 04/02/2011 +-- Design Name: +-- Module Name: PresentStateMachine - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + RegEn <= '0'; + if (start = '1') then + next_state <= SM_START; + else + next_state <= NOP; + end if; + when SM_START => + ready <= '0'; + RegEn <= '1'; + cnt_res <= '1'; + if (start = '1') then + if (num = "00000") then + ctrl_mux <= '0'; + next_state <= SM_START; + elsif (num = "11111") then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: Decode/kody.vhd =================================================================== --- Decode/kody.vhd (nonexistent) +++ Decode/kody.vhd (revision 3) @@ -0,0 +1,35 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, SM_START, SM_READY); + type decode_states is (NOP, KG_START, DEC_START, DEC_READY); + -- constant as control command from input -- + constant cnop : std_logic_vector(3 downto 0) := "0000"; --0 no operations + constant cdec : std_logic_vector(3 downto 0) := "0001"; --1 decode text + constant crdk1 : std_logic_vector(3 downto 0) := "0010"; --2 read key part 1 + constant crdk2 : std_logic_vector(3 downto 0) := "0011"; --3 read key part 2 + constant crdk3 : std_logic_vector(3 downto 0) := "0100"; --4 read key part 3 + constant cmkd : std_logic_vector(3 downto 0) := "0101"; --5 make decrypt key + constant ccod : std_logic_vector(3 downto 0) := "0110"; --6 code text + constant crdt1 : std_logic_vector(3 downto 0) := "0111"; --7 read text part 1 + constant crdt2 : std_logic_vector(3 downto 0) := "1000"; --8 read text part 2 + constant ccto1 : std_logic_vector(3 downto 0) := "1001"; --9 ciphertext output part 1 (LSW) + constant ccto2 : std_logic_vector(3 downto 0) := "1010"; --A ciphertext output part 2 (MSW) + -- For input registers (early version, now for mux's) -- + constant in_ld_reg_L : std_logic_vector(1 downto 0) := "00"; -- Load low part of the register (64 & 80 bit) + constant in_ld_reg_H : std_logic_vector(1 downto 0) := "01"; -- Load high part of the register (64 & 80 bit) + constant in_ld_reg_HH : std_logic_vector(1 downto 0) := "10"; -- Load highest part of the register (80 bit only) + constant in_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) + -- For output register -- + constant out_ld_reg : std_logic_vector(1 downto 0) := "00"; -- Load the output register + constant out_reg_L : std_logic_vector(1 downto 0) := "01"; -- send low part of the register to the output + constant out_reg_H : std_logic_vector(1 downto 0) := "10"; -- senf high part of the register to the output + constant out_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) +end kody; \ No newline at end of file Index: Decode/AsyncMux.vhd =================================================================== --- Decode/AsyncMux.vhd (nonexistent) +++ Decode/AsyncMux.vhd (revision 3) @@ -0,0 +1,50 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23:24:35 06/24/2013 +-- Design Name: +-- Module Name: AsyncMux - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); +end AsyncMux; + +architecture Behavioral of AsyncMux is + +begin + output <= input0 when (ctrl = '0') else + input1; +end Behavioral; + Index: Decode/pLayer_inv.vhd =================================================================== --- Decode/pLayer_inv.vhd (nonexistent) +++ Decode/pLayer_inv.vhd (revision 3) @@ -0,0 +1,99 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:06:24 05/13/2010 +-- Design Name: +-- Module Name: pLayer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer_inv is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer_inv; + +architecture Behavioral of pLayer_inv is +begin + output(0) <= input(0); + output(1) <= input(16); + output(2) <= input(32); + output(3) <= input(48); + output(4) <= input(1); + output(5) <= input(17); + output(6) <= input(33); + output(7) <= input(49); + output(8) <= input(2); + output(9) <= input(18); + output(10) <= input(34); + output(11) <= input(50); + output(12) <= input(3); + output(13) <= input(19); + output(14) <= input(35); + output(15) <= input(51); + output(16) <= input(4); + output(17) <= input(20); + output(18) <= input(36); + output(19) <= input(52); + output(20) <= input(5); + output(21) <= input(21); + output(22) <= input(37); + output(23) <= input(53); + output(24) <= input(6); + output(25) <= input(22); + output(26) <= input(38); + output(27) <= input(54); + output(28) <= input(7); + output(29) <= input(23); + output(30) <= input(39); + output(31) <= input(55); + output(32) <= input(8); + output(33) <= input(24); + output(34) <= input(40); + output(35) <= input(56); + output(36) <= input(9); + output(37) <= input(25); + output(38) <= input(41); + output(39) <= input(57); + output(40) <= input(10); + output(41) <= input(26); + output(42) <= input(42); + output(43) <= input(58); + output(44) <= input(11); + output(45) <= input(27); + output(46) <= input(43); + output(47) <= input(59); + output(48) <= input(12); + output(49) <= input(28); + output(50) <= input(44); + output(51) <= input(60); + output(52) <= input(13); + output(53) <= input(29); + output(54) <= input(45); + output(55) <= input(61); + output(56) <= input(14); + output(57) <= input(30); + output(58) <= input(46); + output(59) <= input(62); + output(60) <= input(15); + output(61) <= input(31); + output(62) <= input(47); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: Decode/PresentKeyGenTB.vhd =================================================================== --- Decode/PresentKeyGenTB.vhd (nonexistent) +++ Decode/PresentKeyGenTB.vhd (revision 3) @@ -0,0 +1,126 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:21:14 06/25/2013 +-- Design Name: +-- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Pure/PresentTB.vhd +-- Project Name: Present_Pure +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: PresentEnc +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentKeyGenTB IS +END PresentKeyGenTB; + +ARCHITECTURE behavior OF PresentKeyGenTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentEncKeyGen + PORT( + key : IN std_logic_vector(79 downto 0); + key_end : OUT std_logic_vector(79 downto 0); + start : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + ready : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal start : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal key_end : std_logic_vector(79 downto 0); + signal ready : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentEncKeyGen PORT MAP ( + key => key, + key_end => key_end, + start => start, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + + reset <= '1'; + start <= '0'; + wait for 100 ns; + reset <= '0'; + + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + assert false severity failure; + + end process; + +END; Index: Decode/PresentEncKeyGen.vhd =================================================================== --- Decode/PresentEncKeyGen.vhd (nonexistent) +++ Decode/PresentEncKeyGen.vhd (revision 3) @@ -0,0 +1,140 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 18:02:34 05/15/2010 +-- Design Name: +-- Module Name: PresentEnc - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: + +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEncKeyGen is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_80: integer := 80 + ); + port( + key : in std_logic_vector(w_80 - 1 downto 0); + key_end : out std_logic_vector(w_80 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEncKeyGen; + +architecture Behavioral of PresentEncKeyGen is + + component Reg is + generic(width : integer := w_80); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 80 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + signal keynum : std_logic_vector (w_5-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + mixer: keyupd port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + key_end <= keyfout; + ready <= ready_sig; +end Behavioral; Index: Decode/slayer_inv.vhd =================================================================== --- Decode/slayer_inv.vhd (nonexistent) +++ Decode/slayer_inv.vhd (revision 3) @@ -0,0 +1,55 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:48:15 05/13/2010 +-- Design Name: +-- Module Name: permutation - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer_inv is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer_inv; + +architecture Behavioral of slayer_inv is + + begin + output <= x"0" when input = x"C" else + x"1" when input = x"5" else + x"2" when input = x"6" else + x"3" when input = x"B" else + x"4" when input = x"9" else + x"5" when input = x"0" else + x"6" when input = x"A" else + x"7" when input = x"D" else + x"8" when input = x"3" else + x"9" when input = x"E" else + x"A" when input = x"F" else + x"B" when input = x"8" else + x"C" when input = x"4" else + x"D" when input = x"7" else + x"E" when input = x"1" else + x"F" when input = x"2" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: Decode/txt_util.vhd =================================================================== --- Decode/txt_util.vhd (nonexistent) +++ Decode/txt_util.vhd (revision 3) @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: Decode/keyupd_inv.vhd =================================================================== --- Decode/keyupd_inv.vhd (nonexistent) +++ Decode/keyupd_inv.vhd (revision 3) @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:45:36 05/13/2010 +-- Design Name: +-- Module Name: keyupd - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd_inv is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd_inv; + +architecture Behavioral of keyupd_inv is + + component slayer_inv is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer_inv port map(input => changin, output => changed); + changin <= key(79 downto 76); + keytemp(79 downto 76)<= changed; + keytemp(75 downto 20) <= key(75 downto 20); + keytemp(19 downto 15)<= key(19 downto 15) xor num; + keytemp(14 downto 0) <= key(14 downto 0); + keyout <= keytemp(60 downto 0) & keytemp(79 downto 61); + end Behavioral; \ No newline at end of file Index: Decode/Reg.vhd =================================================================== --- Decode/Reg.vhd (nonexistent) +++ Decode/Reg.vhd (revision 3) @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23:41:41 06/24/2013 +-- Design Name: +-- Module Name: Reg - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg is + generic(width : integer := 64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end Reg; + +architecture Behavioral of Reg is + +signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); + +begin + clock : process(clk, reset) + begin + if (reset = '1') then + reg <= (others => '0'); + elsif (clk = '1' and clk'Event) then + if (enable = '1') then + reg <= input; + end if; + end if; + end process clock; + output <= reg; +end Behavioral; + Index: Decode/PresentFullDecoderTB.vhd =================================================================== --- Decode/PresentFullDecoderTB.vhd (nonexistent) +++ Decode/PresentFullDecoderTB.vhd (revision 3) @@ -0,0 +1,135 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23:12:57 07/14/2013 +-- Design Name: +-- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Decode/PresentFullDecoderTB.vhd +-- Project Name: PresentDecode +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: PresentFullDecoder +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentFullDecoderTB IS +END PresentFullDecoderTB; + +ARCHITECTURE behavior OF PresentFullDecoderTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentFullDecoder + PORT( + ciphertext : IN std_logic_vector(63 downto 0); + key : IN std_logic_vector(79 downto 0); + plaintext : OUT std_logic_vector(63 downto 0); + start : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + ready : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal ciphertext : std_logic_vector(63 downto 0) := (others => '0'); + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal start : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal plaintext : std_logic_vector(63 downto 0); + signal ready : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentFullDecoder PORT MAP ( + ciphertext => ciphertext, + key => key, + plaintext => plaintext, + start => start, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + + reset <= '1'; + start <= '0'; + ciphertext <= x"5579c1387b228445"; + key <= (others => '0'); + wait for 100 ns; + reset <= '0'; + + ciphertext <= x"5579c1387b228445"; + key <= (others => '0'); + start <= '1'; + wait for clk_period*80; + start <= '0'; + wait for clk_period; + + ciphertext <= x"e72c46c0f5945049"; + key <= (others => '1'); + start <= '1'; + wait for clk_period*80; + start <= '0'; + wait for clk_period; + + ciphertext <= x"a112ffc72f68417b"; + key <= (others => '0'); + start <= '1'; + wait for clk_period*80; + start <= '0'; + wait for clk_period; + + ciphertext <= x"3333dcd3213210d2"; + key <= (others => '1'); + start <= '1'; + wait for clk_period*80; + start <= '0'; + wait for clk_period; + + assert false severity failure; + + end process; + +END; Index: Decode/counter.vhd =================================================================== --- Decode/counter.vhd (nonexistent) +++ Decode/counter.vhd (revision 3) @@ -0,0 +1,49 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:47:04 04/02/2011 +-- Design Name: +-- Module Name: counter - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt + 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: Decode/PresentDecStateMachine.vhd =================================================================== --- Decode/PresentDecStateMachine.vhd (nonexistent) +++ Decode/PresentDecStateMachine.vhd (revision 3) @@ -0,0 +1,104 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:17:10 04/02/2011 +-- Design Name: +-- Module Name: PresentStateMachine - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentDecStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentDecStateMachine; + +architecture Behavioral of PresentDecStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + if (start = '1') then + RegEn <= '1'; + next_state <= SM_START; + else + RegEn <= '0'; + next_state <= NOP; + end if; + when SM_START => + ready <= '0'; + cnt_res <= '1'; + if (start = '1') then + if (num = "11111") then + RegEn <= '1'; + ctrl_mux <= '1'; + next_state <= SM_START; + elsif (num = "00000") then + RegEn <= '0'; + ctrl_mux <= '1'; + next_state <= SM_READY; + else + RegEn <= '1'; + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + RegEn <= '0'; + ctrl_mux <= '0'; + next_state <= NOP; + end if; + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: Decode/PresentDecTB.vhd =================================================================== --- Decode/PresentDecTB.vhd (nonexistent) +++ Decode/PresentDecTB.vhd (revision 3) @@ -0,0 +1,135 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:21:14 06/25/2013 +-- Design Name: +-- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Pure/PresentTB.vhd +-- Project Name: Present_Pure +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: PresentEnc +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentDecTB IS +END PresentDecTB; + +ARCHITECTURE behavior OF PresentDecTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentDec + PORT( + plaintext : IN std_logic_vector(63 downto 0); + key : IN std_logic_vector(79 downto 0); + ciphertext : OUT std_logic_vector(63 downto 0); + start : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + ready : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal plaintext : std_logic_vector(63 downto 0) := (others => '0'); + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal start : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal ciphertext : std_logic_vector(63 downto 0); + signal ready : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentDec PORT MAP ( + plaintext => plaintext, + key => key, + ciphertext => ciphertext, + start => start, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + + reset <= '1'; + start <= '0'; + plaintext <= x"5579c1387b228445"; + key <= x"6dab31744f41d7008759"; + wait for 100 ns; + reset <= '0'; + + plaintext <= x"5579c1387b228445"; + key <= x"6dab31744f41d7008759"; + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= x"e72c46c0f5945049"; + key <= x"fe7a548fb60eb167c511"; + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= x"a112ffc72f68417b"; + key <= x"6dab31744f41d7008759"; + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= x"3333dcd3213210d2"; + key <= x"fe7a548fb60eb167c511"; + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + assert false severity failure; + + end process; + +END; Index: Decode/FullDecoderSM.vhd =================================================================== --- Decode/FullDecoderSM.vhd (nonexistent) +++ Decode/FullDecoderSM.vhd (revision 3) @@ -0,0 +1,104 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:24:13 07/14/2013 +-- Design Name: +-- Module Name: FullDecoderSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FullDecoderSM is + port( + key_gen_start : out std_logic; + key_gen_ready : in std_logic; + decode_start : out std_logic; + decode_ready : in std_logic; + full_decoder_start :in std_logic; + full_decoder_ready : out std_logic; + clk, reset :in std_logic + ); +end FullDecoderSM; + +architecture Behavioral of FullDecoderSM is + + signal state : decode_states; + signal next_state : decode_states; + +begin + + states : process(state, full_decoder_start, key_gen_ready, decode_ready) + begin + case state is + when NOP => + key_gen_start <= '0'; + decode_start <= '0'; + full_decoder_ready <= '0'; + if (full_decoder_start = '1') then + next_state <= KG_START; + else + next_state <= NOP; + end if; + when KG_START => + key_gen_start <= '1'; + decode_start <= '0'; + full_decoder_ready <= '0'; + if (key_gen_ready = '1') then + next_state <= DEC_START; + else + next_state <= KG_START; + end if; + when DEC_START => + key_gen_start <= '1'; + decode_start <= '1'; + full_decoder_ready <= '0'; + if (decode_ready = '1') then + next_state <= DEC_READY; + else + next_state <= DEC_START; + end if; + when DEC_READY => + key_gen_start <= '1'; + decode_start <= '1'; + full_decoder_ready <= '1'; + if (full_decoder_start = '1') then + next_state <= DEC_READY; + else + next_state <= NOP; + end if; + end case; + end process states; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + +end Behavioral; + Index: Decode/PresentFullDecoder.vhd =================================================================== --- Decode/PresentFullDecoder.vhd (nonexistent) +++ Decode/PresentFullDecoder.vhd (revision 3) @@ -0,0 +1,141 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:14:34 07/14/2013 +-- Design Name: +-- Module Name: PresentFullDecoder - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentFullDecoder is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + ciphertext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + plaintext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentFullDecoder; + +architecture Behavioral of PresentFullDecoder is + +component PresentEncKeyGen is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_80: integer := 80 + ); + port( + key : in std_logic_vector(w_80 - 1 downto 0); + key_end : out std_logic_vector(w_80 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentEncKeyGen; + +component PresentDec is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentDec; + +component FullDecoderSM is + port( + key_gen_start : out std_logic; + key_gen_ready : in std_logic; + decode_start : out std_logic; + decode_ready : in std_logic; + full_decoder_start :in std_logic; + full_decoder_ready : out std_logic; + clk, reset :in std_logic + ); +end component FullDecoderSM; + +signal key_gen_output : std_logic_vector(w_80 - 1 downto 0); + +signal key_gen_start : std_logic; +signal key_gen_ready : std_logic; + +signal decode_start : std_logic; +signal decode_ready : std_logic; + +begin + + keyGen : PresentEncKeyGen + port map( + key => key, + key_end => key_gen_output, + start => key_gen_start, + clk => clk, + reset => reset, + ready => key_gen_ready + ); + + decoder : PresentDec + port map( + plaintext => ciphertext, + key => key_gen_output, + ciphertext => plaintext, + start => decode_start, + clk => clk, + reset => reset, + ready => decode_ready + ); + + SM : FullDecoderSM + port map( + key_gen_start => key_gen_start, + key_gen_ready => key_gen_ready, + decode_start => decode_start, + decode_ready => decode_ready, + full_decoder_start => start, + full_decoder_ready => ready, + clk => clk, + reset => reset + ); + +end Behavioral; +--- TODO -- Modyfikacja SM w zwi¹zku ze start i licznikiem (jak w czasie liczenia start = 0!!!) Index: Decode/counter_inv.vhd =================================================================== --- Decode/counter_inv.vhd (nonexistent) +++ Decode/counter_inv.vhd (revision 3) @@ -0,0 +1,49 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:47:04 04/02/2011 +-- Design Name: +-- Module Name: counter - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter_inv is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter_inv; + +architecture Behavioral of counter_inv is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '1'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt - 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: Decode/PresentDec.vhd =================================================================== --- Decode/PresentDec.vhd (nonexistent) +++ Decode/PresentDec.vhd (revision 3) @@ -0,0 +1,186 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 18:02:34 05/15/2010 +-- Design Name: +-- Module Name: PresentEnc - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: + +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentDec is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentDec; + +architecture Behavioral of PresentDec is + + component Reg is + generic(width : integer := w_64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentDecStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + component slayer_inv is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + component pLayer_inv is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + component keyupd_inv is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + component counter_inv is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + mux_64: AsyncMux generic map(width => w_64) port map( + input0 => plaintext, + input1 => Pout, + ctrl => mux_ctrl, + output => textToReg + ); + regText : Reg generic map(width => w_64) port map( + input => textToReg, + output => toXor, + enable => RegEn, + clk => clk, + reset => reset + ); + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + slayers_inv : for N in 15 downto 0 generate + s_x: slayer_inv port map( + input => P(4*N+3 downto 4*N), + output => Pout(4*N+3 downto 4*N) + ); + end generate slayers_inv; + p1: pLayer_inv port map( + input => ciph, + output => P + ); + mixer: keyupd_inv port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentDecStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter_inv port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + ciph <= toXor xor keyfout(79 downto 16); + ciphertext <= ciph; + ready <= ready_sig; +end Behavioral; Index: Decode =================================================================== --- Decode (nonexistent) +++ Decode (revision 3)
Decode Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting/rxtxSerial.dll =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: JavaTests/PresentCommTesting/rxtxSerial.dll =================================================================== --- JavaTests/PresentCommTesting/rxtxSerial.dll (nonexistent) +++ JavaTests/PresentCommTesting/rxtxSerial.dll (revision 3)
JavaTests/PresentCommTesting/rxtxSerial.dll Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: JavaTests/PresentCommTesting/.classpath =================================================================== --- JavaTests/PresentCommTesting/.classpath (nonexistent) +++ JavaTests/PresentCommTesting/.classpath (revision 3) @@ -0,0 +1,9 @@ + + + + + + + + + Index: JavaTests/PresentCommTesting/.project =================================================================== --- JavaTests/PresentCommTesting/.project (nonexistent) +++ JavaTests/PresentCommTesting/.project (revision 3) @@ -0,0 +1,17 @@ + + + PresentCommTesting + + + + + + org.eclipse.jdt.core.javabuilder + + + + + + org.eclipse.jdt.core.javanature + + Index: JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar =================================================================== --- JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar (nonexistent) +++ JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar (revision 3)
JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: JavaTests/PresentCommTesting/lib/RXTXcomm.jar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: JavaTests/PresentCommTesting/lib/RXTXcomm.jar =================================================================== --- JavaTests/PresentCommTesting/lib/RXTXcomm.jar (nonexistent) +++ JavaTests/PresentCommTesting/lib/RXTXcomm.jar (revision 3)
JavaTests/PresentCommTesting/lib/RXTXcomm.jar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: JavaTests/PresentCommTesting/lib =================================================================== --- JavaTests/PresentCommTesting/lib (nonexistent) +++ JavaTests/PresentCommTesting/lib (revision 3)
JavaTests/PresentCommTesting/lib Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java =================================================================== --- JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java (nonexistent) +++ JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java (revision 3) @@ -0,0 +1,90 @@ +package pl.com.kgajewski.serialcomm.datagen; +import java.io.BufferedWriter; +import java.io.File; +import java.io.FileWriter; +import java.io.IOException; + +import org.apache.commons.lang3.StringUtils; + + +public class PresentDataGenerator { + public static void main(String[] args) { + String drive = "e:\\"; + String data = "a112ffc72f68417b"; + String key = "00000000000000000000"; + + String data2 = "3333dcd3213210d2"; + String key2 = "ffffffffffffffffffff"; + + try { + System.out.println("key"); + File f1 = new File(drive + "key.txt"); + f1.createNewFile(); + formatDataFromHex(key, f1); + + System.out.println("data"); + File f2 = new File(drive + "data.txt"); + f1.createNewFile(); + formatDataFromHex(data, f2); + + System.out.println("key2"); + File f3 = new File(drive + "key2.txt"); + f3.createNewFile(); + formatDataFromHex(key2, f3); + + System.out.println("data2"); + File f4 = new File(drive + "data2.txt"); + f4.createNewFile(); + formatDataFromHex(data2, f4); + + } catch (IOException e1) { + // TODO Auto-generated catch block + e1.printStackTrace(); + } + + } + + private static void formatDataFromHex(String str, File f) throws IOException { + BufferedWriter bfw = new BufferedWriter(new FileWriter(f)); + for (int i = str.length(); i > 0; i -= 2) { + String substr = str.substring(i - 2, i); + + parseByteStringHex(bfw, substr); + } + bfw.close(); + } + + private static void parseByteStringHex(BufferedWriter bfw, String str) + throws IOException { + Integer i = Integer.valueOf(str, 16); + String s = Integer.toString(i, 2); + String tmp = ""; + for (int j = 8 - s.length(); j > 0; j--) { + tmp = tmp.concat("0"); + } + parseByteString(bfw, tmp + s); + } + + private static void parseByteString(BufferedWriter bfw, String str) + throws IOException { + int ones = 0; + bfw.write(str); + bfw.write("\n"); + str = StringUtils.reverse(str); + + for (int j = 0; j < str.length(); j++) { + bfw.write(str.charAt(j)); + bfw.write("\n"); + if (str.charAt(j) == '1') { + ones++; + } + } + if (ones % 2 == 1) { + bfw.write("0"); + } else { + bfw.write("1"); + } + bfw.write("\n"); + } + +} Index: JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen =================================================================== --- JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen (nonexistent) +++ JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen (revision 3)
JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java =================================================================== --- JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java (nonexistent) +++ JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java (revision 3) @@ -0,0 +1,261 @@ +package pl.com.kgajewski.serialcomm.gui; + +import gnu.io.CommPort; +import gnu.io.CommPortIdentifier; +import gnu.io.PortInUseException; +import gnu.io.SerialPort; +import gnu.io.SerialPortEvent; +import gnu.io.SerialPortEventListener; + +import java.io.IOException; +import java.io.InputStream; +import java.io.OutputStream; +import java.math.BigInteger; +import java.util.Enumeration; +import java.util.HashMap; +import java.util.TooManyListenersException; + +import org.apache.commons.lang3.ArrayUtils; +import org.apache.commons.lang3.StringUtils; +import org.eclipse.swt.graphics.Color; + +public class Communication implements SerialPortEventListener { + + //passed from main GUI + Window window = null; + + // just a boolean flag that i use for enabling + // and disabling buttons depending on whether the program + // is connected to a serial port or not + private boolean bConnected = false; + + // the timeout value for connecting with the port + final static int TIMEOUT = 2000; + + // for containing the ports that will be found + private Enumeration ports = null; + // map the port names to CommPortIdentifiers + private HashMap portMap = new HashMap(); + + // this is the object that contains the opened port + private CommPortIdentifier selectedPortIdentifier = null; + private SerialPort serialPort = null; + + // input and output streams for sending and receiving data + private InputStream input = null; + private OutputStream output = null; + + public Communication(Window window) { + this.window = window; + } + + // a string for recording what goes on in the program + // this string is written to the GUI + String logText = ""; + + // search for all the serial ports + // pre style="font-size: 11px;": none + // post: adds all the found ports to a combo box on the GUI + public void searchForPorts() { + ports = CommPortIdentifier.getPortIdentifiers(); + + while (ports.hasMoreElements()) { + CommPortIdentifier curPort = (CommPortIdentifier) ports + .nextElement(); + + // get only serial ports + if (curPort.getPortType() == CommPortIdentifier.PORT_SERIAL) { + window.combo.add(curPort.getName()); + portMap.put(curPort.getName(), curPort); + } + } + } + + // connect to the selected port in the combo box + // pre style="font-size: 11px;": ports are already found by using the + // searchForPorts + // method + // post: the connected comm port is stored in commPort, otherwise, + // an exception is generated + public void connect() { + if (window.combo.getSelectionIndex() >= 0) { + String selectedPort = (String) window.combo.getItem(window.combo.getSelectionIndex()); + selectedPortIdentifier = (CommPortIdentifier) portMap + .get(selectedPort); + + CommPort commPort = null; + + try { + // the method below returns an object of type CommPort + commPort = selectedPortIdentifier.open("pl.com.kgajewski.cerialcomm", + TIMEOUT); + // the CommPort object can be casted to a SerialPort object + serialPort = (SerialPort) commPort; + serialPort.setSerialPortParams(115200,SerialPort.DATABITS_8,SerialPort.STOPBITS_1,SerialPort.PARITY_ODD); + + // for controlling GUI elements + setConnected(true); + + // logging + logText = selectedPort + " opened successfully."; + window.text.setForeground(new Color(window.shell.getDisplay(), 0, 0, 0)); + window.appendText(logText + "\n"); + + // CODE ON SETTING BAUD RATE ETC OMITTED + // XBEE PAIR ASSUMED TO HAVE SAME SETTINGS ALREADY + + // enables the controls on the GUI if a successful connection is + // made + window.toggleControls(); + + } catch (PortInUseException e) { + logText = selectedPort + " is in use. (" + e.toString() + ")"; + + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } catch (Exception e) { + logText = "Failed to open " + selectedPort + "(" + e.toString() + + ")"; + window.appendText(logText + "\n"); + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + } + } + } + // open the input and output streams + // pre style="font-size: 11px;": an open port + // post: initialized input and output streams for use to communicate data + public boolean initIOStream() { + // return value for whether opening the streams is successful or not + boolean successful = false; + + try { + // + input = serialPort.getInputStream(); + output = serialPort.getOutputStream(); + + successful = true; + return successful; + } catch (IOException e) { + logText = "I/O Streams failed to open. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + return successful; + } + } + + // starts the event listener that knows whenever data is available to be + // read + // pre style="font-size: 11px;": an open serial port + // post: an event listener for the serial port that knows when data is + // received + public void initListener() { + try { + serialPort.addEventListener(this); + serialPort.notifyOnDataAvailable(true); + } catch (TooManyListenersException e) { + logText = "Too many listeners. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + //disconnect the serial port + //pre style="font-size: 11px;": an open serial port + //post: closed serial port + public void disconnect() + { + //close the serial port + try + { + serialPort.removeEventListener(); + serialPort.close(); + input.close(); + output.close(); + setConnected(false); + window.toggleControls(); + + logText = "Disconnected."; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + catch (Exception e) + { + logText = "Failed to close " + serialPort.getName() + + "(" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + //what happens when data is received + //pre style="font-size: 11px;": serial event is triggered + //post: processing on the data it reads + public void serialEvent(SerialPortEvent evt) { + if (evt.getEventType() == SerialPortEvent.DATA_AVAILABLE) + { + try + { + byte [] buffer = new byte[10]; + int n = input.read(buffer); + if (n > 0) + { + if (n == 1) { + BigInteger command = new BigInteger(new byte []{0, buffer[0]}); + final String s = "Command = " + command.toString(16) + "\n"; + window.appendText(s); + } else { + buffer = ArrayUtils.subarray(buffer, 0, buffer.length - 2); + buffer = ArrayUtils.add(buffer, (byte)0); + ArrayUtils.reverse(buffer); + BigInteger data = new BigInteger(buffer); + window.appendText(data.toString(16) + "\n"); + } + } + else + { + window.appendText("\n"); + } + } + catch (Exception e) + { + logText = "Failed to read data. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + } + + //method that can be called to send data + //pre style="font-size: 11px;": open serial port + //post: data sent to the other device + public void writeData(String str) + { + try + { + for (int i = str.length()-1; i > 0; i -= 2) { + String s = str.substring(i-1, i+1); + byte b = (byte)(Integer.parseInt(s, 16) & 0xFF); + output.write(b); + Thread.sleep(1); + } + } + catch (Exception e) + { + logText = "Failed to write data. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + final public boolean getConnected() + { + return bConnected; + } + + public void setConnected(boolean bConnected) + { + this.bConnected = bConnected; + } + + +} Index: JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java =================================================================== --- JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java (nonexistent) +++ JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java (revision 3) @@ -0,0 +1,159 @@ +package pl.com.kgajewski.serialcomm.gui; + +import org.eclipse.swt.SWT; +import org.eclipse.swt.events.MouseAdapter; +import org.eclipse.swt.events.MouseEvent; +import org.eclipse.swt.widgets.Button; +import org.eclipse.swt.widgets.Combo; +import org.eclipse.swt.widgets.Composite; +import org.eclipse.swt.widgets.Display; +import org.eclipse.swt.widgets.Label; +import org.eclipse.swt.widgets.Shell; +import org.eclipse.swt.widgets.Text; + +public class Window { + + //Communicator object + Communication communication = null; + public Display display; + protected Shell shell; + public Text text; + private Text data; + private Text key; + public Combo combo; + private Button btnConnect; + private Button btnDisconnect; + private Button btnSendData; + + public void toggleControls() + { + if (communication.getConnected() == true) + { + btnDisconnect.setEnabled(true); + btnConnect.setEnabled(false); + btnSendData.setEnabled(true); + } + else + { + btnDisconnect.setEnabled(false); + btnConnect.setEnabled(true); + btnSendData.setEnabled(false); + } + } + + /** + * Launch the application. + * + * @param args + */ + public static void main(String[] args) { + try { + Window window = new Window(); + window.open(); + } catch (Exception e) { + e.printStackTrace(); + } + } + + /** + * Open the window. + */ + public void open() { + display = Display.getDefault(); + createContents(); + communication = new Communication(this); + communication.searchForPorts(); + toggleControls(); + shell.open(); + shell.layout(); + while (!shell.isDisposed()) { + if (!display.readAndDispatch()) { + display.sleep(); + } + } + } + + /** + * Create contents of the window. + */ + protected void createContents() { + shell = new Shell(); + shell.setSize(470, 274); + shell.setText("SWT Application"); + shell.setLayout(null); + + Composite composite = new Composite(shell, SWT.NONE); + composite.setBounds(0, 0, 444, 236); + + text = new Text(composite, SWT.BORDER | SWT.MULTI); + this.text.setBounds(107, 126, 327, 105); + + combo = new Combo(composite, SWT.NONE); + combo.setBounds(10, 10, 91, 23); + + btnConnect = new Button(composite, SWT.NONE); + btnConnect.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.connect(); + if (communication.getConnected() == true) + { + if (communication.initIOStream() == true) + { + communication.initListener(); + } + } + } + }); + btnConnect.setBounds(107, 10, 75, 25); + btnConnect.setText("Connect"); + + btnDisconnect = new Button(composite, SWT.NONE); + btnDisconnect.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.disconnect(); + } + }); + btnDisconnect.setBounds(188, 10, 75, 25); + btnDisconnect.setText("Disconnect"); + + Label lblLog = new Label(composite, SWT.NONE); + lblLog.setBounds(107, 105, 186, 15); + lblLog.setText("Log"); + + data = new Text(composite, SWT.BORDER); + data.setBounds(45, 39, 248, 21); + + key = new Text(composite, SWT.BORDER); + key.setBounds(45, 66, 248, 21); + + btnSendData = new Button(composite, SWT.NONE); + btnSendData.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.writeData(data.getText()); + communication.writeData(key.getText()); + } + }); + btnSendData.setBounds(10, 100, 75, 25); + btnSendData.setText("Send"); + + Label lblData = new Label(composite, SWT.NONE); + lblData.setBounds(10, 39, 29, 15); + lblData.setText("Data"); + + Label lblKey = new Label(composite, SWT.NONE); + lblKey.setBounds(10, 66, 55, 15); + lblKey.setText("Key"); + } + + public void appendText(final String s) { + display.syncExec(new Runnable() { + public void run() { + text.append(s); + } + }); + + } +} Index: JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui =================================================================== --- JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui (nonexistent) +++ JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui (revision 3)
JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm =================================================================== --- JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm (nonexistent) +++ JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm (revision 3)
JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting/src/pl/com/kgajewski =================================================================== --- JavaTests/PresentCommTesting/src/pl/com/kgajewski (nonexistent) +++ JavaTests/PresentCommTesting/src/pl/com/kgajewski (revision 3)
JavaTests/PresentCommTesting/src/pl/com/kgajewski Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting/src/pl/com =================================================================== --- JavaTests/PresentCommTesting/src/pl/com (nonexistent) +++ JavaTests/PresentCommTesting/src/pl/com (revision 3)
JavaTests/PresentCommTesting/src/pl/com Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting/src/pl =================================================================== --- JavaTests/PresentCommTesting/src/pl (nonexistent) +++ JavaTests/PresentCommTesting/src/pl (revision 3)
JavaTests/PresentCommTesting/src/pl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting/src =================================================================== --- JavaTests/PresentCommTesting/src (nonexistent) +++ JavaTests/PresentCommTesting/src (revision 3)
JavaTests/PresentCommTesting/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting/bin =================================================================== --- JavaTests/PresentCommTesting/bin (nonexistent) +++ JavaTests/PresentCommTesting/bin (revision 3)
JavaTests/PresentCommTesting/bin Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting/rxtxParallel.dll =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: JavaTests/PresentCommTesting/rxtxParallel.dll =================================================================== --- JavaTests/PresentCommTesting/rxtxParallel.dll (nonexistent) +++ JavaTests/PresentCommTesting/rxtxParallel.dll (revision 3)
JavaTests/PresentCommTesting/rxtxParallel.dll Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs =================================================================== --- JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs (nonexistent) +++ JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs (revision 3) @@ -0,0 +1,11 @@ +eclipse.preferences.version=1 +org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled +org.eclipse.jdt.core.compiler.codegen.targetPlatform=1.6 +org.eclipse.jdt.core.compiler.codegen.unusedLocal=preserve +org.eclipse.jdt.core.compiler.compliance=1.6 +org.eclipse.jdt.core.compiler.debug.lineNumber=generate +org.eclipse.jdt.core.compiler.debug.localVariable=generate +org.eclipse.jdt.core.compiler.debug.sourceFile=generate +org.eclipse.jdt.core.compiler.problem.assertIdentifier=error +org.eclipse.jdt.core.compiler.problem.enumIdentifier=error +org.eclipse.jdt.core.compiler.source=1.6 Index: JavaTests/PresentCommTesting/.settings =================================================================== --- JavaTests/PresentCommTesting/.settings (nonexistent) +++ JavaTests/PresentCommTesting/.settings (revision 3)
JavaTests/PresentCommTesting/.settings Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests/PresentCommTesting =================================================================== --- JavaTests/PresentCommTesting (nonexistent) +++ JavaTests/PresentCommTesting (revision 3)
JavaTests/PresentCommTesting Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: JavaTests =================================================================== --- JavaTests (nonexistent) +++ JavaTests (revision 3)
JavaTests Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/slayer.vhd =================================================================== --- PureTesting/slayer.vhd (nonexistent) +++ PureTesting/slayer.vhd (revision 3) @@ -0,0 +1,55 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:48:15 05/13/2010 +-- Design Name: +-- Module Name: permutation - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: PureTesting/ShiftRegTB.vhd =================================================================== --- PureTesting/ShiftRegTB.vhd (nonexistent) +++ PureTesting/ShiftRegTB.vhd (revision 3) @@ -0,0 +1,119 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:11:18 10/08/2012 +-- Design Name: +-- Module Name: E:/spent i praca/OpenCores/mRSAKeyFinalizer/ShiftRegTB.vhd +-- Project Name: mRSAKeyFinalizer +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: ShiftReg +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +use work.RSAFinalizerProperties.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY ShiftRegTB IS +END ShiftRegTB; + +ARCHITECTURE behavior OF ShiftRegTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT ShiftReg +-- generic (length_1 : integer := WORD_LENGTH; +-- length_2 : integer := BYTE + GENERIC ( + length_1 : integer := BYTE; + length_2 : integer := WORD_LENGTH + ); + PORT( + input : in STD_LOGIC_VECTOR(7 downto 0); + --input : IN std_logic_vector(63 downto 0); + output : out STD_LOGIC_VECTOR(63 downto 0); + --output : OUT std_logic_vector(7 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + END COMPONENT; + + + --Inputs + signal input : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + --signal input : std_logic_vector(63 downto 0) := (others => '0'); + signal en : STD_LOGIC := '0'; + signal shift : STD_LOGIC := '0'; + signal clk : STD_LOGIC := '0'; + signal reset : STD_LOGIC := '0'; + + --Outputs + signal output : STD_LOGIC_VECTOR(63 downto 0); + --signal output : std_logic_vector(7 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: ShiftReg PORT MAP ( + input => input, + output => output, + en => en, + shift => shift, + clk => clk, + reset => reset + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + reset <= '0'; + shift <= '0'; + input <= "10101010"; + --input <= "1111000011110000111100001111000011110000111100001111000011110000"; + wait for 100 ns; + reset <= '1'; + wait for clk_period*10; + en <= '1'; + wait for clk_period*1; + en <= '0'; + wait for clk_period*1; + shift <= '1'; + wait for clk_period*10; + assert false severity failure; + end process; + +END; Index: PureTesting/keyupd.vhd =================================================================== --- PureTesting/keyupd.vhd (nonexistent) +++ PureTesting/keyupd.vhd (revision 3) @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:45:36 05/13/2010 +-- Design Name: +-- Module Name: keyupd - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: PureTesting/PresentTB.vhd =================================================================== --- PureTesting/PresentTB.vhd (nonexistent) +++ PureTesting/PresentTB.vhd (revision 3) @@ -0,0 +1,133 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:21:14 06/25/2013 +-- Design Name: +-- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Pure/PresentTB.vhd +-- Project Name: Present_Pure +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: PresentEnc +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentTB IS +END PresentTB; + +ARCHITECTURE behavior OF PresentTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentEnc + PORT( + plaintext : IN std_logic_vector(63 downto 0); + key : IN std_logic_vector(79 downto 0); + ciphertext : OUT std_logic_vector(63 downto 0); + start : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + ready : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal plaintext : std_logic_vector(63 downto 0) := (others => '0'); + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal start : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal ciphertext : std_logic_vector(63 downto 0); + signal ready : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentEnc PORT MAP ( + plaintext => plaintext, + key => key, + ciphertext => ciphertext, + start => start, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + + reset <= '1'; + start <= '0'; + wait for 100 ns; + reset <= '0'; + + plaintext <= (others => '0'); + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '0'); + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '1'); + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '1'); + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + assert false severity failure; + + end process; + +END; Index: PureTesting/PresentStateMachine.vhd =================================================================== --- PureTesting/PresentStateMachine.vhd (nonexistent) +++ PureTesting/PresentStateMachine.vhd (revision 3) @@ -0,0 +1,100 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:17:10 04/02/2011 +-- Design Name: +-- Module Name: PresentStateMachine - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + RegEn <= '0'; + if (start = '1') then + next_state <= SM_START; + else + next_state <= NOP; + end if; + when SM_START => + ready <= '0'; + RegEn <= '1'; + cnt_res <= '1'; + if (start = '1') then + if (num = "00000") then + ctrl_mux <= '0'; + next_state <= SM_START; + elsif (num = "11111") then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: PureTesting/PresentEnc.vhd =================================================================== --- PureTesting/PresentEnc.vhd (nonexistent) +++ PureTesting/PresentEnc.vhd (revision 3) @@ -0,0 +1,186 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 18:02:34 05/15/2010 +-- Design Name: +-- Module Name: PresentEnc - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: + +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEnc is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEnc; + +architecture Behavioral of PresentEnc is + + component Reg is + generic(width : integer := w_64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + component slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + component pLayer is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + mux_64: AsyncMux generic map(width => w_64) port map( + input0 => plaintext, + input1 => Pout, + ctrl => mux_ctrl, + output => textToReg + ); + regText : Reg generic map(width => w_64) port map( + input => textToReg, + output => toXor, + enable => RegEn, + clk => clk, + reset => reset + ); + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + slayers : for N in 15 downto 0 generate + s_x: slayer port map( + input => ciph(4*N+3 downto 4*N), + output => P(4*N+3 downto 4*N) + ); + end generate slayers; + p1: pLayer port map( + input => P, + output => Pout + ); + mixer: keyupd port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + ciph <= toXor xor keyfout(79 downto 16); + ciphertext <= ciph; + ready <= ready_sig; +end Behavioral; Index: PureTesting/kody.vhd =================================================================== --- PureTesting/kody.vhd (nonexistent) +++ PureTesting/kody.vhd (revision 3) @@ -0,0 +1,15 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, SM_START, SM_READY); + type stany_comm is (NOP, READ_DATA_KEY, DECODE_READ_KEY, MOVE_KEY, TEMP_STATE, TEMP2_STATE, TEMP_OUT, + NOP_FOR_KEY, READ_DATA_TEXT, DECODE_READ_TEXT, MOVE_TEXT, + PRESENT_ENCODE, WRITE_OUT, MOVE_OUT); +end kody; \ No newline at end of file Index: PureTesting/AsyncMux.vhd =================================================================== --- PureTesting/AsyncMux.vhd (nonexistent) +++ PureTesting/AsyncMux.vhd (revision 3) @@ -0,0 +1,50 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23:24:35 06/24/2013 +-- Design Name: +-- Module Name: AsyncMux - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); +end AsyncMux; + +architecture Behavioral of AsyncMux is + +begin + output <= input0 when (ctrl = '0') else + input1; +end Behavioral; + Index: PureTesting/PresentCommImpl.ucf =================================================================== --- PureTesting/PresentCommImpl.ucf (nonexistent) +++ PureTesting/PresentCommImpl.ucf (revision 3) @@ -0,0 +1,7 @@ +NET "DATA_RXD" LOC= "R7" | IOSTANDARD= LVTTL | SLEW= FAST ; +NET "DATA_TXD" LOC= "M14" | IOSTANDARD= LVTTL | DRIVE= 8 | SLEW= FAST ; +NET "CLK" LOC= "C9" | IOSTANDARD= LVCMOS33 | SLEW= FAST ; +NET "CLK" TNM_NET = "clk_group"; +TIMESPEC "TS_CLK" = PERIOD "clk_group" 20 ns HIGH 40%; +NET "RESET" LOC= "K17" | IOSTANDARD= LVTTL | PULLDOWN; +SYSTEM_JITTER = 1 ns; \ No newline at end of file Index: PureTesting/ShiftReg.vhd =================================================================== --- PureTesting/ShiftReg.vhd (nonexistent) +++ PureTesting/ShiftReg.vhd (revision 3) @@ -0,0 +1,70 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:39:23 10/08/2012 +-- Design Name: +-- Module Name: ShiftReg - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ShiftReg is + generic ( + length_1 : integer := 8; + length_2 : integer := 64; + internal_data : integer := 64 + ); + port ( + input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); + output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end ShiftReg; + +architecture Behavioral of ShiftReg is + +signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0); + +begin + reg : process (clk, reset, data) + begin + if (clk'event and clk = '1') then + if (reset = '1') then + data <= (others => '0'); + elsif (en = '1') then + data(internal_data - 1 downto internal_data - length_1) <= input; + else + if (shift = '1') then + data <= '0' & data(internal_data - 1 downto 1); + end if; + end if; + end if; + output <= data(length_2 - 1 downto 0); + end process reg; + +end Behavioral; + Index: PureTesting/txt_util.vhd =================================================================== --- PureTesting/txt_util.vhd (nonexistent) +++ PureTesting/txt_util.vhd (revision 3) @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: PureTesting/Reg.vhd =================================================================== --- PureTesting/Reg.vhd (nonexistent) +++ PureTesting/Reg.vhd (revision 3) @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23:41:41 06/24/2013 +-- Design Name: +-- Module Name: Reg - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg is + generic(width : integer := 64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end Reg; + +architecture Behavioral of Reg is + +signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); + +begin + clock : process(clk, reset) + begin + if (reset = '1') then + reg <= (others => '0'); + elsif (clk = '1' and clk'Event) then + if (enable = '1') then + reg <= input; + end if; + end if; + end process clock; + output <= reg; +end Behavioral; + Index: PureTesting/counter.vhd =================================================================== --- PureTesting/counter.vhd (nonexistent) +++ PureTesting/counter.vhd (revision 3) @@ -0,0 +1,49 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:47:04 04/02/2011 +-- Design Name: +-- Module Name: counter - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt + 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: PureTesting/PresentCommTB.vhd =================================================================== --- PureTesting/PresentCommTB.vhd (nonexistent) +++ PureTesting/PresentCommTB.vhd (revision 3) @@ -0,0 +1,346 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:26:35 07/05/2013 +-- Design Name: +-- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Testing/VHDL/PresentCommTB.vhd +-- Project Name: PresentComm +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: PresentComm +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE std.textio.all; +USE work.txt_util.all; +USE ieee.std_logic_textio.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentCommTB IS +END PresentCommTB; + +ARCHITECTURE behavior OF PresentCommTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentComm + PORT( + DATA_RXD : IN std_logic; + CLK : IN std_logic; + RESET : IN std_logic; + DATA_TXD : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal DATA_RXD : std_logic := '0'; + signal CLK : std_logic := '0'; + signal RESET : std_logic := '0'; + + --Outputs + signal DATA_TXD : std_logic; + + -- Clock period definitions + constant CLK_period : time := 20 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentComm PORT MAP ( + DATA_RXD => DATA_RXD, + CLK => CLK, + RESET => RESET, + DATA_TXD => DATA_TXD + ); + + -- Clock process definitions + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + + -- Stimulus process + stim_proc: process + + file txt :text is in "test/data.txt"; + file key :text is in "test/key.txt"; + file txt2 :text is in "test/data2.txt"; + file key2 :text is in "test/key2.txt"; + + variable line_in : line; + variable line_content : string(1 to 8); + variable data : STD_LOGIC; + + begin + + DATA_RXD <= '1'; + RESET <= '1'; + wait for 1000 ns; + RESET <= '0'; + + wait for CLK_period*10; + + while not (endfile(txt)) loop + readline(txt, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "Koniec bajtu"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + while not (endfile(key)) loop + readline(key, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "Koniec bajtu"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + wait for 2000 us; + + while not (endfile(txt2)) loop + readline(txt2, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "Koniec bajtu"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + while not (endfile(key2)) loop + readline(key2, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "Koniec bajtu"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + wait for 2000 us; + + assert false severity failure; + end process; + +END; Index: PureTesting/sLayerTB.vhd =================================================================== --- PureTesting/sLayerTB.vhd (nonexistent) +++ PureTesting/sLayerTB.vhd (revision 3) @@ -0,0 +1,95 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:11:33 05/16/2010 +-- Design Name: +-- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/sLayerTB.vhd +-- Project Name: szyfrator +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: slayer +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY sLayerTB IS +END sLayerTB; + +ARCHITECTURE behavior OF sLayerTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT slayer + PORT( + input : IN std_logic_vector(3 downto 0); + output : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --BiDirs + signal input : std_logic_vector(3 downto 0); + signal output : std_logic_vector(3 downto 0); + + -- Clock period definitions + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: slayer PORT MAP ( + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <= '0'; + wait for clk_period; + input <= x"0"; + wait for clk_period; + input <= x"A"; + wait for clk_period; + input <= x"F"; + wait for clk_period; + -- insert stimulus here + assert false severity failure; + end process; + +END; \ No newline at end of file Index: PureTesting/keyupdTB.vhd =================================================================== --- PureTesting/keyupdTB.vhd (nonexistent) +++ PureTesting/keyupdTB.vhd (revision 3) @@ -0,0 +1,106 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:00:18 05/16/2010 +-- Design Name: +-- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/keyupdTB.vhd +-- Project Name: szyfrator +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: keyupd +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY keyupdTB IS +END keyupdTB; + +ARCHITECTURE behavior OF keyupdTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT keyupd + PORT( + key : IN std_logic_vector(79 downto 0); + num : IN std_logic_vector(4 downto 0); + keyout : OUT std_logic_vector(79 downto 0)--; + --clk, reset : std_logic + ); + END COMPONENT; + + + --Inputs + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal num : std_logic_vector(4 downto 0) := (others => '0'); + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal keyout : std_logic_vector(79 downto 0); + + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: keyupd PORT MAP ( + key => key, + num => num, + keyout => keyout--, + --clk => clk, + --reset => reset + ); + + -- No clocks detected in port list. Replace clk below with + -- appropriate port name + + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <='0'; + wait for clk_period; + key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + num <= "00001"; + wait for clk_period; + key <= x"c0000000000000008000"; + num <= "00010"; + wait for clk_period; + key <= x"50001800000000010000"; + num <= "00011"; + wait for clk_period; + key <= x"8ba27a0eb8783ac96d59"; + num <= "11111"; + wait for clk_period; + assert false severity failure; + end process; +END; \ No newline at end of file Index: PureTesting/RS232RefComp.vhd =================================================================== --- PureTesting/RS232RefComp.vhd (nonexistent) +++ PureTesting/RS232RefComp.vhd (revision 3) @@ -0,0 +1,406 @@ +------------------------------------------------------------------------ +-- RS232RefCom.vhd +------------------------------------------------------------------------ +-- Author: Dan Pederson +-- Copyright 2004 Digilent, Inc. +------------------------------------------------------------------------ +-- Description: This file defines a UART which tranfers data from +-- serial form to parallel form and vice versa. +------------------------------------------------------------------------ +-- Revision History: +-- 07/15/04 (Created) DanP +-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant +-- in the Clock Dividing Processes +------------------------------------------------------------------------ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Rs232RefComp is + Port ( + TXD : out std_logic := '1'; + RXD : in std_logic; + CLK : in std_logic; --Master Clock + DBIN : in std_logic_vector (7 downto 0); --Data Bus in + DBOUT : out std_logic_vector (7 downto 0); --Data Bus out + RDA : inout std_logic; --Read Data Available + TBE : inout std_logic := '1'; --Transfer Bus Empty + RD : in std_logic; --Read Strobe + WR : in std_logic; --Write Strobe + PE : out std_logic; --Parity Error Flag + FE : out std_logic; --Frame Error Flag + OE : out std_logic; --Overwrite Error Flag + RST : in std_logic := '0'); --Master Reset +end Rs232RefComp; + +architecture Behavioral of Rs232RefComp is +------------------------------------------------------------------------ +-- Component Declarations +------------------------------------------------------------------------ + +------------------------------------------------------------------------ +-- Local Type Declarations +------------------------------------------------------------------------ + --Receive state machine + type rstate is ( + strIdle, --Idle state + strEightDelay, --Delays for 8 clock cycles + strGetData, --Shifts in the 8 data bits, and checks parity + strCheckStop --Sets framing error flag if Stop bit is wrong + ); + + type tstate is ( + sttIdle, --Idle state + sttTransfer, --Move data into shift register + sttShift --Shift out data + ); + + type TBEstate is ( + stbeIdle, + stbeSetTBE, + stbeWaitLoad, + stbeWaitWrite + ); + + +------------------------------------------------------------------------ +-- Signal Declarations +------------------------------------------------------------------------ + constant baudDivide : std_logic_vector(7 downto 0) := "00001101"; --Baud Rate dividor, set now for a rate of 9600. + --Found by dividing 50MHz by 9600 and 16. + signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register + signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register + signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register + signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register + signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk + signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk + signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times + signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer + signal rClk : std_logic := '0'; --Receiving Clock + signal tClk : std_logic; --Transfering Clock + signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits + signal parError: std_logic; --Parity error bit + signal frameError: std_logic; --Frame error bit + signal CE : std_logic; --Clock enable for the latch + signal ctRst : std_logic := '0'; + signal load : std_logic := '0'; + signal shift : std_logic := '0'; + signal par : std_logic; + signal tClkRST : std_logic := '0'; + signal rShift : std_logic := '0'; + signal dataRST : std_logic := '0'; + signal dataIncr: std_logic := '0'; + + signal strCur : rstate := strIdle; --Current state in the Receive state machine + signal strNext : rstate; --Next state in the Receive state machine + signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine + signal sttNext : tstate; --Next state in the Transfer staet machine + signal stbeCur : TBEstate := stbeIdle; + signal stbeNext: TBEstate; + +------------------------------------------------------------------------ +-- Module Implementation +------------------------------------------------------------------------ + +begin + frameError <= not rdSReg(9); + parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) ); + DBOUT <= rdReg; + tfReg <= DBIN; + par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) ); + +--Clock Dividing Functions-- + + process (CLK, clkDiv) --set up clock divide for rClk + begin + if (Clk = '1' and Clk'event) then + if (clkDiv = baudDivide) then + clkDiv <= "000000000"; + else + clkDiv <= clkDiv +1; + end if; + end if; + end process; + + process (clkDiv, rClk, CLK) --Define rClk + begin + if CLK = '1' and CLK'Event then + if clkDiv = baudDivide then + rClk <= not rClk; + else + rClk <= rClk; + end if; + end if; + end process; + + process (rClk) --set up clock divide for tClk + begin + if (rClk = '1' and rClk'event) then + rClkDiv <= rClkDiv +1; + end if; + end process; + + tClk <= rClkDiv(3); --define tClk + + process (rClk, ctRst) --set up a counter based on rClk + begin + if rClk = '1' and rClk'Event then + if ctRst = '1' then + ctr <= "0000"; + else + ctr <= ctr +1; + end if; + end if; + end process; + + process (tClk, tClkRST) --set up a counter based on tClk + begin + if (tClk = '1' and tClk'event) then + if tClkRST = '1' then + tfCtr <= "0000"; + else + tfCtr <= tfCtr +1; + end if; + end if; + end process; + + --This process controls the error flags-- + process (rClk, RST, RD, CE) + begin + if RD = '1' or RST = '1' then + FE <= '0'; + OE <= '0'; + RDA <= '0'; + PE <= '0'; + elsif rClk = '1' and rClk'event then + if CE = '1' then + FE <= frameError; + OE <= RDA; + RDA <= '1'; + PE <= parError; + rdReg(7 downto 0) <= rdSReg (7 downto 0); + end if; + end if; + end process; + + --This process controls the receiving shift register-- + process (rClk, rShift) + begin + if rClk = '1' and rClk'Event then + if rShift = '1' then + rdSReg <= (RXD & rdSReg(9 downto 1)); + end if; + end if; + end process; + + --This process controls the dataCtr to keep track of shifted values-- + process (rClk, dataRST) + begin + if (rClk = '1' and rClk'event) then + if dataRST = '1' then + dataCtr <= "0000"; + elsif dataIncr = '1' then + dataCtr <= dataCtr +1; + end if; + end if; + end process; + + --Receiving State Machine-- + process (rClk, RST) + begin + if rClk = '1' and rClk'Event then + if RST = '1' then + strCur <= strIdle; + else + strCur <= strNext; + end if; + end if; + end process; + + --This process generates the sequence of steps needed receive the data + + process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA) + begin + case strCur is + + when strIdle => + dataIncr <= '0'; + rShift <= '0'; + dataRst <= '0'; + + CE <= '0'; + if RXD = '0' then + ctRst <= '1'; + strNext <= strEightDelay; + else + ctRst <= '0'; + strNext <= strIdle; + end if; + + when strEightDelay => + dataIncr <= '0'; + rShift <= '0'; + CE <= '0'; + + if ctr(2 downto 0) = "111" then + ctRst <= '1'; + dataRST <= '1'; + strNext <= strGetData; + else + ctRst <= '0'; + dataRST <= '0'; + strNext <= strEightDelay; + end if; + + when strGetData => + CE <= '0'; + dataRst <= '0'; + if ctr(3 downto 0) = "1111" then + ctRst <= '1'; + dataIncr <= '1'; + rShift <= '1'; + else + ctRst <= '0'; + dataIncr <= '0'; + rShift <= '0'; + end if; + + if dataCtr = "1010" then + strNext <= strCheckStop; + else + strNext <= strGetData; + end if; + + when strCheckStop => + dataIncr <= '0'; + rShift <= '0'; + dataRst <= '0'; + ctRst <= '0'; + + CE <= '1'; + strNext <= strIdle; + + end case; + + end process; + + --TBE State Machine-- + process (CLK, RST) + begin + if CLK = '1' and CLK'Event then + if RST = '1' then + stbeCur <= stbeIdle; + else + stbeCur <= stbeNext; + end if; + end if; + end process; + + --This process gererates the sequence of events needed to control the TBE flag-- + process (stbeCur, CLK, WR, DBIN, load) + begin + + case stbeCur is + + when stbeIdle => + TBE <= '1'; + if WR = '1' then + stbeNext <= stbeSetTBE; + else + stbeNext <= stbeIdle; + end if; + + when stbeSetTBE => + TBE <= '0'; + if load = '1' then + stbeNext <= stbeWaitLoad; + else + stbeNext <= stbeSetTBE; + end if; + + when stbeWaitLoad => + if load = '0' then + stbeNext <= stbeWaitWrite; + else + stbeNext <= stbeWaitLoad; + end if; + + when stbeWaitWrite => + if WR = '0' then + stbeNext <= stbeIdle; + else + stbeNext <= stbeWaitWrite; + end if; + end case; + end process; + + --This process loads and shifts out the transfer shift register-- + process (load, shift, tClk, tfSReg) + begin + TXD <= tfsReg(0); + if tClk = '1' and tClk'Event then + if load = '1' then + tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0'); + end if; + if shift = '1' then + + tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1)); + end if; + end if; + end process; + + -- Transfer State Machine-- + process (tClk, RST) + begin + if (tClk = '1' and tClk'Event) then + if RST = '1' then + sttCur <= sttIdle; + else + sttCur <= sttNext; + end if; + end if; + end process; + + -- This process generates the sequence of steps needed transfer the data-- + process (sttCur, tfCtr, tfReg, TBE, tclk) + begin + + case sttCur is + + when sttIdle => + tClkRST <= '0'; + shift <= '0'; + load <= '0'; + if TBE = '1' then + sttNext <= sttIdle; + else + sttNext <= sttTransfer; + end if; + + when sttTransfer => + shift <= '0'; + load <= '1'; + tClkRST <= '1'; + sttNext <= sttShift; + + + when sttShift => + shift <= '1'; + load <= '0'; + tClkRST <= '0'; + if tfCtr = "1100" then + sttNext <= sttIdle; + else + sttNext <= sttShift; + end if; + end case; + end process; + +end Behavioral; \ No newline at end of file Index: PureTesting/pLayer.vhd =================================================================== --- PureTesting/pLayer.vhd (nonexistent) +++ PureTesting/pLayer.vhd (revision 3) @@ -0,0 +1,99 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:06:24 05/13/2010 +-- Design Name: +-- Module Name: pLayer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer; + +architecture Behavioral of pLayer is +begin + output(0) <= input(0); + output(16) <= input(1); + output(32) <= input(2); + output(48) <= input(3); + output(1) <= input(4); + output(17) <= input(5); + output(33) <= input(6); + output(49) <= input(7); + output(2) <= input(8); + output(18) <= input(9); + output(34) <= input(10); + output(50) <= input(11); + output(3) <= input(12); + output(19) <= input(13); + output(35) <= input(14); + output(51) <= input(15); + output(4) <= input(16); + output(20) <= input(17); + output(36) <= input(18); + output(52) <= input(19); + output(5) <= input(20); + output(21) <= input(21); + output(37) <= input(22); + output(53) <= input(23); + output(6) <= input(24); + output(22) <= input(25); + output(38) <= input(26); + output(54) <= input(27); + output(7) <= input(28); + output(23) <= input(29); + output(39) <= input(30); + output(55) <= input(31); + output(8) <= input(32); + output(24) <= input(33); + output(40) <= input(34); + output(56) <= input(35); + output(9) <= input(36); + output(25) <= input(37); + output(41) <= input(38); + output(57) <= input(39); + output(10) <= input(40); + output(26) <= input(41); + output(42) <= input(42); + output(58) <= input(43); + output(11) <= input(44); + output(27) <= input(45); + output(43) <= input(46); + output(59) <= input(47); + output(12) <= input(48); + output(28) <= input(49); + output(44) <= input(50); + output(60) <= input(51); + output(13) <= input(52); + output(29) <= input(53); + output(45) <= input(54); + output(61) <= input(55); + output(14) <= input(56); + output(30) <= input(57); + output(46) <= input(58); + output(62) <= input(59); + output(15) <= input(60); + output(31) <= input(61); + output(47) <= input(62); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: PureTesting/PresentComm.vhd =================================================================== --- PureTesting/PresentComm.vhd (nonexistent) +++ PureTesting/PresentComm.vhd (revision 3) @@ -0,0 +1,236 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:01:00 06/26/2013 +-- Design Name: +-- Module Name: PresentComm - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentComm is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_64: integer := 64; + w_80: integer := 80 + ); + port ( + DATA_RXD : in STD_LOGIC; + CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + DATA_TXD : out STD_LOGIC + ); +end PresentComm; + +architecture Behavioral of PresentComm is + +component ShiftReg is + generic ( + length_1 : integer := 8; + length_2 : integer := w_64; + internal_data : integer := w_64 + ); + port ( + input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); + output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end component ShiftReg; + +component Rs232RefComp is + Port ( + TXD : out std_logic := '1'; + RXD : in std_logic; + CLK : in std_logic; --Master Clock + DBIN : in std_logic_vector (7 downto 0); --Data Bus in + DBOUT : out std_logic_vector (7 downto 0); --Data Bus out + RDA : inout std_logic; --Read Data Available + TBE : inout std_logic := '1'; --Transfer Bus Empty + RD : in std_logic; --Read Strobe + WR : in std_logic; --Write Strobe + PE : out std_logic; --Parity Error Flag + FE : out std_logic; --Frame Error Flag + OE : out std_logic; --Overwrite Error Flag + RST : in std_logic := '0'); --Master Reset +end component Rs232RefComp; + +component PresentEnc is + generic ( + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentEnc; + +component PresentCommSM is + port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + RDAsig : in STD_LOGIC; + TBEsig : in STD_LOGIC; + RDsig : out STD_LOGIC; + WRsig : out STD_LOGIC; + textDataEn : out STD_LOGIC; + textDataShift : out STD_LOGIC; + keyDataEn : out STD_LOGIC; + keyDataShift : out STD_LOGIC; + ciphDataEn : out STD_LOGIC; + ciphDataShift : out STD_LOGIC; + startSig : out STD_LOGIC; + readySig : in STD_LOGIC + ); +end component PresentCommSM; + +signal keyText : STD_LOGIC_VECTOR(w_80 - 1 downto 0); +signal plaintext : STD_LOGIC_VECTOR(w_64 - 1 downto 0); +signal ciphertext : STD_LOGIC_VECTOR(w_64 - 1 downto 0); + +signal dataTXD : STD_LOGIC_VECTOR(7 downto 0); +signal dataRXD : STD_LOGIC_VECTOR(7 downto 0); +signal RDAsig : STD_LOGIC; +signal TBEsig : STD_LOGIC; +signal RDsig : STD_LOGIC; +signal WRsig : STD_LOGIC; +signal PEsig : STD_LOGIC; +signal FEsig : STD_LOGIC; +signal OEsig : STD_LOGIC; + +signal keyDataEn : STD_LOGIC; +signal keyDataShift : STD_LOGIC; + +signal textDataEn : STD_LOGIC; +signal textDataShift : STD_LOGIC; + +signal ciphDataEn : STD_LOGIC; +signal ciphDataShift : STD_LOGIC; + +signal startSig : STD_LOGIC; +signal readySig : STD_LOGIC; + +begin + + RS232 : Rs232RefComp + Port map( + TXD => DATA_TXD, + RXD => DATA_RXD, + CLK => clk, + DBIN => dataTXD, + DBOUT => dataRXD, + RDA => RDAsig, + TBE => TBEsig, + RD => RDsig, + WR => WRsig, + PE => PEsig, + FE => FEsig, + OE => OEsig, + RST => reset + ); + + textReg : ShiftReg + generic map( + length_1 => 8, + length_2 => w_64, + internal_data => w_64 + ) + port map( + input => dataRXD, + output => plaintext, + en => textDataEn, + shift => textDataShift, + clk => clk, + reset => reset + ); + + keyReg : ShiftReg + generic map( + length_1 => 8, + length_2 => w_80, + internal_data => w_80 + ) + port map( + input => dataRXD, + output => keyText, + en => keyDataEn, + shift => keyDataShift, + clk => clk, + reset => reset + ); + + present :PresentEnc + port map( + plaintext => plaintext, + key => keyText, + ciphertext => ciphertext, + start => startSig, + clk => clk, + reset => reset, + ready => readySig + ); + + outReg : ShiftReg + generic map( + length_1 => w_64, + length_2 => 8, + internal_data => w_64 + ) + port map( + input => ciphertext, + output => dataTXD, + en => ciphDataEn, + shift => ciphDataShift, + clk => clk, + reset => reset + ); + + SM : PresentCommSM + port map( + clk => clk, + reset => reset, + RDAsig => RDAsig, + TBEsig => TBEsig, + RDsig => RDsig, + WRsig => WRsig, + textDataEn => textDataEn, + textDataShift => textDataShift, + keyDataEn => keyDataEn, + keyDataShift => keyDataShift, + ciphDataEn => ciphDataEn, + ciphDataShift => ciphDataShift, + startSig => startSig, + readySig => readySig + ); + +end Behavioral; + Index: PureTesting/PresentCommSM.vhd =================================================================== --- PureTesting/PresentCommSM.vhd (nonexistent) +++ PureTesting/PresentCommSM.vhd (revision 3) @@ -0,0 +1,367 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:49:35 06/26/2013 +-- Design Name: +-- Module Name: PresentCommSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentCommSM is + port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + RDAsig : in STD_LOGIC; + TBEsig : in STD_LOGIC; + RDsig : out STD_LOGIC; + WRsig : out STD_LOGIC; + textDataEn : out STD_LOGIC; + textDataShift : out STD_LOGIC; + keyDataEn : out STD_LOGIC; + keyDataShift : out STD_LOGIC; + ciphDataEn : out STD_LOGIC; + ciphDataShift : out STD_LOGIC; + startSig : out STD_LOGIC; + readySig : in STD_LOGIC + ); +end PresentCommSM; + +architecture Behavioral of PresentCommSM is + +component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end component counter; + +signal state : stany_comm := NOP; +signal next_state : stany_comm := NOP; + +-- modify for variable key size +signal serialDataCtrCt : STD_LOGIC; +signal serialDataCtrOut : STD_LOGIC_VECTOR(3 downto 0); +signal serialDataCtrReset : STD_LOGIC; +signal ctrReset : STD_LOGIC; +-- DO NOT MODIFY!!! +signal shiftDataCtrCt : STD_LOGIC; +signal shiftDataCtrOut : STD_LOGIC_VECTOR(2 downto 0); + +begin + ctrReset <= serialDataCtrReset or reset; + SM : process(state, RDAsig, TBEsig, shiftDataCtrOut, serialDataCtrOut, readySig) + begin + case state is + when NOP => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + if (RDAsig = '1') then + next_state <= READ_DATA_TEXT; + else + next_state <= NOP; + end if; + when READ_DATA_TEXT => + RDsig <= '1'; + WRsig <= '0'; + textDataEn <= '1'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= DECODE_READ_TEXT; + when DECODE_READ_TEXT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + if (serialDataCtrOut(3 downto 0) = "1000") then + next_state <= TEMP_STATE; + else + next_state <= MOVE_TEXT; + end if; + when TEMP_STATE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= NOP_FOR_KEY; + when MOVE_TEXT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '1'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut(2 downto 0) = "111") then + next_state <= NOP; + else + next_state <= MOVE_TEXT; + end if; + when NOP_FOR_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + if (RDAsig = '1') then + next_state <= READ_DATA_KEY; + else + next_state <= NOP_FOR_KEY; + end if; + when READ_DATA_KEY => + RDsig <= '1'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '1'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= DECODE_READ_KEY; + when DECODE_READ_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + if (serialDataCtrOut(3 downto 0) = "1010") then + next_state <= TEMP2_STATE; + else + next_state <= MOVE_KEY; + end if; + when TEMP2_STATE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= PRESENT_ENCODE; + when MOVE_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '1'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut(2 downto 0) = "111") then + next_state <= NOP_FOR_KEY; + else + next_state <= MOVE_KEY; + end if; + when PRESENT_ENCODE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + if (readySig = '1') then + ciphDataEn <= '1'; + next_state <= WRITE_OUT; + else + ciphDataEn <= '0'; + next_state <= PRESENT_ENCODE; + end if; + when WRITE_OUT => + RDsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + if (serialDataCtrOut = "1000") then + WRsig <= '0'; + next_state <= TEMP_OUT; + else + WRsig <= '1'; + next_state <= MOVE_OUT; + end if; + when TEMP_OUT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= NOP; + when MOVE_OUT => + if (TBEsig = '0') then + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= MOVE_OUT; + else + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '1'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut = "111") then + next_state <= WRITE_OUT; + else + next_state <= MOVE_OUT; + end if; + end if; + end case; + end process SM; + + state_modifier : process (clk, reset) + begin + if (clk = '1' and clk'Event) then + if (reset = '1') then + state <= NOP; + else + state <= next_state; + end if; + end if; + end process state_modifier; + + dataCounter : counter + generic map( + w_5 => 4 + ) + port map ( + cnt_res => serialDataCtrCt, + num => serialDataCtrOut, + clk => clk, + reset => ctrReset + ); + + shiftCounter : counter + generic map( + w_5 => 3 + ) + port map ( + cnt_res => shiftDataCtrCt, + num => shiftDataCtrOut, + clk => clk, + reset => reset + ); + +end Behavioral; + Index: PureTesting =================================================================== --- PureTesting (nonexistent) +++ PureTesting (revision 3)
PureTesting Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/txt_util.vhd =================================================================== --- 32BitIO/txt_util.vhd (nonexistent) +++ 32BitIO/txt_util.vhd (revision 3) @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: Pure/counter.vhd =================================================================== --- Pure/counter.vhd (nonexistent) +++ Pure/counter.vhd (revision 3) @@ -0,0 +1,49 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:47:04 04/02/2011 +-- Design Name: +-- Module Name: counter - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt + 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: Pure/slayer.vhd =================================================================== --- Pure/slayer.vhd (nonexistent) +++ Pure/slayer.vhd (revision 3) @@ -0,0 +1,55 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:48:15 05/13/2010 +-- Design Name: +-- Module Name: permutation - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: Pure/keyupd.vhd =================================================================== --- Pure/keyupd.vhd (nonexistent) +++ Pure/keyupd.vhd (revision 3) @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:45:36 05/13/2010 +-- Design Name: +-- Module Name: keyupd - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: Pure/sLayerTB.vhd =================================================================== --- Pure/sLayerTB.vhd (nonexistent) +++ Pure/sLayerTB.vhd (revision 3) @@ -0,0 +1,95 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:11:33 05/16/2010 +-- Design Name: +-- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/sLayerTB.vhd +-- Project Name: szyfrator +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: slayer +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY sLayerTB IS +END sLayerTB; + +ARCHITECTURE behavior OF sLayerTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT slayer + PORT( + input : IN std_logic_vector(3 downto 0); + output : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --BiDirs + signal input : std_logic_vector(3 downto 0); + signal output : std_logic_vector(3 downto 0); + + -- Clock period definitions + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: slayer PORT MAP ( + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <= '0'; + wait for clk_period; + input <= x"0"; + wait for clk_period; + input <= x"A"; + wait for clk_period; + input <= x"F"; + wait for clk_period; + -- insert stimulus here + assert false severity failure; + end process; + +END; \ No newline at end of file Index: Pure/PresentStateMachine.vhd =================================================================== --- Pure/PresentStateMachine.vhd (nonexistent) +++ Pure/PresentStateMachine.vhd (revision 3) @@ -0,0 +1,100 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:17:10 04/02/2011 +-- Design Name: +-- Module Name: PresentStateMachine - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + RegEn <= '0'; + if (start = '1') then + next_state <= SM_START; + else + next_state <= NOP; + end if; + when SM_START => + ready <= '0'; + RegEn <= '1'; + cnt_res <= '1'; + if (start = '1') then + if (num = "00000") then + ctrl_mux <= '0'; + next_state <= SM_START; + elsif (num = "11111") then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: Pure/kody.vhd =================================================================== --- Pure/kody.vhd (nonexistent) +++ Pure/kody.vhd (revision 3) @@ -0,0 +1,34 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, SM_START, SM_READY); + -- constant as control command from input -- + constant cnop : std_logic_vector(3 downto 0) := "0000"; --0 no operations + constant cdec : std_logic_vector(3 downto 0) := "0001"; --1 decode text + constant crdk1 : std_logic_vector(3 downto 0) := "0010"; --2 read key part 1 + constant crdk2 : std_logic_vector(3 downto 0) := "0011"; --3 read key part 2 + constant crdk3 : std_logic_vector(3 downto 0) := "0100"; --4 read key part 3 + constant cmkd : std_logic_vector(3 downto 0) := "0101"; --5 make decrypt key + constant ccod : std_logic_vector(3 downto 0) := "0110"; --6 code text + constant crdt1 : std_logic_vector(3 downto 0) := "0111"; --7 read text part 1 + constant crdt2 : std_logic_vector(3 downto 0) := "1000"; --8 read text part 2 + constant ccto1 : std_logic_vector(3 downto 0) := "1001"; --9 ciphertext output part 1 (LSW) + constant ccto2 : std_logic_vector(3 downto 0) := "1010"; --A ciphertext output part 2 (MSW) + -- For input registers (early version, now for mux's) -- + constant in_ld_reg_L : std_logic_vector(1 downto 0) := "00"; -- Load low part of the register (64 & 80 bit) + constant in_ld_reg_H : std_logic_vector(1 downto 0) := "01"; -- Load high part of the register (64 & 80 bit) + constant in_ld_reg_HH : std_logic_vector(1 downto 0) := "10"; -- Load highest part of the register (80 bit only) + constant in_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) + -- For output register -- + constant out_ld_reg : std_logic_vector(1 downto 0) := "00"; -- Load the output register + constant out_reg_L : std_logic_vector(1 downto 0) := "01"; -- send low part of the register to the output + constant out_reg_H : std_logic_vector(1 downto 0) := "10"; -- senf high part of the register to the output + constant out_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) +end kody; \ No newline at end of file Index: Pure/PresentEnc.vhd =================================================================== --- Pure/PresentEnc.vhd (nonexistent) +++ Pure/PresentEnc.vhd (revision 3) @@ -0,0 +1,186 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 18:02:34 05/15/2010 +-- Design Name: +-- Module Name: PresentEnc - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: + +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEnc is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEnc; + +architecture Behavioral of PresentEnc is + + component Reg is + generic(width : integer := w_64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + component slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + component pLayer is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + mux_64: AsyncMux generic map(width => w_64) port map( + input0 => plaintext, + input1 => Pout, + ctrl => mux_ctrl, + output => textToReg + ); + regText : Reg generic map(width => w_64) port map( + input => textToReg, + output => toXor, + enable => RegEn, + clk => clk, + reset => reset + ); + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + slayers : for N in 15 downto 0 generate + s_x: slayer port map( + input => ciph(4*N+3 downto 4*N), + output => P(4*N+3 downto 4*N) + ); + end generate slayers; + p1: pLayer port map( + input => P, + output => Pout + ); + mixer: keyupd port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + ciph <= toXor xor keyfout(79 downto 16); + ciphertext <= ciph; + ready <= ready_sig; +end Behavioral; Index: Pure/PresentTB.vhd =================================================================== --- Pure/PresentTB.vhd (nonexistent) +++ Pure/PresentTB.vhd (revision 3) @@ -0,0 +1,133 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:21:14 06/25/2013 +-- Design Name: +-- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Pure/PresentTB.vhd +-- Project Name: Present_Pure +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: PresentEnc +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentTB IS +END PresentTB; + +ARCHITECTURE behavior OF PresentTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentEnc + PORT( + plaintext : IN std_logic_vector(63 downto 0); + key : IN std_logic_vector(79 downto 0); + ciphertext : OUT std_logic_vector(63 downto 0); + start : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + ready : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal plaintext : std_logic_vector(63 downto 0) := (others => '0'); + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal start : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal ciphertext : std_logic_vector(63 downto 0); + signal ready : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentEnc PORT MAP ( + plaintext => plaintext, + key => key, + ciphertext => ciphertext, + start => start, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + + reset <= '1'; + start <= '0'; + wait for 100 ns; + reset <= '0'; + + plaintext <= (others => '0'); + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '0'); + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '1'); + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '1'); + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + assert false severity failure; + + end process; + +END; Index: Pure/keyupdTB.vhd =================================================================== --- Pure/keyupdTB.vhd (nonexistent) +++ Pure/keyupdTB.vhd (revision 3) @@ -0,0 +1,106 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:00:18 05/16/2010 +-- Design Name: +-- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/keyupdTB.vhd +-- Project Name: szyfrator +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: keyupd +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY keyupdTB IS +END keyupdTB; + +ARCHITECTURE behavior OF keyupdTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT keyupd + PORT( + key : IN std_logic_vector(79 downto 0); + num : IN std_logic_vector(4 downto 0); + keyout : OUT std_logic_vector(79 downto 0)--; + --clk, reset : std_logic + ); + END COMPONENT; + + + --Inputs + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal num : std_logic_vector(4 downto 0) := (others => '0'); + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal keyout : std_logic_vector(79 downto 0); + + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: keyupd PORT MAP ( + key => key, + num => num, + keyout => keyout--, + --clk => clk, + --reset => reset + ); + + -- No clocks detected in port list. Replace clk below with + -- appropriate port name + + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <='0'; + wait for clk_period; + key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + num <= "00001"; + wait for clk_period; + key <= x"c0000000000000008000"; + num <= "00010"; + wait for clk_period; + key <= x"50001800000000010000"; + num <= "00011"; + wait for clk_period; + key <= x"8ba27a0eb8783ac96d59"; + num <= "11111"; + wait for clk_period; + assert false severity failure; + end process; +END; \ No newline at end of file Index: Pure/AsyncMux.vhd =================================================================== --- Pure/AsyncMux.vhd (nonexistent) +++ Pure/AsyncMux.vhd (revision 3) @@ -0,0 +1,50 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23:24:35 06/24/2013 +-- Design Name: +-- Module Name: AsyncMux - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); +end AsyncMux; + +architecture Behavioral of AsyncMux is + +begin + output <= input0 when (ctrl = '0') else + input1; +end Behavioral; + Index: Pure/pLayer.vhd =================================================================== --- Pure/pLayer.vhd (nonexistent) +++ Pure/pLayer.vhd (revision 3) @@ -0,0 +1,99 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:06:24 05/13/2010 +-- Design Name: +-- Module Name: pLayer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer; + +architecture Behavioral of pLayer is +begin + output(0) <= input(0); + output(16) <= input(1); + output(32) <= input(2); + output(48) <= input(3); + output(1) <= input(4); + output(17) <= input(5); + output(33) <= input(6); + output(49) <= input(7); + output(2) <= input(8); + output(18) <= input(9); + output(34) <= input(10); + output(50) <= input(11); + output(3) <= input(12); + output(19) <= input(13); + output(35) <= input(14); + output(51) <= input(15); + output(4) <= input(16); + output(20) <= input(17); + output(36) <= input(18); + output(52) <= input(19); + output(5) <= input(20); + output(21) <= input(21); + output(37) <= input(22); + output(53) <= input(23); + output(6) <= input(24); + output(22) <= input(25); + output(38) <= input(26); + output(54) <= input(27); + output(7) <= input(28); + output(23) <= input(29); + output(39) <= input(30); + output(55) <= input(31); + output(8) <= input(32); + output(24) <= input(33); + output(40) <= input(34); + output(56) <= input(35); + output(9) <= input(36); + output(25) <= input(37); + output(41) <= input(38); + output(57) <= input(39); + output(10) <= input(40); + output(26) <= input(41); + output(42) <= input(42); + output(58) <= input(43); + output(11) <= input(44); + output(27) <= input(45); + output(43) <= input(46); + output(59) <= input(47); + output(12) <= input(48); + output(28) <= input(49); + output(44) <= input(50); + output(60) <= input(51); + output(13) <= input(52); + output(29) <= input(53); + output(45) <= input(54); + output(61) <= input(55); + output(14) <= input(56); + output(30) <= input(57); + output(46) <= input(58); + output(62) <= input(59); + output(15) <= input(60); + output(31) <= input(61); + output(47) <= input(62); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: Pure/txt_util.vhd =================================================================== --- Pure/txt_util.vhd (nonexistent) +++ Pure/txt_util.vhd (revision 3) @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: Pure/Reg.vhd =================================================================== --- Pure/Reg.vhd (nonexistent) +++ Pure/Reg.vhd (revision 3) @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23:41:41 06/24/2013 +-- Design Name: +-- Module Name: Reg - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg is + generic(width : integer := 64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end Reg; + +architecture Behavioral of Reg is + +signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); + +begin + clock : process(clk, reset) + begin + if (reset = '1') then + reg <= (others => '0'); + elsif (clk = '1' and clk'Event) then + if (enable = '1') then + reg <= input; + end if; + end if; + end process clock; + output <= reg; +end Behavioral; + Index: Pure =================================================================== --- Pure (nonexistent) +++ Pure (revision 3)
Pure Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property

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