Subversion Repositories product_code_iterative_decoder

/modelsim_bench.vhdl

/modelsim_bench.do

/input.vhdl

/analyze.sh

analyze.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: output.vhdl =================================================================== --- output.vhdl (nonexistent) +++ output.vhdl (revision 10) @@ -0,0 +1,77 @@ +-- $Id: output.vhdl,v 1.1.1.1 2005-11-15 01:51:29 arif_endro Exp $ +------------------------------------------------------------------------------- +-- Title : Output Data +-- Project : +------------------------------------------------------------------------------- +-- File : output.vhdl +-- Author : "Arif E. Nugroho" +-- Created : 2005/11/01 +-- Last update : +-- Simulators : +-- Synthesizers: +-- Target : +------------------------------------------------------------------------------- +-- Description : Save output to file, to be analyzed. +------------------------------------------------------------------------------- +-- Copyright (C) 2005 Arif E. Nugroho +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- +-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION +-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT +-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE +-- ASSOCIATED DISCLAIMER. +-- +------------------------------------------------------------------------------- +-- +-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO +-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use std.textio.all; + +entity output is + port ( + start : in bit; + y0 : in bit; + y1 : in bit; + y2 : in bit; + y3 : in bit + ); +end output; + +architecture test_bench of output is + +file send_out_ptr : text open write_mode is "send_out.txt"; +signal send_out : bit_vector (03 downto 00); + +begin -- architecture test_bench + + process (start) + variable send_out_ln : line; + begin + if (start = '0' and start'event) then + for a in send_out'range loop + write(send_out_ln, send_out(a)); + writeline(send_out_ptr, send_out_ln); + end loop; + end if; + end process; + send_out <= ( y0 & y1 & y2 & y3 ); + +end test_bench;