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Rev 3 → Rev 10

/twos_c_8bit.vhdl
0,0 → 1,65
-- $Id: twos_c_8bit.vhdl,v 1.1.1.1 2005-11-15 01:52:31 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Two's complement
-- Project :
-------------------------------------------------------------------------------
-- File : twos_c_8bit
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2005/11/01
-- Last update :
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : Calculate two's complement of 8 bit signed signal
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity twos_c_8bit is
port (
twos_c_i : in bit_vector (07 downto 00);
twos_c_o : out bit_vector (07 downto 00)
);
end twos_c_8bit;
 
architecture data_flow of twos_c_8bit is
 
begin
 
twos_c_o(00) <= (twos_c_i(00));
twos_c_o(01) <= (not(twos_c_i(01)) xor (not(twos_c_i(00))));
twos_c_o(02) <= (not(twos_c_i(02)) xor (not(twos_c_i(00)) and not(twos_c_i(01))));
twos_c_o(03) <= (not(twos_c_i(03)) xor ((not(twos_c_i(00)) and not(twos_c_i(01))) and not(twos_c_i(02))));
twos_c_o(04) <= (not(twos_c_i(04)) xor ((not(twos_c_i(00)) and not(twos_c_i(01))) and (not(twos_c_i(02)) and not(twos_c_i(03)))));
twos_c_o(05) <= (not(twos_c_i(05)) xor (((not(twos_c_i(00)) and not(twos_c_i(01))) and (not(twos_c_i(02)) and not(twos_c_i(03)))) and not(twos_c_i(04))));
twos_c_o(06) <= (not(twos_c_i(06)) xor (((not(twos_c_i(00)) and not(twos_c_i(01))) and (not(twos_c_i(02)) and not(twos_c_i(03)))) and (not(twos_c_i(04)) and not(twos_c_i(05)))));
twos_c_o(07) <= (not(twos_c_i(07)) xor (((not(twos_c_i(00)) and not(twos_c_i(01))) and (not(twos_c_i(02)) and not(twos_c_i(03)))) and ((not(twos_c_i(04)) and not(twos_c_i(05))) and not(twos_c_i(06)))));
 
end data_flow;
/adder_08bit.vhdl
0,0 → 1,157
-- $Id: adder_08bit.vhdl,v 1.1.1.1 2005-11-15 01:52:30 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : 8 bit adder
-- Project :
-------------------------------------------------------------------------------
-- File : adder_08bit.vhdl
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2005/11/01
-- Last update :
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : 8 bit signed adder
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity adder_08bit is
port (
addend_08bit : in bit_vector (07 downto 0);
augend_08bit : in bit_vector (07 downto 0);
adder08_output: out bit_vector (08 downto 0)
);
end adder_08bit;
 
architecture structural of adder_08bit is
 
component fulladder
port (
addend : in bit;
augend : in bit;
carry_in : in bit;
sum : out bit;
carry : out bit
);
end component;
 
signal c00 : bit;
signal c01 : bit;
signal c02 : bit;
signal c03 : bit;
signal c04 : bit;
signal c05 : bit;
signal c06 : bit;
signal c07 : bit;
signal c08 : bit;
signal over08 : bit;
signal adder08_output_int : bit_vector (08 downto 0);
 
begin
 
c00 <= '0';
over08 <= (addend_08bit (07) xor augend_08bit (07));
adder08_output_int (08) <= ((adder08_output_int (07) and over08) or
(c08 and (not (over08))));
adder08_output <= adder08_output_int;
 
fa07 : fulladder
port map (
addend => addend_08bit(07),
augend => augend_08bit(07),
carry_in => c07,
sum => adder08_output_int(07),
carry => c08
);
 
fa06 : fulladder
port map (
addend => addend_08bit(06),
augend => augend_08bit(06),
carry_in => c06,
sum => adder08_output_int(06),
carry => c07
);
 
fa05 : fulladder
port map (
addend => addend_08bit(05),
augend => augend_08bit(05),
carry_in => c05,
sum => adder08_output_int(05),
carry => c06
);
 
fa04 : fulladder
port map (
addend => addend_08bit(04),
augend => augend_08bit(04),
carry_in => c04,
sum => adder08_output_int(04),
carry => c05
);
 
fa03 : fulladder
port map (
addend => addend_08bit(03),
augend => augend_08bit(03),
carry_in => c03,
sum => adder08_output_int(03),
carry => c04
);
 
fa02 : fulladder
port map (
addend => addend_08bit(02),
augend => augend_08bit(02),
carry_in => c02,
sum => adder08_output_int(02),
carry => c03
);
 
fa01 : fulladder
port map (
addend => addend_08bit(01),
augend => augend_08bit(01),
carry_in => c01,
sum => adder08_output_int(01),
carry => c02
);
 
fa00 : fulladder
port map (
addend => addend_08bit(00),
augend => augend_08bit(00),
carry_in => c00,
sum => adder08_output_int(00),
carry => c01
);
 
end structural;
/bit_comparator.vhdl
0,0 → 1,63
-- $Id: bit_comparator.vhdl,v 1.1.1.1 2005-11-15 01:52:30 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Bit comparator
-- Project :
-------------------------------------------------------------------------------
-- File : bit_comparator.vhdl
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2005/11/01
-- Last update :
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : Compare two input
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity bit_comparator is
port (
a_i : in bit;
b_i : in bit;
eq_i : in bit;
gt_i : in bit;
lt_i : in bit;
eq_o : out bit;
gt_o : out bit;
lt_o : out bit
);
end bit_comparator;
 
architecture data_flow of bit_comparator is
begin
lt_o <= (((not(a_i) and lt_i) or (b_i and lt_i)) or (not(a_i) and b_i));
eq_o <= (((a_i and b_i) and eq_i) or ((not(a_i) and not(b_i)) and eq_i));
gt_o <= (((a_i and gt_i) or (not(b_i) and gt_i)) or (a_i and not(b_i)));
end data_flow;
/ser2par8bit.vhdl
0,0 → 1,103
-- $Id: ser2par8bit.vhdl,v 1.1.1.1 2005-11-15 01:52:31 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Serial to paralel 8bit
-- Project :
-------------------------------------------------------------------------------
-- File : ser2par8bit.vhdl
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2005/11/01
-- Last update :
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : Conversion from serial input to paralel output
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.ALL;
 
entity ser2par8bit is
port (
clock : in bit;
clear : in bit;
start : in bit;
rxin : in bit_vector (07 downto 00);
y0 : out bit_vector (07 downto 00);
y1 : out bit_vector (07 downto 00);
y2 : out bit_vector (07 downto 00);
y3 : out bit_vector (07 downto 00);
r0 : out bit_vector (07 downto 00);
r1 : out bit_vector (07 downto 00);
c0 : out bit_vector (07 downto 00);
c1 : out bit_vector (07 downto 00)
);
end ser2par8bit;
 
architecture data_flow of ser2par8bit is
 
subtype type_word is bit_vector (07 downto 00);
type type_fifo is array (09 downto 00) of type_word;
signal fifo8bx7 : type_fifo;
 
begin
 
process (clock, clear)
begin
if (clear = '1') then
fifo8bx7 (00) <= (others => '0');
fifo8bx7 (01) <= (others => '0');
fifo8bx7 (02) <= (others => '0');
fifo8bx7 (03) <= (others => '0');
fifo8bx7 (04) <= (others => '0');
fifo8bx7 (05) <= (others => '0');
fifo8bx7 (06) <= (others => '0');
fifo8bx7 (07) <= (others => '0');
fifo8bx7 (08) <= (others => '0');
fifo8bx7 (09) <= (others => '0');
elsif ((clock = '0') and clock'event) then
fifo8bx7 (00) <= rxin (07 downto 00);
fifo8bx7 (09 downto 01) <= fifo8bx7 (08 downto 00);
end if;
end process;
 
process (start)
begin
if (start = '0' and start'event) then
y0 <= fifo8bx7 (08);
y1 <= fifo8bx7 (07);
y2 <= fifo8bx7 (06);
y3 <= fifo8bx7 (05);
r0 <= fifo8bx7 (04);
r1 <= fifo8bx7 (03);
c0 <= fifo8bx7 (02);
c1 <= fifo8bx7 (01);
end if;
end process;
 
end data_flow;
/product_code.vhdl
0,0 → 1,375
-- $Id: product_code.vhdl,v 1.1.1.1 2005-11-15 01:52:31 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Product Code Iterative Decoder
-- Project :
-------------------------------------------------------------------------------
-- File : product_code.vhdl
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2005/11/01
-- Last update :
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : Connector of all component in Product Code Iterative Decoder.
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity product_code is
port (
clock : in bit;
start : in bit;
rxin : in bit_vector (07 downto 00);
y0d : out bit;
y1d : out bit;
y2d : out bit;
y3d : out bit
);
end product_code;
 
architecture structural of product_code is
 
component ser2par8bit
port (
clock : in bit;
clear : in bit;
start : in bit;
rxin : in bit_vector (07 downto 00);
y0 : out bit_vector (07 downto 00);
y1 : out bit_vector (07 downto 00);
y2 : out bit_vector (07 downto 00);
y3 : out bit_vector (07 downto 00);
r0 : out bit_vector (07 downto 00);
r1 : out bit_vector (07 downto 00);
c0 : out bit_vector (07 downto 00);
c1 : out bit_vector (07 downto 00)
);
end component;
 
component ext_val
port (
ext_a_i : in bit_vector (07 downto 00);
ext_b_i : in bit_vector (07 downto 00);
ext_r_o : out bit_vector (07 downto 00)
);
end component;
 
component adder_08bit
port (
addend_08bit : in bit_vector (07 downto 00);
augend_08bit : in bit_vector (07 downto 00);
adder08_output : out bit_vector (08 downto 00)
);
end component;
 
signal y0e : bit_vector (07 downto 00);
signal y1e : bit_vector (07 downto 00);
signal y2e : bit_vector (07 downto 00);
signal y3e : bit_vector (07 downto 00);
 
signal y0 : bit_vector (07 downto 00);
signal y1 : bit_vector (07 downto 00);
signal y2 : bit_vector (07 downto 00);
signal y3 : bit_vector (07 downto 00);
signal r0 : bit_vector (07 downto 00);
signal r1 : bit_vector (07 downto 00);
signal c0 : bit_vector (07 downto 00);
signal c1 : bit_vector (07 downto 00);
 
signal ext_b_c_0_b : bit_vector (08 downto 00);
signal ext_b_c_1_b : bit_vector (08 downto 00);
signal ext_b_c_2_b : bit_vector (08 downto 00);
signal ext_b_c_3_b : bit_vector (08 downto 00);
 
signal augend_sum_c_0 : bit_vector (07 downto 00);
signal augend_sum_c_1 : bit_vector (07 downto 00);
signal augend_sum_c_2 : bit_vector (07 downto 00);
signal augend_sum_c_3 : bit_vector (07 downto 00);
 
signal ext_r_r_0 : bit_vector (07 downto 00);
signal ext_r_r_1 : bit_vector (07 downto 00);
signal ext_r_r_2 : bit_vector (07 downto 00);
signal ext_r_r_3 : bit_vector (07 downto 00);
 
signal ext_b_r_0_b : bit_vector (08 downto 00);
signal ext_b_r_1_b : bit_vector (08 downto 00);
signal ext_b_r_2_b : bit_vector (08 downto 00);
signal ext_b_r_3_b : bit_vector (08 downto 00);
 
signal ext_b_r_0 : bit_vector (07 downto 00);
signal ext_b_r_1 : bit_vector (07 downto 00);
signal ext_b_r_2 : bit_vector (07 downto 00);
signal ext_b_r_3 : bit_vector (07 downto 00);
 
signal ext_r_c_0 : bit_vector (07 downto 00);
signal ext_r_c_1 : bit_vector (07 downto 00);
signal ext_r_c_2 : bit_vector (07 downto 00);
signal ext_r_c_3 : bit_vector (07 downto 00);
 
signal ext_b_c_0 : bit_vector (07 downto 00);
signal ext_b_c_1 : bit_vector (07 downto 00);
signal ext_b_c_2 : bit_vector (07 downto 00);
signal ext_b_c_3 : bit_vector (07 downto 00);
 
signal y0p_b : bit_vector (08 downto 00);
signal y1p_b : bit_vector (08 downto 00);
signal y2p_b : bit_vector (08 downto 00);
signal y3p_b : bit_vector (08 downto 00);
 
signal y0p : bit;
signal y1p : bit;
signal y2p : bit;
signal y3p : bit;
 
constant gnd : bit := '0';
 
begin
 
ext_b_c_0 (07 downto 00) <= ext_b_c_0_b (07 downto 00);
ext_b_c_1 (07 downto 00) <= ext_b_c_1_b (07 downto 00);
ext_b_c_2 (07 downto 00) <= ext_b_c_2_b (07 downto 00);
ext_b_c_3 (07 downto 00) <= ext_b_c_3_b (07 downto 00);
 
ext_b_r_0 (07 downto 00) <= ext_b_r_0_b (07 downto 00);
ext_b_r_1 (07 downto 00) <= ext_b_r_1_b (07 downto 00);
ext_b_r_2 (07 downto 00) <= ext_b_r_2_b (07 downto 00);
ext_b_r_3 (07 downto 00) <= ext_b_r_3_b (07 downto 00);
 
first : ser2par8bit
port map (
clock => clock,
clear => gnd,
start => start,
rxin => rxin,
y0 => y0,
y1 => y1,
y2 => y2,
y3 => y3,
r0 => r0,
r1 => r1,
c0 => c0,
c1 => c1
);
 
sum_r_0 : adder_08bit
port map (
addend_08bit => y0,
augend_08bit => y0e,
adder08_output => ext_b_r_1_b
);
 
sum_r_1 : adder_08bit
port map (
addend_08bit => y1,
augend_08bit => y1e,
adder08_output => ext_b_r_0_b
);
 
sum_r_2 : adder_08bit
port map (
addend_08bit => y2,
augend_08bit => y2e,
adder08_output => ext_b_r_3_b
);
 
sum_r_3 : adder_08bit
port map (
addend_08bit => y3,
augend_08bit => y3e,
adder08_output => ext_b_r_2_b
);
 
sum_c_0 : adder_08bit
port map (
addend_08bit => y0,
augend_08bit => augend_sum_c_0,
adder08_output => ext_b_c_2_b
);
 
sum_c_1 : adder_08bit
port map (
addend_08bit => y1,
augend_08bit => augend_sum_c_1,
adder08_output => ext_b_c_3_b
);
 
sum_c_2 : adder_08bit
port map (
addend_08bit => y2,
augend_08bit => augend_sum_c_2,
adder08_output => ext_b_c_0_b
);
 
sum_c_3 : adder_08bit
port map (
addend_08bit => y3,
augend_08bit => augend_sum_c_3,
adder08_output => ext_b_c_1_b
);
 
sum_p_0 : adder_08bit
port map (
addend_08bit => ext_b_r_1,
augend_08bit => ext_r_r_0,
adder08_output => y0p_b
);
 
sum_p_1 : adder_08bit
port map (
addend_08bit => ext_b_r_0,
augend_08bit => ext_r_r_1,
adder08_output => y1p_b
);
 
sum_p_2 : adder_08bit
port map (
addend_08bit => ext_b_r_3,
augend_08bit => ext_r_r_2,
adder08_output => y2p_b
);
 
sum_p_3 : adder_08bit
port map (
addend_08bit => ext_b_r_2,
augend_08bit => ext_r_r_3,
adder08_output => y3p_b
);
 
row0 : ext_val
port map (
ext_a_i => r0,
ext_b_i => ext_b_r_0,
ext_r_o => ext_r_r_0
);
 
row1 : ext_val
port map (
ext_a_i => r0,
ext_b_i => ext_b_r_1,
ext_r_o => ext_r_r_1
);
 
row2 : ext_val
port map (
ext_a_i => r1,
ext_b_i => ext_b_r_2,
ext_r_o => ext_r_r_2
);
 
row3 : ext_val
port map (
ext_a_i => r1,
ext_b_i => ext_b_r_3,
ext_r_o => ext_r_r_3
);
 
col0 : ext_val
port map (
ext_a_i => c0,
ext_b_i => ext_b_c_0,
ext_r_o => ext_r_c_0
);
 
col1 : ext_val
port map (
ext_a_i => c1,
ext_b_i => ext_b_c_1,
ext_r_o => ext_r_c_1
);
 
col2 : ext_val
port map (
ext_a_i => c0,
ext_b_i => ext_b_c_2,
ext_r_o => ext_r_c_2
);
 
col3 : ext_val
port map (
ext_a_i => c1,
ext_b_i => ext_b_c_3,
ext_r_o => ext_r_c_3
);
 
process (start)
begin
if (start = '1' and start'event) then
 
y0p <= y0p_b (07);
y1p <= y1p_b (07);
y2p <= y2p_b (07);
y3p <= y3p_b (07);
 
end if;
end process;
 
process (start)
begin
if (start = '0' and start'event) then
 
y0d <= y0p;
y1d <= y1p;
y2d <= y2p;
y3d <= y3p;
 
end if;
end process;
 
process (clock, start)
begin
 
if (clock = '0' and clock'event) then
 
if (start = '1') then
y0e <= ( others => '0' );
y1e <= ( others => '0' );
y2e <= ( others => '0' );
y3e <= ( others => '0' );
 
augend_sum_c_0 <= ( others => '0' );
augend_sum_c_1 <= ( others => '0' );
augend_sum_c_2 <= ( others => '0' );
augend_sum_c_3 <= ( others => '0' );
else
y0e <= ext_r_c_0;
y1e <= ext_r_c_1;
y2e <= ext_r_c_2;
y3e <= ext_r_c_3;
augend_sum_c_0 <= ext_r_r_0;
augend_sum_c_1 <= ext_r_r_1;
augend_sum_c_2 <= ext_r_r_2;
augend_sum_c_3 <= ext_r_r_3;
end if;
 
end if;
end process;
 
end structural;
/comparator_7bit.vhdl
0,0 → 1,197
-- $Id: comparator_7bit.vhdl,v 1.1.1.1 2005-11-15 01:52:30 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : 7 bit comparator
-- Project :
-------------------------------------------------------------------------------
-- File : comparator_7bit.vhdl
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2005/11/01
-- Last update :
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : Compare two input ( 7 bit signal )
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity comparator_7bit is
port (
a_7bit_i : in bit_vector (06 downto 00);
b_7bit_i : in bit_vector (06 downto 00);
a_eq_b : out bit;
a_gt_b : out bit;
a_lt_b : out bit
);
end comparator_7bit;
 
architecture structural of comparator_7bit is
 
component bit_comparator
port (
a_i : in bit;
b_i : in bit;
eq_i : in bit;
gt_i : in bit;
lt_i : in bit;
eq_o : out bit;
gt_o : out bit;
lt_o : out bit
);
end component;
 
signal eq_i_0 : bit;
signal gt_i_0 : bit;
signal lt_i_0 : bit;
 
signal eq_o_0 : bit;
signal gt_o_0 : bit;
signal lt_o_0 : bit;
 
signal eq_o_1 : bit;
signal gt_o_1 : bit;
signal lt_o_1 : bit;
 
signal eq_o_2 : bit;
signal gt_o_2 : bit;
signal lt_o_2 : bit;
 
signal eq_o_3 : bit;
signal gt_o_3 : bit;
signal lt_o_3 : bit;
 
signal eq_o_4 : bit;
signal gt_o_4 : bit;
signal lt_o_4 : bit;
 
signal eq_o_5 : bit;
signal gt_o_5 : bit;
signal lt_o_5 : bit;
 
signal eq_o_6 : bit;
signal gt_o_6 : bit;
signal lt_o_6 : bit;
 
begin
 
eq_i_0 <= '1'; -- 20051015 Fixed
gt_i_0 <= '0';
lt_i_0 <= '0';
 
a_eq_b <= eq_o_6;
a_gt_b <= gt_o_6;
a_lt_b <= lt_o_6;
 
cmp6 : bit_comparator
port map (
a_i => a_7bit_i (06),
b_i => b_7bit_i (06),
eq_i => eq_o_5,
gt_i => gt_o_5,
lt_i => lt_o_5,
eq_o => eq_o_6,
gt_o => gt_o_6,
lt_o => lt_o_6
);
 
cmp5 : bit_comparator
port map (
a_i => a_7bit_i (05),
b_i => b_7bit_i (05),
eq_i => eq_o_4,
gt_i => gt_o_4,
lt_i => lt_o_4,
eq_o => eq_o_5,
gt_o => gt_o_5,
lt_o => lt_o_5
);
 
cmp4 : bit_comparator
port map (
a_i => a_7bit_i (04),
b_i => b_7bit_i (04),
eq_i => eq_o_3,
gt_i => gt_o_3,
lt_i => lt_o_3,
eq_o => eq_o_4,
gt_o => gt_o_4,
lt_o => lt_o_4
);
 
cmp3 : bit_comparator
port map (
a_i => a_7bit_i (03),
b_i => b_7bit_i (03),
eq_i => eq_o_2,
gt_i => gt_o_2,
lt_i => lt_o_2,
eq_o => eq_o_3,
gt_o => gt_o_3,
lt_o => lt_o_3
);
 
cmp2 : bit_comparator
port map (
a_i => a_7bit_i (02),
b_i => b_7bit_i (02),
eq_i => eq_o_1,
gt_i => gt_o_1,
lt_i => lt_o_1,
eq_o => eq_o_2,
gt_o => gt_o_2,
lt_o => lt_o_2
);
 
cmp1 : bit_comparator
port map (
a_i => a_7bit_i (01),
b_i => b_7bit_i (01),
eq_i => eq_o_0,
gt_i => gt_o_0,
lt_i => lt_o_0,
eq_o => eq_o_1,
gt_o => gt_o_1,
lt_o => lt_o_1
);
 
cmp0 : bit_comparator
port map (
a_i => a_7bit_i (00),
b_i => b_7bit_i (00),
eq_i => eq_i_0,
gt_i => gt_i_0,
lt_i => lt_i_0,
eq_o => eq_o_0,
gt_o => gt_o_0,
lt_o => lt_o_0
);
 
end structural;
/Makefile
0,0 → 1,51
# $Id: Makefile,v 1.1.1.1 2005-11-15 01:52:30 arif_endro Exp $
# -----------------------------------------------------------------------------
# Title : Alliance Makefile
# Project :
# -----------------------------------------------------------------------------
# File : Makefile
# Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
# Created : 2005/11/01
# Last update :
# Simulators :
# Synthesizers:
# Target :
# -----------------------------------------------------------------------------
# Description : Alliance Makefile from preliminary synthesis
# -----------------------------------------------------------------------------
# Copyright (C) 2005 Arif E. Nugroho
###############################################################################
##
## THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
## PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
## ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
## ASSOCIATED DISCLAIMER.
##
###############################################################################
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
## IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
## EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
## PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
## OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
## WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
## ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
##
###############################################################################
 
VASY = vasy -V -H -s -o
SOURCES = product_code.vhdl
 
all: $(SOURCES)
for SOURCE in $(SOURCES); do\
$(VASY) $${SOURCE};\
done
 
%.vhd : %.vhdl
$(VASY) $<
 
clean:
-rm -v *.vhd
/ext_val.vhdl
0,0 → 1,137
-- $Id: ext_val.vhdl,v 1.1.1.1 2005-11-15 01:52:30 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : External Values
-- Project :
-------------------------------------------------------------------------------
-- File : ext_val.vhdl
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2005/11/01
-- Last update :
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : External Values calculations
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity ext_val is
port (
ext_a_i : in bit_vector (07 downto 00);
ext_b_i : in bit_vector (07 downto 00);
ext_r_o : out bit_vector (07 downto 00)
);
end ext_val;
 
architecture structural of ext_val is
 
component twos_c_8bit
port (
twos_c_i : in bit_vector (07 downto 00);
twos_c_o : out bit_vector (07 downto 00)
);
end component;
 
component comparator_7bit
port (
a_7bit_i : in bit_vector (06 downto 00);
b_7bit_i : in bit_vector (06 downto 00);
a_eq_b : out bit;
a_gt_b : out bit;
a_lt_b : out bit
);
end component;
 
signal twos_c_a_i : bit_vector (07 downto 00);
signal twos_c_a_o : bit_vector (07 downto 00);
signal twos_c_b_i : bit_vector (07 downto 00);
signal twos_c_b_o : bit_vector (07 downto 00);
signal twos_c_r_i : bit_vector (07 downto 00);
signal twos_c_r_o : bit_vector (07 downto 00);
signal a_8bit_i : bit_vector (07 downto 00);
signal b_8bit_i : bit_vector (07 downto 00);
signal ext_r : bit_vector (07 downto 00);
signal a_eq_b : bit;
signal a_gt_b : bit;
signal a_lt_b : bit;
signal sgn_a_b : bit;
 
begin
 
twos_c_a_i <= ext_a_i;
twos_c_b_i <= ext_b_i;
twos_c_r_i <= ext_r;
 
sgn_a_b <= ext_a_i (07) xor ext_b_i (07);
 
a_8bit_i <= ext_a_i (07 downto 00) when ( ext_a_i (07) = '0' ) else
twos_c_a_o (07 downto 00) when ( ext_a_i (07) = '1' ) else
B"0000_0000";
 
b_8bit_i <= ext_b_i (07 downto 00) when ( ext_b_i (07) = '0' ) else
twos_c_b_o (07 downto 00) when ( ext_b_i (07) = '1' ) else
B"0000_0000";
 
ext_r <= a_8bit_i when ( a_lt_b = '1' ) else
b_8bit_i when ( a_lt_b = '0' ) else
B"0000_0000";
 
ext_r_o <= ext_r when ( sgn_a_b = '0' ) else
twos_c_r_o when ( sgn_a_b = '1' ) else
B"0000_0000";
 
compare : comparator_7bit
port map (
a_7bit_i => a_8bit_i (06 downto 00),
b_7bit_i => b_8bit_i (06 downto 00),
a_eq_b => a_eq_b,
a_gt_b => a_gt_b,
a_lt_b => a_lt_b
);
 
complement_a : twos_c_8bit
port map (
twos_c_i => twos_c_a_i,
twos_c_o => twos_c_a_o
);
 
complement_b : twos_c_8bit
port map (
twos_c_i => twos_c_b_i,
twos_c_o => twos_c_b_o
);
 
complement_r : twos_c_8bit
port map (
twos_c_i => twos_c_r_i,
twos_c_o => twos_c_r_o
);
 
end structural;
/fulladder.vhdl
0,0 → 1,59
-- $Id: fulladder.vhdl,v 1.1.1.1 2005-11-15 01:52:30 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Full Adder component
-- Project :
-------------------------------------------------------------------------------
-- File : fulladder.vhdl
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2004/12/01
-- Last update :
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : Simple one bit adder with carry
-------------------------------------------------------------------------------
-- Copyright (C) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.ALL;
 
entity fulladder is
port (
addend : in bit;
augend : in bit;
carry_in : in bit;
sum : out bit;
carry : out bit
);
end fulladder;
architecture data_flow of fulladder is
begin
sum <= ((addend xor augend) xor carry_in);
carry <= ((addend and augend) or (carry_in and (addend or augend)));
end data_flow;

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