URL
https://opencores.org/ocsvn/product_code_iterative_decoder/product_code_iterative_decoder/trunk
Subversion Repositories product_code_iterative_decoder
Compare Revisions
- This comparison shows the changes necessary to convert path
/product_code_iterative_decoder
- from Rev 13 to Rev 14
- ↔ Reverse comparison
Rev 13 → Rev 14
/trunk/bench/modelsim_bench.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Top modules for test bench. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/bench/input.vhdl
11,13 → 11,10
-- Synthesizers: |
-- Target : |
------------------------------------------------------------------------------- |
|
-- Description : |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/bench/output.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Save output to file, to be analyzed. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/source/twos_c_8bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Calculate two's complement of 8 bit signed signal |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/source/adder_08bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : 8 bit signed adder |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/source/bit_comparator.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Compare two input |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/source/ser2par8bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Conversion from serial input to paralel output |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/source/product_code.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Connector of all component in Product Code Iterative Decoder. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/source/comparator_7bit.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Compare two input ( 7 bit signal ) |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/source/ext_val.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : External Values calculations |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/source/fulladder.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Simple one bit adder with carry |
------------------------------------------------------------------------------- |
-- Copyright (C) 2004 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2004 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/xilinx/analyze.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/xilinx/input0DB.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/xilinx/input3DB.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/xilinx/input6DB.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/xilinx/xilinx.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/xilinx/input9DB.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/trunk/xilinx/input.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |