OpenCores
URL https://opencores.org/ocsvn/ps2/ps2/trunk

Subversion Repositories ps2

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /ps2/tags/rel_11/sim
    from Rev 38 to Rev 51
    ↔ Reverse comparison
  •

Rev 38 → Rev 51

/rtl_sim/run/ncelab.args
0,0 → 1,10
-MESSAGES
-NOCOPYRIGHT
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-LOGFILE ../log/ncelab.log
-TIMESCALE 1ns/100ps
-SNAPSHOT worklib.ps2_test_bench:rtl
-NO_TCHK_MSG
-ACCESS +RWC
worklib.ps2_test_bench
/rtl_sim/run/ncsim.key
0,0 → 1,10
exit
/rtl_sim/run/ncvlog.args
0,0 → 1,21
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-MESSAGES
-INCDIR ../../../bench/verilog
-INCDIR ../../../rtl/verilog
-NOCOPYRIGHT
-LOGFILE ../log/ncvlog.log
-DEFINE "PS2_NUM_OF_NORMAL_SCANCODES 85"
-DEFINE "PS2_NUM_OF_EXTENDED_SCANCODES 38"
-DEFINE "SIM"
../../../rtl/verilog/ps2_keyboard.v
../../../rtl/verilog/ps2_mouse.v
../../../rtl/verilog/ps2_top.v
../../../rtl/verilog/ps2_translation_table.v
../../../rtl/verilog/ps2_wb_if.v
../../../rtl/verilog/ps2_io_ctrl.v
../../../bench/verilog/ps2_keyboard_model.v
../../../bench/verilog/ps2_test_bench.v
../../../bench/verilog/wb_master32.v
../../../bench/verilog/wb_master_behavioral.v
../../../bench/verilog/ps2_sim_top.v
/rtl_sim/run/ncsim.args
0,0 → 1,7
-MESSAGES
-NOCOPYRIGHT
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-INPUT ncsim.tcl
-LOGFILE ../log/ncsim.log
worklib.ps2_test_bench:rtl
/rtl_sim/run/ncsim.tcl
0,0 → 1,4
database -open waves -shm -into ../out/waves.shm
probe -create -database waves ps2_test_bench -shm -all -depth all
run
quit
/rtl_sim/run/run_sim
0,0 → 1,99
#!/bin/csh -f
 
set current_par = 0
set output_waveform = 0
while ( $current_par < $# )
@ current_par = $current_par + 1
case wave:
@ output_waveform = 1
breaksw
default:
echo 'Unknown option "'$argv[$current_par]'"!'
exit
breaksw
endsw
end
 
echo "-CDSLIB ../bin/cds.lib" > ncvlog.args
echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args
echo "-MESSAGES" >> ncvlog.args
echo "-INCDIR ../../../bench/verilog" >> ncvlog.args
echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args
echo "-NOCOPYRIGHT" >> ncvlog.args
echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args
echo '-DEFINE "PS2_NUM_OF_NORMAL_SCANCODES 85"' >> ./ncvlog.args
echo '-DEFINE "PS2_NUM_OF_EXTENDED_SCANCODES 38"' >> ./ncvlog.args
echo '-DEFINE "SIM"' >> ./ncvlog.args
 
 
foreach filename ( `cat ../bin/rtl_file_list` )
echo "../../../rtl/verilog/"$filename >> ncvlog.args
end
 
foreach filename ( `cat ../bin/sim_file_list` )
echo "../../../bench/verilog/"$filename >> ncvlog.args
end
 
ncvlog -f ncvlog.args
 
echo "-MESSAGES" > ncelab.args
echo "-NOCOPYRIGHT" >> ncelab.args
echo "-CDSLIB ../bin/cds.lib" >> ncelab.args
echo "-HDLVAR ../bin/hdl.var" >> ncelab.args
echo "-LOGFILE ../log/ncelab.log" >> ncelab.args
echo "-TIMESCALE 1ns/100ps" >> ncelab.args
echo "-SNAPSHOT worklib.ps2_test_bench:rtl" >> ncelab.args
echo "-NO_TCHK_MSG" >> ncelab.args
echo "-ACCESS +RWC" >> ncelab.args
echo "worklib.ps2_test_bench" >> ncelab.args
 
ncelab -f ncelab.args
 
echo "-MESSAGES" > ncsim.args
echo "-NOCOPYRIGHT" >> ncsim.args
echo "-CDSLIB ../bin/cds.lib" >> ncsim.args
echo "-HDLVAR ../bin/hdl.var" >> ncsim.args
echo "-INPUT ncsim.tcl" >> ncsim.args
echo "-LOGFILE ../log/ncsim.log" >> ncsim.args
echo "worklib.ps2_test_bench:rtl" >> ncsim.args
 
if ( $output_waveform ) then
echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl
echo "probe -create -database waves ps2_test_bench -shm -all -depth all" >> ./ncsim.tcl
echo "run" >> ./ncsim.tcl
else
echo "run" > ./ncsim.tcl
endif
 
echo "quit" >> ncsim.tcl
 
ncsim -LICQUEUE -f ./ncsim.args
 
set exit_line_nb = `sed -n '/exit/=' < ../log/ncsim.log`
 
#echo "$exit_line_nb"
 
set dead_line_nb = 0
 
if ( $exit_line_nb ) then
 
@ dead_line_nb = $exit_line_nb - 1
set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ../log/ncsim.log`
set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ../log/ncsim.log`
 
echo "$dead_line"
echo "$exit_line"
 
echo "TEST: ps2"
if ( "$dead_line" == "report (deaddead)" ) then
if ( "$exit_line" == "exit (00000000)" ) then
echo "STATUS: passed" #|tee -a ../log/run_sim.log 2>&1
else
echo "STATUS: failed" #|tee -a ../log/run_sim.log 2>&1
endif
else
echo "STATUS: failed"
endif
 
endif
 
rtl_sim/run/run_sim Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/bin/rtl_file_list =================================================================== --- rtl_sim/bin/rtl_file_list (nonexistent) +++ rtl_sim/bin/rtl_file_list (revision 51) @@ -0,0 +1,6 @@ +ps2_keyboard.v +ps2_mouse.v +ps2_top.v +ps2_translation_table.v +ps2_wb_if.v +ps2_io_ctrl.v Index: rtl_sim/bin/sim_file_list =================================================================== --- rtl_sim/bin/sim_file_list (nonexistent) +++ rtl_sim/bin/sim_file_list (revision 51) @@ -0,0 +1,5 @@ +ps2_keyboard_model.v +ps2_test_bench.v +wb_master32.v +wb_master_behavioral.v +ps2_sim_top.v Index: rtl_sim/bin/xilinx_file_list =================================================================== --- rtl_sim/bin/xilinx_file_list (nonexistent) +++ rtl_sim/bin/xilinx_file_list (revision 51) @@ -0,0 +1,2 @@ +RAMB4_S8.v +glbl.v Index: rtl_sim/bin/cds.lib =================================================================== --- rtl_sim/bin/cds.lib (nonexistent) +++ rtl_sim/bin/cds.lib (revision 51) @@ -0,0 +1,6 @@ +# +# cds.lib: Defines the locations of compiled libraries. +# Created by ncprep on Wed Aug 1 15:03:54 2001 +# + +define worklib ./INCA_libs/worklib Index: rtl_sim/bin/hdl.var =================================================================== --- rtl_sim/bin/hdl.var (nonexistent) +++ rtl_sim/bin/hdl.var (revision 51) @@ -0,0 +1,9 @@ +# +# hdl.var: Defines variables used by the INCA tools. +# Created by ncprep on Wed Aug 1 15:03:54 2001 +# + +softinclude $CDS_INST_DIR/tools/inca/files/hdl.var + +define LIB_MAP ( $LIB_MAP, + => worklib ) +define VIEW_MAP ( $VIEW_MAP, .v => v)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.