URL
https://opencores.org/ocsvn/pss/pss/trunk
Subversion Repositories pss
Compare Revisions
- This comparison shows the changes necessary to convert path
/pss
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/trunk/pss/hdl/pss_soc_top.v
4,7 → 4,7
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9 |
Version 0.99 |
|
The FreeBSD license |
|
73,20 → 73,21
#( |
.CPU_PRESENT(1), |
.CPU_RESET_DEFAULT(0), |
.A31_DEFAULTS(1), |
.MEM_DATA("print_your_full_hex_filename"), |
.A31_DEFAULT(1), |
.MEM_DATA("D:/Research/Computer_Science/Projects/Practice/zpu/pss/pss/SW/onboard/Heartbeat/Heartbeat.hex"), |
.MEM_SIZE_KB(8) |
) |
pss |
PSS |
( |
.clk_i(clk_i), |
.arst_i(rst_i), |
.srst_i(0), |
.srst_o(sync_reset), |
|
.rx_i(rx_i), |
.tx_o(tx_o), |
|
.INT_i(interrupts), |
.INT_bi(interrupts), |
|
.xport_req_o(uc_bus_enb), |
.xport_ack_i(1'b1), |
/trunk/pss/hdl/pss/as_reset_cntrl.v
File deleted
/trunk/pss/hdl/pss/udm/uart_rx.v
4,7 → 4,7
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9 |
Version 0.99 |
|
The FreeBSD license |
|
/trunk/pss/hdl/pss/udm/udm.v
4,7 → 4,7
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9 |
Version 0.99 |
|
The FreeBSD license |
|
/trunk/pss/hdl/pss/udm/uart_tx.v
4,7 → 4,7
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9 |
Version 0.99 |
|
The FreeBSD license |
|
/trunk/pss/hdl/pss/udm/udm_controller.v
4,7 → 4,7
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9 |
Version 0.99 |
|
The FreeBSD license |
|
/trunk/pss/hdl/pss/zpu_uc/int_controller.v
File deleted
/trunk/pss/hdl/pss/zpu_uc/zpu_uc_systemcontroller.v
File deleted
/trunk/pss/hdl/pss/zpu_uc/edge_detector.v
File deleted
/trunk/pss/hdl/pss/zpu_uc/zpu_core_stub.v
File deleted
/trunk/pss/hdl/pss/zpu_uc/zpu_core/zpu_core_stub.v
0,0 → 1,35
module zpu_core_stub |
( |
input clk, |
input sreset, |
input enable, |
output cpu_present, |
output [31:0] pc_bo, |
|
output mem_req, |
output mem_we, |
input mem_ack, |
input [31:0] mem_read, |
output [31:0] mem_write, |
output [31:0] out_mem_addr, |
output [3:0] mem_writeMask, |
|
input interrupt, |
output interrupt_ack, |
output break_o, |
output [63:0] zpu_status |
); |
|
assign cpu_present = 1'b0; |
assign pc_bo = 32'h0; |
assign mem_req = 1'b0; |
assign mem_we = 1'bx; |
assign mem_write = 32'hx; |
assign out_mem_addr = 32'hx; |
assign mem_writeMask = 4'h0; |
|
assign interrupt_ack = 1'b0; |
assign break_o = 1'b0; |
assign zpu_status = 64'h0; |
|
endmodule |
/trunk/pss/hdl/pss/zpu_uc/zpu_uc.v
4,7 → 4,7
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9 |
Version 0.9.0 |
|
The FreeBSD license |
|
38,14 → 38,20
#( |
parameter CPU_PRESENT = 1, |
parameter CPU_RESET_DEFAULT = 1, |
parameter A31_DEFAULTS = 1, |
parameter A31_DEFAULT = 1, |
parameter MEM_DATA = "data.bin", |
parameter MEM_SIZE_KB = 1 |
) |
( |
input clk_i, rst_i, |
input [3:0] INT_i, |
input clk_i, |
|
input arst_i, |
output srst_o, |
input srst_i, |
output ext_rst_o, |
|
input [3:0] INT_bi, |
|
// Expansion bus |
output xport_req_o, |
input xport_ack_i, |
65,7 → 71,10
output [31:0] dbg_data_bo |
); |
|
// ZPU system bus |
wire app_reset; |
assign app_reset = srst_i | srst_o; |
|
// CPU system bus |
wire cpu_bus_enb; |
wire cpu_bus_we; |
wire cpu_bus_ack; |
85,7 → 94,7
wire [31:0] ram1_bus_rddata; |
wire [31:0] ram1_bus_wrdata; |
|
// ZPU control |
// CPU control |
wire cpu_present; |
wire [63:0] zpu_status; |
wire cpu_break; |
96,22 → 105,6
wire cpu_reset; |
wire cpu_enb; |
|
// INTC programming interface |
wire intc_ie; |
wire intc_ie_we; |
wire intc_ie_data; |
wire [7:0] intc_mask; |
wire [7:0] intc_pending; |
wire intc_clr_cmd; |
wire [7:0] intc_clr_code; |
|
// interrupts |
wire [3:0] INT; |
wire bus_error_int; |
wire trap_int; |
wire sgi_int; |
wire dma_int; |
|
generate |
if (CPU_PRESENT == 1) |
|
123,7 → 116,7
zpu_core |
( |
.clk(clk_i), |
.sreset(rst_i | cpu_reset), |
.sreset(app_reset | cpu_reset), |
.enable(cpu_enb), |
.cpu_present(cpu_present), |
.pc_bo(cpu_pc), |
147,7 → 140,7
zpu_core_stub zpu_core |
( |
.clk(clk_i), |
.sreset(rst_i | cpu_reset), |
.sreset(app_reset | cpu_reset), |
.enable(cpu_enb), |
.cpu_present(cpu_present), |
.pc_bo(cpu_pc), |
168,48 → 161,26
|
endgenerate |
|
edge_detector edge_det0 |
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[0]), .out(INT[0]) ); |
|
edge_detector edge_det1 |
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[1]), .out(INT[1]) ); |
|
edge_detector edge_det2 |
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[2]), .out(INT[2]) ); |
|
edge_detector edge_det3 |
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[3]), .out(INT[3]) ); |
|
// Interrupt controller |
int_controller int_controller |
( |
.clk_i(clk_i), |
.rst_i(rst_i), |
.interrupt_bi({INT, dma_int, sgi_int, trap_int, bus_error_int}), |
|
.ie_o(intc_ie), |
.ie_we_i(intc_ie_we), |
.ie_data_i(intc_ie_data), |
.mask_bi(intc_mask), |
.pending_bo(intc_pending), |
.clr_cmd_i(intc_clr_cmd), |
.clr_code_bi(intc_clr_code), |
|
.cpu_req_o(cpu_interrupt), |
.cpu_ack_i(cpu_interrupt_ack) |
); |
|
ZPU_uC_SystemController |
PSS_MotherBlock |
#( |
.A31_DEFAULTS(A31_DEFAULTS), |
.A31_DEFAULT(A31_DEFAULT), |
.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT), |
.MEM_SIZE_KB(MEM_SIZE_KB) |
) |
SystemController |
MotherBlock |
( |
.clk_i(clk_i), |
.rst_i(rst_i), |
|
.arst_i(arst_i), |
.srst_o(srst_o), |
.srst_i(srst_i), |
.ext_rst_o(ext_rst_o), |
|
.INT_bi(INT_bi), |
.cpu_ireq_o(cpu_interrupt), |
.cpu_iack_i(cpu_interrupt_ack), |
|
//// Masters //// |
// Debug bus // |
.dbg_enb_i(dbg_enb_i), |
251,25 → 222,11
.xport_resp_i(xport_resp_i), |
.xport_rdata_bi(xport_rdata_bi), |
|
// INTC bus // |
.intc_ie_i(intc_ie), |
.intc_ie_we_o(intc_ie_we), |
.intc_ie_data_o(intc_ie_data), |
.intc_mask_bo(intc_mask), |
.intc_pending_bi(intc_pending), |
.intc_clr_cmd_o(intc_clr_cmd), |
.intc_clr_code_bo(intc_clr_code), |
|
.cpu_present(cpu_present), |
.cpu_present_i(cpu_present), |
.cpu_pc_bi(cpu_pc), |
.cpu_break_i(cpu_break), |
.cpu_reset_o(cpu_reset), |
.cpu_enb_o(cpu_enb), |
|
.bus_error_int_o(bus_error_int), |
.trap_int_o(trap_int), |
.dma_int_o(dma_int), |
.sgi_int_o(sgi_int) |
.cpu_enb_o(cpu_enb) |
); |
|
ram_dual |
/trunk/pss/hdl/pss/zpu_uc/motherblock/pss_busbridge.v
0,0 → 1,173
/* |
PSS |
|
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9.0 |
|
The FreeBSD license |
|
Redistribution and use in source and binary forms, with or without |
modification, are permitted provided that the following conditions |
are met: |
|
1. Redistributions of source code must retain the above copyright |
notice, this list of conditions and the following disclaimer. |
2. Redistributions in binary form must reproduce the above |
copyright notice, this list of conditions and the following |
disclaimer in the documentation and/or other materials |
provided with the distribution. |
|
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY |
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
|
|
module PSS_BusBridge |
( |
input clk_i, rst_i, |
|
input xport_busy_i, |
output xport_busy_o, |
|
input a31_i, |
|
//// Masters //// |
// Debug bus // |
input bus_enb_i, |
input bus_we_i, |
input [31:0] bus_addr_bi, |
input [31:0] bus_wdata_bi, |
input [3:0] bus_writemask_bi, |
output reg bus_ack_o, |
output reg [31:0] bus_rdata_bo, |
|
// Expansion bus // |
output reg xport_req_o, |
input xport_ack_i, |
input xport_err_i, |
output reg xport_we_o, |
output reg [31:0] xport_addr_bo, |
output reg [31:0] xport_wdata_bo, |
output reg [3:0] xport_writemask_bo, |
input xport_resp_i, |
input [31:0] xport_rdata_bi |
); |
|
localparam ST_IDLE = 2'h0; |
localparam ST_WR_WAIT_ACK = 2'h1; |
localparam ST_RD_WAIT_ACK = 2'h2; |
localparam ST_RD_WAIT_RESP = 2'h3; |
|
reg [1:0] bb_state; |
|
assign xport_busy_o = bus_enb_i; |
|
assign rdata_bo = xport_rdata_bi; |
|
always @(posedge clk_i) |
begin |
if (rst_i) |
begin |
bb_state <= ST_IDLE; |
|
bus_ack_o <= 1'b0; |
bus_rdata_bo <= 32'hx; |
|
xport_req_o <= 1'b0; |
xport_we_o <= 1'b0; |
xport_addr_bo <= 32'hx; |
xport_wdata_bo <= 32'hx; |
xport_writemask_bo <= 4'hx; |
end |
else |
begin |
|
bus_ack_o <= 1'b0; |
bus_rdata_bo <= 32'hx; |
|
case (bb_state) |
|
ST_IDLE: |
begin |
if ((bus_enb_i == 1'b1) && (bus_ack_o == 1'b0)) |
begin |
if (bus_we_i == 1'b1) |
begin |
xport_req_o <= 1'b1; |
xport_we_o <= 1'b1; |
xport_addr_bo <= bus_addr_bi; |
xport_wdata_bo <= bus_wdata_bi; |
xport_writemask_bo <= bus_writemask_bi; |
bb_state <= ST_WR_WAIT_ACK; |
end |
else |
begin |
xport_req_o <= 1'b1; |
xport_we_o <= 1'b0; |
xport_addr_bo <= bus_addr_bi; |
xport_wdata_bo <= bus_wdata_bi; |
xport_writemask_bo <= bus_writemask_bi; |
bb_state <= ST_RD_WAIT_ACK; |
end |
end |
end |
|
ST_WR_WAIT_ACK: |
begin |
if (xport_ack_i == 1'b1) |
begin |
xport_req_o <= 1'b0; |
xport_we_o <= 1'b0; |
xport_addr_bo <= 32'hx; |
xport_wdata_bo <= 32'hx; |
xport_writemask_bo <= 4'hx; |
|
bus_ack_o <= 1'b1; |
|
bb_state <= ST_IDLE; |
end |
end |
|
ST_RD_WAIT_ACK: |
begin |
if (xport_ack_i == 1'b1) |
begin |
xport_req_o <= 1'b0; |
xport_we_o <= 1'b0; |
xport_addr_bo <= 32'hx; |
xport_wdata_bo <= 32'hx; |
xport_writemask_bo <= 4'hx; |
|
bb_state <= ST_RD_WAIT_RESP; |
end |
end |
|
ST_RD_WAIT_RESP: |
begin |
if (xport_resp_i == 1'b1) |
begin |
bus_ack_o <= 1'b1; |
bus_rdata_bo <= xport_rdata_bi; |
|
bb_state <= ST_IDLE; |
end |
end |
|
endcase |
|
end |
end |
|
endmodule |
/trunk/pss/hdl/pss/zpu_uc/motherblock/pss_motherblock.v
0,0 → 1,448
/* |
PSS |
|
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9.0 |
|
The FreeBSD license |
|
Redistribution and use in source and binary forms, with or without |
modification, are permitted provided that the following conditions |
are met: |
|
1. Redistributions of source code must retain the above copyright |
notice, this list of conditions and the following disclaimer. |
2. Redistributions in binary form must reproduce the above |
copyright notice, this list of conditions and the following |
disclaimer in the documentation and/or other materials |
provided with the distribution. |
|
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY |
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
|
|
module PSS_MotherBlock |
#( |
parameter A31_DEFAULT = 1, |
parameter CPU_RESET_DEFAULT = 1, |
parameter MEM_SIZE_KB = 1 |
) |
( |
input clk_i, |
|
input arst_i, |
output srst_o, |
input srst_i, |
output ext_rst_o, |
|
input [3:0] INT_bi, |
output cpu_ireq_o, |
input cpu_iack_i, |
|
//// Masters //// |
// Debug bus // |
input dbg_enb_i, |
input dbg_we_i, |
input [31:0] dbg_addr_bi, |
input [31:0] dbg_wdata_bi, |
output dbg_ack_o, |
output [31:0] dbg_rdata_bo, |
|
// ZPU bus // |
input cpu_enb_i, |
input cpu_we_i, |
input [31:0] cpu_wdata_bi, |
input [31:0] cpu_addr_bi, |
input [3:0] cpu_writemask_bi, |
output cpu_ack_o, |
output [31:0] cpu_rdata_bo, |
|
//// Slaves //// |
// RAM0 bus // |
output [31:0] ram0_addr_bo, |
output ram0_we_o, |
output [31:0] ram0_wdata_bo, |
input [31:0] ram0_rdata_bi, |
|
// RAM1 bus // |
output [31:0] ram1_addr_bo, |
output ram1_we_o, |
output [31:0] ram1_wdata_bo, |
input [31:0] ram1_rdata_bi, |
|
// Expansion bus // |
output reg xport_req_o, |
input xport_ack_i, |
input xport_err_i, |
output reg xport_we_o, |
output reg [31:0] xport_addr_bo, |
output reg [31:0] xport_wdata_bo, |
input xport_resp_i, |
input [31:0] xport_rdata_bi, |
|
input cpu_present_i, |
input [31:0] cpu_pc_bi, |
input cpu_break_i, |
output cpu_reset_o, |
output cpu_enb_o |
); |
|
wire app_reset; |
assign app_reset = srst_i | srst_o; |
|
pss_reset_cntrl reset_cntrl |
( |
.clk_i(clk_i), |
.arst_i(arst_i), |
.srst_o(srst_o) |
); |
|
// interrupts |
wire [3:0] INT; |
wire bus_error_int; |
wire trap_int; |
wire sgi_int; |
wire dma_int; |
|
wire bus_error; |
wire [31:0] bus_error_addr; |
|
assign bus_error_int = bus_error; |
|
// INTC programming interface |
wire intc_ie; |
wire intc_ie_we; |
wire intc_ie_data; |
wire [7:0] intc_mask; |
wire [7:0] intc_pending; |
wire intc_clr_cmd; |
wire [7:0] intc_clr_code; |
|
pss_edge_detector edge_det0 |
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[0]), .out(INT[0]) ); |
|
pss_edge_detector edge_det1 |
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[1]), .out(INT[1]) ); |
|
pss_edge_detector edge_det2 |
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[2]), .out(INT[2]) ); |
|
pss_edge_detector edge_det3 |
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[3]), .out(INT[3]) ); |
|
// Interrupt controller |
pss_int_controller int_controller |
( |
.clk_i(clk_i), |
.rst_i(rst_i), |
.interrupt_bi({INT, dma_int, sgi_int, trap_int, bus_error_int}), |
|
.ie_o(intc_ie), |
.ie_we_i(intc_ie_we), |
.ie_data_i(intc_ie_data), |
.mask_bi(intc_mask), |
.pending_bo(intc_pending), |
.clr_cmd_i(intc_clr_cmd), |
.clr_code_bi(intc_clr_code), |
|
.cpu_req_o(cpu_ireq_o), |
.cpu_ack_i(cpu_iack_i) |
); |
|
assign cpu_enb_o = 1'b1; |
|
reg trap_enable; |
reg [31:0] trap_addr; |
|
wire dma_req, dma_cmd, dma_autoinc; |
wire [31:0] dma_sourceaddr; |
wire [31:0] dma_destaddr; |
wire [31:0] dma_size; |
|
wire a31; |
wire dma_works, bb_works; |
|
//////// |
wire sfr_enb; |
wire sfr_we; |
wire [31:0] sfr_wdata; |
wire [31:0] sfr_addr; |
wire [3:0] sfr_writemask; |
wire sfr_ack; |
wire [31:0] sfr_rdata; |
|
wire ext_enb; |
wire ext_we; |
wire [31:0] ext_wdata; |
wire [31:0] ext_addr; |
wire [3:0] ext_writemask; |
wire ext_ack; |
wire [31:0] ext_rdata; |
|
// RAM0 control // |
wire ram0_enb; |
reg ram0_ack, ram0_ack_rd; |
|
always @(posedge clk_i) |
begin |
if (app_reset == 1'b1) ram0_ack_rd <= 1'b0; |
else if ((ram0_enb == 1'b1) && (ram0_we_o == 1'b0) && (ram0_ack_rd == 1'b0)) ram0_ack_rd <= 1'b1; |
else ram0_ack_rd <= 1'b0; |
end |
|
always @* |
begin |
if ((ram0_enb == 1'b1) && (ram0_we_o == 1'b1)) ram0_ack = 1'b1; |
else ram0_ack = ram0_ack_rd; |
end |
|
|
PSS_IC |
#( |
.MEM_SIZE_KB(MEM_SIZE_KB) |
) |
IC_fabric |
( |
.clk_i(clk_i), |
.rst_i(app_reset), |
|
//// Masters //// |
.m0_enb_i(dbg_enb_i), |
.m0_we_i(dbg_we_i), |
.m0_addr_bi(dbg_addr_bi), |
.m0_wdata_bi(dbg_wdata_bi), |
.m0_writemask_bi(dbg_writemask_bi), |
.m0_ack_o(dbg_ack_o), |
.m0_rdata_bo(dbg_rdata_bo), |
|
.m1_enb_i(cpu_enb_i), |
.m1_we_i(cpu_we_i), |
.m1_addr_bi(cpu_addr_bi), |
.m1_wdata_bi(cpu_wdata_bi), |
.m1_writemask_bi(cpu_writemask_bi), |
.m1_ack_o(cpu_ack_o), |
.m1_rdata_bo(cpu_rdata_bo), |
|
//// Slaves //// |
.s0_enb_o(ram0_enb), |
.s0_we_o(ram0_we_o), |
.s0_addr_bo(ram0_addr_bo), |
.s0_wdata_bo(ram0_wdata_bo), |
.s0_writemask_bo(ram0_writemask_bo), |
.s0_ack_i(ram0_ack), |
.s0_rdata_bi(ram0_rdata_bi), |
|
.s1_enb_o(sfr_enb), |
.s1_we_o(sfr_we), |
.s1_addr_bo(sfr_addr), |
.s1_wdata_bo(sfr_wdata), |
.s1_writemask_bo(sfr_writemask), |
.s1_ack_i(sfr_ack), |
.s1_rdata_bi(sfr_rdata), |
|
.s2_enb_o(ext_enb), |
.s2_we_o(ext_we), |
.s2_addr_bo(ext_addr), |
.s2_wdata_bo(ext_wdata), |
.s2_writemask_bo(ext_writemask), |
.s2_ack_i(ext_ack), |
.s2_rdata_bi(ext_rdata), |
|
.error_o(bus_error), |
.error_addr_bo(bus_error_addr) |
); |
|
|
PSS_SFR |
#( |
.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT), |
.A31_DEFAULT(A31_DEFAULT), |
.MEM_SIZE_KB(MEM_SIZE_KB) |
) |
SFR |
( |
.clk_i(clk_i), |
.rst_i(app_reset), |
|
.bus_enb_i(sfr_enb), |
.bus_we_i(sfr_we), |
.bus_wdata_bi(sfr_wdata), |
.bus_addr_bi(sfr_addr), |
.bus_writemask_bi(sfr_writemask), |
.bus_ack_o(sfr_ack), |
.bus_rdata_bo(sfr_rdata), |
|
.cpu_present_i(cpu_present_i), |
.cpu_break_i(cpu_break_i), |
.cpu_pc_bi(cpu_pc_bi), |
|
.trap_cpu_enb_i(cpu_enb_i), |
.trap_cpu_addr_bi(cpu_addr_bi), |
|
.cpu_reset_o(cpu_reset_o), |
.a31_o(a31), |
|
.bus_error_i(bus_error), |
.bus_error_addr_bi(bus_error_addr), |
|
.sgi_int_o(sgi_int), |
.trap_int_o(trap_int), |
|
.intc_ie_i(intc_ie), |
.intc_pending_bi(intc_pending), |
.intc_ie_we_o(intc_ie_we), |
.intc_ie_data_o(intc_ie_data), |
.intc_mask_bo(intc_mask), |
.intc_clr_cmd_o(intc_clr_cmd), |
.intc_clr_code_bo(intc_clr_code), |
|
.dma_req_o(dma_req), |
.dma_cmd_o(dma_cmd), |
.dma_autoinc_o(dma_autoinc), |
.dma_size_bo(dma_size), |
.dma_sourceaddr_bo(dma_sourceaddr), |
.dma_destaddr_bo(dma_destaddr) |
); |
|
|
wire bb_xport_req; |
reg bb_xport_ack; |
reg bb_xport_err; |
wire bb_xport_we; |
wire [31:0] bb_xport_addr; |
wire [31:0] bb_xport_wdata; |
reg bb_xport_resp; |
reg [31:0] bb_xport_rdata; |
|
wire dma_xport_req; |
reg dma_xport_ack; |
reg dma_xport_err; |
wire dma_xport_we; |
wire [31:0] dma_xport_addr; |
wire [31:0] dma_xport_wdata; |
reg dma_xport_resp; |
reg [31:0] dma_xport_rdata; |
|
|
PSS_DMA DMA |
( |
.clk_i(clk_i), |
.rst_i(app_reset), |
|
.xport_busy_i(bb_works), |
.xport_busy_o(dma_works), |
|
.dma_int_o(dma_int), |
|
.dma_req_i(dma_req), |
.dma_cmd_i(dma_cmd), |
.dma_autoinc_i(dma_autoinc), |
.dma_size_bi(REG_DMA_SIZE), |
.dma_sourceaddr_bi(REG_DMA_SOURCEADDR), |
.dma_destaddr_bi(REG_DMA_DESTADDR), |
|
.ram_addr_bo(ram1_addr_bo), |
.ram_we_o(ram1_we_o), |
.ram_wdata_bo(ram1_wdata_bo), |
.ram_rdata_bi(ram1_rdata_bi), |
|
.xport_req_o(dma_xport_req), |
.xport_ack_i(dma_xport_ack), |
.xport_err_i(dma_xport_err), |
.xport_we_o(dma_xport_we), |
.xport_addr_bo(dma_xport_addr), |
.xport_wdata_bo(dma_xport_wdata), |
.xport_resp_i(dma_xport_resp), |
.xport_rdata_bi(dma_xport_rdata) |
); |
|
|
PSS_BusBridge BusBridge |
( |
.clk_i(clk_i), |
.rst_i(app_reset), |
|
.xport_busy_i(dma_works), |
.xport_busy_o(bb_works), |
|
.a31_i(a31), |
|
.bus_enb_i(ext_enb), |
.bus_we_i(ext_we), |
.bus_addr_bi(ext_addr), |
.bus_wdata_bi(ext_wdata), |
.bus_writemask_bi(ext_writemask), |
.bus_ack_o(ext_ack), |
.bus_rdata_bo(ext_rdata), |
|
// Expansion bus // |
.xport_req_o(bb_xport_req), |
.xport_ack_i(bb_xport_ack), |
.xport_err_i(bb_xport_err), |
.xport_we_o(bb_xport_we), |
.xport_addr_bo(bb_xport_addr), |
.xport_wdata_bo(bb_xport_wdata), |
.xport_resp_i(bb_xport_resp), |
.xport_rdata_bi(bb_xport_rdata) |
); |
|
// bus switch |
always @* |
begin |
|
bb_xport_ack = 1'b0; |
bb_xport_err = 1'b0; |
bb_xport_resp = 1'b0; |
bb_xport_rdata = 32'bx; |
|
dma_xport_ack = 1'b0; |
dma_xport_err = 1'b0; |
dma_xport_resp = 1'b0; |
dma_xport_rdata = 32'bx; |
|
if (dma_works == 1'b0) // switch to bus bridge |
begin |
|
bb_xport_ack = xport_ack_i; |
bb_xport_err = xport_err_i; |
bb_xport_resp = xport_resp_i; |
bb_xport_rdata = xport_rdata_bi; |
|
xport_req_o = bb_xport_req; |
xport_we_o = bb_xport_we; |
xport_addr_bo = bb_xport_addr; |
xport_wdata_bo = bb_xport_wdata; |
|
end |
|
else // switch to dma |
begin |
|
dma_xport_ack = xport_ack_i; |
dma_xport_err = xport_err_i; |
dma_xport_resp = xport_resp_i; |
dma_xport_rdata = xport_rdata_bi; |
|
xport_req_o = dma_xport_req; |
xport_we_o = dma_xport_we; |
xport_addr_bo = dma_xport_addr; |
xport_wdata_bo = dma_xport_wdata; |
|
end |
|
end |
|
endmodule |
/trunk/pss/hdl/pss/zpu_uc/motherblock/pss_sfr.v
0,0 → 1,232
module PSS_SFR |
#( |
parameter CPU_RESET_DEFAULT = 1, |
parameter A31_DEFAULT = 1, |
parameter MEM_SIZE_KB = 1 |
) |
( |
input clk_i, rst_i, |
|
// bus controls |
input bus_enb_i, |
input bus_we_i, |
input [31:0] bus_wdata_bi, |
input [31:0] bus_addr_bi, |
input [3:0] bus_writemask_bi, |
output reg bus_ack_o, |
output reg [31:0] bus_rdata_bo, |
|
// special function signals |
input cpu_present_i, |
input cpu_break_i, |
input [31:0] cpu_pc_bi, |
|
input trap_cpu_enb_i, |
input [31:0] trap_cpu_addr_bi, |
|
output reg cpu_reset_o, |
output cpu_enb_o, |
output reg a31_o, |
|
input bus_error_i, |
input [31:0] bus_error_addr_bi, |
|
// interrupts |
output reg bus_error_int_o, |
output reg sgi_int_o, |
output reg trap_int_o, |
|
// interrupt controller signals |
input intc_ie_i, |
input [7:0] intc_pending_bi, |
output reg intc_ie_we_o, |
output reg intc_ie_data_o, |
output reg [7:0] intc_mask_bo, |
output reg intc_clr_cmd_o, |
output reg [7:0] intc_clr_code_bo, |
|
// DMA controls |
output reg dma_req_o, |
output reg dma_cmd_o, |
output reg dma_autoinc_o, |
output reg [31:0] dma_size_bo, |
output reg [31:0] dma_sourceaddr_bo, |
output reg [31:0] dma_destaddr_bo |
); |
|
//// System registers //// |
localparam REG_CPU_CONTROL_ADDR = 8'h00; |
localparam REG_CPU_PC_ADDR = 8'h04; |
localparam REG_A31 = 8'h08; |
|
localparam REG_INTC_CONTROL_ADDR = 8'h10; |
localparam REG_INTC_MASK_ADDR = 8'h14; |
localparam REG_INTC_REQ_ADDR = 8'h18; |
localparam REG_MEM_SIZE_KB = 8'h1C; |
|
localparam REG_DMA_CONTROL_ADDR = 8'h20; |
localparam REG_DMA_SOURCEADDR_ADDR = 8'h24; |
localparam REG_DMA_DESTADDR_ADDR = 8'h28; |
localparam REG_DMA_SIZE_ADDR = 8'h2C; |
|
localparam REG_SGI_ADDR = 8'h30; |
|
localparam REG_BUS_ERROR_ADDR_ADDR = 8'h38; |
localparam REG_BUS_ERROR_PC_ADDR = 8'h3C; |
|
localparam REG_TRAP_CONTROL_ADDR = 8'h40; |
localparam REG_TRAP_ADDR_ADDR = 8'h44; |
|
assign cpu_enb_o = 1'b1; |
|
reg trap_enable; |
reg [31:0] trap_addr; |
|
reg [31:0] bus_error_pc; |
reg [31:0] bus_error_addr; |
|
reg bus_ack_rd; |
always @(posedge clk_i) |
begin |
if (rst_i) bus_ack_rd <= 1'b0; |
else if ((bus_enb_i == 1'b1) && (bus_we_i == 1'b0) && (bus_ack_rd == 1'b0)) bus_ack_rd <= 1'b1; |
else bus_ack_rd <= 1'b0; |
end |
|
always @* |
begin |
if ((bus_enb_i == 1'b1) && (bus_we_i == 1'b1)) bus_ack_o = 1'b1; |
else bus_ack_o = bus_ack_rd; |
end |
|
always @(posedge clk_i) |
begin |
if (rst_i) |
begin |
|
cpu_reset_o <= CPU_RESET_DEFAULT; |
a31_o <= A31_DEFAULT; |
|
trap_enable <= 1'b0; |
trap_addr <= 32'h0; |
|
sgi_int_o <= 1'b0; |
|
dma_req_o <= 1'b0; |
dma_cmd_o <= 1'b0; |
dma_autoinc_o <= 1'b0; |
|
intc_ie_we_o <= 1'b0; |
intc_ie_data_o <= 1'bx; |
intc_mask_bo <= 8'h0; |
intc_clr_cmd_o <= 1'b0; |
intc_clr_code_bo <= 8'hx; |
|
dma_sourceaddr_bo <= 32'h0; |
dma_destaddr_bo <= 32'h0; |
dma_size_bo <= 32'h0; |
end |
else |
begin |
|
sgi_int_o <= 1'b0; |
|
intc_ie_we_o <= 1'b0; |
intc_clr_cmd_o <= 1'b0; |
bus_rdata_bo <= 32'hx; |
|
dma_req_o <= 1'b0; |
|
if (bus_enb_i == 1'b1) |
begin |
if (bus_we_i == 1'b0) |
case (bus_addr_bi[7:0]) |
REG_CPU_CONTROL_ADDR: bus_rdata_bo <= {cpu_present_i, 29'h0, cpu_break_i, cpu_reset_o}; |
REG_CPU_PC_ADDR: bus_rdata_bo <= cpu_pc_bi; |
REG_A31: bus_rdata_bo <= {31'h0, a31_o}; |
|
REG_INTC_CONTROL_ADDR: bus_rdata_bo <= {31'h0, intc_ie_i}; |
REG_INTC_MASK_ADDR: bus_rdata_bo <= {24'h0, intc_mask_bo}; |
REG_INTC_REQ_ADDR: bus_rdata_bo <= {24'h0, intc_pending_bi}; |
REG_MEM_SIZE_KB: bus_rdata_bo <= MEM_SIZE_KB; |
|
REG_DMA_SOURCEADDR_ADDR: bus_rdata_bo <= dma_sourceaddr_bo; |
REG_DMA_DESTADDR_ADDR: bus_rdata_bo <= dma_destaddr_bo; |
REG_DMA_SIZE_ADDR: bus_rdata_bo <= dma_size_bo; |
|
REG_TRAP_CONTROL_ADDR: bus_rdata_bo <= {31'h0, trap_enable}; |
REG_TRAP_ADDR_ADDR: bus_rdata_bo <= trap_addr; |
|
REG_BUS_ERROR_ADDR_ADDR: bus_rdata_bo <= bus_error_addr; |
REG_BUS_ERROR_PC_ADDR: bus_rdata_bo <= bus_error_pc; |
endcase |
else |
case (bus_addr_bi[7:0]) |
REG_CPU_CONTROL_ADDR: cpu_reset_o <= bus_wdata_bi[0]; |
REG_A31: a31_o <= bus_wdata_bi[0]; |
|
REG_INTC_CONTROL_ADDR: begin intc_ie_we_o <= 1'b1; intc_ie_data_o <= bus_wdata_bi[0]; end |
REG_INTC_MASK_ADDR: intc_mask_bo <= bus_wdata_bi[7:0]; |
REG_INTC_REQ_ADDR: begin intc_clr_cmd_o <= 1'b1; intc_clr_code_bo <= bus_wdata_bi[7:0]; end |
|
REG_DMA_CONTROL_ADDR: begin dma_req_o <= 1'b1; dma_cmd_o <= bus_wdata_bi[1]; dma_autoinc_o <= bus_wdata_bi[2]; end |
REG_DMA_SOURCEADDR_ADDR: begin |
if (bus_wdata_bi[31] == 1'b1) |
dma_sourceaddr_bo <= {a31_o, bus_wdata_bi[30:0]}; |
else |
dma_sourceaddr_bo <= bus_wdata_bi; |
end |
REG_DMA_DESTADDR_ADDR: begin |
|
if (bus_wdata_bi[31] == 1'b1) |
dma_destaddr_bo <= {a31_o, bus_wdata_bi[30:0]}; |
else |
dma_destaddr_bo <= bus_wdata_bi; |
end |
REG_DMA_SIZE_ADDR: dma_size_bo <= bus_wdata_bi; |
|
REG_SGI_ADDR: sgi_int_o <= 1'b1; |
|
REG_TRAP_CONTROL_ADDR: trap_enable <= bus_wdata_bi[0]; |
REG_TRAP_ADDR_ADDR: trap_addr <= bus_wdata_bi; |
endcase |
end |
end |
end |
|
// trap logic |
always @(posedge clk_i) |
begin |
if (rst_i) |
trap_int_o <= 1'b0; |
else |
begin |
trap_int_o <= 1'b0; |
if (trap_enable == 1'b1) |
if (trap_cpu_enb_i == 1'b1) |
if (trap_cpu_addr_bi == trap_addr) |
trap_int_o <= 1'b1; |
end |
end |
|
always @(posedge clk_i) |
begin |
if (rst_i) |
begin |
bus_error_int_o <= 1'b0; |
bus_error_addr <= 32'h0; |
bus_error_pc <= 32'h0; |
end |
else |
begin |
bus_error_int_o <= 1'b0; |
if (bus_error_i == 1'b1) |
begin |
bus_error_int_o <= 1'b1; |
bus_error_addr <= bus_error_addr_bi; |
bus_error_pc <= cpu_pc_bi; |
end |
end |
end |
|
endmodule |
/trunk/pss/hdl/pss/zpu_uc/motherblock/pss_ic.v
0,0 → 1,441
/* |
PSS |
|
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9 |
|
The FreeBSD license |
|
Redistribution and use in source and binary forms, with or without |
modification, are permitted provided that the following conditions |
are met: |
|
1. Redistributions of source code must retain the above copyright |
notice, this list of conditions and the following disclaimer. |
2. Redistributions in binary form must reproduce the above |
copyright notice, this list of conditions and the following |
disclaimer in the documentation and/or other materials |
provided with the distribution. |
|
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY |
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
|
|
module PSS_IC |
#( |
parameter MEM_SIZE_KB = 1 |
) |
( |
input clk_i, |
input rst_i, |
|
//// Masters //// |
input m0_enb_i, |
input m0_we_i, |
input [31:0] m0_addr_bi, |
input [31:0] m0_wdata_bi, |
input [3:0] m0_writemask_bi, |
output reg m0_ack_o, |
output reg [31:0] m0_rdata_bo, |
|
input m1_enb_i, |
input m1_we_i, |
input [31:0] m1_addr_bi, |
input [31:0] m1_wdata_bi, |
input [3:0] m1_writemask_bi, |
output reg m1_ack_o, |
output reg [31:0] m1_rdata_bo, |
|
//// Slaves //// |
output reg s0_enb_o, |
output reg s0_we_o, |
output reg [31:0] s0_addr_bo, |
output reg [31:0] s0_wdata_bo, |
output reg [3:0] s0_writemask_bo, |
input s0_ack_i, |
input [31:0] s0_rdata_bi, |
|
output reg s1_enb_o, |
output reg s1_we_o, |
output reg [31:0] s1_addr_bo, |
output reg [31:0] s1_wdata_bo, |
output reg [3:0] s1_writemask_bo, |
input s1_ack_i, |
input [31:0] s1_rdata_bi, |
|
output reg s2_enb_o, |
output reg s2_we_o, |
output reg [31:0] s2_addr_bo, |
output reg [31:0] s2_wdata_bo, |
output reg [3:0] s2_writemask_bo, |
input s2_ack_i, |
input [31:0] s2_rdata_bi, |
|
output reg error_o, |
output reg [31:0] error_addr_bo |
); |
|
reg m0_s0_enb, m0_s1_enb, m0_s2_enb, m0_err_enb; |
reg m1_s0_enb, m1_s1_enb, m1_s2_enb, m1_err_enb; |
|
always @* |
begin |
m0_s0_enb = 1'b0; |
m0_s1_enb = 1'b0; |
m0_s2_enb = 1'b0; |
m0_err_enb = 1'b0; |
|
if (m0_enb_i == 1'b1) |
begin |
if (m0_addr_bi[31:10] < MEM_SIZE_KB) |
m0_s0_enb = 1'b1; |
else if (m0_addr_bi[31:16] == 16'h4000) |
m0_s1_enb = 1'b1; |
else if (m0_addr_bi[31] == 1'b1) |
m0_s2_enb = 1'b1; |
else m0_err_enb = 1'b1; |
end |
end |
|
always @* |
begin |
m1_s0_enb = 1'b0; |
m1_s1_enb = 1'b0; |
m1_s2_enb = 1'b0; |
m1_err_enb = 1'b0; |
|
if (m1_enb_i == 1'b1) |
begin |
if (m1_addr_bi[31:10] < MEM_SIZE_KB) |
m1_s0_enb = 1'b1; |
else if (m1_addr_bi[31:16] == 16'h4000) |
m1_s1_enb = 1'b1; |
else if (m1_addr_bi[31] == 1'b1) |
m1_s2_enb = 1'b1; |
else m1_err_enb = 1'b1; |
end |
end |
|
reg s0_pending, s1_pending, s2_pending; |
reg s0_curmaster, s1_curmaster, s2_curmaster; |
|
// Transaction drivers |
always @(posedge clk_i) |
begin |
if (rst_i) |
begin |
s0_pending <= 1'b0; |
s0_curmaster <= 1'bx; |
end |
else |
begin |
if ((s0_pending == 1'b0) && (s0_ack_i == 1'b0)) |
begin |
if (m0_s0_enb == 1'b1) |
begin |
s0_pending <= 1'b1; |
s0_curmaster <= 1'b0; |
end |
else if (m1_s0_enb == 1'b1) |
begin |
s0_pending <= 1'b1; |
s0_curmaster <= 1'b1; |
end |
end |
else |
begin |
if (s0_ack_i == 1'b1) |
begin |
s0_pending <= 1'b0; |
s0_curmaster <= 1'bx; |
end |
end |
end |
end |
|
always @(posedge clk_i) |
begin |
if (rst_i) |
begin |
s1_pending <= 1'b0; |
s1_curmaster <= 1'bx; |
end |
else |
begin |
if ((s1_pending == 1'b0) && (s1_ack_i == 1'b0)) |
begin |
if (m0_s1_enb == 1'b1) |
begin |
s1_pending <= 1'b1; |
s1_curmaster <= 1'b0; |
end |
else if (m1_s1_enb == 1'b1) |
begin |
s1_pending <= 1'b1; |
s1_curmaster <= 1'b1; |
end |
end |
else |
begin |
if (s1_ack_i == 1'b1) |
begin |
s1_pending <= 1'b0; |
s1_curmaster <= 1'bx; |
end |
end |
end |
end |
|
always @(posedge clk_i) |
begin |
if (rst_i) |
begin |
s2_pending <= 1'b0; |
s2_curmaster <= 1'bx; |
end |
else |
begin |
if ((s2_pending == 1'b0) && (s2_ack_i == 1'b0)) |
begin |
if (m0_s2_enb == 1'b1) |
begin |
s2_pending <= 1'b1; |
s2_curmaster <= 1'b0; |
end |
else if (m1_s2_enb == 1'b1) |
begin |
s2_pending <= 1'b1; |
s2_curmaster <= 1'b1; |
end |
end |
else |
begin |
if (s2_ack_i == 1'b1) |
begin |
s2_pending <= 1'b0; |
s2_curmaster <= 1'bx; |
end |
end |
end |
end |
|
// Slave drivers |
always @* |
begin |
s0_enb_o = 1'b0; |
s0_we_o = 1'b0; |
s0_addr_bo = 32'hx; |
s0_wdata_bo = 32'hx; |
s0_writemask_bo = 4'hx; |
if (s0_pending == 1'b1) |
begin |
if (s0_curmaster == 1'b0) |
begin |
s0_enb_o = m0_enb_i; |
s0_we_o = m0_we_i; |
s0_addr_bo = m0_addr_bi; |
s0_wdata_bo = m0_wdata_bi; |
s0_writemask_bo = m0_writemask_bi; |
end |
else |
begin |
s0_enb_o = m1_enb_i; |
s0_we_o = m1_we_i; |
s0_addr_bo = m1_addr_bi; |
s0_wdata_bo = m1_wdata_bi; |
s0_writemask_bo = m1_writemask_bi; |
end |
end |
else if (m0_s0_enb == 1'b1) |
begin |
s0_enb_o = m0_enb_i; |
s0_we_o = m0_we_i; |
s0_addr_bo = m0_addr_bi; |
s0_wdata_bo = m0_wdata_bi; |
s0_writemask_bo = m0_writemask_bi; |
end |
else if (m1_s0_enb == 1'b1) |
begin |
s0_enb_o = m1_enb_i; |
s0_we_o = m1_we_i; |
s0_addr_bo = m1_addr_bi; |
s0_wdata_bo = m1_wdata_bi; |
s0_writemask_bo = m1_writemask_bi; |
end |
end |
|
always @* |
begin |
s1_enb_o = 1'b0; |
s1_we_o = 1'b0; |
s1_addr_bo = 32'hx; |
s1_wdata_bo = 32'hx; |
s1_writemask_bo = 4'hx; |
if (s1_pending == 1'b1) |
begin |
if (s1_curmaster == 1'b0) |
begin |
s1_enb_o = m0_enb_i; |
s1_we_o = m0_we_i; |
s1_addr_bo = m0_addr_bi; |
s1_wdata_bo = m0_wdata_bi; |
s1_writemask_bo = m0_writemask_bi; |
end |
else |
begin |
s1_enb_o = m1_enb_i; |
s1_we_o = m1_we_i; |
s1_addr_bo = m1_addr_bi; |
s1_wdata_bo = m1_wdata_bi; |
s1_writemask_bo = m1_writemask_bi; |
end |
end |
else if (m0_s1_enb == 1'b1) |
begin |
s1_enb_o = m0_enb_i; |
s1_we_o = m0_we_i; |
s1_addr_bo = m0_addr_bi; |
s1_wdata_bo = m0_wdata_bi; |
s1_writemask_bo = m0_writemask_bi; |
end |
else if (m1_s1_enb == 1'b1) |
begin |
s1_enb_o = m1_enb_i; |
s1_we_o = m1_we_i; |
s1_addr_bo = m1_addr_bi; |
s1_wdata_bo = m1_wdata_bi; |
s1_writemask_bo = m1_writemask_bi; |
end |
end |
|
always @* |
begin |
s2_enb_o = 1'b0; |
s2_we_o = 1'b0; |
s2_addr_bo = 32'hx; |
s2_wdata_bo = 32'hx; |
s2_writemask_bo = 4'hx; |
if (s2_pending == 1'b1) |
begin |
if (s2_curmaster == 1'b0) |
begin |
s2_enb_o = m0_enb_i; |
s2_we_o = m0_we_i; |
s2_addr_bo = m0_addr_bi; |
s2_wdata_bo = m0_wdata_bi; |
s2_writemask_bo = m0_writemask_bi; |
end |
else |
begin |
s2_enb_o = m1_enb_i; |
s2_we_o = m1_we_i; |
s2_addr_bo = m1_addr_bi; |
s2_wdata_bo = m1_wdata_bi; |
s2_writemask_bo = m1_writemask_bi; |
end |
end |
else if (m0_s2_enb == 1'b1) |
begin |
s2_enb_o = m0_enb_i; |
s2_we_o = m0_we_i; |
s2_addr_bo = m0_addr_bi; |
s2_wdata_bo = m0_wdata_bi; |
s2_writemask_bo = m0_writemask_bi; |
end |
else if (m1_s2_enb == 1'b1) |
begin |
s2_enb_o = m1_enb_i; |
s2_we_o = m1_we_i; |
s2_addr_bo = m1_addr_bi; |
s2_wdata_bo = m1_wdata_bi; |
s2_writemask_bo = m1_writemask_bi; |
end |
end |
|
// Master drivers |
always @* |
begin |
m0_ack_o = 1'b0; |
m0_rdata_bo = 32'hx; |
if ((s0_pending == 1'b1) && (s0_curmaster == 1'b0)) |
begin |
m0_ack_o = s0_ack_i; |
m0_rdata_bo = s0_rdata_bi; |
end |
else if ((s1_pending == 1'b1) && (s1_curmaster == 1'b0)) |
begin |
m0_ack_o = s1_ack_i; |
m0_rdata_bo = s1_rdata_bi; |
end |
else if ((s2_pending == 1'b1) && (s2_curmaster == 1'b0)) |
begin |
m0_ack_o = s2_ack_i; |
m0_rdata_bo = s2_rdata_bi; |
end |
else if (m0_s0_enb == 1'b1) |
begin |
m0_ack_o = s0_ack_i; |
m0_rdata_bo = s0_rdata_bi; |
end |
else if (m0_s1_enb == 1'b1) |
begin |
m0_ack_o = s1_ack_i; |
m0_rdata_bo = s1_rdata_bi; |
end |
else if (m0_s2_enb == 1'b1) |
begin |
m0_ack_o = s2_ack_i; |
m0_rdata_bo = s2_rdata_bi; |
end |
end |
|
always @* |
begin |
m1_ack_o = 1'b0; |
m1_rdata_bo = 32'hx; |
if ((s0_pending == 1'b1) && (s0_curmaster == 1'b1)) |
begin |
m1_ack_o = s0_ack_i; |
m1_rdata_bo = s0_rdata_bi; |
end |
else if ((s1_pending == 1'b1) && (s1_curmaster == 1'b1)) |
begin |
m1_ack_o = s1_ack_i; |
m1_rdata_bo = s1_rdata_bi; |
end |
else if ((s2_pending == 1'b1) && (s2_curmaster == 1'b1)) |
begin |
m1_ack_o = s2_ack_i; |
m1_rdata_bo = s2_rdata_bi; |
end |
else if (m1_s0_enb == 1'b1) |
begin |
m1_ack_o = s0_ack_i; |
m1_rdata_bo = s0_rdata_bi; |
end |
else if (m1_s1_enb == 1'b1) |
begin |
m1_ack_o = s1_ack_i; |
m1_rdata_bo = s1_rdata_bi; |
end |
else if (m1_s2_enb == 1'b1) |
begin |
m1_ack_o = s2_ack_i; |
m1_rdata_bo = s2_rdata_bi; |
end |
end |
|
endmodule |
/trunk/pss/hdl/pss/zpu_uc/motherblock/pss_int_controller.v
0,0 → 1,109
/* |
PSS |
|
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.99 |
|
The FreeBSD license |
|
Redistribution and use in source and binary forms, with or without |
modification, are permitted provided that the following conditions |
are met: |
|
1. Redistributions of source code must retain the above copyright |
notice, this list of conditions and the following disclaimer. |
2. Redistributions in binary form must reproduce the above |
copyright notice, this list of conditions and the following |
disclaimer in the documentation and/or other materials |
provided with the distribution. |
|
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY |
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
|
|
module pss_int_controller |
( |
input clk_i, rst_i, |
|
input [7:0] interrupt_bi, |
|
// control interface |
output ie_o, |
input ie_we_i, |
input ie_data_i, |
input [7:0] mask_bi, |
output [7:0] pending_bo, |
input clr_cmd_i, |
input [7:0] clr_code_bi, |
|
// cpu interface |
output reg cpu_req_o, |
input cpu_ack_i |
); |
|
reg [7:0] int_req, int_req_next; |
reg IE; |
|
wire [7:0] interrupt_masked; |
assign interrupt_masked = interrupt_bi & mask_bi; |
assign pending_bo = int_req; |
assign ie_o = IE; |
|
|
always @* |
begin |
// default |
int_req_next = int_req; |
// deasserting from cpu |
if (clr_cmd_i == 1'b1) int_req_next = int_req_next & ~clr_code_bi; |
// asserting from external interrupts |
int_req_next = int_req_next | interrupt_masked; |
end |
|
always @(posedge clk_i) |
begin |
if (rst_i) |
int_req <= 8'h0; |
else |
int_req <= int_req_next; |
end |
|
|
always @(posedge clk_i) |
begin |
if (rst_i) |
begin |
IE <= 1'b0; |
cpu_req_o <= 1'b0; |
end |
else |
begin |
|
if (ie_we_i == 1'b1) |
IE <= ie_data_i; |
|
if ((IE == 1'b1) && (int_req != 8'h0)) |
begin |
cpu_req_o <= 1'b1; |
IE <= 1'b0; |
end |
else if (cpu_ack_i == 1'b1) |
cpu_req_o <= 1'b0; |
|
end |
end |
|
endmodule |
/trunk/pss/hdl/pss/zpu_uc/motherblock/pss_edge_detector.v
0,0 → 1,77
/* |
PSS |
|
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.99 |
|
The FreeBSD license |
|
Redistribution and use in source and binary forms, with or without |
modification, are permitted provided that the following conditions |
are met: |
|
1. Redistributions of source code must retain the above copyright |
notice, this list of conditions and the following disclaimer. |
2. Redistributions in binary form must reproduce the above |
copyright notice, this list of conditions and the following |
disclaimer in the documentation and/or other materials |
provided with the distribution. |
|
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY |
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
|
|
module pss_edge_detector |
( |
input clk_i, rst_i, |
|
input in, |
output reg out |
); |
|
reg edge_inv; |
reg inbuf0, inbuf1, inbuf2; |
|
always @(posedge in, posedge rst_i) |
begin |
if (rst_i) |
edge_inv <= 1'b0; |
else |
edge_inv <= ~edge_inv; |
end |
|
always @(posedge clk_i) |
begin |
if (rst_i) |
begin |
inbuf0 <= 1'b0; |
inbuf1 <= 1'b0; |
inbuf2 <= 1'b0; |
out <= 1'b0; |
end |
else |
begin |
inbuf0 <= edge_inv; |
inbuf1 <= inbuf0; |
inbuf2 <= inbuf1; |
if (inbuf1 != inbuf2) |
out <= 1'b1; |
else |
out <= 1'b0; |
end |
end |
|
endmodule |
/trunk/pss/hdl/pss/zpu_uc/motherblock/pss_dma.v
0,0 → 1,246
/* |
PSS |
|
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9 |
|
The FreeBSD license |
|
Redistribution and use in source and binary forms, with or without |
modification, are permitted provided that the following conditions |
are met: |
|
1. Redistributions of source code must retain the above copyright |
notice, this list of conditions and the following disclaimer. |
2. Redistributions in binary form must reproduce the above |
copyright notice, this list of conditions and the following |
disclaimer in the documentation and/or other materials |
provided with the distribution. |
|
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY |
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
|
|
module PSS_DMA |
( |
input clk_i, rst_i, |
|
input xport_busy_i, |
output xport_busy_o, |
|
output reg dma_int_o, |
|
input dma_req_i, |
input dma_cmd_i, |
input dma_autoinc_i, |
input [31:0] dma_size_bi, |
input [31:0] dma_sourceaddr_bi, |
input [31:0] dma_destaddr_bi, |
|
// RAM 1 interface |
output reg [31:0] ram_addr_bo, |
output reg ram_we_o, |
output reg [31:0] ram_wdata_bo, |
input [31:0] ram_rdata_bi, |
|
// Expansion bus // |
output reg xport_req_o, |
input xport_ack_i, |
input xport_err_i, |
output reg xport_we_o, |
output reg [31:0] xport_addr_bo, |
output reg [31:0] xport_wdata_bo, |
input xport_resp_i, |
input [31:0] xport_rdata_bi |
); |
|
localparam DMA_IDLE = 3'h0; |
localparam DMA_WAIT = 3'h1; |
localparam DMA_PRESTART = 3'h2; |
localparam DMA_WORK = 3'h3; |
localparam DMA_LOAD = 3'h4; |
localparam DMA_STORE = 3'h5; |
|
reg [2:0] DMA_state; |
|
reg [31:0] dma_sourceaddr; |
reg [31:0] dma_destaddr; |
reg [31:0] dma_size, dma_size_aux; |
|
assign xport_busy_o = ((DMA_state == DMA_IDLE) || (DMA_state == DMA_WAIT)) ? 1'b0 : 1'b1; |
|
// DMA data logic |
reg [31:0] ram1_addr, ram1_addr_shadow; |
|
always @* |
begin |
if (DMA_state != DMA_LOAD) |
ram_addr_bo = ram1_addr; |
else if (xport_ack_i == 1'b1) |
ram_addr_bo = ram1_addr; |
else |
ram_addr_bo = ram1_addr_shadow; |
end |
|
always @(posedge clk_i) |
begin |
if (rst_i) |
ram1_addr_shadow <= 32'h0; |
else if (xport_ack_i == 1'b1) |
ram1_addr_shadow <= ram1_addr; |
end |
|
always @* |
begin |
|
xport_req_o = 1'b0; |
xport_we_o = 1'b0; |
xport_addr_bo = 32'hx; |
xport_wdata_bo = 32'hx; |
|
ram1_addr = dma_sourceaddr; |
ram_we_o = 1'b0; |
ram_wdata_bo = 32'hx; |
|
if (DMA_state == DMA_LOAD) |
begin |
|
if (dma_size != 32'h0) |
begin |
xport_req_o = 1'b1; |
xport_we_o = 1'b0; |
xport_addr_bo = dma_sourceaddr; |
xport_wdata_bo = 32'hx; |
end |
|
if (dma_size_aux != 32'h0) |
begin |
ram1_addr = dma_destaddr; |
ram_we_o = xport_resp_i; |
ram_wdata_bo = xport_rdata_bi; |
end |
|
end |
|
else if (DMA_state == DMA_STORE) |
begin |
|
if (dma_size != 32'h0) |
begin |
xport_req_o = 1'b1; |
xport_we_o = 1'b1; |
xport_addr_bo = dma_destaddr; |
xport_wdata_bo = ram_rdata_bi; |
end |
|
end |
|
end |
|
// DMA control logic |
always @(posedge clk_i) |
begin |
if (rst_i) |
begin |
|
DMA_state <= DMA_IDLE; |
|
dma_sourceaddr <= 32'h0; |
dma_destaddr <= 32'h0; |
dma_size <= 32'h0; |
|
dma_int_o <= 1'b0; |
|
end |
else |
begin |
|
dma_int_o <= 1'b0; |
|
case (DMA_state) |
|
DMA_IDLE: |
begin |
if (dma_req_i) |
begin |
dma_size <= dma_size_bi; |
dma_size_aux <= dma_size_bi; |
dma_sourceaddr <= dma_sourceaddr_bi; |
dma_destaddr <= dma_destaddr_bi; |
|
DMA_state <= DMA_WAIT; |
end |
end |
|
DMA_WAIT: |
begin |
if (!xport_busy_i) // no pending requests |
if (dma_cmd_i) |
begin |
dma_sourceaddr <= dma_sourceaddr + 32'h4; |
DMA_state <= DMA_STORE; |
end |
else |
DMA_state <= DMA_LOAD; |
end |
|
DMA_STORE: |
begin |
if (xport_ack_i == 1'b1) |
if (dma_size == 32'h4) |
begin |
DMA_state <= DMA_IDLE; |
dma_int_o <= 1'b1; |
end |
else |
begin |
dma_size <= dma_size - 32'h4; |
dma_sourceaddr <= dma_sourceaddr + 32'h4; |
if (dma_autoinc_i == 1'b1) dma_destaddr <= dma_destaddr + 32'h4; |
end |
end |
|
DMA_LOAD: |
begin |
|
if ( (xport_ack_i == 1'b1) && (dma_size != 32'h0) ) |
begin |
if (dma_autoinc_i == 1'b1) dma_sourceaddr <= dma_sourceaddr + 32'h4; |
dma_size <= dma_size - 32'h4; |
end |
|
if ( (xport_resp_i == 1'b1) && (dma_size_aux != 32'h0) ) |
begin |
dma_destaddr <= dma_destaddr + 32'h4; |
dma_size_aux <= dma_size_aux - 32'h4; |
end |
|
if ( (dma_size == 32'h0) && (dma_size_aux == 32'h0) ) |
begin |
DMA_state <= DMA_IDLE; |
dma_int_o <= 1'b1; |
end |
|
end |
|
default: |
DMA_state <= DMA_IDLE; |
|
endcase |
end |
end |
|
endmodule |
/trunk/pss/hdl/pss/zpu_uc/motherblock/pss_reset_cntrl.v
0,0 → 1,60
/* |
PSS |
|
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.99 |
|
The FreeBSD license |
|
Redistribution and use in source and binary forms, with or without |
modification, are permitted provided that the following conditions |
are met: |
|
1. Redistributions of source code must retain the above copyright |
notice, this list of conditions and the following disclaimer. |
2. Redistributions in binary form must reproduce the above |
copyright notice, this list of conditions and the following |
disclaimer in the documentation and/or other materials |
provided with the distribution. |
|
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY |
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
|
|
module pss_reset_cntrl |
( |
input clk_i, arst_i, |
output reg srst_o |
); |
|
reg [15:0] reset_counter; |
|
always @(posedge clk_i, posedge arst_i) |
begin |
if (arst_i) |
begin |
reset_counter <= 16'h0; |
srst_o <= 1'b1; |
end |
else |
begin |
reset_counter <= {1'b1, reset_counter[15:1]}; |
if (reset_counter == 16'hFFFF) srst_o <= 1'b0; |
end |
end |
|
|
endmodule |
/trunk/pss/hdl/pss/pss.v
4,7 → 4,7
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> |
All rights reserved. |
|
Version 0.9 |
Version 0.99 |
|
The FreeBSD license |
|
38,18 → 38,19
#( |
parameter CPU_PRESENT = 1, |
parameter CPU_RESET_DEFAULT = 1, |
parameter A31_DEFAULTS = 1, |
parameter A31_DEFAULT = 1, |
parameter MEM_SIZE_KB = 1, |
parameter MEM_DATA = "" |
) |
( |
input clk_i, arst_i, |
output srst_o, |
input clk_i, |
input arst_i, srst_i, |
output srst_o, ext_rst_o, |
|
input rx_i, |
input rx_i, |
output tx_o, |
|
input [3:0] INT_i, |
input [3:0] INT_bi, |
|
// Expansion bus |
output xport_req_o, |
62,16 → 63,9
input [31:0] xport_rdata_bi |
); |
|
wire sync_rst, udm_rst; |
as_reset_cntrl as_reset_cntrl |
( |
.clk_i(clk_i), |
.rst_i(arst_i), |
.rst_o(sync_rst) |
); |
wire zpu_uc_srst, udm_rst; |
assign zpu_uc_srst = srst_i | udm_rst; |
|
assign srst_o = sync_rst | udm_rst; |
|
wire dbg_bus_enb; |
wire dbg_bus_we; |
wire [31:0] dbg_bus_addr; |
82,7 → 76,7
udm udm |
( |
.clk_i(clk_i), |
.rst_i(sync_rst), |
.rst_i(srst_o), |
|
.rx_i(rx_i), |
.tx_o(tx_o), |
101,7 → 95,7
#( |
.CPU_PRESENT(CPU_PRESENT), |
.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT), |
.A31_DEFAULTS(A31_DEFAULTS), |
.A31_DEFAULT(A31_DEFAULT), |
.MEM_DATA(MEM_DATA), |
.MEM_SIZE_KB(MEM_SIZE_KB) |
) |
108,9 → 102,15
ZPU_uC |
( |
.clk_i(clk_i), |
.rst_i(srst_o), |
.INT_i(INT_i), |
|
.arst_i(arst_i), |
.srst_o(srst_o), |
|
.srst_i(zpu_uc_srst), |
.ext_rst_o(ext_rst_o), |
|
.INT_bi(INT_bi), |
|
// Expansion bus |
.xport_req_o(xport_req_o), |
.xport_ack_i(xport_ack_i), |
/trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.c
0,0 → 1,18
#define IO_GPR (*(volatile unsigned int *)(0x8A000000)) |
|
|
int main() |
{ |
int counter; |
int i; |
|
counter = 0; |
|
while(1) |
{ |
counter++; |
IO_GPR = counter; |
|
for (i = 0; i < 100000; i++) {} |
} |
} |
/trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.hex
0,0 → 1,776
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/trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.elf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.elf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.bin
===================================================================
--- trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.bin (nonexistent)
+++ trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.bin (revision 5)
trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.bin
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/pss/SW/onboard/Heartbeatdelay/build.sh
===================================================================
--- trunk/pss/SW/onboard/Heartbeatdelay/build.sh (nonexistent)
+++ trunk/pss/SW/onboard/Heartbeatdelay/build.sh (revision 5)
@@ -0,0 +1,4 @@
+zpu-elf-gcc -O3 -phi `pwd`/heartbeatdelay.c -o heartbeatdelay.elf -Wl,--relax -Wl,--gc-sections -g
+zpu-elf-objdump --disassemble-all >heartbeatdelay.dis heartbeatdelay.elf
+zpu-elf-objcopy -O binary heartbeatdelay.elf heartbeatdelay.bin
+hexdump -v -e '4/1 "%02x"' -e '"\n"' heartbeatdelay.bin > heartbeatdelay.hex
Index: trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.dis
===================================================================
--- trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.dis (nonexistent)
+++ trunk/pss/SW/onboard/Heartbeatdelay/heartbeatdelay.dis (revision 5)
@@ -0,0 +1,23117 @@
+
+heartbeatdelay.elf: file format elf32-zpu
+
+Disassembly of section .fixed_vectors:
+
+00000000 <_start>:
+ 0: 0b nop
+ 1: 0b nop
+ 2: 0b nop
+ 3: 0b nop
+ 4: 82 im 2
+ 5: 70 loadsp 0
+ 6: 0b nop
+ 7: 0b nop
+ 8: 0b nop
+ 9: 90 im 16
+ a: fc im -4
+ b: 0c store
+ c: 3a config
+ d: 0b nop
+ e: 0b nop
+ f: 0b nop
+ 10: 8e im 14
+ 11: c3 im -61
+ 12: 04 poppc
+ ...
+
+00000020 <_zpu_interrupt_vector>:
+ 20: 80 im 0
+ 21: 08 load
+ 22: 84 im 4
+ 23: 08 load
+ 24: 88 im 8
+ 25: 08 load
+ 26: 0b nop
+ 27: 0b nop
+ 28: 0b nop
+ 29: 8f im 15
+ 2a: 83 im 3
+ 2b: 2d call
+ 2c: 88 im 8
+ 2d: 0c store
+ 2e: 84 im 4
+ 2f: 0c store
+ 30: 80 im 0
+ 31: 0c store
+ 32: 04 poppc
+ ...
+
+00000040 <_loadh>:
+ 40: 71 loadsp 4
+ 41: fd im -3
+ 42: 06 and
+ 43: 08 load
+ 44: 72 loadsp 8
+ 45: 83 im 3
+ 46: 06 and
+ 47: 09 not
+ 48: 81 im 1
+ 49: 05 add
+ 4a: 82 im 2
+ 4b: 05 add
+ 4c: 83 im 3
+ 4d: 2b ashiftleft
+ 4e: 2a lshiftright
+ 4f: 83 im 3
+ 50: ff im -1
+ 51: ff im -1
+ 52: 06 and
+ 53: 52 storesp 8
+ 54: 04 poppc
+ ...
+
+00000060 <_storeh>:
+ 60: 71 loadsp 4
+ 61: fd im -3
+ 62: 06 and
+ 63: 08 load
+ 64: 83 im 3
+ 65: ff im -1
+ 66: ff im -1
+ 67: 73 loadsp 12
+ 68: 83 im 3
+ 69: 06 and
+ 6a: 09 not
+ 6b: 81 im 1
+ 6c: 05 add
+ 6d: 82 im 2
+ 6e: 05 add
+ 6f: 83 im 3
+ 70: 2b ashiftleft
+ 71: 2b ashiftleft
+ 72: 09 not
+ 73: 06 and
+ 74: 73 loadsp 12
+ 75: 83 im 3
+ 76: ff im -1
+ 77: ff im -1
+ 78: 0b nop
+ 79: 0b nop
+ 7a: 0b nop
+ 7b: 0b nop
+ 7c: 83 im 3
+ 7d: a7 im 39
+ 7e: 04 poppc
+ ...
+
+00000080 <_lessthan>:
+ 80: 72 loadsp 8
+ 81: 09 not
+ 82: 81 im 1
+ 83: 05 add
+ 84: 72 loadsp 8
+ 85: 05 add
+ 86: 73 loadsp 12
+ 87: 73 loadsp 12
+ 88: 09 not
+ 89: 06 and
+ 8a: 09 not
+ 8b: 06 and
+ 8c: 73 loadsp 12
+ 8d: 09 not
+ 8e: 73 loadsp 12
+ 8f: 06 and
+ 90: 07 or
+ 91: 0a flip
+ 92: 81 im 1
+ 93: 06 and
+ 94: 53 storesp 12
+ 95: 51 storesp 4
+ 96: 04 poppc
+ ...
+
+000000a0 <_lessthanorequal>:
+ a0: 72 loadsp 8
+ a1: 72 loadsp 8
+ a2: 24 lessthan
+ a3: 73 loadsp 12
+ a4: 73 loadsp 12
+ a5: 2e eq
+ a6: 07 or
+ a7: 53 storesp 12
+ a8: 51 storesp 4
+ a9: 04 poppc
+ ...
+
+000000c0 <_ulessthan>:
+ c0: 71 loadsp 4
+ c1: 73 loadsp 12
+ c2: 71 loadsp 4
+ c3: 09 not
+ c4: 71 loadsp 4
+ c5: 06 and
+ c6: 81 im 1
+ c7: 06 and
+ c8: 30 neg
+ c9: 72 loadsp 8
+ ca: 0a flip
+ cb: 10 addsp 0
+ cc: 0a flip
+ cd: 72 loadsp 8
+ ce: 0a flip
+ cf: 10 addsp 0
+ d0: 0a flip
+ d1: 31 sub
+ d2: 05 add
+ d3: 0a flip
+ d4: 81 im 1
+ d5: 06 and
+ d6: 51 storesp 4
+ d7: 51 storesp 4
+ d8: 53 storesp 12
+ d9: 51 storesp 4
+ da: 04 poppc
+ db: 00 breakpoint
+ dc: 00 breakpoint
+ dd: 00 breakpoint
+ ...
+
+000000e0 <_ulessthanorequal>:
+ e0: 72 loadsp 8
+ e1: 72 loadsp 8
+ e2: 26 ulessthan
+ e3: 73 loadsp 12
+ e4: 73 loadsp 12
+ e5: 2e eq
+ e6: 07 or
+ e7: 53 storesp 12
+ e8: 51 storesp 4
+ e9: 04 poppc
+ ...
+
+00000100 <_swap>:
+ ...
+
+00000120 <_slowmult>:
+ 120: 0b nop
+ 121: 0b nop
+ 122: 0b nop
+ 123: 88 im 8
+ 124: c3 im -61
+ 125: 04 poppc
+ ...
+
+00000140 <_lshiftright>:
+ 140: 72 loadsp 8
+ 141: 0a flip
+ 142: 72 loadsp 8
+ 143: 2b ashiftleft
+ 144: 0a flip
+ 145: 53 storesp 12
+ 146: 51 storesp 4
+ 147: 04 poppc
+ ...
+
+00000160 <_ashiftleft>:
+ 160: 72 loadsp 8
+ 161: 72 loadsp 8
+ 162: 9f im 31
+ 163: 06 and
+ 164: 09 not
+ 165: 81 im 1
+ 166: 05 add
+ 167: 0b nop
+ 168: 0b nop
+ 169: 0b nop
+ 16a: 88 im 8
+ 16b: a6 im 38
+ 16c: 05 add
+ 16d: 04 poppc
+ ...
+
+00000180 <_ashiftright>:
+ 180: 72 loadsp 8
+ 181: 72 loadsp 8
+ 182: 2a lshiftright
+ 183: ff im -1
+ 184: 73 loadsp 12
+ 185: 9f im 31
+ 186: 06 and
+ 187: 2a lshiftright
+ 188: 09 not
+ 189: 74 loadsp 16
+ 18a: 09 not
+ 18b: 0a flip
+ 18c: 81 im 1
+ 18d: 06 and
+ 18e: ff im -1
+ 18f: 05 add
+ 190: 06 and
+ 191: 07 or
+ 192: 53 storesp 12
+ 193: 51 storesp 4
+ 194: 04 poppc
+ ...
+
+000001a0 <_call>:
+ 1a0: 71 loadsp 4
+ 1a1: 71 loadsp 4
+ 1a2: 53 storesp 12
+ 1a3: 51 storesp 4
+ 1a4: 02 pushsp
+ 1a5: 0d popsp
+ 1a6: 04 poppc
+
+000001a7 <_storehtail>:
+ 1a7: 06 and
+ 1a8: 73 loadsp 12
+ 1a9: 83 im 3
+ 1aa: 06 and
+ 1ab: 09 not
+ 1ac: 81 im 1
+ 1ad: 05 add
+ 1ae: 82 im 2
+ 1af: 05 add
+ 1b0: 83 im 3
+ 1b1: 2b ashiftleft
+ 1b2: 0b nop
+ 1b3: 2b ashiftleft
+ 1b4: 07 or
+ 1b5: 72 loadsp 8
+ 1b6: fc im -4
+ 1b7: 06 and
+ 1b8: 0c store
+ 1b9: 51 storesp 4
+ 1ba: 51 storesp 4
+ 1bb: 04 poppc
+ 1bc: 00 breakpoint
+ 1bd: 00 breakpoint
+ ...
+
+000001c0 <_eq>:
+ 1c0: 72 loadsp 8
+ 1c1: 09 not
+ 1c2: 81 im 1
+ 1c3: 05 add
+ 1c4: 72 loadsp 8
+ 1c5: 05 add
+ 1c6: 09 not
+ 1c7: 70 loadsp 0
+ 1c8: 81 im 1
+ 1c9: 05 add
+ 1ca: 09 not
+ 1cb: 06 and
+ 1cc: 0a flip
+ 1cd: 81 im 1
+ 1ce: 06 and
+ 1cf: 53 storesp 12
+ 1d0: 51 storesp 4
+ 1d1: 04 poppc
+ ...
+
+000001e0 <_neq>:
+ 1e0: 72 loadsp 8
+ 1e1: 09 not
+ 1e2: 81 im 1
+ 1e3: 05 add
+ 1e4: 72 loadsp 8
+ 1e5: 05 add
+ 1e6: 09 not
+ 1e7: 70 loadsp 0
+ 1e8: 81 im 1
+ 1e9: 05 add
+ 1ea: 09 not
+ 1eb: 06 and
+ 1ec: 0a flip
+ 1ed: 09 not
+ 1ee: 81 im 1
+ 1ef: 06 and
+ 1f0: 53 storesp 12
+ 1f1: 51 storesp 4
+ 1f2: 04 poppc
+ ...
+
+00000200 <_neg>:
+ 200: 71 loadsp 4
+ 201: 09 not
+ 202: 81 im 1
+ 203: 05 add
+ 204: 52 storesp 8
+ 205: 04 poppc
+ ...
+
+00000220 <_sub>:
+ 220: 72 loadsp 8
+ 221: 72 loadsp 8
+ 222: 09 not
+ 223: 81 im 1
+ 224: 05 add
+ 225: 05 add
+ 226: 53 storesp 12
+ 227: 51 storesp 4
+ 228: 04 poppc
+ ...
+
+00000240 <_xor>:
+ 240: 72 loadsp 8
+ 241: 09 not
+ 242: 72 loadsp 8
+ 243: 06 and
+ 244: 73 loadsp 12
+ 245: 73 loadsp 12
+ 246: 09 not
+ 247: 06 and
+ 248: 07 or
+ 249: 53 storesp 12
+ 24a: 51 storesp 4
+ 24b: 04 poppc
+ ...
+
+00000260 <_loadb>:
+ 260: 71 loadsp 4
+ 261: fc im -4
+ 262: 06 and
+ 263: 08 load
+ 264: 72 loadsp 8
+ 265: 83 im 3
+ 266: 06 and
+ 267: 09 not
+ 268: 81 im 1
+ 269: 05 add
+ 26a: 83 im 3
+ 26b: 05 add
+ 26c: 10 addsp 0
+ 26d: 10 addsp 0
+ 26e: 10 addsp 0
+ 26f: 2a lshiftright
+ 270: 81 im 1
+ 271: ff im -1
+ 272: 06 and
+ 273: 52 storesp 8
+ 274: 04 poppc
+ ...
+
+00000280 <_storeb>:
+ 280: 71 loadsp 4
+ 281: fc im -4
+ 282: 06 and
+ 283: 08 load
+ 284: 0b nop
+ 285: 0b nop
+ 286: 0b nop
+ 287: 90 im 16
+ 288: e8 im -24
+ 289: 73 loadsp 12
+ 28a: 83 im 3
+ 28b: 06 and
+ 28c: 10 addsp 0
+ 28d: 10 addsp 0
+ 28e: 05 add
+ 28f: 08 load
+ 290: 06 and
+ 291: 0b nop
+ 292: 0b nop
+ 293: 0b nop
+ 294: 88 im 8
+ 295: a9 im 41
+ 296: 04 poppc
+ ...
+
+000002a0 <_div>:
+ 2a0: 80 im 0
+ 2a1: 08 load
+ 2a2: 84 im 4
+ 2a3: 08 load
+ 2a4: 88 im 8
+ 2a5: 08 load
+ 2a6: 75 loadsp 20
+ 2a7: 75 loadsp 20
+ 2a8: 0b nop
+ 2a9: 0b nop
+ 2aa: 0b nop
+ 2ab: 8a im 10
+ 2ac: c7 im -57
+ 2ad: 2d call
+ 2ae: 50 storesp 0
+ 2af: 50 storesp 0
+ 2b0: 80 im 0
+ 2b1: 08 load
+ 2b2: 56 storesp 24
+ 2b3: 88 im 8
+ 2b4: 0c store
+ 2b5: 84 im 4
+ 2b6: 0c store
+ 2b7: 80 im 0
+ 2b8: 0c store
+ 2b9: 51 storesp 4
+ 2ba: 04 poppc
+ 2bb: 00 breakpoint
+ 2bc: 00 breakpoint
+ 2bd: 00 breakpoint
+ ...
+
+000002c0 <_mod>:
+ 2c0: 80 im 0
+ 2c1: 08 load
+ 2c2: 84 im 4
+ 2c3: 08 load
+ 2c4: 88 im 8
+ 2c5: 08 load
+ 2c6: 75 loadsp 20
+ 2c7: 75 loadsp 20
+ 2c8: 0b nop
+ 2c9: 0b nop
+ 2ca: 0b nop
+ 2cb: 8b im 11
+ 2cc: f9 im -7
+ 2cd: 2d call
+ 2ce: 50 storesp 0
+ 2cf: 50 storesp 0
+ 2d0: 80 im 0
+ 2d1: 08 load
+ 2d2: 56 storesp 24
+ 2d3: 88 im 8
+ 2d4: 0c store
+ 2d5: 84 im 4
+ 2d6: 0c store
+ 2d7: 80 im 0
+ 2d8: 0c store
+ 2d9: 51 storesp 4
+ 2da: 04 poppc
+ 2db: 00 breakpoint
+ 2dc: 00 breakpoint
+ 2dd: 00 breakpoint
+ ...
+
+000002e0 <_eqbranch>:
+ 2e0: 72 loadsp 8
+ 2e1: 09 not
+ 2e2: 70 loadsp 0
+ 2e3: 81 im 1
+ 2e4: 05 add
+ 2e5: 09 not
+ 2e6: 06 and
+ 2e7: 0a flip
+ 2e8: 81 im 1
+ 2e9: 06 and
+ 2ea: ff im -1
+ 2eb: 05 add
+ 2ec: 70 loadsp 0
+ 2ed: 54 storesp 16
+ 2ee: 71 loadsp 4
+ 2ef: 06 and
+ 2f0: 73 loadsp 12
+ 2f1: 09 not
+ 2f2: 72 loadsp 8
+ 2f3: 74 loadsp 16
+ 2f4: 05 add
+ 2f5: ff im -1
+ 2f6: 05 add
+ 2f7: 06 and
+ 2f8: 07 or
+ 2f9: 51 storesp 4
+ 2fa: 51 storesp 4
+ 2fb: 51 storesp 4
+ 2fc: 04 poppc
+ 2fd: 00 breakpoint
+ ...
+
+00000300 <_neqbranch>:
+ 300: 72 loadsp 8
+ 301: 09 not
+ 302: 70 loadsp 0
+ 303: 81 im 1
+ 304: 05 add
+ 305: 09 not
+ 306: 06 and
+ 307: 0a flip
+ 308: 09 not
+ 309: 81 im 1
+ 30a: 06 and
+ 30b: ff im -1
+ 30c: 05 add
+ 30d: 70 loadsp 0
+ 30e: 54 storesp 16
+ 30f: 71 loadsp 4
+ 310: 06 and
+ 311: 73 loadsp 12
+ 312: 09 not
+ 313: 72 loadsp 8
+ 314: 74 loadsp 16
+ 315: 05 add
+ 316: ff im -1
+ 317: 05 add
+ 318: 06 and
+ 319: 07 or
+ 31a: 51 storesp 4
+ 31b: 51 storesp 4
+ 31c: 51 storesp 4
+ 31d: 04 poppc
+ ...
+
+00000320 <_poppcrel>:
+ 320: 05 add
+ 321: ff im -1
+ 322: 05 add
+ 323: 04 poppc
+ ...
+
+00000340 <_config>:
+ 340: 81 im 1
+ 341: 0b nop
+ 342: 0b nop
+ 343: 0b nop
+ 344: 0b nop
+ 345: 90 im 16
+ 346: f8 im -8
+ 347: 0c store
+ 348: 51 storesp 4
+ 349: 04 poppc
+ ...
+
+00000360 <_pushpc>:
+ 360: 71 loadsp 4
+ 361: 81 im 1
+ 362: 05 add
+ 363: 52 storesp 8
+ 364: 04 poppc
+ ...
+
+00000380 <_syscall_emulate>:
+ ...
+
+000003a0 <_pushspadd>:
+ 3a0: 02 pushsp
+ 3a1: 84 im 4
+ 3a2: 05 add
+ 3a3: 72 loadsp 8
+ 3a4: 10 addsp 0
+ 3a5: 10 addsp 0
+ 3a6: 05 add
+ 3a7: 52 storesp 8
+ 3a8: 04 poppc
+ ...
+
+000003c0 <_halfmult>:
+ ...
+
+000003e0 <_callpcrel>:
+ 3e0: 71 loadsp 4
+ 3e1: 71 loadsp 4
+ 3e2: 05 add
+ 3e3: ff im -1
+ 3e4: 05 add
+ 3e5: 71 loadsp 4
+ 3e6: 53 storesp 12
+ 3e7: 51 storesp 4
+ 3e8: 02 pushsp
+ 3e9: 0d popsp
+ 3ea: 04 poppc
+ ...
+Disassembly of section .init:
+
+00000400 <_init>:
+ 400: 81 im 1
+ 401: f3 im -13
+ 402: 3f callpcrel
+ 403: 88 im 8
+ 404: a3 im 35
+ 405: 3f callpcrel
+ 406: 04 poppc
+Disassembly of section .text:
+
+00000407 <_ashiftleftBegin>:
+ 407: 10 addsp 0
+ 408: 10 addsp 0
+ 409: 10 addsp 0
+ 40a: 10 addsp 0
+ 40b: 10 addsp 0
+ 40c: 10 addsp 0
+ 40d: 10 addsp 0
+ 40e: 10 addsp 0
+ 40f: 10 addsp 0
+ 410: 10 addsp 0
+ 411: 10 addsp 0
+ 412: 10 addsp 0
+ 413: 10 addsp 0
+ 414: 10 addsp 0
+ 415: 10 addsp 0
+ 416: 10 addsp 0
+ 417: 10 addsp 0
+ 418: 10 addsp 0
+ 419: 10 addsp 0
+ 41a: 10 addsp 0
+ 41b: 10 addsp 0
+ 41c: 10 addsp 0
+ 41d: 10 addsp 0
+ 41e: 10 addsp 0
+ 41f: 10 addsp 0
+ 420: 10 addsp 0
+ 421: 10 addsp 0
+ 422: 10 addsp 0
+ 423: 10 addsp 0
+ 424: 10 addsp 0
+ 425: 10 addsp 0
+
+00000426 <_ashiftleftEnd>:
+ 426: 53 storesp 12
+ 427: 51 storesp 4
+ 428: 04 poppc
+
+00000429 <_storebtail>:
+ 429: 73 loadsp 12
+ 42a: 81 im 1
+ 42b: ff im -1
+ 42c: 06 and
+ 42d: 73 loadsp 12
+ 42e: 83 im 3
+ 42f: 06 and
+ 430: 09 not
+ 431: 81 im 1
+ 432: 05 add
+ 433: 83 im 3
+ 434: 05 add
+ 435: 10 addsp 0
+ 436: 10 addsp 0
+ 437: 10 addsp 0
+ 438: 2b ashiftleft
+ 439: 07 or
+ 43a: 72 loadsp 8
+ 43b: fc im -4
+ 43c: 06 and
+ 43d: 0c store
+ 43e: 51 storesp 4
+ 43f: 51 storesp 4
+ 440: 04 poppc
+
+00000441 <_syscall>:
+ 441: 3c syscall
+ 442: 04 poppc
+
+00000443 <_slowmultImpl>:
+ 443: 72 loadsp 8
+ 444: 72 loadsp 8
+ 445: 80 im 0
+ 446: 72 loadsp 8
+ 447: 81 im 1
+ 448: 06 and
+ 449: ff im -1
+ 44a: 05 add
+ 44b: 09 not
+ 44c: 72 loadsp 8
+ 44d: 06 and
+ 44e: 05 add
+ 44f: 71 loadsp 4
+ 450: 10 addsp 0
+ 451: 52 storesp 8
+ 452: 72 loadsp 8
+ 453: 0a flip
+ 454: 10 addsp 0
+ 455: 0a flip
+ 456: 53 storesp 12
+ 457: 72 loadsp 8
+ 458: ed im -19
+ 459: 38 neqbranch
+ 45a: 51 storesp 4
+ 45b: 51 storesp 4
+ 45c: 53 storesp 12
+ 45d: 51 storesp 4
+ 45e: 04 poppc
+
+0000045f <_initIO>:
+ 45f: 90 im 16
+ 460: f8 im -8
+ 461: 08 load
+ 462: 80 im 0
+ 463: 2e eq
+ 464: a1 im 33
+ 465: 38 neqbranch
+
+00000466 <.LSM10>:
+ 466: 90 im 16
+ 467: fc im -4
+ 468: 08 load
+ 469: 82 im 2
+ 46a: 2e eq
+ 46b: b9 im 57
+ 46c: 38 neqbranch
+
+0000046d <.LSM11>:
+ 46d: 83 im 3
+ 46e: 80 im 0
+ 46f: 80 im 0
+ 470: 0b nop
+ 471: 0b nop
+ 472: 0b nop
+ 473: 0b nop
+ 474: 98 im 24
+ 475: a0 im 32
+ 476: 0c store
+
+00000477 <.LSM12>:
+ 477: 82 im 2
+ 478: a0 im 32
+ 479: 80 im 0
+ 47a: 0b nop
+ 47b: 98 im 24
+ 47c: a4 im 36
+ 47d: 0c store
+
+0000047e <.LSM13>:
+ 47e: 82 im 2
+ 47f: 90 im 16
+ 480: 80 im 0
+ 481: 0b nop
+ 482: 98 im 24
+ 483: a8 im 40
+ 484: 0c store
+
+00000485 <.LSM14>:
+ 485: 04 poppc
+
+00000486 <.L11>:
+ 486: f8 im -8
+ 487: 80 im 0
+ 488: 80 im 0
+ 489: 80 im 0
+ 48a: a4 im 36
+ 48b: 0b nop
+ 48c: 0b nop
+ 48d: 0b nop
+ 48e: 0b nop
+ 48f: 98 im 24
+ 490: a0 im 32
+ 491: 0c store
+
+00000492 <.LSM16>:
+ 492: f8 im -8
+ 493: 80 im 0
+ 494: 80 im 0
+ 495: 82 im 2
+ 496: 80 im 0
+ 497: 0b nop
+ 498: 98 im 24
+ 499: a4 im 36
+ 49a: 0c store
+
+0000049b <.LSM17>:
+ 49b: f8 im -8
+ 49c: 80 im 0
+ 49d: 80 im 0
+ 49e: 84 im 4
+ 49f: 80 im 0
+ 4a0: 0b nop
+ 4a1: 98 im 24
+ 4a2: a8 im 40
+ 4a3: 0c store
+
+000004a4 <.LSM18>:
+ 4a4: 04 poppc
+
+000004a5 <.L16>:
+ 4a5: 80 im 0
+ 4a6: c0 im -64
+ 4a7: a8 im 40
+ 4a8: 80 im 0
+ 4a9: 8c im 12
+ 4aa: 0b nop
+ 4ab: 0b nop
+ 4ac: 0b nop
+ 4ad: 0b nop
+ 4ae: 98 im 24
+ 4af: a0 im 32
+ 4b0: 0c store
+
+000004b1 <.LSM20>:
+ 4b1: 80 im 0
+ 4b2: c0 im -64
+ 4b3: a8 im 40
+ 4b4: 80 im 0
+ 4b5: 94 im 20
+ 4b6: 0b nop
+ 4b7: 98 im 24
+ 4b8: a4 im 36
+ 4b9: 0c store
+
+000004ba <.LSM21>:
+ 4ba: 0b nop
+ 4bb: 0b nop
+ 4bc: 0b nop
+ 4bd: 90 im 16
+ 4be: d4 im -44
+ 4bf: 0b nop
+ 4c0: 98 im 24
+ 4c1: a8 im 40
+ 4c2: 0c store
+
+000004c3 <.LSM22>:
+ 4c3: 04 poppc
+
+000004c4 <__do_global_dtors_aux>:
+ 4c4: ff im -1
+ 4c5: 3d pushspadd
+ 4c6: 0d popsp
+ 4c7: 98 im 24
+ 4c8: ac im 44
+ 4c9: 33 loadb
+ 4ca: 51 storesp 4
+ 4cb: 70 loadsp 0
+ 4cc: a3 im 35
+ 4cd: 38 neqbranch
+ 4ce: 91 im 17
+ 4cf: 84 im 4
+ 4d0: 08 load
+ 4d1: 70 loadsp 0
+ 4d2: 08 load
+ 4d3: 52 storesp 8
+ 4d4: 52 storesp 8
+ 4d5: 70 loadsp 0
+ 4d6: 80 im 0
+ 4d7: 2e eq
+ 4d8: 92 im 18
+ 4d9: 38 neqbranch
+
+000004da <.L10>:
+ 4da: 84 im 4
+ 4db: 12 addsp 8
+ 4dc: 91 im 17
+ 4dd: 84 im 4
+ 4de: 0c store
+ 4df: 70 loadsp 0
+ 4e0: 2d call
+ 4e1: 91 im 17
+ 4e2: 84 im 4
+ 4e3: 08 load
+ 4e4: 70 loadsp 0
+ 4e5: 08 load
+ 4e6: 52 storesp 8
+ 4e7: 52 storesp 8
+ 4e8: 70 loadsp 0
+ 4e9: f0 im -16
+ 4ea: 38 neqbranch
+
+000004eb <.L7>:
+ 4eb: 81 im 1
+ 4ec: 0b nop
+ 4ed: 98 im 24
+ 4ee: ac im 44
+ 4ef: 34 storeb
+
+000004f0 <.L1>:
+ 4f0: 83 im 3
+ 4f1: 3d pushspadd
+ 4f2: 0d popsp
+ 4f3: 04 poppc
+
+000004f4 :
+ 4f4: 04 poppc
+
+000004f5 :
+ 4f5: 80 im 0
+ 4f6: 3d pushspadd
+ 4f7: 0d popsp
+ 4f8: 0b nop
+ 4f9: 0b nop
+ 4fa: 0b nop
+ 4fb: 98 im 24
+ 4fc: 9c im 28
+ 4fd: 08 load
+ 4fe: 80 im 0
+ 4ff: 2e eq
+ 500: 8e im 14
+ 501: 38 neqbranch
+ 502: 0b nop
+ 503: 0b nop
+ 504: 0b nop
+ 505: 0b nop
+ 506: 80 im 0
+ 507: 0b nop
+ 508: 80 im 0
+ 509: 2e eq
+ 50a: 09 not
+ 50b: 81 im 1
+ 50c: 06 and
+ 50d: 85 im 5
+ 50e: 38 neqbranch
+
+0000050f <.L12>:
+ 50f: 82 im 2
+ 510: 3d pushspadd
+ 511: 0d popsp
+ 512: 04 poppc
+
+00000513 <.L15>:
+ 513: 0b nop
+ 514: 0b nop
+ 515: 0b nop
+ 516: 98 im 24
+ 517: 9c im 28
+ 518: 51 storesp 4
+ 519: 0b nop
+ 51a: 0b nop
+ 51b: 0b nop
+ 51c: f5 im -11
+ 51d: e2 im -30
+ 51e: 3f callpcrel
+ 51f: 82 im 2
+ 520: 3d pushspadd
+ 521: 0d popsp
+ 522: 04 poppc
+
+00000523 :
+ 523: 04 poppc
+
+00000524 :
+ 524: ff im -1
+ 525: 3d pushspadd
+ 526: 0d popsp
+
+00000527 <.LM2>:
+ 527: 80 im 0
+ 528: 52 storesp 8
+
+00000529 <.L2>:
+ 529: 81 im 1
+ 52a: 12 addsp 8
+
+0000052b <.LM4>:
+ 52b: 70 loadsp 0
+ 52c: 80 im 0
+ 52d: d1 im -47
+ 52e: 0a flip
+ 52f: 0c store
+ 530: 52 storesp 8
+ 531: 86 im 6
+ 532: 8d im 13
+ 533: 9f im 31
+ 534: 51 storesp 4
+
+00000535 <.L7>:
+ 535: ce im -50
+ 536: 11 addsp 4
+ 537: 51 storesp 4
+ 538: 80 im 0
+ 539: 71 loadsp 4
+ 53a: 24 lessthan
+ 53b: ed im -19
+ 53c: 38 neqbranch
+ 53d: ce im -50
+ 53e: 11 addsp 4
+ 53f: 51 storesp 4
+ 540: 70 loadsp 0
+ 541: 80 im 0
+ 542: 25 lessthanorequal
+ 543: f1 im -15
+ 544: 38 neqbranch
+ 545: e3 im -29
+ 546: 39 poppcrel
+
+00000547 <__divsi3>:
+ 547: 8c im 12
+ 548: 08 load
+ 549: 02 pushsp
+ 54a: 8c im 12
+ 54b: 0c store
+ 54c: f9 im -7
+ 54d: 3d pushspadd
+ 54e: 0d popsp
+ 54f: 80 im 0
+ 550: 0b nop
+ 551: 8c im 12
+ 552: 08 load
+ 553: fc im -4
+ 554: 05 add
+ 555: 0c store
+ 556: 8c im 12
+ 557: 08 load
+ 558: 88 im 8
+ 559: 05 add
+ 55a: 08 load
+ 55b: 80 im 0
+ 55c: 25 lessthanorequal
+ 55d: ab im 43
+ 55e: 38 neqbranch
+ 55f: 8c im 12
+ 560: 08 load
+ 561: 88 im 8
+ 562: 05 add
+ 563: 08 load
+ 564: 30 neg
+ 565: 8c im 12
+ 566: 08 load
+ 567: 88 im 8
+ 568: 05 add
+ 569: 0c store
+ 56a: 80 im 0
+ 56b: 0b nop
+ 56c: 8c im 12
+ 56d: 08 load
+ 56e: f4 im -12
+ 56f: 05 add
+ 570: 0c store
+ 571: 8c im 12
+ 572: 08 load
+ 573: fc im -4
+ 574: 05 add
+ 575: 08 load
+ 576: 88 im 8
+ 577: 38 neqbranch
+ 578: 81 im 1
+ 579: 0b nop
+ 57a: 8c im 12
+ 57b: 08 load
+ 57c: f4 im -12
+ 57d: 05 add
+ 57e: 0c store
+
+0000057f <.L3>:
+ 57f: 8c im 12
+ 580: 08 load
+ 581: f4 im -12
+ 582: 05 add
+ 583: 08 load
+ 584: 8c im 12
+ 585: 08 load
+ 586: fc im -4
+ 587: 05 add
+ 588: 0c store
+
+00000589 <.L2>:
+ 589: 8c im 12
+ 58a: 08 load
+ 58b: 8c im 12
+ 58c: 05 add
+ 58d: 08 load
+ 58e: 80 im 0
+ 58f: 25 lessthanorequal
+ 590: ab im 43
+ 591: 38 neqbranch
+ 592: 8c im 12
+ 593: 08 load
+ 594: 8c im 12
+ 595: 05 add
+ 596: 08 load
+ 597: 30 neg
+ 598: 8c im 12
+ 599: 08 load
+ 59a: 8c im 12
+ 59b: 05 add
+ 59c: 0c store
+ 59d: 80 im 0
+ 59e: 0b nop
+ 59f: 8c im 12
+ 5a0: 08 load
+ 5a1: f0 im -16
+ 5a2: 05 add
+ 5a3: 0c store
+ 5a4: 8c im 12
+ 5a5: 08 load
+ 5a6: fc im -4
+ 5a7: 05 add
+ 5a8: 08 load
+ 5a9: 88 im 8
+ 5aa: 38 neqbranch
+ 5ab: 81 im 1
+ 5ac: 0b nop
+ 5ad: 8c im 12
+ 5ae: 08 load
+ 5af: f0 im -16
+ 5b0: 05 add
+ 5b1: 0c store
+
+000005b2 <.L5>:
+ 5b2: 8c im 12
+ 5b3: 08 load
+ 5b4: f0 im -16
+ 5b5: 05 add
+ 5b6: 08 load
+ 5b7: 8c im 12
+ 5b8: 08 load
+ 5b9: fc im -4
+ 5ba: 05 add
+ 5bb: 0c store
+
+000005bc <.L4>:
+ 5bc: 80 im 0
+ 5bd: 53 storesp 12
+ 5be: 8c im 12
+ 5bf: 08 load
+ 5c0: 8c im 12
+ 5c1: 05 add
+ 5c2: 08 load
+ 5c3: 52 storesp 8
+ 5c4: 8c im 12
+ 5c5: 08 load
+ 5c6: 88 im 8
+ 5c7: 05 add
+ 5c8: 08 load
+ 5c9: 51 storesp 4
+ 5ca: 81 im 1
+ 5cb: a7 im 39
+ 5cc: 3f callpcrel
+ 5cd: 80 im 0
+ 5ce: 08 load
+ 5cf: 70 loadsp 0
+ 5d0: 8c im 12
+ 5d1: 08 load
+ 5d2: f8 im -8
+ 5d3: 05 add
+ 5d4: 0c store
+ 5d5: 54 storesp 16
+ 5d6: 8c im 12
+ 5d7: 08 load
+ 5d8: fc im -4
+ 5d9: 05 add
+ 5da: 08 load
+ 5db: 80 im 0
+ 5dc: 2e eq
+ 5dd: 8c im 12
+ 5de: 38 neqbranch
+ 5df: 8c im 12
+ 5e0: 08 load
+ 5e1: f8 im -8
+ 5e2: 05 add
+ 5e3: 08 load
+ 5e4: 30 neg
+ 5e5: 8c im 12
+ 5e6: 08 load
+ 5e7: f8 im -8
+ 5e8: 05 add
+ 5e9: 0c store
+
+000005ea <.L6>:
+ 5ea: 8c im 12
+ 5eb: 08 load
+ 5ec: f8 im -8
+ 5ed: 05 add
+ 5ee: 08 load
+ 5ef: 70 loadsp 0
+ 5f0: 80 im 0
+ 5f1: 0c store
+ 5f2: 54 storesp 16
+ 5f3: 89 im 9
+ 5f4: 3d pushspadd
+ 5f5: 0d popsp
+ 5f6: 8c im 12
+ 5f7: 0c store
+ 5f8: 04 poppc
+
+000005f9 <__modsi3>:
+ 5f9: 8c im 12
+ 5fa: 08 load
+ 5fb: 02 pushsp
+ 5fc: 8c im 12
+ 5fd: 0c store
+ 5fe: fb im -5
+ 5ff: 3d pushspadd
+ 600: 0d popsp
+ 601: 80 im 0
+ 602: 0b nop
+ 603: 8c im 12
+ 604: 08 load
+ 605: fc im -4
+ 606: 05 add
+ 607: 0c store
+ 608: 8c im 12
+ 609: 08 load
+ 60a: 88 im 8
+ 60b: 05 add
+ 60c: 08 load
+ 60d: 80 im 0
+ 60e: 25 lessthanorequal
+ 60f: 93 im 19
+ 610: 38 neqbranch
+ 611: 8c im 12
+ 612: 08 load
+ 613: 88 im 8
+ 614: 05 add
+ 615: 08 load
+ 616: 30 neg
+ 617: 8c im 12
+ 618: 08 load
+ 619: 88 im 8
+ 61a: 05 add
+ 61b: 0c store
+ 61c: 81 im 1
+ 61d: 0b nop
+ 61e: 8c im 12
+ 61f: 08 load
+ 620: fc im -4
+ 621: 05 add
+ 622: 0c store
+
+00000623 <.L8>:
+ 623: 8c im 12
+ 624: 08 load
+ 625: 8c im 12
+ 626: 05 add
+ 627: 08 load
+ 628: 80 im 0
+ 629: 25 lessthanorequal
+ 62a: 8c im 12
+ 62b: 38 neqbranch
+ 62c: 8c im 12
+ 62d: 08 load
+ 62e: 8c im 12
+ 62f: 05 add
+ 630: 08 load
+ 631: 30 neg
+ 632: 8c im 12
+ 633: 08 load
+ 634: 8c im 12
+ 635: 05 add
+ 636: 0c store
+
+00000637 <.L9>:
+ 637: 81 im 1
+ 638: 53 storesp 12
+ 639: 8c im 12
+ 63a: 08 load
+ 63b: 8c im 12
+ 63c: 05 add
+ 63d: 08 load
+ 63e: 52 storesp 8
+ 63f: 8c im 12
+ 640: 08 load
+ 641: 88 im 8
+ 642: 05 add
+ 643: 08 load
+ 644: 51 storesp 4
+ 645: ad im 45
+ 646: 3f callpcrel
+ 647: 80 im 0
+ 648: 08 load
+ 649: 70 loadsp 0
+ 64a: 8c im 12
+ 64b: 08 load
+ 64c: f8 im -8
+ 64d: 05 add
+ 64e: 0c store
+ 64f: 54 storesp 16
+ 650: 8c im 12
+ 651: 08 load
+ 652: fc im -4
+ 653: 05 add
+ 654: 08 load
+ 655: 80 im 0
+ 656: 2e eq
+ 657: 8c im 12
+ 658: 38 neqbranch
+ 659: 8c im 12
+ 65a: 08 load
+ 65b: f8 im -8
+ 65c: 05 add
+ 65d: 08 load
+ 65e: 30 neg
+ 65f: 8c im 12
+ 660: 08 load
+ 661: f8 im -8
+ 662: 05 add
+ 663: 0c store
+
+00000664 <.L10>:
+ 664: 8c im 12
+ 665: 08 load
+ 666: f8 im -8
+ 667: 05 add
+ 668: 08 load
+ 669: 70 loadsp 0
+ 66a: 80 im 0
+ 66b: 0c store
+ 66c: 54 storesp 16
+ 66d: 87 im 7
+ 66e: 3d pushspadd
+ 66f: 0d popsp
+ 670: 8c im 12
+ 671: 0c store
+ 672: 04 poppc
+
+00000673 :
+ 673: 8c im 12
+ 674: 08 load
+ 675: 02 pushsp
+ 676: 8c im 12
+ 677: 0c store
+ 678: fd im -3
+ 679: 3d pushspadd
+ 67a: 0d popsp
+ 67b: 81 im 1
+ 67c: 0b nop
+ 67d: 8c im 12
+ 67e: 08 load
+ 67f: fc im -4
+ 680: 05 add
+ 681: 0c store
+ 682: 80 im 0
+ 683: 0b nop
+ 684: 8c im 12
+ 685: 08 load
+ 686: f8 im -8
+ 687: 05 add
+ 688: 0c store
+
+00000689 <.L2>:
+ 689: 8c im 12
+ 68a: 08 load
+ 68b: 8c im 12
+ 68c: 05 add
+ 68d: 08 load
+ 68e: 8c im 12
+ 68f: 08 load
+ 690: 88 im 8
+ 691: 05 add
+ 692: 08 load
+ 693: 27 ulessthanorequal
+ 694: ac im 44
+ 695: 38 neqbranch
+ 696: 8c im 12
+ 697: 08 load
+ 698: fc im -4
+ 699: 05 add
+ 69a: 08 load
+ 69b: 80 im 0
+ 69c: 2e eq
+ 69d: a3 im 35
+ 69e: 38 neqbranch
+ 69f: 80 im 0
+ 6a0: 0b nop
+ 6a1: 8c im 12
+ 6a2: 08 load
+ 6a3: 8c im 12
+ 6a4: 05 add
+ 6a5: 08 load
+ 6a6: 24 lessthan
+ 6a7: 99 im 25
+ 6a8: 38 neqbranch
+ 6a9: 8c im 12
+ 6aa: 08 load
+ 6ab: 8c im 12
+ 6ac: 05 add
+ 6ad: 08 load
+ 6ae: 10 addsp 0
+ 6af: 8c im 12
+ 6b0: 08 load
+ 6b1: 8c im 12
+ 6b2: 05 add
+ 6b3: 0c store
+ 6b4: 8c im 12
+ 6b5: 08 load
+ 6b6: fc im -4
+ 6b7: 05 add
+ 6b8: 08 load
+ 6b9: 10 addsp 0
+ 6ba: 8c im 12
+ 6bb: 08 load
+ 6bc: fc im -4
+ 6bd: 05 add
+ 6be: 0c store
+ 6bf: c9 im -55
+ 6c0: 39 poppcrel
+
+000006c1 <.L4>:
+ 6c1: 8c im 12
+ 6c2: 08 load
+ 6c3: fc im -4
+ 6c4: 05 add
+ 6c5: 08 load
+ 6c6: 80 im 0
+ 6c7: 2e eq
+ 6c8: 80 im 0
+ 6c9: c9 im -55
+ 6ca: 38 neqbranch
+ 6cb: 8c im 12
+ 6cc: 08 load
+ 6cd: 8c im 12
+ 6ce: 05 add
+ 6cf: 08 load
+ 6d0: 8c im 12
+ 6d1: 08 load
+ 6d2: 88 im 8
+ 6d3: 05 add
+ 6d4: 08 load
+ 6d5: 26 ulessthan
+ 6d6: a1 im 33
+ 6d7: 38 neqbranch
+ 6d8: 8c im 12
+ 6d9: 08 load
+ 6da: 88 im 8
+ 6db: 05 add
+ 6dc: 08 load
+ 6dd: 8c im 12
+ 6de: 08 load
+ 6df: 8c im 12
+ 6e0: 05 add
+ 6e1: 08 load
+ 6e2: 31 sub
+ 6e3: 8c im 12
+ 6e4: 08 load
+ 6e5: 88 im 8
+ 6e6: 05 add
+ 6e7: 0c store
+ 6e8: 8c im 12
+ 6e9: 08 load
+ 6ea: f8 im -8
+ 6eb: 05 add
+ 6ec: 08 load
+ 6ed: 8c im 12
+ 6ee: 08 load
+ 6ef: fc im -4
+ 6f0: 05 add
+ 6f1: 08 load
+ 6f2: 07 or
+ 6f3: 8c im 12
+ 6f4: 08 load
+ 6f5: f8 im -8
+ 6f6: 05 add
+ 6f7: 0c store
+
+000006f8 <.L6>:
+ 6f8: 8c im 12
+ 6f9: 08 load
+ 6fa: fc im -4
+ 6fb: 05 add
+ 6fc: 08 load
+ 6fd: 81 im 1
+ 6fe: 2a lshiftright
+ 6ff: 8c im 12
+ 700: 08 load
+ 701: fc im -4
+ 702: 05 add
+ 703: 0c store
+ 704: 8c im 12
+ 705: 08 load
+ 706: 8c im 12
+ 707: 05 add
+ 708: 08 load
+ 709: 81 im 1
+ 70a: 2a lshiftright
+ 70b: 8c im 12
+ 70c: 08 load
+ 70d: 8c im 12
+ 70e: 05 add
+ 70f: 0c store
+ 710: ff im -1
+ 711: af im 47
+ 712: 39 poppcrel
+
+00000713 <.L5>:
+ 713: 8c im 12
+ 714: 08 load
+ 715: 90 im 16
+ 716: 05 add
+ 717: 08 load
+ 718: 80 im 0
+ 719: 2e eq
+ 71a: 8f im 15
+ 71b: 38 neqbranch
+ 71c: 8c im 12
+ 71d: 08 load
+ 71e: 88 im 8
+ 71f: 05 add
+ 720: 08 load
+ 721: 70 loadsp 0
+ 722: 8c im 12
+ 723: 08 load
+ 724: f4 im -12
+ 725: 05 add
+ 726: 0c store
+ 727: 51 storesp 4
+ 728: 8d im 13
+ 729: 39 poppcrel
+
+0000072a <.L7>:
+ 72a: 8c im 12
+ 72b: 08 load
+ 72c: f8 im -8
+ 72d: 05 add
+ 72e: 08 load
+ 72f: 70 loadsp 0
+ 730: 8c im 12
+ 731: 08 load
+ 732: f4 im -12
+ 733: 05 add
+ 734: 0c store
+ 735: 51 storesp 4
+
+00000736 <.L1>:
+ 736: 8c im 12
+ 737: 08 load
+ 738: f4 im -12
+ 739: 05 add
+ 73a: 08 load
+ 73b: 80 im 0
+ 73c: 0c store
+ 73d: 85 im 5
+ 73e: 3d pushspadd
+ 73f: 0d popsp
+ 740: 8c im 12
+ 741: 0c store
+ 742: 04 poppc
+
+00000743 <_premain>:
+ 743: fd im -3
+ 744: 3d pushspadd
+ 745: 0d popsp
+
+00000746 <.LSM1>:
+ 746: 80 im 0
+ 747: 0b nop
+ 748: 90 im 16
+ 749: fc im -4
+ 74a: 08 load
+ 74b: 54 storesp 16
+ 74c: 54 storesp 16
+ 74d: 72 loadsp 8
+ 74e: 81 im 1
+ 74f: 2e eq
+ 750: 98 im 24
+ 751: 38 neqbranch
+ 752: 73 loadsp 12
+ 753: 98 im 24
+ 754: b0 im 48
+ 755: 0c store
+
+00000756 <.LSM2>:
+ 756: fa im -6
+ 757: 87 im 7
+ 758: 3f callpcrel
+
+00000759 <.LSM3>:
+ 759: f9 im -7
+ 75a: a5 im 37
+ 75b: 3f callpcrel
+
+0000075c <.LSM4>:
+ 75c: 91 im 17
+ 75d: 88 im 8
+ 75e: 52 storesp 8
+ 75f: 81 im 1
+ 760: 51 storesp 4
+ 761: fb im -5
+ 762: c1 im -63
+ 763: 3f callpcrel
+
+00000764 <.LSM5>:
+ 764: 80 im 0
+ 765: 08 load
+ 766: 51 storesp 4
+ 767: 9e im 30
+ 768: 3f callpcrel
+
+00000769 <.L6>:
+ 769: 72 loadsp 8
+ 76a: 98 im 24
+ 76b: b0 im 48
+ 76c: 0c store
+
+0000076d <.LSM7>:
+ 76d: f9 im -7
+ 76e: f0 im -16
+ 76f: 3f callpcrel
+
+00000770 <.LSM8>:
+ 770: f9 im -7
+ 771: 8e im 14
+ 772: 3f callpcrel
+
+00000773 <.LSM9>:
+ 773: 91 im 17
+ 774: 88 im 8
+ 775: 52 storesp 8
+ 776: 81 im 1
+ 777: 51 storesp 4
+ 778: fb im -5
+ 779: aa im 42
+ 77a: 3f callpcrel
+
+0000077b <.LSM10>:
+ 77b: 80 im 0
+ 77c: 08 load
+ 77d: 51 storesp 4
+ 77e: 87 im 7
+ 77f: 3f callpcrel
+
+00000780 <_exit>:
+ ...
+
+00000781 <.L8>:
+ 781: ff im -1
+ 782: 39 poppcrel
+
+00000783 <_zpu_interrupt>:
+ ...
+
+00000784 <.L12>:
+ 784: ff im -1
+ 785: 39 poppcrel
+
+00000786 :
+ 786: f7 im -9
+ 787: 3d pushspadd
+ 788: 0d popsp
+ 789: 7b loadsp 44
+
+0000078a <.LM2>:
+ 78a: 91 im 17
+ 78b: 8c im 12
+ 78c: 08 load
+ 78d: 82 im 2
+ 78e: c8 im -56
+ 78f: 11 addsp 4
+ 790: 08 load
+ 791: 5a storesp 40
+ 792: 54 storesp 16
+ 793: 5a storesp 40
+
+00000794 <.LM3>:
+ 794: 77 loadsp 28
+ 795: 80 im 0
+ 796: 2e eq
+ 797: 80 im 0
+ 798: d9 im -39
+ 799: 38 neqbranch
+
+0000079a <.L12>:
+ 79a: 81 im 1
+ 79b: 88 im 8
+ 79c: 18 addsp 32
+
+0000079d <.LM5>:
+ 79d: 84 im 4
+ 79e: 19 addsp 36
+ 79f: 08 load
+ 7a0: ff im -1
+ 7a1: 05 add
+ 7a2: 81 im 1
+ 7a3: 71 loadsp 4
+ 7a4: 2b ashiftleft
+ 7a5: 59 storesp 36
+ 7a6: 55 storesp 20
+ 7a7: 59 storesp 36
+ 7a8: 80 im 0
+ 7a9: 74 loadsp 16
+ 7aa: 24 lessthan
+ 7ab: 80 im 0
+ 7ac: e9 im -23
+ 7ad: 38 neqbranch
+
+000007ae <.L5>:
+ 7ae: 80 im 0
+ 7af: 74 loadsp 16
+ 7b0: 24 lessthan
+ 7b1: b5 im 53
+ 7b2: 38 neqbranch
+ 7b3: 73 loadsp 12
+ 7b4: 82 im 2
+ 7b5: 2b ashiftleft
+ 7b6: 78 loadsp 32
+ 7b7: 11 addsp 4
+ 7b8: 88 im 8
+ 7b9: 05 add
+ 7ba: 56 storesp 24
+ 7bb: 56 storesp 24
+
+000007bc <.L11>:
+ 7bc: 81 im 1
+ 7bd: 80 im 0
+ 7be: 19 addsp 36
+ 7bf: 08 load
+ 7c0: 77 loadsp 28
+ 7c1: 06 and
+ 7c2: 53 storesp 12
+ 7c3: 72 loadsp 8
+ 7c4: 80 im 0
+ 7c5: 2e eq
+ 7c6: b5 im 53
+ 7c7: 38 neqbranch
+
+000007c8 <.LM7>:
+ 7c8: 78 loadsp 32
+ 7c9: 16 addsp 24
+ 7ca: 70 loadsp 0
+ 7cb: 08 load
+ 7cc: 53 storesp 12
+ 7cd: 53 storesp 12
+ 7ce: 79 loadsp 36
+ 7cf: 51 storesp 4
+ 7d0: 74 loadsp 16
+ 7d1: 08 load
+ 7d2: 53 storesp 12
+ 7d3: 72 loadsp 8
+ 7d4: 2d call
+
+000007d5 <.LM8>:
+ 7d5: ff im -1
+ 7d6: 14 addsp 16
+ 7d7: fc im -4
+ 7d8: 17 addsp 28
+ 7d9: fc im -4
+ 7da: 17 addsp 28
+ 7db: 79 loadsp 36
+ 7dc: 81 im 1
+ 7dd: 2c ashiftright
+ 7de: 5a storesp 40
+ 7df: 57 storesp 28
+ 7e0: 57 storesp 28
+ 7e1: 54 storesp 16
+ 7e2: 73 loadsp 12
+ 7e3: 80 im 0
+ 7e4: 25 lessthanorequal
+ 7e5: d6 im -42
+ 7e6: 38 neqbranch
+
+000007e7 <.L17>:
+ 7e7: 77 loadsp 28
+ 7e8: 08 load
+ 7e9: 58 storesp 32
+ 7ea: 77 loadsp 28
+ 7eb: ff im -1
+ 7ec: ad im 45
+ 7ed: 38 neqbranch
+ 7ee: 91 im 17
+ 7ef: 8c im 12
+ 7f0: 08 load
+ 7f1: 53 storesp 12
+
+000007f2 <.L15>:
+ 7f2: bc im 60
+ 7f3: 13 addsp 12
+ 7f4: 08 load
+ 7f5: a5 im 37
+ 7f6: 38 neqbranch
+
+000007f7 <.LM11>:
+ 7f7: 79 loadsp 36
+ 7f8: 51 storesp 4
+ 7f9: ff im -1
+ 7fa: 85 im 5
+ 7fb: 3f callpcrel
+
+000007fc <.L9>:
+ 7fc: 74 loadsp 16
+ 7fd: 08 load
+ 7fe: 53 storesp 12
+ 7ff: 72 loadsp 8
+ 800: 2d call
+
+00000801 <.LM13>:
+ 801: ff im -1
+ 802: 14 addsp 16
+ 803: fc im -4
+ 804: 17 addsp 28
+ 805: fc im -4
+ 806: 17 addsp 28
+ 807: 79 loadsp 36
+ 808: 81 im 1
+ 809: 2c ashiftright
+ 80a: 5a storesp 40
+ 80b: 57 storesp 28
+ 80c: 57 storesp 28
+ 80d: 54 storesp 16
+ 80e: 73 loadsp 12
+ 80f: 80 im 0
+ 810: 25 lessthanorequal
+ 811: ff im -1
+ 812: a9 im 41
+ 813: 38 neqbranch
+ 814: d2 im -46
+ 815: 39 poppcrel
+
+00000816 <.L19>:
+ 816: 80 im 0
+ 817: 57 storesp 28
+ 818: ff im -1
+ 819: 94 im 20
+ 81a: 39 poppcrel
+
+0000081b <.L20>:
+ 81b: 72 loadsp 8
+ 81c: 51 storesp 4
+ 81d: bc im 60
+ 81e: 13 addsp 12
+ 81f: 08 load
+ 820: 53 storesp 12
+ 821: 72 loadsp 8
+ 822: 2d call
+
+00000823 <.LM15>:
+ 823: 79 loadsp 36
+ 824: 51 storesp 4
+ 825: fe im -2
+ 826: d9 im -39
+ 827: 3f callpcrel
+
+00000828 <__do_global_ctors_aux>:
+ 828: ff im -1
+ 829: 3d pushspadd
+ 82a: 0d popsp
+ 82b: 98 im 24
+ 82c: 90 im 16
+ 82d: 0b nop
+ 82e: fc im -4
+ 82f: 05 add
+ 830: 70 loadsp 0
+ 831: 08 load
+ 832: 52 storesp 8
+ 833: 52 storesp 8
+ 834: 70 loadsp 0
+ 835: ff im -1
+ 836: 2e eq
+ 837: 91 im 17
+ 838: 38 neqbranch
+
+00000839 <.L10>:
+ 839: 70 loadsp 0
+ 83a: 2d call
+ 83b: fc im -4
+ 83c: 12 addsp 8
+ 83d: 70 loadsp 0
+ 83e: 08 load
+ 83f: 52 storesp 8
+ 840: 52 storesp 8
+ 841: 70 loadsp 0
+ 842: ff im -1
+ 843: 2e eq
+ 844: 09 not
+ 845: 81 im 1
+ 846: 06 and
+ 847: f1 im -15
+ 848: 38 neqbranch
+
+00000849 <.L7>:
+ 849: 83 im 3
+ 84a: 3d pushspadd
+ 84b: 0d popsp
+ 84c: 04 poppc
+
+0000084d :
+ 84d: 04 poppc
+Disassembly of section .fini:
+
+0000084e <_fini>:
+ 84e: f8 im -8
+ 84f: f4 im -12
+ 850: 3f callpcrel
+ 851: 04 poppc
+Disassembly of section .rodata:
+
+00000854 :
+ 854: 00 breakpoint
+ 855: 00 breakpoint
+ 856: 00 breakpoint
+ 857: 40 storesp 64
+ 858: 64 loadsp 80
+ 859: 75 loadsp 20
+ 85a: 6d loadsp 116
+ 85b: 6d loadsp 116
+ 85c: 79 loadsp 36
+ 85d: 2e eq
+ 85e: 65 loadsp 84
+ 85f: 78 loadsp 32
+ 860: 65 loadsp 84
+ 861: 00 breakpoint
+ 862: 00 breakpoint
+ 863: 00 breakpoint
+ 864: 43 storesp 76
+ ...
+Disassembly of section .data:
+
+00000868 <__data_start>:
+ 868: 00 breakpoint
+ 869: ff im -1
+ 86a: ff im -1
+ 86b: ff im -1
+ 86c: ff im -1
+ 86d: 00 breakpoint
+ 86e: ff im -1
+ 86f: ff im -1
+ 870: ff im -1
+ 871: ff im -1
+ 872: 00 breakpoint
+ 873: ff im -1
+ 874: ff im -1
+ 875: ff im -1
+ 876: ff im -1
+ ...
+
+00000878 <_hardware>:
+ 878: 00 breakpoint
+ 879: 00 breakpoint
+ ...
+
+0000087c <_cpu_config>:
+ 87c: 00 breakpoint
+ 87d: 00 breakpoint
+ ...
+
+00000880 <__dso_handle>:
+ 880: 00 breakpoint
+ 881: 00 breakpoint
+ ...
+
+00000884 :
+ 884: 00 breakpoint
+ 885: 00 breakpoint
+ 886: 0c store
+ 887: 18 addsp 32
+
+00000888 :
+ 888: 00 breakpoint
+ 889: 00 breakpoint
+ 88a: 08 load
+ 88b: 58 storesp 32
+
+0000088c <_impure_ptr>:
+ 88c: 00 breakpoint
+ 88d: 00 breakpoint
+ 88e: 08 load
+ 88f: 90 im 16
+
+00000890 :
+ 890: 00 breakpoint
+ 891: 00 breakpoint
+ 892: 00 breakpoint
+ 893: 00 breakpoint
+ 894: 00 breakpoint
+ 895: 00 breakpoint
+ 896: 0a flip
+ 897: f8 im -8
+ 898: 00 breakpoint
+ 899: 00 breakpoint
+ 89a: 0b nop
+ 89b: 54 storesp 16
+ 89c: 00 breakpoint
+ 89d: 00 breakpoint
+ 89e: 0b nop
+ 89f: b0 im 48
+ ...
+ 8c4: 00 breakpoint
+ 8c5: 00 breakpoint
+ 8c6: 08 load
+ 8c7: 64 loadsp 80
+ ...
+ 938: 00 breakpoint
+ 939: 00 breakpoint
+ 93a: 00 breakpoint
+ 93b: 01 .byte 1
+ 93c: 33 loadb
+ 93d: 0e .byte 14
+ 93e: ab im 43
+ 93f: cd im -51
+ 940: 12 addsp 8
+ 941: 34 storeb
+ 942: e6 im -26
+ 943: 6d loadsp 116
+ 944: de im -34
+ 945: ec im -20
+ 946: 00 breakpoint
+ 947: 05 add
+ 948: 00 breakpoint
+ 949: 0b nop
+ ...
+Disassembly of section .ctors:
+
+00000c0c <___ctors>:
+ c0c: ff im -1
+ c0d: ff im -1
+ c0e: ff im -1
+ c0f: ff im -1
+
+00000c10 <__CTOR_END__>:
+ c10: 00 breakpoint
+ c11: 00 breakpoint
+ ...
+Disassembly of section .dtors:
+
+00000c14 <___dtors>:
+ c14: ff im -1
+ c15: ff im -1
+ c16: ff im -1
+ c17: ff im -1
+
+00000c18 <__DTOR_END__>:
+ c18: 00 breakpoint
+ c19: 00 breakpoint
+ ...
+Disassembly of section .jcr:
+
+00000c1c <__JCR_END__>:
+ c1c: 00 breakpoint
+ c1d: 00 breakpoint
+ ...
+Disassembly of section .bss:
+
+00000c20 :
+ c20: 00 breakpoint
+ c21: 00 breakpoint
+ ...
+
+00000c24 :
+ c24: 00 breakpoint
+ c25: 00 breakpoint
+ ...
+
+00000c28 :
+ c28: 00 breakpoint
+ c29: 00 breakpoint
+ ...
+
+00000c2c :
+ c2c: 00 breakpoint
+ c2d: 00 breakpoint
+ ...
+
+00000c30 <_use_syscall>:
+ c30: 00 breakpoint
+ c31: 00 breakpoint
+ ...
+Disassembly of section .debug_aranges:
+
+00000000 <.debug_aranges>:
+ 0: 00 breakpoint
+ 1: 00 breakpoint
+ 2: 00 breakpoint
+ 3: 3c syscall
+ 4: 00 breakpoint
+ 5: 02 pushsp
+ 6: 00 breakpoint
+ 7: 00 breakpoint
+ 8: 00 breakpoint
+ 9: 00 breakpoint
+ a: 04 poppc
+ ...
+ 1f: 29 mult
+ 20: 00 breakpoint
+ 21: 00 breakpoint
+ 22: 00 breakpoint
+ 23: 00 breakpoint
+ 24: 00 breakpoint
+ 25: 00 breakpoint
+ 26: 00 breakpoint
+ 27: 25 lessthanorequal
+ 28: 00 breakpoint
+ 29: 00 breakpoint
+ 2a: 04 poppc
+ 2b: 5f storesp 60
+ 2c: 00 breakpoint
+ 2d: 00 breakpoint
+ 2e: 00 breakpoint
+ 2f: 85 im 5
+ 30: 00 breakpoint
+ 31: 00 breakpoint
+ 32: 00 breakpoint
+ 33: 00 breakpoint
+ 34: 00 breakpoint
+ 35: 00 breakpoint
+ 36: 00 breakpoint
+ 37: 6c loadsp 112
+ ...
+ 40: 00 breakpoint
+ 41: 00 breakpoint
+ 42: 00 breakpoint
+ 43: 1c addsp 48
+ 44: 00 breakpoint
+ 45: 02 pushsp
+ 46: 00 breakpoint
+ 47: 00 breakpoint
+ 48: 01 .byte 1
+ 49: 75 loadsp 20
+ 4a: 04 poppc
+ 4b: 00 breakpoint
+ 4c: 00 breakpoint
+ 4d: 00 breakpoint
+ 4e: 00 breakpoint
+ 4f: 00 breakpoint
+ 50: 00 breakpoint
+ 51: 00 breakpoint
+ 52: 05 add
+ 53: 24 lessthan
+ 54: 00 breakpoint
+ 55: 00 breakpoint
+ 56: 00 breakpoint
+ 57: 2f neq
+ ...
+ 60: 00 breakpoint
+ 61: 00 breakpoint
+ 62: 00 breakpoint
+ 63: 1c addsp 48
+ 64: 00 breakpoint
+ 65: 02 pushsp
+ 66: 00 breakpoint
+ 67: 00 breakpoint
+ 68: 01 .byte 1
+ 69: d2 im -46
+ 6a: 04 poppc
+ ...
+ 77: b8 im 56
+ ...
+ 80: 00 breakpoint
+ 81: 00 breakpoint
+ 82: 00 breakpoint
+ 83: 94 im 20
+ 84: 00 breakpoint
+ 85: 02 pushsp
+ 86: 00 breakpoint
+ 87: 00 breakpoint
+ 88: 02 pushsp
+ 89: d1 im -47
+ 8a: 04 poppc
+ ...
+ 97: 00 breakpoint
+ 98: 00 breakpoint
+ 99: 00 breakpoint
+ 9a: 07 or
+ 9b: 43 storesp 76
+ 9c: 00 breakpoint
+ 9d: 00 breakpoint
+ 9e: 00 breakpoint
+ 9f: 6a loadsp 104
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+ a1: 00 breakpoint
+ a2: 07 or
+ a3: 80 im 0
+ a4: 00 breakpoint
+ a5: 00 breakpoint
+ a6: 00 breakpoint
+ a7: 07 or
+ a8: 00 breakpoint
+ a9: 00 breakpoint
+ aa: 07 or
+ ab: 83 im 3
+ ac: 00 breakpoint
+ ad: 00 breakpoint
+ ae: 00 breakpoint
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+ b1: 00 breakpoint
+ b2: 00 breakpoint
+ b3: 00 breakpoint
+ b4: 00 breakpoint
+ b5: 00 breakpoint
+ b6: 00 breakpoint
+ b7: 98 im 24
+ b8: 00 breakpoint
+ b9: 00 breakpoint
+ ba: 00 breakpoint
+ bb: 00 breakpoint
+ bc: 00 breakpoint
+ bd: 00 breakpoint
+ be: 00 breakpoint
+ bf: b4 im 52
+ c0: 00 breakpoint
+ c1: 00 breakpoint
+ c2: 00 breakpoint
+ c3: 00 breakpoint
+ c4: 00 breakpoint
+ c5: 00 breakpoint
+ c6: 00 breakpoint
+ c7: 5a storesp 40
+ c8: 00 breakpoint
+ c9: 00 breakpoint
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+ cb: 00 breakpoint
+ cc: 00 breakpoint
+ cd: 00 breakpoint
+ ce: 00 breakpoint
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+ d1: 00 breakpoint
+ d2: 00 breakpoint
+ d3: 00 breakpoint
+ d4: 00 breakpoint
+ d5: 00 breakpoint
+ d6: 00 breakpoint
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+ d9: 00 breakpoint
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+ db: 00 breakpoint
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+ de: 00 breakpoint
+ df: 56 storesp 24
+ e0: 00 breakpoint
+ e1: 00 breakpoint
+ e2: 00 breakpoint
+ e3: 00 breakpoint
+ e4: 00 breakpoint
+ e5: 00 breakpoint
+ e6: 00 breakpoint
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+ e8: 00 breakpoint
+ e9: 00 breakpoint
+ ea: 00 breakpoint
+ eb: 00 breakpoint
+ ec: 00 breakpoint
+ ed: 00 breakpoint
+ ee: 00 breakpoint
+ ef: 3d pushspadd
+ f0: 00 breakpoint
+ f1: 00 breakpoint
+ f2: 00 breakpoint
+ f3: 00 breakpoint
+ f4: 00 breakpoint
+ f5: 00 breakpoint
+ f6: 00 breakpoint
+ f7: 95 im 21
+ f8: 00 breakpoint
+ f9: 00 breakpoint
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+ fb: 00 breakpoint
+ fc: 00 breakpoint
+ fd: 00 breakpoint
+ fe: 00 breakpoint
+ ff: 58 storesp 32
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+ 101: 00 breakpoint
+ 102: 00 breakpoint
+ 103: 00 breakpoint
+ 104: 00 breakpoint
+ 105: 00 breakpoint
+ 106: 00 breakpoint
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+ 109: 00 breakpoint
+ 10a: 00 breakpoint
+ 10b: 00 breakpoint
+ 10c: 00 breakpoint
+ 10d: 00 breakpoint
+ 10e: 00 breakpoint
+ 10f: 3c syscall
+ ...
+ 118: 00 breakpoint
+ 119: 00 breakpoint
+ 11a: 00 breakpoint
+ 11b: 1c addsp 48
+ 11c: 00 breakpoint
+ 11d: 02 pushsp
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+ 11f: 00 breakpoint
+ 120: 0b nop
+ 121: b9 im 57
+ 122: 04 poppc
+ ...
+ 12f: 09 not
+ ...
+ 138: 00 breakpoint
+ 139: 00 breakpoint
+ 13a: 00 breakpoint
+ 13b: 1c addsp 48
+ 13c: 00 breakpoint
+ 13d: 02 pushsp
+ 13e: 00 breakpoint
+ 13f: 00 breakpoint
+ 140: 14 addsp 16
+ 141: a2 im 34
+ 142: 04 poppc
+ 143: 00 breakpoint
+ 144: 00 breakpoint
+ 145: 00 breakpoint
+ 146: 00 breakpoint
+ 147: 00 breakpoint
+ 148: 00 breakpoint
+ 149: 00 breakpoint
+ 14a: 07 or
+ 14b: 86 im 6
+ 14c: 00 breakpoint
+ 14d: 00 breakpoint
+ 14e: 00 breakpoint
+ 14f: d1 im -47
+ ...
+ 158: 00 breakpoint
+ 159: 00 breakpoint
+ 15a: 00 breakpoint
+ 15b: 1c addsp 48
+ 15c: 00 breakpoint
+ 15d: 02 pushsp
+ 15e: 00 breakpoint
+ 15f: 00 breakpoint
+ 160: 26 ulessthan
+ 161: a7 im 39
+ 162: 04 poppc
+ ...
+ 16f: b2 im 50
+ ...
+ 178: 00 breakpoint
+ 179: 00 breakpoint
+ 17a: 00 breakpoint
+ 17b: 1c addsp 48
+ 17c: 00 breakpoint
+ 17d: 02 pushsp
+ 17e: 00 breakpoint
+ 17f: 00 breakpoint
+ 180: 27 ulessthanorequal
+ 181: ab im 43
+ 182: 04 poppc
+ ...
+ 18f: 73 loadsp 12
+ ...
+Disassembly of section .debug_pubnames:
+
+00000000 <.debug_pubnames>:
+ 0: 00 breakpoint
+ 1: 00 breakpoint
+ 2: 00 breakpoint
+ 3: 49 storesp 100
+ 4: 00 breakpoint
+ 5: 02 pushsp
+ 6: 00 breakpoint
+ 7: 00 breakpoint
+ 8: 00 breakpoint
+ 9: 00 breakpoint
+ a: 00 breakpoint
+ b: 00 breakpoint
+ c: 01 .byte 1
+ d: 75 loadsp 20
+ e: 00 breakpoint
+ f: 00 breakpoint
+ 10: 00 breakpoint
+ 11: 6a loadsp 104
+ 12: 69 loadsp 100
+ 13: 6e loadsp 120
+ 14: 62 loadsp 72
+ 15: 79 loadsp 36
+ 16: 74 loadsp 16
+ 17: 65 loadsp 84
+ 18: 00 breakpoint
+ 19: 00 breakpoint
+ 1a: 00 breakpoint
+ 1b: 00 breakpoint
+ 1c: 93 im 19
+ 1d: 6f loadsp 124
+ 1e: 75 loadsp 20
+ 1f: 74 loadsp 16
+ 20: 62 loadsp 72
+ 21: 79 loadsp 36
+ 22: 74 loadsp 16
+ 23: 65 loadsp 84
+ 24: 00 breakpoint
+ 25: 00 breakpoint
+ 26: 00 breakpoint
+ 27: 00 breakpoint
+ 28: b8 im 56
+ 29: 5f storesp 60
+ 2a: 69 loadsp 100
+ 2b: 6e loadsp 120
+ 2c: 69 loadsp 100
+ 2d: 74 loadsp 16
+ 2e: 49 storesp 100
+ 2f: 4f storesp 124
+ 30: 00 breakpoint
+ 31: 00 breakpoint
+ 32: 00 breakpoint
+ 33: 00 breakpoint
+ 34: cc im -52
+ 35: 5f storesp 60
+ 36: 72 loadsp 8
+ 37: 65 loadsp 84
+ 38: 61 loadsp 68
+ 39: 64 loadsp 80
+ 3a: 43 storesp 76
+ 3b: 79 loadsp 36
+ 3c: 63 loadsp 76
+ 3d: 6c loadsp 112
+ 3e: 65 loadsp 84
+ 3f: 73 loadsp 12
+ 40: 00 breakpoint
+ 41: 00 breakpoint
+ 42: 00 breakpoint
+ 43: 01 .byte 1
+ 44: 4c storesp 112
+ 45: 4d storesp 116
+ 46: 48 storesp 96
+ 47: 5a storesp 40
+ ...
+ 50: 17 addsp 28
+ 51: 00 breakpoint
+ 52: 02 pushsp
+ 53: 00 breakpoint
+ 54: 00 breakpoint
+ 55: 01 .byte 1
+ 56: 75 loadsp 20
+ 57: 00 breakpoint
+ 58: 00 breakpoint
+ 59: 00 breakpoint
+ 5a: 5d storesp 52
+ 5b: 00 breakpoint
+ 5c: 00 breakpoint
+ 5d: 00 breakpoint
+ 5e: 21 .byte 33
+ 5f: 6d loadsp 116
+ 60: 61 loadsp 68
+ 61: 69 loadsp 100
+ 62: 6e loadsp 120
+ ...
+ 6b: 19 addsp 36
+ 6c: 00 breakpoint
+ 6d: 02 pushsp
+ 6e: 00 breakpoint
+ 6f: 00 breakpoint
+ 70: 01 .byte 1
+ 71: d2 im -46
+ 72: 00 breakpoint
+ 73: 00 breakpoint
+ 74: 00 breakpoint
+ 75: ff im -1
+ 76: 00 breakpoint
+ 77: 00 breakpoint
+ 78: 00 breakpoint
+ 79: 45 storesp 84
+ 7a: 6d loadsp 116
+ 7b: 65 loadsp 84
+ 7c: 6d loadsp 116
+ 7d: 63 loadsp 76
+ 7e: 70 loadsp 0
+ 7f: 79 loadsp 36
+ ...
+ 88: b0 im 48
+ 89: 00 breakpoint
+ 8a: 02 pushsp
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+ 8c: 00 breakpoint
+ 8d: 02 pushsp
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+ 8f: 00 breakpoint
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+ 91: 08 load
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+ 93: 00 breakpoint
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+ 95: 02 pushsp
+ 96: f3 im -13
+ 97: 5f storesp 60
+ 98: 70 loadsp 0
+ 99: 72 loadsp 8
+ 9a: 65 loadsp 84
+ 9b: 6d loadsp 116
+ 9c: 61 loadsp 68
+ 9d: 69 loadsp 100
+ 9e: 6e loadsp 120
+ 9f: 00 breakpoint
+ a0: 00 breakpoint
+ a1: 00 breakpoint
+ a2: 03 .byte 3
+ a3: 24 lessthan
+ a4: 5f storesp 60
+ a5: 65 loadsp 84
+ a6: 78 loadsp 32
+ a7: 69 loadsp 100
+ a8: 74 loadsp 16
+ a9: 00 breakpoint
+ aa: 00 breakpoint
+ ab: 00 breakpoint
+ ac: 03 .byte 3
+ ad: 4b storesp 108
+ ae: 5f storesp 60
+ af: 7a loadsp 40
+ b0: 70 loadsp 0
+ b1: 75 loadsp 20
+ b2: 5f storesp 60
+ b3: 69 loadsp 100
+ b4: 6e loadsp 120
+ b5: 74 loadsp 16
+ b6: 65 loadsp 84
+ b7: 72 loadsp 8
+ b8: 72 loadsp 8
+ b9: 75 loadsp 20
+ ba: 70 loadsp 0
+ bb: 74 loadsp 16
+ bc: 00 breakpoint
+ bd: 00 breakpoint
+ be: 00 breakpoint
+ bf: 03 .byte 3
+ c0: 5f storesp 60
+ c1: 77 loadsp 28
+ c2: 72 loadsp 8
+ c3: 69 loadsp 100
+ c4: 74 loadsp 16
+ c5: 65 loadsp 84
+ c6: 00 breakpoint
+ c7: 00 breakpoint
+ c8: 00 breakpoint
+ c9: 04 poppc
+ ca: 11 addsp 4
+ cb: 72 loadsp 8
+ cc: 65 loadsp 84
+ cd: 61 loadsp 68
+ ce: 64 loadsp 80
+ cf: 00 breakpoint
+ d0: 00 breakpoint
+ d1: 00 breakpoint
+ d2: 04 poppc
+ d3: eb im -21
+ d4: 6f loadsp 124
+ d5: 70 loadsp 0
+ d6: 65 loadsp 84
+ d7: 6e loadsp 120
+ d8: 00 breakpoint
+ d9: 00 breakpoint
+ da: 00 breakpoint
+ db: 05 add
+ dc: 69 loadsp 100
+ dd: 63 loadsp 76
+ de: 6c loadsp 112
+ df: 6f loadsp 124
+ e0: 73 loadsp 12
+ e1: 65 loadsp 84
+ e2: 00 breakpoint
+ e3: 00 breakpoint
+ e4: 00 breakpoint
+ e5: 05 add
+ e6: b6 im 54
+ e7: 66 loadsp 88
+ e8: 74 loadsp 16
+ e9: 72 loadsp 8
+ ea: 75 loadsp 20
+ eb: 6e loadsp 120
+ ec: 63 loadsp 76
+ ed: 61 loadsp 68
+ ee: 74 loadsp 16
+ ef: 65 loadsp 84
+ f0: 00 breakpoint
+ f1: 00 breakpoint
+ f2: 00 breakpoint
+ f3: 05 add
+ f4: ef im -17
+ f5: 75 loadsp 20
+ f6: 6e loadsp 120
+ f7: 6c loadsp 112
+ f8: 69 loadsp 100
+ f9: 6e loadsp 120
+ fa: 6b loadsp 108
+ fb: 00 breakpoint
+ fc: 00 breakpoint
+ fd: 00 breakpoint
+ fe: 06 and
+ ff: 50 storesp 0
+ 100: 6c loadsp 112
+ 101: 73 loadsp 12
+ 102: 65 loadsp 84
+ 103: 65 loadsp 84
+ 104: 6b loadsp 108
+ 105: 00 breakpoint
+ 106: 00 breakpoint
+ 107: 00 breakpoint
+ 108: 07 or
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+ 10a: 66 loadsp 88
+ 10b: 73 loadsp 12
+ 10c: 74 loadsp 16
+ 10d: 61 loadsp 68
+ 10e: 74 loadsp 16
+ 10f: 00 breakpoint
+ 110: 00 breakpoint
+ 111: 00 breakpoint
+ 112: 07 or
+ 113: d2 im -46
+ 114: 73 loadsp 12
+ 115: 74 loadsp 16
+ 116: 61 loadsp 68
+ 117: 74 loadsp 16
+ 118: 00 breakpoint
+ 119: 00 breakpoint
+ 11a: 00 breakpoint
+ 11b: 08 load
+ 11c: 56 storesp 24
+ 11d: 69 loadsp 100
+ 11e: 73 loadsp 12
+ 11f: 61 loadsp 68
+ 120: 74 loadsp 16
+ 121: 74 loadsp 16
+ 122: 79 loadsp 36
+ 123: 00 breakpoint
+ 124: 00 breakpoint
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+ 126: 08 load
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+ 128: 5f storesp 60
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+ 12a: 73 loadsp 12
+ 12b: 65 loadsp 84
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+ 12e: 79 loadsp 36
+ 12f: 73 loadsp 12
+ 130: 63 loadsp 76
+ 131: 61 loadsp 68
+ 132: 6c loadsp 112
+ 133: 6c loadsp 112
+ ...
+ 13c: 1a addsp 40
+ 13d: 00 breakpoint
+ 13e: 02 pushsp
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+ 141: 0b nop
+ 142: b9 im 57
+ 143: 00 breakpoint
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+ 145: 08 load
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+ 147: 00 breakpoint
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+ 149: 08 load
+ 14a: bc im 60
+ 14b: 5f storesp 60
+ 14c: 5f storesp 60
+ 14d: 65 loadsp 84
+ 14e: 72 loadsp 8
+ 14f: 72 loadsp 8
+ 150: 6e loadsp 120
+ 151: 6f loadsp 124
+ ...
+ 15a: 17 addsp 28
+ 15b: 00 breakpoint
+ 15c: 02 pushsp
+ 15d: 00 breakpoint
+ 15e: 00 breakpoint
+ 15f: 14 addsp 16
+ 160: a2 im 34
+ 161: 00 breakpoint
+ 162: 00 breakpoint
+ 163: 09 not
+ 164: 25 lessthanorequal
+ 165: 00 breakpoint
+ 166: 00 breakpoint
+ 167: 08 load
+ 168: bc im 60
+ 169: 65 loadsp 84
+ 16a: 78 loadsp 32
+ 16b: 69 loadsp 100
+ 16c: 74 loadsp 16
+ ...
+ 175: 1e addsp 56
+ 176: 00 breakpoint
+ 177: 02 pushsp
+ 178: 00 breakpoint
+ 179: 00 breakpoint
+ 17a: 1d addsp 52
+ 17b: c7 im -57
+ 17c: 00 breakpoint
+ 17d: 00 breakpoint
+ 17e: 08 load
+ 17f: e0 im -32
+ 180: 00 breakpoint
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+ 182: 08 load
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+ 184: 5f storesp 60
+ 185: 69 loadsp 100
+ 186: 6d loadsp 116
+ 187: 70 loadsp 0
+ 188: 75 loadsp 20
+ 189: 72 loadsp 8
+ 18a: 65 loadsp 84
+ 18b: 5f storesp 60
+ 18c: 70 loadsp 0
+ 18d: 74 loadsp 16
+ 18e: 72 loadsp 8
+ ...
+ 197: 19 addsp 36
+ 198: 00 breakpoint
+ 199: 02 pushsp
+ 19a: 00 breakpoint
+ 19b: 00 breakpoint
+ 19c: 26 ulessthan
+ 19d: a7 im 39
+ 19e: 00 breakpoint
+ 19f: 00 breakpoint
+ 1a0: 01 .byte 1
+ 1a1: 04 poppc
+ 1a2: 00 breakpoint
+ 1a3: 00 breakpoint
+ 1a4: 00 breakpoint
+ 1a5: 85 im 5
+ 1a6: 6d loadsp 116
+ 1a7: 65 loadsp 84
+ 1a8: 6d loadsp 116
+ 1a9: 73 loadsp 12
+ 1aa: 65 loadsp 84
+ 1ab: 74 loadsp 16
+ ...
+ 1b4: 19 addsp 36
+ 1b5: 00 breakpoint
+ 1b6: 02 pushsp
+ 1b7: 00 breakpoint
+ 1b8: 00 breakpoint
+ 1b9: 27 ulessthanorequal
+ 1ba: ab im 43
+ 1bb: 00 breakpoint
+ 1bc: 00 breakpoint
+ 1bd: 00 breakpoint
+ 1be: d3 im -45
+ 1bf: 00 breakpoint
+ 1c0: 00 breakpoint
+ 1c1: 00 breakpoint
+ 1c2: 88 im 8
+ 1c3: 73 loadsp 12
+ 1c4: 74 loadsp 16
+ 1c5: 72 loadsp 8
+ 1c6: 6c loadsp 112
+ 1c7: 65 loadsp 84
+ 1c8: 6e loadsp 120
+ 1c9: 00 breakpoint
+ 1ca: 00 breakpoint
+ 1cb: 00 breakpoint
+ ...
+Disassembly of section .debug_info:
+
+00000000 <.Ldebug_info0>:
+ 0: 00 breakpoint
+ 1: 00 breakpoint
+ 2: 01 .byte 1
+ 3: 71 loadsp 4
+ 4: 00 breakpoint
+ 5: 02 pushsp
+ 6: 00 breakpoint
+ 7: 00 breakpoint
+ 8: 00 breakpoint
+ 9: 00 breakpoint
+ a: 04 poppc
+ b: 01 .byte 1
+ c: 00 breakpoint
+ d: 00 breakpoint
+ e: 00 breakpoint
+ f: 00 breakpoint
+ 10: 00 breakpoint
+ 11: 00 breakpoint
+ 12: 00 breakpoint
+ 13: 5e storesp 56
+ 14: 01 .byte 1
+ 15: 00 breakpoint
+ 16: 00 breakpoint
+ 17: 00 breakpoint
+ 18: 74 loadsp 16
+ 19: 00 breakpoint
+ 1a: 00 breakpoint
+ 1b: 00 breakpoint
+ 1c: be im 62
+ 1d: 02 pushsp
+ 1e: 00 breakpoint
+ 1f: 00 breakpoint
+ 20: 00 breakpoint
+ 21: 11 addsp 4
+ 22: 04 poppc
+ 23: 07 or
+ 24: 02 pushsp
+ 25: 00 breakpoint
+ 26: 00 breakpoint
+ 27: 00 breakpoint
+ 28: 28 swap
+ 29: 04 poppc
+ 2a: 05 add
+ 2b: 02 pushsp
+ 2c: 00 breakpoint
+ 2d: 00 breakpoint
+ 2e: 00 breakpoint
+ 2f: 23 storeh
+ 30: 08 load
+ 31: 05 add
+ 32: 03 .byte 3
+ 33: 69 loadsp 100
+ 34: 6e loadsp 120
+ 35: 74 loadsp 16
+ 36: 00 breakpoint
+ 37: 04 poppc
+ 38: 05 add
+ 39: 02 pushsp
+ 3a: 00 breakpoint
+ 3b: 00 breakpoint
+ 3c: 00 breakpoint
+ 3d: 16 addsp 24
+ 3e: 04 poppc
+ 3f: 07 or
+ 40: 02 pushsp
+ 41: 00 breakpoint
+ 42: 00 breakpoint
+ 43: 00 breakpoint
+ 44: 11 addsp 4
+ 45: 04 poppc
+ 46: 07 or
+ 47: 02 pushsp
+ 48: 00 breakpoint
+ 49: 00 breakpoint
+ 4a: 00 breakpoint
+ 4b: 9a im 26
+ 4c: 01 .byte 1
+ 4d: 08 load
+ 4e: 02 pushsp
+ 4f: 00 breakpoint
+ 50: 00 breakpoint
+ 51: 00 breakpoint
+ 52: a8 im 40
+ 53: 02 pushsp
+ 54: 05 add
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+ 56: 00 breakpoint
+ 57: 00 breakpoint
+ 58: 00 breakpoint
+ 59: a3 im 35
+ 5a: 01 .byte 1
+ 5b: 08 load
+ 5c: 02 pushsp
+ 5d: 00 breakpoint
+ 5e: 00 breakpoint
+ 5f: 00 breakpoint
+ 60: 4b storesp 108
+ 61: 02 pushsp
+ 62: 07 or
+ 63: 02 pushsp
+ 64: 00 breakpoint
+ 65: 00 breakpoint
+ 66: 00 breakpoint
+ 67: 0c store
+ 68: 08 load
+ 69: 07 or
+ 6a: 04 poppc
+ 6b: 00 breakpoint
+ 6c: 00 breakpoint
+ 6d: 00 breakpoint
+ 6e: 93 im 19
+ 6f: 01 .byte 1
+ 70: 00 breakpoint
+ 71: 00 breakpoint
+ 72: 00 breakpoint
+ 73: b2 im 50
+ 74: 0b nop
+ 75: 18 addsp 32
+ 76: 00 breakpoint
+ 77: 00 breakpoint
+ 78: 00 breakpoint
+ 79: 32 xor
+ ...
+ 82: 02 pushsp
+ 83: 90 im 16
+ 84: 20 .byte 32
+ 85: 05 add
+ 86: 76 loadsp 24
+ 87: 61 loadsp 68
+ 88: 6c loadsp 112
+ 89: 00 breakpoint
+ 8a: 0b nop
+ 8b: 19 addsp 36
+ 8c: 00 breakpoint
+ 8d: 00 breakpoint
+ 8e: 00 breakpoint
+ 8f: 32 xor
+ 90: 01 .byte 1
+ 91: 59 storesp 36
+ 92: 00 breakpoint
+ 93: 06 and
+ 94: 00 breakpoint
+ 95: 00 breakpoint
+ 96: 00 breakpoint
+ 97: b8 im 56
+ 98: 01 .byte 1
+ 99: 00 breakpoint
+ 9a: 00 breakpoint
+ 9b: 00 breakpoint
+ 9c: 37 eqbranch
+ 9d: 0b nop
+ 9e: 2c ashiftright
+ 9f: 01 .byte 1
+ ...
+ a8: 02 pushsp
+ a9: 90 im 16
+ aa: 20 .byte 32
+ ab: 07 or
+ ac: 63 loadsp 76
+ ad: 00 breakpoint
+ ae: 0b nop
+ af: 2b ashiftleft
+ b0: 00 breakpoint
+ b1: 00 breakpoint
+ b2: 00 breakpoint
+ b3: 32 xor
+ b4: 02 pushsp
+ b5: 91 im 17
+ b6: 0c store
+ b7: 00 breakpoint
+ b8: 08 load
+ b9: 01 .byte 1
+ ba: 00 breakpoint
+ bb: 00 breakpoint
+ bc: 00 breakpoint
+ bd: fd im -3
+ be: 0b nop
+ bf: 35 div
+ c0: 01 .byte 1
+ c1: 00 breakpoint
+ c2: 00 breakpoint
+ c3: 04 poppc
+ c4: 5f storesp 60
+ c5: 00 breakpoint
+ c6: 00 breakpoint
+ c7: 04 poppc
+ c8: c4 im -60
+ c9: 02 pushsp
+ ca: 90 im 16
+ cb: 20 .byte 32
+ cc: 04 poppc
+ cd: 00 breakpoint
+ ce: 00 breakpoint
+ cf: 01 .byte 1
+ d0: 05 add
+ d1: 01 .byte 1
+ d2: 00 breakpoint
+ d3: 00 breakpoint
+ d4: 00 breakpoint
+ d5: 3f callpcrel
+ d6: 0b nop
+ d7: 50 storesp 0
+ d8: 00 breakpoint
+ d9: 00 breakpoint
+ da: 00 breakpoint
+ db: 2b ashiftleft
+ ...
+ e4: 02 pushsp
+ e5: 90 im 16
+ e6: 20 .byte 32
+ e7: 09 not
+ e8: 00 breakpoint
+ e9: 00 breakpoint
+ ea: 01 .byte 1
+ eb: 05 add
+ ec: 0b nop
+ ed: 51 storesp 4
+ ee: 00 breakpoint
+ ef: 00 breakpoint
+ f0: 00 breakpoint
+ f1: 2b ashiftleft
+ f2: 06 and
+ f3: 5c storesp 48
+ f4: 93 im 19
+ f5: 04 poppc
+ f6: 5d storesp 52
+ f7: 93 im 19
+ f8: 04 poppc
+ f9: 05 add
+ fa: 69 loadsp 100
+ fb: 00 breakpoint
+ fc: 0b nop
+ fd: 52 storesp 8
+ fe: 00 breakpoint
+ ff: 00 breakpoint
+ 100: 00 breakpoint
+ 101: 39 poppcrel
+ 102: 01 .byte 1
+ 103: 5e storesp 56
+ 104: 00 breakpoint
+ 105: 0a flip
+ 106: 00 breakpoint
+ 107: 00 breakpoint
+ 108: 00 breakpoint
+ 109: 6a loadsp 104
+ 10a: 0b nop
+ 10b: 06 and
+ 10c: 00 breakpoint
+ 10d: 00 breakpoint
+ 10e: 00 breakpoint
+ 10f: 32 xor
+ 110: 01 .byte 1
+ 111: 01 .byte 1
+ 112: 0a flip
+ 113: 00 breakpoint
+ 114: 00 breakpoint
+ 115: 00 breakpoint
+ 116: 00 breakpoint
+ 117: 0b nop
+ 118: 0b nop
+ 119: 00 breakpoint
+ 11a: 00 breakpoint
+ 11b: 00 breakpoint
+ 11c: 32 xor
+ 11d: 01 .byte 1
+ 11e: 01 .byte 1
+ 11f: 09 not
+ 120: 00 breakpoint
+ 121: 00 breakpoint
+ 122: 00 breakpoint
+ 123: b9 im 57
+ 124: 0b nop
+ 125: 0c store
+ 126: 00 breakpoint
+ 127: 00 breakpoint
+ 128: 01 .byte 1
+ 129: 30 neg
+ 12a: 05 add
+ 12b: 03 .byte 3
+ 12c: 00 breakpoint
+ 12d: 00 breakpoint
+ 12e: 0c store
+ 12f: 20 .byte 32
+ 130: 0b nop
+ 131: 04 poppc
+ 132: 00 breakpoint
+ 133: 00 breakpoint
+ 134: 01 .byte 1
+ 135: 36 mod
+ 136: 0c store
+ 137: 00 breakpoint
+ 138: 00 breakpoint
+ 139: 00 breakpoint
+ 13a: 32 xor
+ 13b: 09 not
+ 13c: 00 breakpoint
+ 13d: 00 breakpoint
+ 13e: 00 breakpoint
+ 13f: 31 sub
+ 140: 0b nop
+ 141: 0d popsp
+ 142: 00 breakpoint
+ 143: 00 breakpoint
+ 144: 01 .byte 1
+ 145: 30 neg
+ 146: 05 add
+ 147: 03 .byte 3
+ 148: 00 breakpoint
+ 149: 00 breakpoint
+ 14a: 0c store
+ 14b: 24 lessthan
+ 14c: 0d popsp
+ 14d: 4d storesp 116
+ 14e: 48 storesp 96
+ 14f: 5a storesp 40
+ 150: 00 breakpoint
+ 151: 0b nop
+ 152: 0e .byte 14
+ 153: 00 breakpoint
+ 154: 00 breakpoint
+ 155: 01 .byte 1
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+ ...
+
+00000175 <.Ldebug_info0>:
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+
+000001d2 <.Ldebug_info0>:
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+
+000002d1 <.Ldebug_info0>:
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+ bb2: 05 add
+ bb3: 03 .byte 3
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+ bb5: 00 breakpoint
+ bb6: 08 load
+ bb7: 88 im 8
+ ...
+
+00000bb9 <.Ldebug_info0>:
+ bb9: 00 breakpoint
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+ bbd: 00 breakpoint
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+ bc3: 04 poppc
+ bc4: 01 .byte 1
+ bc5: 00 breakpoint
+ bc6: 00 breakpoint
+ bc7: 0a flip
+ bc8: e6 im -26
+ ...
+ bd1: 00 breakpoint
+ bd2: 00 breakpoint
+ bd3: 00 breakpoint
+ bd4: 5e storesp 56
+ bd5: 01 .byte 1
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+ bff: 03 .byte 3
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+ c09: 00 breakpoint
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+ c31: 00 breakpoint
+ c32: 7c loadsp 48
+ c33: 03 .byte 3
+ c34: 00 breakpoint
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+ c37: 00 breakpoint
+ c38: 00 breakpoint
+ c39: 11 addsp 4
+ c3a: 04 poppc
+ c3b: 07 or
+ c3c: 03 .byte 3
+ c3d: 00 breakpoint
+ c3e: 00 breakpoint
+ c3f: 00 breakpoint
+ c40: 9a im 26
+ c41: 01 .byte 1
+ c42: 08 load
+ c43: 09 not
+ c44: 00 breakpoint
+ c45: 00 breakpoint
+ c46: 00 breakpoint
+ c47: af im 47
+ c48: 08 load
+ c49: 02 pushsp
+ c4a: 21 .byte 33
+ c4b: 0a flip
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+ c4d: 00 breakpoint
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+ c53: 00 breakpoint
+ c54: 00 breakpoint
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+ c5b: 00 breakpoint
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+ c5d: 3a config
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+ c61: 00 breakpoint
+ c62: 00 breakpoint
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+ c7b: 00 breakpoint
+ c7c: 00 breakpoint
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+ c82: 00 breakpoint
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+ c88: 00 breakpoint
+ c89: 00 breakpoint
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+ c94: 00 breakpoint
+ c95: 01 .byte 1
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+ c98: 00 breakpoint
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+ ca0: 00 breakpoint
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+ ca3: 04 poppc
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+ ca6: 00 breakpoint
+ ca7: 01 .byte 1
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+ cae: 6b loadsp 108
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+ cb3: 00 breakpoint
+ cb4: 00 breakpoint
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+ cc1: 00 breakpoint
+ cc2: 00 breakpoint
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+ cc9: 00 breakpoint
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+ cd7: 00 breakpoint
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+ cda: 04 poppc
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+ cdd: 00 breakpoint
+ cde: 00 breakpoint
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+ ce0: 02 pushsp
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+ ce5: 78 loadsp 32
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+ cea: 00 breakpoint
+ ceb: 01 .byte 1
+ cec: 3e halfmult
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+ cf0: 00 breakpoint
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+ cf4: 00 breakpoint
+ cf5: 00 breakpoint
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+ cf9: 00 breakpoint
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+ cfd: 00 breakpoint
+ cfe: 00 breakpoint
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+ d02: 00 breakpoint
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+ d05: 00 breakpoint
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+ d15: 00 breakpoint
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+ d94: 00 breakpoint
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+ db4: 00 breakpoint
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+ dc3: 00 breakpoint
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+ dd5: 01 .byte 1
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+ f10: 00 breakpoint
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+ f32: 00 breakpoint
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+ f40: 00 breakpoint
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+ f56: 00 breakpoint
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+ f79: 00 breakpoint
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+ f83: 04 poppc
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+ f91: 00 breakpoint
+ f92: 00 breakpoint
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+ 18fc: 00 breakpoint
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+ 18ff: 03 .byte 3
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+ 1920: 00 breakpoint
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+ 1927: 12 addsp 8
+ 1928: 00 breakpoint
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+ 192c: 03 .byte 3
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+ 1930: 00 breakpoint
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+ 1936: 12 addsp 8
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+ 193b: 03 .byte 3
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+ 1940: 01 .byte 1
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+ 1945: 12 addsp 8
+ 1946: 00 breakpoint
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+ 1954: 12 addsp 8
+ 1955: 00 breakpoint
+ 1956: 00 breakpoint
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+ 1959: 03 .byte 3
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+ 1960: 02 pushsp
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+ 1962: 50 storesp 0
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+ 1964: 00 breakpoint
+ 1965: 00 breakpoint
+ 1966: 06 and
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+ 1971: 54 storesp 16
+ 1972: 12 addsp 8
+ 1973: 00 breakpoint
+ 1974: 00 breakpoint
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+ 1977: 03 .byte 3
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+ 197a: 00 breakpoint
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+ 197e: 02 pushsp
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+ 1980: 58 storesp 32
+ 1981: 12 addsp 8
+ 1982: 00 breakpoint
+ 1983: 00 breakpoint
+ 1984: 07 or
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+ 1986: 03 .byte 3
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+ 1989: 00 breakpoint
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+ 198d: 03 .byte 3
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+ 1990: 02 pushsp
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+ 1992: 00 breakpoint
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+ 1994: 05 add
+ 1995: 6c loadsp 112
+ 1996: 03 .byte 3
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+ 1999: 00 breakpoint
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+ 199d: 03 .byte 3
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+ 19a0: 02 pushsp
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+ 19a2: 00 breakpoint
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+ 1cb2: 03 .byte 3
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+ 1d1e: 1a addsp 40
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+ 1d20: 00 breakpoint
+ 1d21: 08 load
+ 1d22: 88 im 8
+ 1d23: 01 .byte 1
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+ 1d26: 00 breakpoint
+ 1d27: 06 and
+ 1d28: 02 pushsp
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+ 1d2a: 0f .byte 15
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+ 1d2e: 08 load
+ 1d2f: 7c loadsp 48
+ 1d30: 0f .byte 15
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+ 1d34: 01 .byte 1
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+ 1d3e: 00 breakpoint
+ 1d3f: 00 breakpoint
+ 1d40: 2c ashiftright
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+ 1d48: 0f .byte 15
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+ 1d70: 00 breakpoint
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+ 1d75: 20 .byte 32
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+ 1d7f: 00 breakpoint
+ 1d80: 2c ashiftright
+ 1d81: 01 .byte 1
+ 1d82: 5f storesp 60
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+ 1d86: 07 or
+ 1d87: 3e halfmult
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+ 1d8a: 02 pushsp
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+ 1d8c: 01 .byte 1
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+ 1d8e: 1e addsp 56
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+ 1d91: 05 add
+ 1d92: ce im -50
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+ 1d98: 10 addsp 0
+ 1d99: 01 .byte 1
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+ 1d9b: 1d addsp 52
+ 1d9c: 6e loadsp 120
+ 1d9d: 00 breakpoint
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+ 1da0: 00 breakpoint
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+ 1da3: 2c ashiftright
+ 1da4: 01 .byte 1
+ 1da5: 59 storesp 36
+ 1da6: 1d addsp 52
+ 1da7: 69 loadsp 100
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+ 1dad: 00 breakpoint
+ 1dae: 2c ashiftright
+ 1daf: 01 .byte 1
+ 1db0: 5c storesp 48
+ 1db1: 00 breakpoint
+ 1db2: 0f .byte 15
+ 1db3: 04 poppc
+ 1db4: 00 breakpoint
+ 1db5: 00 breakpoint
+ 1db6: 01 .byte 1
+ 1db7: d9 im -39
+ 1db8: 1f addsp 60
+ 1db9: 00 breakpoint
+ 1dba: 00 breakpoint
+ 1dbb: 05 add
+ 1dbc: 3e halfmult
+ 1dbd: 03 .byte 3
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+ 1dc0: 00 breakpoint
+ 1dc1: 00 breakpoint
+ 1dc2: 06 and
+ 1dc3: 02 pushsp
+ 1dc4: 01 .byte 1
+ 1dc5: 01 .byte 1
+ ...
+
+00001dc7 <.Ldebug_info0>:
+ 1dc7: 00 breakpoint
+ 1dc8: 00 breakpoint
+ 1dc9: 08 load
+ 1dca: dc im -36
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+ 1dcf: 06 and
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+ 1dd1: 04 poppc
+ 1dd2: 01 .byte 1
+ 1dd3: 00 breakpoint
+ 1dd4: 00 breakpoint
+ 1dd5: 0d popsp
+ 1dd6: d6 im -42
+ ...
+ 1ddf: 00 breakpoint
+ 1de0: 00 breakpoint
+ 1de1: 00 breakpoint
+ 1de2: 5e storesp 56
+ 1de3: 01 .byte 1
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+ 1de6: 08 load
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+ 1de9: 00 breakpoint
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+ 1dee: 00 breakpoint
+ 1def: 00 breakpoint
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+ 1df5: 00 breakpoint
+ 1df6: 00 breakpoint
+ 1df7: 23 storeh
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+ 1df9: 05 add
+ 1dfa: 03 .byte 3
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+ 1e05: 58 storesp 32
+ 1e06: 02 pushsp
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+ 1e0c: 46 storesp 88
+ 1e0d: 02 pushsp
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+ 1e18: 6c loadsp 112
+ 1e19: 04 poppc
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+ 1e1b: 20 .byte 32
+ 1e1c: 06 and
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+ 1e20: 1c addsp 48
+ 1e21: 01 .byte 1
+ 1e22: 1e addsp 56
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+ 1e25: 00 breakpoint
+ 1e26: 3a config
+ 1e27: 06 and
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+ 1e2a: 05 add
+ 1e2b: b6 im 54
+ 1e2c: 01 .byte 1
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+ 1e2f: 00 breakpoint
+ 1e30: 00 breakpoint
+ 1e31: 6c loadsp 112
+ 1e32: 00 breakpoint
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+ 1e37: 7c loadsp 48
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+ 1e3a: 00 breakpoint
+ 1e3b: 83 im 3
+ 1e3c: 08 load
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+ 1e3e: 00 breakpoint
+ 1e3f: 00 breakpoint
+ 1e40: 7c loadsp 48
+ 1e41: 03 .byte 3
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+ 1e47: 11 addsp 4
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+ 1e49: 07 or
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+ 1e4c: 00 breakpoint
+ 1e4d: 00 breakpoint
+ 1e4e: 9a im 26
+ 1e4f: 01 .byte 1
+ 1e50: 08 load
+ 1e51: 09 not
+ 1e52: 00 breakpoint
+ 1e53: 00 breakpoint
+ 1e54: 00 breakpoint
+ 1e55: af im 47
+ 1e56: 08 load
+ 1e57: 01 .byte 1
+ 1e58: 21 .byte 33
+ 1e59: 0a flip
+ 1e5a: 00 breakpoint
+ 1e5b: 00 breakpoint
+ 1e5c: 04 poppc
+ 1e5d: 78 loadsp 32
+ 1e5e: 01 .byte 1
+ 1e5f: 1b addsp 44
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+ 1e61: 00 breakpoint
+ 1e62: 00 breakpoint
+ 1e63: 33 loadb
+ 1e64: 02 pushsp
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+ 1e69: 00 breakpoint
+ 1e6a: 04 poppc
+ 1e6b: 3a config
+ 1e6c: 01 .byte 1
+ 1e6d: 20 .byte 32
+ 1e6e: 00 breakpoint
+ 1e6f: 00 breakpoint
+ 1e70: 00 breakpoint
+ 1e71: 4d storesp 116
+ 1e72: 02 pushsp
+ 1e73: 23 storeh
+ 1e74: 04 poppc
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+ 1e76: 0b nop
+ 1e77: 00 breakpoint
+ 1e78: 00 breakpoint
+ 1e79: 06 and
+ 1e7a: ce im -50
+ 1e7b: 01 .byte 1
+ 1e7c: 21 .byte 33
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+ 1e7f: 00 breakpoint
+ 1e80: 8a im 10
+ 1e81: 0b nop
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+ 1e83: 00 breakpoint
+ 1e84: 05 add
+ 1e85: 8c im 12
+ 1e86: 01 .byte 1
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+ 1e89: 00 breakpoint
+ 1e8a: 00 breakpoint
+ 1e8b: 33 loadb
+ 1e8c: 0c store
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+ 1e8f: 00 breakpoint
+ 1e90: 00 breakpoint
+ 1e91: 03 .byte 3
+ 1e92: fd im -3
+ 1e93: 03 .byte 3
+ 1e94: 13 addsp 12
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+ 1e96: 00 breakpoint
+ 1e97: 00 breakpoint
+ 1e98: d2 im -46
+ 1e99: 02 pushsp
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+ 1e9b: 00 breakpoint
+ 1e9c: 00 breakpoint
+ 1e9d: 11 addsp 4
+ 1e9e: 04 poppc
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+ 1ea2: 00 breakpoint
+ 1ea3: 01 .byte 1
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+ 1ea6: 00 breakpoint
+ 1ea7: 06 and
+ 1ea8: d9 im -39
+ 1ea9: 18 addsp 32
+ 1eaa: 03 .byte 3
+ 1eab: 29 mult
+ 1eac: 0a flip
+ 1ead: 00 breakpoint
+ 1eae: 00 breakpoint
+ 1eaf: 07 or
+ 1eb0: 67 loadsp 92
+ 1eb1: 03 .byte 3
+ 1eb2: 2a lshiftright
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+ 1eb5: 01 .byte 1
+ 1eb6: 38 neqbranch
+ 1eb7: 02 pushsp
+ 1eb8: 23 storeh
+ 1eb9: 00 breakpoint
+ 1eba: 0e .byte 14
+ 1ebb: 5f storesp 60
+ 1ebc: 6b loadsp 108
+ 1ebd: 00 breakpoint
+ 1ebe: 03 .byte 3
+ 1ebf: 2b ashiftleft
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+ 1ec1: 00 breakpoint
+ 1ec2: 00 breakpoint
+ 1ec3: 33 loadb
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+ 1ec9: 00 breakpoint
+ 1eca: 06 and
+ 1ecb: e1 im -31
+ 1ecc: 03 .byte 3
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+ 1ece: 00 breakpoint
+ 1ecf: 00 breakpoint
+ 1ed0: 00 breakpoint
+ 1ed1: 33 loadb
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+ 1ed6: 00 breakpoint
+ 1ed7: 00 breakpoint
+ 1ed8: 07 or
+ 1ed9: 5c storesp 48
+ 1eda: 03 .byte 3
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+ 1edd: 00 breakpoint
+ 1ede: 00 breakpoint
+ 1edf: 33 loadb
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+ 1ee2: 0c store
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+ 1ee5: 00 breakpoint
+ 1ee6: 06 and
+ 1ee7: 41 storesp 68
+ 1ee8: 03 .byte 3
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+ 1eeb: 00 breakpoint
+ 1eec: 00 breakpoint
+ 1eed: 33 loadb
+ 1eee: 02 pushsp
+ 1eef: 23 storeh
+ 1ef0: 10 addsp 0
+ 1ef1: 0e .byte 14
+ 1ef2: 5f storesp 60
+ 1ef3: 78 loadsp 32
+ 1ef4: 00 breakpoint
+ 1ef5: 03 .byte 3
+ 1ef6: 2c ashiftright
+ 1ef7: 00 breakpoint
+ 1ef8: 00 breakpoint
+ 1ef9: 01 .byte 1
+ 1efa: 3e halfmult
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+ 1efd: 14 addsp 16
+ 1efe: 00 breakpoint
+ 1eff: 0f .byte 15
+ 1f00: 04 poppc
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+ 1f02: 00 breakpoint
+ 1f03: 00 breakpoint
+ 1f04: d9 im -39
+ 1f05: 07 or
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+ 1f07: 00 breakpoint
+ 1f08: 01 .byte 1
+ 1f09: 4e storesp 120
+ 1f0a: 00 breakpoint
+ 1f0b: 00 breakpoint
+ 1f0c: 00 breakpoint
+ 1f0d: c7 im -57
+ 1f0e: 08 load
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+ 1f11: 00 breakpoint
+ 1f12: 7c loadsp 48
+ 1f13: 00 breakpoint
+ 1f14: 00 breakpoint
+ 1f15: 0d popsp
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+ 1f17: 00 breakpoint
+ 1f18: 01 .byte 1
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+ 1f1c: 06 and
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+ 1f1e: 24 lessthan
+ 1f1f: 03 .byte 3
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+ 1f21: 0a flip
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+ 1f23: 00 breakpoint
+ 1f24: 05 add
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+ 1f26: 03 .byte 3
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+ 1f29: 00 breakpoint
+ 1f2a: 00 breakpoint
+ 1f2b: 33 loadb
+ 1f2c: 02 pushsp
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+ 1f2e: 00 breakpoint
+ 1f2f: 0a flip
+ 1f30: 00 breakpoint
+ 1f31: 00 breakpoint
+ 1f32: 05 add
+ 1f33: 01 .byte 1
+ 1f34: 03 .byte 3
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+ 1f36: 00 breakpoint
+ 1f37: 00 breakpoint
+ 1f38: 00 breakpoint
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+ 1f3a: 02 pushsp
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+ 1f3f: 00 breakpoint
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+ 1f41: a6 im 38
+ 1f42: 03 .byte 3
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+ 1f46: 00 breakpoint
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+ 1f4e: 06 and
+ 1f4f: 64 loadsp 80
+ 1f50: 03 .byte 3
+ 1f51: 35 div
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+ 1f53: 00 breakpoint
+ 1f54: 00 breakpoint
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+ 1f5b: 00 breakpoint
+ 1f5c: 07 or
+ 1f5d: 36 mod
+ 1f5e: 03 .byte 3
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+ 1f62: 00 breakpoint
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+ 1f6a: 06 and
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+ 1f6c: 03 .byte 3
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+ 1f77: 00 breakpoint
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+ 1f7a: 03 .byte 3
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+ 1f7e: 00 breakpoint
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+ 1f85: 00 breakpoint
+ 1f86: 07 or
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+ 1f88: 03 .byte 3
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+ 1f8c: 00 breakpoint
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+ 1f92: 00 breakpoint
+ 1f93: 00 breakpoint
+ 1f94: 05 add
+ 1f95: 61 loadsp 68
+ 1f96: 03 .byte 3
+ 1f97: 3a config
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+ 1f99: 00 breakpoint
+ 1f9a: 00 breakpoint
+ 1f9b: 33 loadb
+ 1f9c: 02 pushsp
+ 1f9d: 23 storeh
+ 1f9e: 20 .byte 32
+ 1f9f: 00 breakpoint
+ 1fa0: 0d popsp
+ 1fa1: 00 breakpoint
+ 1fa2: 00 breakpoint
+ 1fa3: 02 pushsp
+ 1fa4: 03 .byte 3
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+ 1fa6: 00 breakpoint
+ 1fa7: 05 add
+ 1fa8: c5 im -59
+ 1fa9: 84 im 4
+ 1faa: 03 .byte 3
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+ 1fac: 0a flip
+ 1fad: 00 breakpoint
+ 1fae: 00 breakpoint
+ 1faf: 05 add
+ 1fb0: 36 mod
+ 1fb1: 03 .byte 3
+ 1fb2: 44 storesp 80
+ 1fb3: 00 breakpoint
+ 1fb4: 00 breakpoint
+ 1fb5: 02 pushsp
+ 1fb6: 03 .byte 3
+ 1fb7: 02 pushsp
+ 1fb8: 23 storeh
+ 1fb9: 00 breakpoint
+ 1fba: 0a flip
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+ 2663: 00 breakpoint
+ 2664: 00 breakpoint
+ 2665: 33 loadb
+ 2666: 00 breakpoint
+ 2667: 0f .byte 15
+ 2668: 04 poppc
+ 2669: 00 breakpoint
+ 266a: 00 breakpoint
+ 266b: 08 load
+ 266c: a6 im 38
+ 266d: 0f .byte 15
+ 266e: 04 poppc
+ 266f: 00 breakpoint
+ 2670: 00 breakpoint
+ 2671: 08 load
+ 2672: 94 im 20
+ 2673: 07 or
+ 2674: 00 breakpoint
+ 2675: 00 breakpoint
+ 2676: 08 load
+ 2677: bc im 60
+ 2678: 00 breakpoint
+ 2679: 00 breakpoint
+ 267a: 06 and
+ 267b: 08 load
+ 267c: 08 load
+ 267d: 00 breakpoint
+ 267e: 00 breakpoint
+ 267f: 00 breakpoint
+ 2680: 7c loadsp 48
+ 2681: 02 pushsp
+ 2682: 00 breakpoint
+ 2683: 1b addsp 44
+ 2684: 00 breakpoint
+ 2685: 00 breakpoint
+ 2686: 05 add
+ 2687: 3e halfmult
+ 2688: 05 add
+ 2689: 0d popsp
+ 268a: 00 breakpoint
+ 268b: 00 breakpoint
+ 268c: 06 and
+ 268d: 02 pushsp
+ 268e: 01 .byte 1
+ 268f: 05 add
+ 2690: 03 .byte 3
+ 2691: 00 breakpoint
+ 2692: 00 breakpoint
+ 2693: 08 load
+ 2694: 8c im 12
+ 2695: 1c addsp 48
+ 2696: 00 breakpoint
+ 2697: 00 breakpoint
+ 2698: 08 load
+ 2699: 33 loadb
+ 269a: 05 add
+ 269b: 0c store
+ 269c: 00 breakpoint
+ 269d: 00 breakpoint
+ 269e: 03 .byte 3
+ 269f: d3 im -45
+ 26a0: 05 add
+ 26a1: 03 .byte 3
+ 26a2: 00 breakpoint
+ 26a3: 00 breakpoint
+ 26a4: 08 load
+ 26a5: 90 im 16
+ ...
+
+000026a7 <.Ldebug_info0>:
+ 26a7: 00 breakpoint
+ 26a8: 00 breakpoint
+ 26a9: 01 .byte 1
+ 26aa: 00 breakpoint
+ 26ab: 00 breakpoint
+ 26ac: 02 pushsp
+ 26ad: 00 breakpoint
+ 26ae: 00 breakpoint
+ 26af: 08 load
+ 26b0: 2f neq
+ 26b1: 04 poppc
+ 26b2: 01 .byte 1
+ 26b3: 00 breakpoint
+ 26b4: 00 breakpoint
+ 26b5: 0f .byte 15
+ 26b6: 27 ulessthanorequal
+ ...
+ 26bf: 00 breakpoint
+ 26c0: 00 breakpoint
+ 26c1: 00 breakpoint
+ 26c2: 5e storesp 56
+ 26c3: 01 .byte 1
+ 26c4: 00 breakpoint
+ 26c5: 00 breakpoint
+ 26c6: 08 load
+ 26c7: be im 62
+ 26c8: 00 breakpoint
+ 26c9: 00 breakpoint
+ 26ca: 01 .byte 1
+ 26cb: 95 im 21
+ 26cc: 02 pushsp
+ 26cd: 00 breakpoint
+ 26ce: 00 breakpoint
+ 26cf: 00 breakpoint
+ 26d0: 28 swap
+ 26d1: 04 poppc
+ 26d2: 05 add
+ 26d3: 02 pushsp
+ 26d4: 00 breakpoint
+ 26d5: 00 breakpoint
+ 26d6: 00 breakpoint
+ 26d7: 23 storeh
+ 26d8: 08 load
+ 26d9: 05 add
+ 26da: 03 .byte 3
+ 26db: 69 loadsp 100
+ 26dc: 6e loadsp 120
+ 26dd: 74 loadsp 16
+ 26de: 00 breakpoint
+ 26df: 04 poppc
+ 26e0: 05 add
+ 26e1: 02 pushsp
+ 26e2: 00 breakpoint
+ 26e3: 00 breakpoint
+ 26e4: 00 breakpoint
+ 26e5: 16 addsp 24
+ 26e6: 04 poppc
+ 26e7: 07 or
+ 26e8: 02 pushsp
+ 26e9: 00 breakpoint
+ 26ea: 00 breakpoint
+ 26eb: 00 breakpoint
+ 26ec: 11 addsp 4
+ 26ed: 04 poppc
+ 26ee: 07 or
+ 26ef: 02 pushsp
+ 26f0: 00 breakpoint
+ 26f1: 00 breakpoint
+ 26f2: 00 breakpoint
+ 26f3: 9a im 26
+ 26f4: 01 .byte 1
+ 26f5: 08 load
+ 26f6: 04 poppc
+ 26f7: 04 poppc
+ 26f8: 02 pushsp
+ 26f9: 00 breakpoint
+ 26fa: 00 breakpoint
+ 26fb: 00 breakpoint
+ 26fc: 11 addsp 4
+ 26fd: 04 poppc
+ 26fe: 07 or
+ 26ff: 02 pushsp
+ 2700: 00 breakpoint
+ 2701: 00 breakpoint
+ 2702: 00 breakpoint
+ 2703: a8 im 40
+ 2704: 02 pushsp
+ 2705: 05 add
+ 2706: 05 add
+ 2707: 04 poppc
+ 2708: 00 breakpoint
+ 2709: 00 breakpoint
+ 270a: 00 breakpoint
+ 270b: 65 loadsp 84
+ 270c: 02 pushsp
+ 270d: 00 breakpoint
+ 270e: 00 breakpoint
+ 270f: 00 breakpoint
+ 2710: a3 im 35
+ 2711: 01 .byte 1
+ 2712: 08 load
+ 2713: 02 pushsp
+ 2714: 00 breakpoint
+ 2715: 00 breakpoint
+ 2716: 00 breakpoint
+ 2717: 4b storesp 108
+ 2718: 02 pushsp
+ 2719: 07 or
+ 271a: 02 pushsp
+ 271b: 00 breakpoint
+ 271c: 00 breakpoint
+ 271d: 00 breakpoint
+ 271e: 0c store
+ 271f: 08 load
+ 2720: 07 or
+ 2721: 06 and
+ 2722: 00 breakpoint
+ 2723: 00 breakpoint
+ 2724: 01 .byte 1
+ 2725: 8e im 14
+ 2726: 02 pushsp
+ 2727: d5 im -43
+ 2728: 00 breakpoint
+ 2729: 00 breakpoint
+ 272a: 00 breakpoint
+ 272b: 51 storesp 4
+ 272c: 07 or
+ 272d: 00 breakpoint
+ 272e: 00 breakpoint
+ 272f: 00 breakpoint
+ 2730: fd im -3
+ 2731: 01 .byte 1
+ 2732: 00 breakpoint
+ 2733: 00 breakpoint
+ 2734: 03 .byte 3
+ 2735: 9b im 27
+ 2736: 04 poppc
+ 2737: 2f neq
+ 2738: 01 .byte 1
+ 2739: 00 breakpoint
+ 273a: 00 breakpoint
+ 273b: 00 breakpoint
+ 273c: 4f storesp 124
+ ...
+ 2745: 02 pushsp
+ 2746: 90 im 16
+ 2747: 20 .byte 32
+ 2748: 08 load
+ 2749: 6d loadsp 116
+ 274a: 00 breakpoint
+ 274b: 04 poppc
+ 274c: 2b ashiftleft
+ 274d: 00 breakpoint
+ 274e: 00 breakpoint
+ 274f: 00 breakpoint
+ 2750: 4f storesp 124
+ 2751: 01 .byte 1
+ 2752: 5c storesp 48
+ 2753: 08 load
+ 2754: 63 loadsp 76
+ 2755: 00 breakpoint
+ 2756: 04 poppc
+ 2757: 2b ashiftleft
+ 2758: 00 breakpoint
+ 2759: 00 breakpoint
+ 275a: 00 breakpoint
+ 275b: 33 loadb
+ 275c: 02 pushsp
+ 275d: 91 im 17
+ 275e: 1c addsp 48
+ 275f: 08 load
+ 2760: 6e loadsp 120
+ 2761: 00 breakpoint
+ 2762: 04 poppc
+ 2763: 2b ashiftleft
+ 2764: 00 breakpoint
+ 2765: 00 breakpoint
+ 2766: 00 breakpoint
+ 2767: 7a loadsp 40
+ 2768: 01 .byte 1
+ 2769: 59 storesp 36
+ 276a: 09 not
+ 276b: 73 loadsp 12
+ 276c: 00 breakpoint
+ 276d: 04 poppc
+ 276e: 3a config
+ 276f: 00 breakpoint
+ 2770: 00 breakpoint
+ 2771: 00 breakpoint
+ 2772: 5f storesp 60
+ 2773: 01 .byte 1
+ 2774: 5a storesp 40
+ 2775: 0a flip
+ 2776: 69 loadsp 100
+ 2777: 00 breakpoint
+ 2778: 04 poppc
+ 2779: 3b pushpc
+ 277a: 00 breakpoint
+ 277b: 00 breakpoint
+ 277c: 00 breakpoint
+ 277d: 33 loadb
+ 277e: 0b nop
+ 277f: 00 breakpoint
+ 2780: 00 breakpoint
+ 2781: 08 load
+ 2782: ed im -19
+ 2783: 04 poppc
+ 2784: 3c syscall
+ 2785: 00 breakpoint
+ 2786: 00 breakpoint
+ 2787: 00 breakpoint
+ 2788: 51 storesp 4
+ 2789: 01 .byte 1
+ 278a: 5a storesp 40
+ 278b: 0b nop
+ 278c: 00 breakpoint
+ 278d: 00 breakpoint
+ 278e: 08 load
+ 278f: b1 im 49
+ 2790: 04 poppc
+ 2791: 3d pushspadd
+ 2792: 00 breakpoint
+ 2793: 00 breakpoint
+ 2794: 00 breakpoint
+ 2795: fd im -3
+ 2796: 01 .byte 1
+ 2797: 58 storesp 32
+ 2798: 09 not
+ 2799: 64 loadsp 80
+ 279a: 00 breakpoint
+ 279b: 04 poppc
+ 279c: 3e halfmult
+ 279d: 00 breakpoint
+ 279e: 00 breakpoint
+ 279f: 00 breakpoint
+ 27a0: 3a config
+ 27a1: 01 .byte 1
+ 27a2: 5b storesp 44
+ 27a3: 00 breakpoint
+ 27a4: 05 add
+ 27a5: 04 poppc
+ 27a6: 00 breakpoint
+ 27a7: 00 breakpoint
+ 27a8: 00 breakpoint
+ 27a9: 51 storesp 4
+ ...
+
+000027ab <.Ldebug_info0>:
+ 27ab: 00 breakpoint
+ 27ac: 00 breakpoint
+ 27ad: 00 breakpoint
+ 27ae: cf im -49
+ 27af: 00 breakpoint
+ 27b0: 02 pushsp
+ 27b1: 00 breakpoint
+ 27b2: 00 breakpoint
+ 27b3: 08 load
+ 27b4: c9 im -55
+ 27b5: 04 poppc
+ 27b6: 01 .byte 1
+ 27b7: 00 breakpoint
+ 27b8: 00 breakpoint
+ 27b9: 10 addsp 0
+ 27ba: c9 im -55
+ ...
+ 27c3: 00 breakpoint
+ 27c4: 00 breakpoint
+ 27c5: 00 breakpoint
+ 27c6: 5e storesp 56
+ 27c7: 01 .byte 1
+ 27c8: 00 breakpoint
+ 27c9: 00 breakpoint
+ 27ca: 08 load
+ 27cb: f4 im -12
+ 27cc: 00 breakpoint
+ 27cd: 00 breakpoint
+ 27ce: 01 .byte 1
+ 27cf: 95 im 21
+ 27d0: 02 pushsp
+ 27d1: 00 breakpoint
+ 27d2: 00 breakpoint
+ 27d3: 00 breakpoint
+ 27d4: 28 swap
+ 27d5: 04 poppc
+ 27d6: 05 add
+ 27d7: 02 pushsp
+ 27d8: 00 breakpoint
+ 27d9: 00 breakpoint
+ 27da: 00 breakpoint
+ 27db: 23 storeh
+ 27dc: 08 load
+ 27dd: 05 add
+ 27de: 03 .byte 3
+ 27df: 69 loadsp 100
+ 27e0: 6e loadsp 120
+ 27e1: 74 loadsp 16
+ 27e2: 00 breakpoint
+ 27e3: 04 poppc
+ 27e4: 05 add
+ 27e5: 02 pushsp
+ 27e6: 00 breakpoint
+ 27e7: 00 breakpoint
+ 27e8: 00 breakpoint
+ 27e9: 16 addsp 24
+ 27ea: 04 poppc
+ 27eb: 07 or
+ 27ec: 02 pushsp
+ 27ed: 00 breakpoint
+ 27ee: 00 breakpoint
+ 27ef: 00 breakpoint
+ 27f0: 11 addsp 4
+ 27f1: 04 poppc
+ 27f2: 07 or
+ 27f3: 02 pushsp
+ 27f4: 00 breakpoint
+ 27f5: 00 breakpoint
+ 27f6: 00 breakpoint
+ 27f7: 9a im 26
+ 27f8: 01 .byte 1
+ 27f9: 08 load
+ 27fa: 02 pushsp
+ 27fb: 00 breakpoint
+ 27fc: 00 breakpoint
+ 27fd: 00 breakpoint
+ 27fe: 11 addsp 4
+ 27ff: 04 poppc
+ 2800: 07 or
+ 2801: 02 pushsp
+ 2802: 00 breakpoint
+ 2803: 00 breakpoint
+ 2804: 00 breakpoint
+ 2805: a8 im 40
+ 2806: 02 pushsp
+ 2807: 05 add
+ 2808: 02 pushsp
+ 2809: 00 breakpoint
+ 280a: 00 breakpoint
+ 280b: 00 breakpoint
+ 280c: a3 im 35
+ 280d: 01 .byte 1
+ 280e: 08 load
+ 280f: 04 poppc
+ 2810: 04 poppc
+ 2811: 00 breakpoint
+ 2812: 00 breakpoint
+ 2813: 00 breakpoint
+ 2814: 6a loadsp 104
+ 2815: 05 add
+ 2816: 00 breakpoint
+ 2817: 00 breakpoint
+ 2818: 00 breakpoint
+ 2819: 5d storesp 52
+ 281a: 02 pushsp
+ 281b: 00 breakpoint
+ 281c: 00 breakpoint
+ 281d: 00 breakpoint
+ 281e: 4b storesp 108
+ 281f: 02 pushsp
+ 2820: 07 or
+ 2821: 02 pushsp
+ 2822: 00 breakpoint
+ 2823: 00 breakpoint
+ 2824: 00 breakpoint
+ 2825: 0c store
+ 2826: 08 load
+ 2827: 07 or
+ 2828: 06 and
+ 2829: 00 breakpoint
+ 282a: 00 breakpoint
+ 282b: 01 .byte 1
+ 282c: 8e im 14
+ 282d: 02 pushsp
+ 282e: d5 im -43
+ 282f: 00 breakpoint
+ 2830: 00 breakpoint
+ 2831: 00 breakpoint
+ 2832: 4f storesp 124
+ 2833: 07 or
+ 2834: 00 breakpoint
+ 2835: 00 breakpoint
+ 2836: 00 breakpoint
+ 2837: cc im -52
+ 2838: 01 .byte 1
+ 2839: 00 breakpoint
+ 283a: 00 breakpoint
+ 283b: 02 pushsp
+ 283c: ca im -54
+ 283d: 04 poppc
+ 283e: 3b pushpc
+ 283f: 01 .byte 1
+ 2840: 00 breakpoint
+ 2841: 00 breakpoint
+ 2842: 00 breakpoint
+ 2843: 7d loadsp 52
+ ...
+ 284c: 02 pushsp
+ 284d: 90 im 16
+ 284e: 20 .byte 32
+ 284f: 08 load
+ 2850: 73 loadsp 12
+ 2851: 74 loadsp 16
+ 2852: 72 loadsp 8
+ 2853: 00 breakpoint
+ 2854: 04 poppc
+ 2855: 39 poppcrel
+ 2856: 00 breakpoint
+ 2857: 00 breakpoint
+ 2858: 00 breakpoint
+ 2859: 64 loadsp 80
+ 285a: 01 .byte 1
+ 285b: 59 storesp 36
+ 285c: 09 not
+ 285d: 00 breakpoint
+ 285e: 00 breakpoint
+ 285f: 09 not
+ 2860: 23 storeh
+ 2861: 04 poppc
+ 2862: 44 storesp 80
+ 2863: 00 breakpoint
+ 2864: 00 breakpoint
+ 2865: 00 breakpoint
+ 2866: 64 loadsp 80
+ 2867: 01 .byte 1
+ 2868: 5b storesp 44
+ 2869: 09 not
+ 286a: 00 breakpoint
+ 286b: 00 breakpoint
+ 286c: 08 load
+ 286d: b1 im 49
+ 286e: 04 poppc
+ 286f: 45 storesp 84
+ 2870: 00 breakpoint
+ 2871: 00 breakpoint
+ 2872: 00 breakpoint
+ 2873: cc im -52
+ 2874: 01 .byte 1
+ 2875: 5a storesp 40
+ 2876: 00 breakpoint
+ 2877: 04 poppc
+ 2878: 04 poppc
+ 2879: 00 breakpoint
+ 287a: 00 breakpoint
+ 287b: 00 breakpoint
+ 287c: 4f storesp 124
+ ...
+Disassembly of section .debug_abbrev:
+
+00000000 <.Ldebug_abbrev0>:
+ 0: 01 .byte 1
+ 1: 11 addsp 4
+ 2: 01 .byte 1
+ 3: 10 addsp 0
+ 4: 06 and
+ 5: 25 lessthanorequal
+ 6: 0e .byte 14
+ 7: 13 addsp 12
+ 8: 0b nop
+ 9: 03 .byte 3
+ a: 0e .byte 14
+ b: 1b addsp 44
+ c: 0e .byte 14
+ d: 00 breakpoint
+ e: 00 breakpoint
+ f: 02 pushsp
+ 10: 24 lessthan
+ 11: 00 breakpoint
+ 12: 03 .byte 3
+ 13: 0e .byte 14
+ 14: 0b nop
+ 15: 0b nop
+ 16: 3e halfmult
+ 17: 0b nop
+ 18: 00 breakpoint
+ 19: 00 breakpoint
+ 1a: 03 .byte 3
+ 1b: 24 lessthan
+ 1c: 00 breakpoint
+ 1d: 03 .byte 3
+ 1e: 08 load
+ 1f: 0b nop
+ 20: 0b nop
+ 21: 3e halfmult
+ 22: 0b nop
+ 23: 00 breakpoint
+ 24: 00 breakpoint
+ 25: 04 poppc
+ 26: 2e eq
+ 27: 01 .byte 1
+ 28: 01 .byte 1
+ 29: 13 addsp 12
+ 2a: 3f callpcrel
+ 2b: 0c store
+ 2c: 03 .byte 3
+ 2d: 0e .byte 14
+ 2e: 3a config
+ 2f: 0b nop
+ 30: 3b pushpc
+ 31: 0b nop
+ 32: 49 storesp 100
+ 33: 13 addsp 12
+ 34: 11 addsp 4
+ 35: 01 .byte 1
+ 36: 12 addsp 8
+ 37: 01 .byte 1
+ 38: 40 storesp 64
+ 39: 0a flip
+ 3a: 00 breakpoint
+ 3b: 00 breakpoint
+ 3c: 05 add
+ 3d: 34 storeb
+ 3e: 00 breakpoint
+ 3f: 03 .byte 3
+ 40: 08 load
+ 41: 3a config
+ 42: 0b nop
+ 43: 3b pushpc
+ 44: 0b nop
+ 45: 49 storesp 100
+ 46: 13 addsp 12
+ 47: 02 pushsp
+ 48: 0a flip
+ 49: 00 breakpoint
+ 4a: 00 breakpoint
+ 4b: 06 and
+ 4c: 2e eq
+ 4d: 01 .byte 1
+ 4e: 01 .byte 1
+ 4f: 13 addsp 12
+ 50: 3f callpcrel
+ 51: 0c store
+ 52: 03 .byte 3
+ 53: 0e .byte 14
+ 54: 3a config
+ 55: 0b nop
+ 56: 3b pushpc
+ 57: 0b nop
+ 58: 27 ulessthanorequal
+ 59: 0c store
+ 5a: 11 addsp 4
+ 5b: 01 .byte 1
+ 5c: 12 addsp 8
+ 5d: 01 .byte 1
+ 5e: 40 storesp 64
+ 5f: 0a flip
+ 60: 00 breakpoint
+ 61: 00 breakpoint
+ 62: 07 or
+ 63: 05 add
+ 64: 00 breakpoint
+ 65: 03 .byte 3
+ 66: 08 load
+ 67: 3a config
+ 68: 0b nop
+ 69: 3b pushpc
+ 6a: 0b nop
+ 6b: 49 storesp 100
+ 6c: 13 addsp 12
+ 6d: 02 pushsp
+ 6e: 0a flip
+ 6f: 00 breakpoint
+ 70: 00 breakpoint
+ 71: 08 load
+ 72: 2e eq
+ 73: 00 breakpoint
+ 74: 3f callpcrel
+ 75: 0c store
+ 76: 03 .byte 3
+ 77: 0e .byte 14
+ 78: 3a config
+ 79: 0b nop
+ 7a: 3b pushpc
+ 7b: 0b nop
+ 7c: 27 ulessthanorequal
+ 7d: 0c store
+ 7e: 11 addsp 4
+ 7f: 01 .byte 1
+ 80: 12 addsp 8
+ 81: 01 .byte 1
+ 82: 40 storesp 64
+ 83: 0a flip
+ 84: 00 breakpoint
+ 85: 00 breakpoint
+ 86: 09 not
+ 87: 34 storeb
+ 88: 00 breakpoint
+ 89: 03 .byte 3
+ 8a: 0e .byte 14
+ 8b: 3a config
+ 8c: 0b nop
+ 8d: 3b pushpc
+ 8e: 0b nop
+ 8f: 49 storesp 100
+ 90: 13 addsp 12
+ 91: 02 pushsp
+ 92: 0a flip
+ 93: 00 breakpoint
+ 94: 00 breakpoint
+ 95: 0a flip
+ 96: 34 storeb
+ 97: 00 breakpoint
+ 98: 03 .byte 3
+ 99: 0e .byte 14
+ 9a: 3a config
+ 9b: 0b nop
+ 9c: 3b pushpc
+ 9d: 0b nop
+ 9e: 49 storesp 100
+ 9f: 13 addsp 12
+ a0: 3f callpcrel
+ a1: 0c store
+ a2: 3c syscall
+ a3: 0c store
+ a4: 00 breakpoint
+ a5: 00 breakpoint
+ a6: 0b nop
+ a7: 0f .byte 15
+ a8: 00 breakpoint
+ a9: 0b nop
+ aa: 0b nop
+ ab: 49 storesp 100
+ ac: 13 addsp 12
+ ad: 00 breakpoint
+ ae: 00 breakpoint
+ af: 0c store
+ b0: 35 div
+ b1: 00 breakpoint
+ b2: 49 storesp 100
+ b3: 13 addsp 12
+ b4: 00 breakpoint
+ b5: 00 breakpoint
+ b6: 0d popsp
+ b7: 34 storeb
+ b8: 00 breakpoint
+ b9: 03 .byte 3
+ ba: 08 load
+ bb: 3a config
+ bc: 0b nop
+ bd: 3b pushpc
+ be: 0b nop
+ bf: 49 storesp 100
+ c0: 13 addsp 12
+ c1: 3f callpcrel
+ c2: 0c store
+ c3: 02 pushsp
+ c4: 0a flip
+ c5: 00 breakpoint
+ c6: 00 breakpoint
+ c7: 0e .byte 14
+ c8: 26 ulessthan
+ c9: 00 breakpoint
+ ca: 49 storesp 100
+ cb: 13 addsp 12
+ cc: 00 breakpoint
+ ...
+
+000000cf <.Ldebug_abbrev0>:
+ cf: 01 .byte 1
+ d0: 11 addsp 4
+ d1: 01 .byte 1
+ d2: 10 addsp 0
+ d3: 06 and
+ d4: 12 addsp 8
+ d5: 01 .byte 1
+ d6: 11 addsp 4
+ d7: 01 .byte 1
+ d8: 25 lessthanorequal
+ d9: 0e .byte 14
+ da: 13 addsp 12
+ db: 0b nop
+ dc: 03 .byte 3
+ dd: 0e .byte 14
+ de: 00 breakpoint
+ df: 00 breakpoint
+ e0: 02 pushsp
+ e1: 2e eq
+ e2: 01 .byte 1
+ e3: 01 .byte 1
+ e4: 13 addsp 12
+ e5: 3f callpcrel
+ e6: 0c store
+ e7: 03 .byte 3
+ e8: 0e .byte 14
+ e9: 3a config
+ ea: 0b nop
+ eb: 3b pushpc
+ ec: 0b nop
+ ed: 49 storesp 100
+ ee: 13 addsp 12
+ ef: 11 addsp 4
+ f0: 01 .byte 1
+ f1: 12 addsp 8
+ f2: 01 .byte 1
+ f3: 40 storesp 64
+ f4: 0a flip
+ f5: 00 breakpoint
+ f6: 00 breakpoint
+ f7: 03 .byte 3
+ f8: 34 storeb
+ f9: 00 breakpoint
+ fa: 03 .byte 3
+ fb: 0e .byte 14
+ fc: 3a config
+ fd: 0b nop
+ fe: 3b pushpc
+ ff: 0b nop
+ 100: 49 storesp 100
+ 101: 13 addsp 12
+ 102: 02 pushsp
+ 103: 0a flip
+ 104: 00 breakpoint
+ 105: 00 breakpoint
+ 106: 04 poppc
+ 107: 34 storeb
+ 108: 00 breakpoint
+ 109: 03 .byte 3
+ 10a: 08 load
+ 10b: 3a config
+ 10c: 0b nop
+ 10d: 3b pushpc
+ 10e: 0b nop
+ 10f: 49 storesp 100
+ 110: 13 addsp 12
+ 111: 02 pushsp
+ 112: 0a flip
+ 113: 00 breakpoint
+ 114: 00 breakpoint
+ 115: 05 add
+ 116: 24 lessthan
+ 117: 00 breakpoint
+ 118: 03 .byte 3
+ 119: 08 load
+ 11a: 0b nop
+ 11b: 0b nop
+ 11c: 3e halfmult
+ 11d: 0b nop
+ 11e: 00 breakpoint
+ ...
+
+00000121 <.Ldebug_abbrev0>:
+ 121: 01 .byte 1
+ 122: 11 addsp 4
+ 123: 01 .byte 1
+ 124: 10 addsp 0
+ 125: 06 and
+ 126: 12 addsp 8
+ 127: 01 .byte 1
+ 128: 11 addsp 4
+ 129: 01 .byte 1
+ 12a: 25 lessthanorequal
+ 12b: 0e .byte 14
+ 12c: 13 addsp 12
+ 12d: 0b nop
+ 12e: 03 .byte 3
+ 12f: 0e .byte 14
+ 130: 1b addsp 44
+ 131: 0e .byte 14
+ 132: 00 breakpoint
+ 133: 00 breakpoint
+ 134: 02 pushsp
+ 135: 24 lessthan
+ 136: 00 breakpoint
+ 137: 03 .byte 3
+ 138: 0e .byte 14
+ 139: 0b nop
+ 13a: 0b nop
+ 13b: 3e halfmult
+ 13c: 0b nop
+ 13d: 00 breakpoint
+ 13e: 00 breakpoint
+ 13f: 03 .byte 3
+ 140: 16 addsp 24
+ 141: 00 breakpoint
+ 142: 03 .byte 3
+ 143: 0e .byte 14
+ 144: 3a config
+ 145: 0b nop
+ 146: 3b pushpc
+ 147: 0b nop
+ 148: 49 storesp 100
+ 149: 13 addsp 12
+ 14a: 00 breakpoint
+ 14b: 00 breakpoint
+ 14c: 04 poppc
+ 14d: 24 lessthan
+ 14e: 00 breakpoint
+ 14f: 03 .byte 3
+ 150: 08 load
+ 151: 0b nop
+ 152: 0b nop
+ 153: 3e halfmult
+ 154: 0b nop
+ 155: 00 breakpoint
+ 156: 00 breakpoint
+ 157: 05 add
+ 158: 2e eq
+ 159: 01 .byte 1
+ 15a: 01 .byte 1
+ 15b: 13 addsp 12
+ 15c: 3f callpcrel
+ 15d: 0c store
+ 15e: 03 .byte 3
+ 15f: 0e .byte 14
+ 160: 3a config
+ 161: 0b nop
+ 162: 3b pushpc
+ 163: 0b nop
+ 164: 27 ulessthanorequal
+ 165: 0c store
+ 166: 49 storesp 100
+ 167: 13 addsp 12
+ 168: 11 addsp 4
+ 169: 01 .byte 1
+ 16a: 12 addsp 8
+ 16b: 01 .byte 1
+ 16c: 40 storesp 64
+ 16d: 0a flip
+ 16e: 00 breakpoint
+ 16f: 00 breakpoint
+ 170: 06 and
+ 171: 05 add
+ 172: 00 breakpoint
+ 173: 03 .byte 3
+ 174: 0e .byte 14
+ 175: 3a config
+ 176: 0b nop
+ 177: 3b pushpc
+ 178: 0b nop
+ 179: 49 storesp 100
+ 17a: 13 addsp 12
+ 17b: 02 pushsp
+ 17c: 0a flip
+ 17d: 00 breakpoint
+ 17e: 00 breakpoint
+ 17f: 07 or
+ 180: 34 storeb
+ 181: 00 breakpoint
+ 182: 03 .byte 3
+ 183: 08 load
+ 184: 3a config
+ 185: 0b nop
+ 186: 3b pushpc
+ 187: 0b nop
+ 188: 49 storesp 100
+ 189: 13 addsp 12
+ 18a: 02 pushsp
+ 18b: 0a flip
+ 18c: 00 breakpoint
+ 18d: 00 breakpoint
+ 18e: 08 load
+ 18f: 34 storeb
+ 190: 00 breakpoint
+ 191: 03 .byte 3
+ 192: 0e .byte 14
+ 193: 3a config
+ 194: 0b nop
+ 195: 3b pushpc
+ 196: 0b nop
+ 197: 49 storesp 100
+ 198: 13 addsp 12
+ 199: 02 pushsp
+ 19a: 0a flip
+ 19b: 00 breakpoint
+ 19c: 00 breakpoint
+ 19d: 09 not
+ 19e: 0f .byte 15
+ 19f: 00 breakpoint
+ 1a0: 0b nop
+ 1a1: 0b nop
+ 1a2: 00 breakpoint
+ 1a3: 00 breakpoint
+ 1a4: 0a flip
+ 1a5: 0f .byte 15
+ 1a6: 00 breakpoint
+ 1a7: 0b nop
+ 1a8: 0b nop
+ 1a9: 49 storesp 100
+ 1aa: 13 addsp 12
+ 1ab: 00 breakpoint
+ 1ac: 00 breakpoint
+ 1ad: 0b nop
+ 1ae: 26 ulessthan
+ 1af: 00 breakpoint
+ 1b0: 00 breakpoint
+ 1b1: 00 breakpoint
+ 1b2: 0c store
+ 1b3: 26 ulessthan
+ 1b4: 00 breakpoint
+ 1b5: 49 storesp 100
+ 1b6: 13 addsp 12
+ 1b7: 00 breakpoint
+ ...
+
+000001ba <.Ldebug_abbrev0>:
+ 1ba: 01 .byte 1
+ 1bb: 11 addsp 4
+ 1bc: 01 .byte 1
+ 1bd: 10 addsp 0
+ 1be: 06 and
+ 1bf: 52 storesp 8
+ 1c0: 01 .byte 1
+ 1c1: 25 lessthanorequal
+ 1c2: 0e .byte 14
+ 1c3: 13 addsp 12
+ 1c4: 0b nop
+ 1c5: 03 .byte 3
+ 1c6: 0e .byte 14
+ 1c7: 1b addsp 44
+ 1c8: 0e .byte 14
+ 1c9: 00 breakpoint
+ 1ca: 00 breakpoint
+ 1cb: 02 pushsp
+ 1cc: 24 lessthan
+ 1cd: 00 breakpoint
+ 1ce: 03 .byte 3
+ 1cf: 0e .byte 14
+ 1d0: 0b nop
+ 1d1: 0b nop
+ 1d2: 3e halfmult
+ 1d3: 0b nop
+ 1d4: 00 breakpoint
+ 1d5: 00 breakpoint
+ 1d6: 03 .byte 3
+ 1d7: 24 lessthan
+ 1d8: 00 breakpoint
+ 1d9: 03 .byte 3
+ 1da: 08 load
+ 1db: 0b nop
+ 1dc: 0b nop
+ 1dd: 3e halfmult
+ 1de: 0b nop
+ 1df: 00 breakpoint
+ 1e0: 00 breakpoint
+ 1e1: 04 poppc
+ 1e2: 0f .byte 15
+ 1e3: 00 breakpoint
+ 1e4: 0b nop
+ 1e5: 0b nop
+ 1e6: 00 breakpoint
+ 1e7: 00 breakpoint
+ 1e8: 05 add
+ 1e9: 0f .byte 15
+ 1ea: 00 breakpoint
+ 1eb: 0b nop
+ 1ec: 0b nop
+ 1ed: 49 storesp 100
+ 1ee: 13 addsp 12
+ 1ef: 00 breakpoint
+ 1f0: 00 breakpoint
+ 1f1: 06 and
+ 1f2: 26 ulessthan
+ 1f3: 00 breakpoint
+ 1f4: 49 storesp 100
+ 1f5: 13 addsp 12
+ 1f6: 00 breakpoint
+ 1f7: 00 breakpoint
+ 1f8: 07 or
+ 1f9: 01 .byte 1
+ 1fa: 01 .byte 1
+ 1fb: 01 .byte 1
+ 1fc: 13 addsp 12
+ 1fd: 49 storesp 100
+ 1fe: 13 addsp 12
+ 1ff: 00 breakpoint
+ 200: 00 breakpoint
+ 201: 08 load
+ 202: 21 .byte 33
+ 203: 00 breakpoint
+ 204: 49 storesp 100
+ 205: 13 addsp 12
+ 206: 2f neq
+ 207: 0b nop
+ 208: 00 breakpoint
+ 209: 00 breakpoint
+ 20a: 09 not
+ 20b: 16 addsp 24
+ 20c: 00 breakpoint
+ 20d: 03 .byte 3
+ 20e: 0e .byte 14
+ 20f: 3a config
+ 210: 0b nop
+ 211: 3b pushpc
+ 212: 0b nop
+ 213: 49 storesp 100
+ 214: 13 addsp 12
+ 215: 00 breakpoint
+ 216: 00 breakpoint
+ 217: 0a flip
+ 218: 13 addsp 12
+ 219: 01 .byte 1
+ 21a: 01 .byte 1
+ 21b: 13 addsp 12
+ 21c: 03 .byte 3
+ 21d: 0e .byte 14
+ 21e: 0b nop
+ 21f: 0b nop
+ 220: 3a config
+ 221: 0b nop
+ 222: 3b pushpc
+ 223: 0b nop
+ 224: 00 breakpoint
+ 225: 00 breakpoint
+ 226: 0b nop
+ 227: 0d popsp
+ 228: 00 breakpoint
+ 229: 03 .byte 3
+ 22a: 0e .byte 14
+ 22b: 3a config
+ 22c: 0b nop
+ 22d: 3b pushpc
+ 22e: 0b nop
+ 22f: 49 storesp 100
+ 230: 13 addsp 12
+ 231: 38 neqbranch
+ 232: 0a flip
+ 233: 00 breakpoint
+ 234: 00 breakpoint
+ 235: 0c store
+ 236: 2e eq
+ 237: 01 .byte 1
+ 238: 01 .byte 1
+ 239: 13 addsp 12
+ 23a: 3f callpcrel
+ 23b: 0c store
+ 23c: 03 .byte 3
+ 23d: 0e .byte 14
+ 23e: 3a config
+ 23f: 0b nop
+ 240: 3b pushpc
+ 241: 0b nop
+ 242: 11 addsp 4
+ 243: 01 .byte 1
+ 244: 12 addsp 8
+ 245: 01 .byte 1
+ 246: 40 storesp 64
+ 247: 0a flip
+ 248: 00 breakpoint
+ 249: 00 breakpoint
+ 24a: 0d popsp
+ 24b: 34 storeb
+ 24c: 00 breakpoint
+ 24d: 03 .byte 3
+ 24e: 08 load
+ 24f: 3a config
+ 250: 0b nop
+ 251: 3b pushpc
+ 252: 0b nop
+ 253: 49 storesp 100
+ 254: 13 addsp 12
+ 255: 00 breakpoint
+ 256: 00 breakpoint
+ 257: 0e .byte 14
+ 258: 2e eq
+ 259: 01 .byte 1
+ 25a: 3f callpcrel
+ 25b: 0c store
+ 25c: 03 .byte 3
+ 25d: 0e .byte 14
+ 25e: 3a config
+ 25f: 0b nop
+ 260: 3b pushpc
+ 261: 0b nop
+ 262: 27 ulessthanorequal
+ 263: 0c store
+ 264: 3c syscall
+ 265: 0c store
+ 266: 00 breakpoint
+ 267: 00 breakpoint
+ 268: 0f .byte 15
+ 269: 05 add
+ 26a: 00 breakpoint
+ 26b: 49 storesp 100
+ 26c: 13 addsp 12
+ 26d: 00 breakpoint
+ 26e: 00 breakpoint
+ 26f: 10 addsp 0
+ 270: 2e eq
+ 271: 01 .byte 1
+ 272: 01 .byte 1
+ 273: 13 addsp 12
+ 274: 3f callpcrel
+ 275: 0c store
+ 276: 03 .byte 3
+ 277: 0e .byte 14
+ 278: 3a config
+ 279: 0b nop
+ 27a: 3b pushpc
+ 27b: 0b nop
+ 27c: 27 ulessthanorequal
+ 27d: 0c store
+ 27e: 11 addsp 4
+ 27f: 01 .byte 1
+ 280: 12 addsp 8
+ 281: 01 .byte 1
+ 282: 40 storesp 64
+ 283: 0a flip
+ 284: 00 breakpoint
+ 285: 00 breakpoint
+ 286: 11 addsp 4
+ 287: 05 add
+ 288: 00 breakpoint
+ 289: 03 .byte 3
+ 28a: 0e .byte 14
+ 28b: 3a config
+ 28c: 0b nop
+ 28d: 3b pushpc
+ 28e: 0b nop
+ 28f: 49 storesp 100
+ 290: 13 addsp 12
+ 291: 02 pushsp
+ 292: 0a flip
+ 293: 00 breakpoint
+ 294: 00 breakpoint
+ 295: 12 addsp 8
+ 296: 2e eq
+ 297: 00 breakpoint
+ 298: 3f callpcrel
+ 299: 0c store
+ 29a: 03 .byte 3
+ 29b: 0e .byte 14
+ 29c: 3a config
+ 29d: 0b nop
+ 29e: 3b pushpc
+ 29f: 0b nop
+ 2a0: 27 ulessthanorequal
+ 2a1: 0c store
+ 2a2: 11 addsp 4
+ 2a3: 01 .byte 1
+ 2a4: 12 addsp 8
+ 2a5: 01 .byte 1
+ 2a6: 40 storesp 64
+ 2a7: 0a flip
+ 2a8: 00 breakpoint
+ 2a9: 00 breakpoint
+ 2aa: 13 addsp 12
+ 2ab: 2e eq
+ 2ac: 01 .byte 1
+ 2ad: 01 .byte 1
+ 2ae: 13 addsp 12
+ 2af: 3f callpcrel
+ 2b0: 0c store
+ 2b1: 03 .byte 3
+ 2b2: 0e .byte 14
+ 2b3: 3a config
+ 2b4: 0b nop
+ 2b5: 3b pushpc
+ 2b6: 0b nop
+ 2b7: 27 ulessthanorequal
+ 2b8: 0c store
+ 2b9: 49 storesp 100
+ 2ba: 13 addsp 12
+ 2bb: 11 addsp 4
+ 2bc: 01 .byte 1
+ 2bd: 12 addsp 8
+ 2be: 01 .byte 1
+ 2bf: 40 storesp 64
+ 2c0: 0a flip
+ 2c1: 00 breakpoint
+ 2c2: 00 breakpoint
+ 2c3: 14 addsp 16
+ 2c4: 05 add
+ 2c5: 00 breakpoint
+ 2c6: 03 .byte 3
+ 2c7: 08 load
+ 2c8: 3a config
+ 2c9: 0b nop
+ 2ca: 3b pushpc
+ 2cb: 0b nop
+ 2cc: 49 storesp 100
+ 2cd: 13 addsp 12
+ 2ce: 02 pushsp
+ 2cf: 0a flip
+ 2d0: 00 breakpoint
+ 2d1: 00 breakpoint
+ 2d2: 15 addsp 20
+ 2d3: 0b nop
+ 2d4: 01 .byte 1
+ 2d5: 01 .byte 1
+ 2d6: 13 addsp 12
+ 2d7: 55 storesp 20
+ 2d8: 06 and
+ 2d9: 00 breakpoint
+ 2da: 00 breakpoint
+ 2db: 16 addsp 24
+ 2dc: 34 storeb
+ 2dd: 00 breakpoint
+ 2de: 03 .byte 3
+ 2df: 08 load
+ 2e0: 3a config
+ 2e1: 0b nop
+ 2e2: 3b pushpc
+ 2e3: 0b nop
+ 2e4: 49 storesp 100
+ 2e5: 13 addsp 12
+ 2e6: 02 pushsp
+ 2e7: 0a flip
+ 2e8: 00 breakpoint
+ 2e9: 00 breakpoint
+ 2ea: 17 addsp 28
+ 2eb: 2e eq
+ 2ec: 01 .byte 1
+ 2ed: 3f callpcrel
+ 2ee: 0c store
+ 2ef: 03 .byte 3
+ 2f0: 0e .byte 14
+ 2f1: 3a config
+ 2f2: 0b nop
+ 2f3: 3b pushpc
+ 2f4: 0b nop
+ 2f5: 49 storesp 100
+ 2f6: 13 addsp 12
+ 2f7: 3c syscall
+ 2f8: 0c store
+ 2f9: 00 breakpoint
+ 2fa: 00 breakpoint
+ 2fb: 18 addsp 32
+ 2fc: 18 addsp 32
+ 2fd: 00 breakpoint
+ 2fe: 00 breakpoint
+ 2ff: 00 breakpoint
+ 300: 19 addsp 36
+ 301: 0b nop
+ 302: 01 .byte 1
+ 303: 01 .byte 1
+ 304: 13 addsp 12
+ 305: 11 addsp 4
+ 306: 01 .byte 1
+ 307: 12 addsp 8
+ 308: 01 .byte 1
+ 309: 00 breakpoint
+ 30a: 00 breakpoint
+ 30b: 1a addsp 40
+ 30c: 0b nop
+ 30d: 01 .byte 1
+ 30e: 11 addsp 4
+ 30f: 01 .byte 1
+ 310: 12 addsp 8
+ 311: 01 .byte 1
+ 312: 00 breakpoint
+ 313: 00 breakpoint
+ 314: 1b addsp 44
+ 315: 34 storeb
+ 316: 00 breakpoint
+ 317: 03 .byte 3
+ 318: 0e .byte 14
+ 319: 3a config
+ 31a: 0b nop
+ 31b: 3b pushpc
+ 31c: 0b nop
+ 31d: 49 storesp 100
+ 31e: 13 addsp 12
+ 31f: 02 pushsp
+ 320: 0a flip
+ 321: 00 breakpoint
+ 322: 00 breakpoint
+ 323: 1c addsp 48
+ 324: 2e eq
+ 325: 01 .byte 1
+ 326: 01 .byte 1
+ 327: 13 addsp 12
+ 328: 3f callpcrel
+ 329: 0c store
+ 32a: 03 .byte 3
+ 32b: 0e .byte 14
+ 32c: 3a config
+ 32d: 0b nop
+ 32e: 3b pushpc
+ 32f: 0b nop
+ 330: 49 storesp 100
+ 331: 13 addsp 12
+ 332: 3c syscall
+ 333: 0c store
+ 334: 00 breakpoint
+ 335: 00 breakpoint
+ 336: 1d addsp 52
+ 337: 2e eq
+ 338: 01 .byte 1
+ 339: 3f callpcrel
+ 33a: 0c store
+ 33b: 03 .byte 3
+ 33c: 0e .byte 14
+ 33d: 3a config
+ 33e: 0b nop
+ 33f: 3b pushpc
+ 340: 0b nop
+ 341: 27 ulessthanorequal
+ 342: 0c store
+ 343: 49 storesp 100
+ 344: 13 addsp 12
+ 345: 3c syscall
+ 346: 0c store
+ 347: 00 breakpoint
+ 348: 00 breakpoint
+ 349: 1e addsp 56
+ 34a: 2e eq
+ 34b: 01 .byte 1
+ 34c: 01 .byte 1
+ 34d: 13 addsp 12
+ 34e: 03 .byte 3
+ 34f: 0e .byte 14
+ 350: 3a config
+ 351: 0b nop
+ 352: 3b pushpc
+ 353: 0b nop
+ 354: 27 ulessthanorequal
+ 355: 0c store
+ 356: 49 storesp 100
+ 357: 13 addsp 12
+ 358: 11 addsp 4
+ 359: 01 .byte 1
+ 35a: 12 addsp 8
+ 35b: 01 .byte 1
+ 35c: 40 storesp 64
+ 35d: 0a flip
+ 35e: 00 breakpoint
+ 35f: 00 breakpoint
+ 360: 1f addsp 60
+ 361: 34 storeb
+ 362: 00 breakpoint
+ 363: 03 .byte 3
+ 364: 08 load
+ 365: 3a config
+ 366: 0b nop
+ 367: 3b pushpc
+ 368: 05 add
+ 369: 49 storesp 100
+ 36a: 13 addsp 12
+ 36b: 02 pushsp
+ 36c: 0a flip
+ 36d: 00 breakpoint
+ 36e: 00 breakpoint
+ 36f: 20 .byte 32
+ 370: 2e eq
+ 371: 01 .byte 1
+ 372: 01 .byte 1
+ 373: 13 addsp 12
+ 374: 03 .byte 3
+ 375: 0e .byte 14
+ 376: 3a config
+ 377: 0b nop
+ 378: 3b pushpc
+ 379: 05 add
+ 37a: 27 ulessthanorequal
+ 37b: 0c store
+ 37c: 11 addsp 4
+ 37d: 01 .byte 1
+ 37e: 12 addsp 8
+ 37f: 01 .byte 1
+ 380: 40 storesp 64
+ 381: 0a flip
+ 382: 00 breakpoint
+ 383: 00 breakpoint
+ 384: 21 .byte 33
+ 385: 05 add
+ 386: 00 breakpoint
+ 387: 03 .byte 3
+ 388: 0e .byte 14
+ 389: 3a config
+ 38a: 0b nop
+ 38b: 3b pushpc
+ 38c: 05 add
+ 38d: 49 storesp 100
+ 38e: 13 addsp 12
+ 38f: 02 pushsp
+ 390: 0a flip
+ 391: 00 breakpoint
+ 392: 00 breakpoint
+ 393: 22 loadh
+ 394: 05 add
+ 395: 00 breakpoint
+ 396: 03 .byte 3
+ 397: 08 load
+ 398: 3a config
+ 399: 0b nop
+ 39a: 3b pushpc
+ 39b: 05 add
+ 39c: 49 storesp 100
+ 39d: 13 addsp 12
+ 39e: 02 pushsp
+ 39f: 0a flip
+ 3a0: 00 breakpoint
+ 3a1: 00 breakpoint
+ 3a2: 23 storeh
+ 3a3: 2e eq
+ 3a4: 01 .byte 1
+ 3a5: 01 .byte 1
+ 3a6: 13 addsp 12
+ 3a7: 3f callpcrel
+ 3a8: 0c store
+ 3a9: 03 .byte 3
+ 3aa: 0e .byte 14
+ 3ab: 3a config
+ 3ac: 0b nop
+ 3ad: 3b pushpc
+ 3ae: 05 add
+ 3af: 27 ulessthanorequal
+ 3b0: 0c store
+ 3b1: 49 storesp 100
+ 3b2: 13 addsp 12
+ 3b3: 11 addsp 4
+ 3b4: 01 .byte 1
+ 3b5: 12 addsp 8
+ 3b6: 01 .byte 1
+ 3b7: 40 storesp 64
+ 3b8: 0a flip
+ 3b9: 00 breakpoint
+ 3ba: 00 breakpoint
+ 3bb: 24 lessthan
+ 3bc: 34 storeb
+ 3bd: 00 breakpoint
+ 3be: 03 .byte 3
+ 3bf: 0e .byte 14
+ 3c0: 3a config
+ 3c1: 0b nop
+ 3c2: 3b pushpc
+ 3c3: 05 add
+ 3c4: 49 storesp 100
+ 3c5: 13 addsp 12
+ 3c6: 02 pushsp
+ 3c7: 0a flip
+ 3c8: 00 breakpoint
+ 3c9: 00 breakpoint
+ 3ca: 25 lessthanorequal
+ 3cb: 34 storeb
+ 3cc: 00 breakpoint
+ 3cd: 03 .byte 3
+ 3ce: 0e .byte 14
+ 3cf: 3a config
+ 3d0: 0b nop
+ 3d1: 3b pushpc
+ 3d2: 0b nop
+ 3d3: 49 storesp 100
+ 3d4: 13 addsp 12
+ 3d5: 3f callpcrel
+ 3d6: 0c store
+ 3d7: 3c syscall
+ 3d8: 0c store
+ 3d9: 00 breakpoint
+ 3da: 00 breakpoint
+ 3db: 26 ulessthan
+ 3dc: 34 storeb
+ 3dd: 00 breakpoint
+ 3de: 03 .byte 3
+ 3df: 0e .byte 14
+ 3e0: 3a config
+ 3e1: 0b nop
+ 3e2: 3b pushpc
+ 3e3: 0b nop
+ 3e4: 49 storesp 100
+ 3e5: 13 addsp 12
+ 3e6: 3f callpcrel
+ 3e7: 0c store
+ 3e8: 02 pushsp
+ 3e9: 0a flip
+ 3ea: 00 breakpoint
+ ...
+
+000003ed <.Ldebug_abbrev0>:
+ 3ed: 01 .byte 1
+ 3ee: 11 addsp 4
+ 3ef: 01 .byte 1
+ 3f0: 10 addsp 0
+ 3f1: 06 and
+ 3f2: 12 addsp 8
+ 3f3: 01 .byte 1
+ 3f4: 11 addsp 4
+ 3f5: 01 .byte 1
+ 3f6: 25 lessthanorequal
+ 3f7: 0e .byte 14
+ 3f8: 13 addsp 12
+ 3f9: 0b nop
+ 3fa: 03 .byte 3
+ 3fb: 0e .byte 14
+ 3fc: 1b addsp 44
+ 3fd: 0e .byte 14
+ 3fe: 00 breakpoint
+ 3ff: 00 breakpoint
+ 400: 02 pushsp
+ 401: 24 lessthan
+ 402: 00 breakpoint
+ 403: 03 .byte 3
+ 404: 08 load
+ 405: 0b nop
+ 406: 0b nop
+ 407: 3e halfmult
+ 408: 0b nop
+ 409: 00 breakpoint
+ 40a: 00 breakpoint
+ 40b: 03 .byte 3
+ 40c: 24 lessthan
+ 40d: 00 breakpoint
+ 40e: 03 .byte 3
+ 40f: 0e .byte 14
+ 410: 0b nop
+ 411: 0b nop
+ 412: 3e halfmult
+ 413: 0b nop
+ 414: 00 breakpoint
+ 415: 00 breakpoint
+ 416: 04 poppc
+ 417: 16 addsp 24
+ 418: 00 breakpoint
+ 419: 03 .byte 3
+ 41a: 0e .byte 14
+ 41b: 3a config
+ 41c: 0b nop
+ 41d: 3b pushpc
+ 41e: 05 add
+ 41f: 49 storesp 100
+ 420: 13 addsp 12
+ 421: 00 breakpoint
+ 422: 00 breakpoint
+ 423: 05 add
+ 424: 17 addsp 28
+ 425: 01 .byte 1
+ 426: 01 .byte 1
+ 427: 13 addsp 12
+ 428: 0b nop
+ 429: 0b nop
+ 42a: 3a config
+ 42b: 0b nop
+ 42c: 3b pushpc
+ 42d: 0b nop
+ 42e: 00 breakpoint
+ 42f: 00 breakpoint
+ 430: 06 and
+ 431: 0d popsp
+ 432: 00 breakpoint
+ 433: 03 .byte 3
+ 434: 0e .byte 14
+ 435: 3a config
+ 436: 0b nop
+ 437: 3b pushpc
+ 438: 0b nop
+ 439: 49 storesp 100
+ 43a: 13 addsp 12
+ 43b: 00 breakpoint
+ 43c: 00 breakpoint
+ 43d: 07 or
+ 43e: 01 .byte 1
+ 43f: 01 .byte 1
+ 440: 01 .byte 1
+ 441: 13 addsp 12
+ 442: 49 storesp 100
+ 443: 13 addsp 12
+ 444: 00 breakpoint
+ 445: 00 breakpoint
+ 446: 08 load
+ 447: 21 .byte 33
+ 448: 00 breakpoint
+ 449: 49 storesp 100
+ 44a: 13 addsp 12
+ 44b: 2f neq
+ 44c: 0b nop
+ 44d: 00 breakpoint
+ 44e: 00 breakpoint
+ 44f: 09 not
+ 450: 13 addsp 12
+ 451: 01 .byte 1
+ 452: 01 .byte 1
+ 453: 13 addsp 12
+ 454: 0b nop
+ 455: 0b nop
+ 456: 3a config
+ 457: 0b nop
+ 458: 3b pushpc
+ 459: 0b nop
+ 45a: 00 breakpoint
+ 45b: 00 breakpoint
+ 45c: 0a flip
+ 45d: 0d popsp
+ 45e: 00 breakpoint
+ 45f: 03 .byte 3
+ 460: 0e .byte 14
+ 461: 3a config
+ 462: 0b nop
+ 463: 3b pushpc
+ 464: 0b nop
+ 465: 49 storesp 100
+ 466: 13 addsp 12
+ 467: 38 neqbranch
+ 468: 0a flip
+ 469: 00 breakpoint
+ 46a: 00 breakpoint
+ 46b: 0b nop
+ 46c: 16 addsp 24
+ 46d: 00 breakpoint
+ 46e: 03 .byte 3
+ 46f: 0e .byte 14
+ 470: 3a config
+ 471: 0b nop
+ 472: 3b pushpc
+ 473: 0b nop
+ 474: 49 storesp 100
+ 475: 13 addsp 12
+ 476: 00 breakpoint
+ 477: 00 breakpoint
+ 478: 0c store
+ 479: 0f .byte 15
+ 47a: 00 breakpoint
+ 47b: 0b nop
+ 47c: 0b nop
+ 47d: 00 breakpoint
+ 47e: 00 breakpoint
+ 47f: 0d popsp
+ 480: 13 addsp 12
+ 481: 01 .byte 1
+ 482: 01 .byte 1
+ 483: 13 addsp 12
+ 484: 03 .byte 3
+ 485: 0e .byte 14
+ 486: 0b nop
+ 487: 0b nop
+ 488: 3a config
+ 489: 0b nop
+ 48a: 3b pushpc
+ 48b: 0b nop
+ 48c: 00 breakpoint
+ 48d: 00 breakpoint
+ 48e: 0e .byte 14
+ 48f: 0d popsp
+ 490: 00 breakpoint
+ 491: 03 .byte 3
+ 492: 08 load
+ 493: 3a config
+ 494: 0b nop
+ 495: 3b pushpc
+ 496: 0b nop
+ 497: 49 storesp 100
+ 498: 13 addsp 12
+ 499: 38 neqbranch
+ 49a: 0a flip
+ 49b: 00 breakpoint
+ 49c: 00 breakpoint
+ 49d: 0f .byte 15
+ 49e: 0f .byte 15
+ 49f: 00 breakpoint
+ 4a0: 0b nop
+ 4a1: 0b nop
+ 4a2: 49 storesp 100
+ 4a3: 13 addsp 12
+ 4a4: 00 breakpoint
+ 4a5: 00 breakpoint
+ 4a6: 10 addsp 0
+ 4a7: 13 addsp 12
+ 4a8: 01 .byte 1
+ 4a9: 01 .byte 1
+ 4aa: 13 addsp 12
+ 4ab: 03 .byte 3
+ 4ac: 0e .byte 14
+ 4ad: 0b nop
+ 4ae: 05 add
+ 4af: 3a config
+ 4b0: 0b nop
+ 4b1: 3b pushpc
+ 4b2: 0b nop
+ 4b3: 00 breakpoint
+ 4b4: 00 breakpoint
+ 4b5: 11 addsp 4
+ 4b6: 15 addsp 20
+ 4b7: 00 breakpoint
+ 4b8: 27 ulessthanorequal
+ 4b9: 0c store
+ 4ba: 00 breakpoint
+ 4bb: 00 breakpoint
+ 4bc: 12 addsp 8
+ 4bd: 0d popsp
+ 4be: 00 breakpoint
+ 4bf: 03 .byte 3
+ 4c0: 0e .byte 14
+ 4c1: 3a config
+ 4c2: 0b nop
+ 4c3: 3b pushpc
+ 4c4: 05 add
+ 4c5: 49 storesp 100
+ 4c6: 13 addsp 12
+ 4c7: 38 neqbranch
+ 4c8: 0a flip
+ 4c9: 00 breakpoint
+ 4ca: 00 breakpoint
+ 4cb: 13 addsp 12
+ 4cc: 15 addsp 20
+ 4cd: 01 .byte 1
+ 4ce: 01 .byte 1
+ 4cf: 13 addsp 12
+ 4d0: 27 ulessthanorequal
+ 4d1: 0c store
+ 4d2: 49 storesp 100
+ 4d3: 13 addsp 12
+ 4d4: 00 breakpoint
+ 4d5: 00 breakpoint
+ 4d6: 14 addsp 16
+ 4d7: 05 add
+ 4d8: 00 breakpoint
+ 4d9: 49 storesp 100
+ 4da: 13 addsp 12
+ 4db: 00 breakpoint
+ 4dc: 00 breakpoint
+ 4dd: 15 addsp 20
+ 4de: 26 ulessthan
+ 4df: 00 breakpoint
+ 4e0: 49 storesp 100
+ 4e1: 13 addsp 12
+ 4e2: 00 breakpoint
+ 4e3: 00 breakpoint
+ 4e4: 16 addsp 24
+ 4e5: 13 addsp 12
+ 4e6: 01 .byte 1
+ 4e7: 01 .byte 1
+ 4e8: 13 addsp 12
+ 4e9: 03 .byte 3
+ 4ea: 0e .byte 14
+ 4eb: 0b nop
+ 4ec: 0b nop
+ 4ed: 3a config
+ 4ee: 0b nop
+ 4ef: 3b pushpc
+ 4f0: 05 add
+ 4f1: 00 breakpoint
+ 4f2: 00 breakpoint
+ 4f3: 17 addsp 28
+ 4f4: 13 addsp 12
+ 4f5: 01 .byte 1
+ 4f6: 01 .byte 1
+ 4f7: 13 addsp 12
+ 4f8: 0b nop
+ 4f9: 0b nop
+ 4fa: 3a config
+ 4fb: 0b nop
+ 4fc: 3b pushpc
+ 4fd: 05 add
+ 4fe: 00 breakpoint
+ 4ff: 00 breakpoint
+ 500: 18 addsp 32
+ 501: 17 addsp 28
+ 502: 01 .byte 1
+ 503: 01 .byte 1
+ 504: 13 addsp 12
+ 505: 0b nop
+ 506: 0b nop
+ 507: 3a config
+ 508: 0b nop
+ 509: 3b pushpc
+ 50a: 05 add
+ 50b: 00 breakpoint
+ 50c: 00 breakpoint
+ 50d: 19 addsp 36
+ 50e: 0d popsp
+ 50f: 00 breakpoint
+ 510: 03 .byte 3
+ 511: 0e .byte 14
+ 512: 3a config
+ 513: 0b nop
+ 514: 3b pushpc
+ 515: 05 add
+ 516: 49 storesp 100
+ 517: 13 addsp 12
+ 518: 00 breakpoint
+ 519: 00 breakpoint
+ 51a: 1a addsp 40
+ 51b: 15 addsp 20
+ 51c: 01 .byte 1
+ 51d: 01 .byte 1
+ 51e: 13 addsp 12
+ 51f: 27 ulessthanorequal
+ 520: 0c store
+ 521: 00 breakpoint
+ 522: 00 breakpoint
+ 523: 1b addsp 44
+ 524: 2e eq
+ 525: 00 breakpoint
+ 526: 3f callpcrel
+ 527: 0c store
+ 528: 03 .byte 3
+ 529: 0e .byte 14
+ 52a: 3a config
+ 52b: 0b nop
+ 52c: 3b pushpc
+ 52d: 0b nop
+ 52e: 27 ulessthanorequal
+ 52f: 0c store
+ 530: 49 storesp 100
+ 531: 13 addsp 12
+ 532: 11 addsp 4
+ 533: 01 .byte 1
+ 534: 12 addsp 8
+ 535: 01 .byte 1
+ 536: 40 storesp 64
+ 537: 0a flip
+ 538: 00 breakpoint
+ 539: 00 breakpoint
+ 53a: 1c addsp 48
+ 53b: 34 storeb
+ 53c: 00 breakpoint
+ 53d: 03 .byte 3
+ 53e: 0e .byte 14
+ 53f: 3a config
+ 540: 0b nop
+ 541: 3b pushpc
+ 542: 05 add
+ 543: 49 storesp 100
+ 544: 13 addsp 12
+ 545: 3f callpcrel
+ 546: 0c store
+ 547: 3c syscall
+ 548: 0c store
+ 549: 00 breakpoint
+ ...
+
+0000054c <.Ldebug_abbrev0>:
+ 54c: 01 .byte 1
+ 54d: 11 addsp 4
+ 54e: 01 .byte 1
+ 54f: 10 addsp 0
+ 550: 06 and
+ 551: 12 addsp 8
+ 552: 01 .byte 1
+ 553: 11 addsp 4
+ 554: 01 .byte 1
+ 555: 25 lessthanorequal
+ 556: 0e .byte 14
+ 557: 13 addsp 12
+ 558: 0b nop
+ 559: 03 .byte 3
+ 55a: 0e .byte 14
+ 55b: 1b addsp 44
+ 55c: 0e .byte 14
+ 55d: 00 breakpoint
+ 55e: 00 breakpoint
+ 55f: 02 pushsp
+ 560: 24 lessthan
+ 561: 00 breakpoint
+ 562: 03 .byte 3
+ 563: 0e .byte 14
+ 564: 0b nop
+ 565: 0b nop
+ 566: 3e halfmult
+ 567: 0b nop
+ 568: 00 breakpoint
+ 569: 00 breakpoint
+ 56a: 03 .byte 3
+ 56b: 24 lessthan
+ 56c: 00 breakpoint
+ 56d: 03 .byte 3
+ 56e: 08 load
+ 56f: 0b nop
+ 570: 0b nop
+ 571: 3e halfmult
+ 572: 0b nop
+ 573: 00 breakpoint
+ 574: 00 breakpoint
+ 575: 04 poppc
+ 576: 16 addsp 24
+ 577: 00 breakpoint
+ 578: 03 .byte 3
+ 579: 0e .byte 14
+ 57a: 3a config
+ 57b: 0b nop
+ 57c: 3b pushpc
+ 57d: 05 add
+ 57e: 49 storesp 100
+ 57f: 13 addsp 12
+ 580: 00 breakpoint
+ 581: 00 breakpoint
+ 582: 05 add
+ 583: 17 addsp 28
+ 584: 01 .byte 1
+ 585: 01 .byte 1
+ 586: 13 addsp 12
+ 587: 0b nop
+ 588: 0b nop
+ 589: 3a config
+ 58a: 0b nop
+ 58b: 3b pushpc
+ 58c: 0b nop
+ 58d: 00 breakpoint
+ 58e: 00 breakpoint
+ 58f: 06 and
+ 590: 0d popsp
+ 591: 00 breakpoint
+ 592: 03 .byte 3
+ 593: 0e .byte 14
+ 594: 3a config
+ 595: 0b nop
+ 596: 3b pushpc
+ 597: 0b nop
+ 598: 49 storesp 100
+ 599: 13 addsp 12
+ 59a: 00 breakpoint
+ 59b: 00 breakpoint
+ 59c: 07 or
+ 59d: 01 .byte 1
+ 59e: 01 .byte 1
+ 59f: 01 .byte 1
+ 5a0: 13 addsp 12
+ 5a1: 49 storesp 100
+ 5a2: 13 addsp 12
+ 5a3: 00 breakpoint
+ 5a4: 00 breakpoint
+ 5a5: 08 load
+ 5a6: 21 .byte 33
+ 5a7: 00 breakpoint
+ 5a8: 49 storesp 100
+ 5a9: 13 addsp 12
+ 5aa: 2f neq
+ 5ab: 0b nop
+ 5ac: 00 breakpoint
+ 5ad: 00 breakpoint
+ 5ae: 09 not
+ 5af: 13 addsp 12
+ 5b0: 01 .byte 1
+ 5b1: 01 .byte 1
+ 5b2: 13 addsp 12
+ 5b3: 0b nop
+ 5b4: 0b nop
+ 5b5: 3a config
+ 5b6: 0b nop
+ 5b7: 3b pushpc
+ 5b8: 0b nop
+ 5b9: 00 breakpoint
+ 5ba: 00 breakpoint
+ 5bb: 0a flip
+ 5bc: 0d popsp
+ 5bd: 00 breakpoint
+ 5be: 03 .byte 3
+ 5bf: 0e .byte 14
+ 5c0: 3a config
+ 5c1: 0b nop
+ 5c2: 3b pushpc
+ 5c3: 0b nop
+ 5c4: 49 storesp 100
+ 5c5: 13 addsp 12
+ 5c6: 38 neqbranch
+ 5c7: 0a flip
+ 5c8: 00 breakpoint
+ 5c9: 00 breakpoint
+ 5ca: 0b nop
+ 5cb: 16 addsp 24
+ 5cc: 00 breakpoint
+ 5cd: 03 .byte 3
+ 5ce: 0e .byte 14
+ 5cf: 3a config
+ 5d0: 0b nop
+ 5d1: 3b pushpc
+ 5d2: 0b nop
+ 5d3: 49 storesp 100
+ 5d4: 13 addsp 12
+ 5d5: 00 breakpoint
+ 5d6: 00 breakpoint
+ 5d7: 0c store
+ 5d8: 0f .byte 15
+ 5d9: 00 breakpoint
+ 5da: 0b nop
+ 5db: 0b nop
+ 5dc: 00 breakpoint
+ 5dd: 00 breakpoint
+ 5de: 0d popsp
+ 5df: 13 addsp 12
+ 5e0: 01 .byte 1
+ 5e1: 01 .byte 1
+ 5e2: 13 addsp 12
+ 5e3: 03 .byte 3
+ 5e4: 0e .byte 14
+ 5e5: 0b nop
+ 5e6: 0b nop
+ 5e7: 3a config
+ 5e8: 0b nop
+ 5e9: 3b pushpc
+ 5ea: 0b nop
+ 5eb: 00 breakpoint
+ 5ec: 00 breakpoint
+ 5ed: 0e .byte 14
+ 5ee: 0d popsp
+ 5ef: 00 breakpoint
+ 5f0: 03 .byte 3
+ 5f1: 08 load
+ 5f2: 3a config
+ 5f3: 0b nop
+ 5f4: 3b pushpc
+ 5f5: 0b nop
+ 5f6: 49 storesp 100
+ 5f7: 13 addsp 12
+ 5f8: 38 neqbranch
+ 5f9: 0a flip
+ 5fa: 00 breakpoint
+ 5fb: 00 breakpoint
+ 5fc: 0f .byte 15
+ 5fd: 0f .byte 15
+ 5fe: 00 breakpoint
+ 5ff: 0b nop
+ 600: 0b nop
+ 601: 49 storesp 100
+ 602: 13 addsp 12
+ 603: 00 breakpoint
+ 604: 00 breakpoint
+ 605: 10 addsp 0
+ 606: 13 addsp 12
+ 607: 01 .byte 1
+ 608: 01 .byte 1
+ 609: 13 addsp 12
+ 60a: 03 .byte 3
+ 60b: 0e .byte 14
+ 60c: 0b nop
+ 60d: 05 add
+ 60e: 3a config
+ 60f: 0b nop
+ 610: 3b pushpc
+ 611: 0b nop
+ 612: 00 breakpoint
+ 613: 00 breakpoint
+ 614: 11 addsp 4
+ 615: 15 addsp 20
+ 616: 00 breakpoint
+ 617: 27 ulessthanorequal
+ 618: 0c store
+ 619: 00 breakpoint
+ 61a: 00 breakpoint
+ 61b: 12 addsp 8
+ 61c: 0d popsp
+ 61d: 00 breakpoint
+ 61e: 03 .byte 3
+ 61f: 0e .byte 14
+ 620: 3a config
+ 621: 0b nop
+ 622: 3b pushpc
+ 623: 05 add
+ 624: 49 storesp 100
+ 625: 13 addsp 12
+ 626: 38 neqbranch
+ 627: 0a flip
+ 628: 00 breakpoint
+ 629: 00 breakpoint
+ 62a: 13 addsp 12
+ 62b: 15 addsp 20
+ 62c: 01 .byte 1
+ 62d: 01 .byte 1
+ 62e: 13 addsp 12
+ 62f: 27 ulessthanorequal
+ 630: 0c store
+ 631: 49 storesp 100
+ 632: 13 addsp 12
+ 633: 00 breakpoint
+ 634: 00 breakpoint
+ 635: 14 addsp 16
+ 636: 05 add
+ 637: 00 breakpoint
+ 638: 49 storesp 100
+ 639: 13 addsp 12
+ 63a: 00 breakpoint
+ 63b: 00 breakpoint
+ 63c: 15 addsp 20
+ 63d: 26 ulessthan
+ 63e: 00 breakpoint
+ 63f: 49 storesp 100
+ 640: 13 addsp 12
+ 641: 00 breakpoint
+ 642: 00 breakpoint
+ 643: 16 addsp 24
+ 644: 13 addsp 12
+ 645: 01 .byte 1
+ 646: 01 .byte 1
+ 647: 13 addsp 12
+ 648: 03 .byte 3
+ 649: 0e .byte 14
+ 64a: 0b nop
+ 64b: 0b nop
+ 64c: 3a config
+ 64d: 0b nop
+ 64e: 3b pushpc
+ 64f: 05 add
+ 650: 00 breakpoint
+ 651: 00 breakpoint
+ 652: 17 addsp 28
+ 653: 13 addsp 12
+ 654: 01 .byte 1
+ 655: 01 .byte 1
+ 656: 13 addsp 12
+ 657: 0b nop
+ 658: 0b nop
+ 659: 3a config
+ 65a: 0b nop
+ 65b: 3b pushpc
+ 65c: 05 add
+ 65d: 00 breakpoint
+ 65e: 00 breakpoint
+ 65f: 18 addsp 32
+ 660: 17 addsp 28
+ 661: 01 .byte 1
+ 662: 01 .byte 1
+ 663: 13 addsp 12
+ 664: 0b nop
+ 665: 0b nop
+ 666: 3a config
+ 667: 0b nop
+ 668: 3b pushpc
+ 669: 05 add
+ 66a: 00 breakpoint
+ 66b: 00 breakpoint
+ 66c: 19 addsp 36
+ 66d: 0d popsp
+ 66e: 00 breakpoint
+ 66f: 03 .byte 3
+ 670: 0e .byte 14
+ 671: 3a config
+ 672: 0b nop
+ 673: 3b pushpc
+ 674: 05 add
+ 675: 49 storesp 100
+ 676: 13 addsp 12
+ 677: 00 breakpoint
+ 678: 00 breakpoint
+ 679: 1a addsp 40
+ 67a: 15 addsp 20
+ 67b: 01 .byte 1
+ 67c: 01 .byte 1
+ 67d: 13 addsp 12
+ 67e: 27 ulessthanorequal
+ 67f: 0c store
+ 680: 00 breakpoint
+ 681: 00 breakpoint
+ 682: 1b addsp 44
+ 683: 2e eq
+ 684: 01 .byte 1
+ 685: 01 .byte 1
+ 686: 13 addsp 12
+ 687: 3f callpcrel
+ 688: 0c store
+ 689: 03 .byte 3
+ 68a: 0e .byte 14
+ 68b: 3a config
+ 68c: 0b nop
+ 68d: 3b pushpc
+ 68e: 0b nop
+ 68f: 27 ulessthanorequal
+ 690: 0c store
+ 691: 11 addsp 4
+ 692: 01 .byte 1
+ 693: 12 addsp 8
+ 694: 01 .byte 1
+ 695: 40 storesp 64
+ 696: 0a flip
+ 697: 00 breakpoint
+ 698: 00 breakpoint
+ 699: 1c addsp 48
+ 69a: 05 add
+ 69b: 00 breakpoint
+ 69c: 03 .byte 3
+ 69d: 0e .byte 14
+ 69e: 3a config
+ 69f: 0b nop
+ 6a0: 3b pushpc
+ 6a1: 0b nop
+ 6a2: 49 storesp 100
+ 6a3: 13 addsp 12
+ 6a4: 02 pushsp
+ 6a5: 0a flip
+ 6a6: 00 breakpoint
+ 6a7: 00 breakpoint
+ 6a8: 1d addsp 52
+ 6a9: 34 storeb
+ 6aa: 00 breakpoint
+ 6ab: 03 .byte 3
+ 6ac: 08 load
+ 6ad: 3a config
+ 6ae: 0b nop
+ 6af: 3b pushpc
+ 6b0: 0b nop
+ 6b1: 49 storesp 100
+ 6b2: 13 addsp 12
+ 6b3: 02 pushsp
+ 6b4: 0a flip
+ 6b5: 00 breakpoint
+ 6b6: 00 breakpoint
+ 6b7: 1e addsp 56
+ 6b8: 34 storeb
+ 6b9: 00 breakpoint
+ 6ba: 03 .byte 3
+ 6bb: 0e .byte 14
+ 6bc: 3a config
+ 6bd: 0b nop
+ 6be: 3b pushpc
+ 6bf: 0b nop
+ 6c0: 49 storesp 100
+ 6c1: 13 addsp 12
+ 6c2: 02 pushsp
+ 6c3: 0a flip
+ 6c4: 00 breakpoint
+ 6c5: 00 breakpoint
+ 6c6: 1f addsp 60
+ 6c7: 34 storeb
+ 6c8: 00 breakpoint
+ 6c9: 03 .byte 3
+ 6ca: 0e .byte 14
+ 6cb: 3a config
+ 6cc: 0b nop
+ 6cd: 3b pushpc
+ 6ce: 05 add
+ 6cf: 49 storesp 100
+ 6d0: 13 addsp 12
+ 6d1: 3f callpcrel
+ 6d2: 0c store
+ 6d3: 3c syscall
+ 6d4: 0c store
+ 6d5: 00 breakpoint
+ ...
+
+000006d8 <.Ldebug_abbrev0>:
+ 6d8: 01 .byte 1
+ 6d9: 11 addsp 4
+ 6da: 01 .byte 1
+ 6db: 10 addsp 0
+ 6dc: 06 and
+ 6dd: 12 addsp 8
+ 6de: 01 .byte 1
+ 6df: 11 addsp 4
+ 6e0: 01 .byte 1
+ 6e1: 25 lessthanorequal
+ 6e2: 0e .byte 14
+ 6e3: 13 addsp 12
+ 6e4: 0b nop
+ 6e5: 03 .byte 3
+ 6e6: 0e .byte 14
+ 6e7: 1b addsp 44
+ 6e8: 0e .byte 14
+ 6e9: 00 breakpoint
+ 6ea: 00 breakpoint
+ 6eb: 02 pushsp
+ 6ec: 24 lessthan
+ 6ed: 00 breakpoint
+ 6ee: 03 .byte 3
+ 6ef: 0e .byte 14
+ 6f0: 0b nop
+ 6f1: 0b nop
+ 6f2: 3e halfmult
+ 6f3: 0b nop
+ 6f4: 00 breakpoint
+ 6f5: 00 breakpoint
+ 6f6: 03 .byte 3
+ 6f7: 24 lessthan
+ 6f8: 00 breakpoint
+ 6f9: 03 .byte 3
+ 6fa: 08 load
+ 6fb: 0b nop
+ 6fc: 0b nop
+ 6fd: 3e halfmult
+ 6fe: 0b nop
+ 6ff: 00 breakpoint
+ 700: 00 breakpoint
+ 701: 04 poppc
+ 702: 16 addsp 24
+ 703: 00 breakpoint
+ 704: 03 .byte 3
+ 705: 0e .byte 14
+ 706: 3a config
+ 707: 0b nop
+ 708: 3b pushpc
+ 709: 05 add
+ 70a: 49 storesp 100
+ 70b: 13 addsp 12
+ 70c: 00 breakpoint
+ 70d: 00 breakpoint
+ 70e: 05 add
+ 70f: 17 addsp 28
+ 710: 01 .byte 1
+ 711: 01 .byte 1
+ 712: 13 addsp 12
+ 713: 0b nop
+ 714: 0b nop
+ 715: 3a config
+ 716: 0b nop
+ 717: 3b pushpc
+ 718: 0b nop
+ 719: 00 breakpoint
+ 71a: 00 breakpoint
+ 71b: 06 and
+ 71c: 0d popsp
+ 71d: 00 breakpoint
+ 71e: 03 .byte 3
+ 71f: 0e .byte 14
+ 720: 3a config
+ 721: 0b nop
+ 722: 3b pushpc
+ 723: 0b nop
+ 724: 49 storesp 100
+ 725: 13 addsp 12
+ 726: 00 breakpoint
+ 727: 00 breakpoint
+ 728: 07 or
+ 729: 01 .byte 1
+ 72a: 01 .byte 1
+ 72b: 01 .byte 1
+ 72c: 13 addsp 12
+ 72d: 49 storesp 100
+ 72e: 13 addsp 12
+ 72f: 00 breakpoint
+ 730: 00 breakpoint
+ 731: 08 load
+ 732: 21 .byte 33
+ 733: 00 breakpoint
+ 734: 49 storesp 100
+ 735: 13 addsp 12
+ 736: 2f neq
+ 737: 0b nop
+ 738: 00 breakpoint
+ 739: 00 breakpoint
+ 73a: 09 not
+ 73b: 13 addsp 12
+ 73c: 01 .byte 1
+ 73d: 01 .byte 1
+ 73e: 13 addsp 12
+ 73f: 0b nop
+ 740: 0b nop
+ 741: 3a config
+ 742: 0b nop
+ 743: 3b pushpc
+ 744: 0b nop
+ 745: 00 breakpoint
+ 746: 00 breakpoint
+ 747: 0a flip
+ 748: 0d popsp
+ 749: 00 breakpoint
+ 74a: 03 .byte 3
+ 74b: 0e .byte 14
+ 74c: 3a config
+ 74d: 0b nop
+ 74e: 3b pushpc
+ 74f: 0b nop
+ 750: 49 storesp 100
+ 751: 13 addsp 12
+ 752: 38 neqbranch
+ 753: 0a flip
+ 754: 00 breakpoint
+ 755: 00 breakpoint
+ 756: 0b nop
+ 757: 16 addsp 24
+ 758: 00 breakpoint
+ 759: 03 .byte 3
+ 75a: 0e .byte 14
+ 75b: 3a config
+ 75c: 0b nop
+ 75d: 3b pushpc
+ 75e: 0b nop
+ 75f: 49 storesp 100
+ 760: 13 addsp 12
+ 761: 00 breakpoint
+ 762: 00 breakpoint
+ 763: 0c store
+ 764: 0f .byte 15
+ 765: 00 breakpoint
+ 766: 0b nop
+ 767: 0b nop
+ 768: 00 breakpoint
+ 769: 00 breakpoint
+ 76a: 0d popsp
+ 76b: 13 addsp 12
+ 76c: 01 .byte 1
+ 76d: 01 .byte 1
+ 76e: 13 addsp 12
+ 76f: 03 .byte 3
+ 770: 0e .byte 14
+ 771: 0b nop
+ 772: 0b nop
+ 773: 3a config
+ 774: 0b nop
+ 775: 3b pushpc
+ 776: 0b nop
+ 777: 00 breakpoint
+ 778: 00 breakpoint
+ 779: 0e .byte 14
+ 77a: 0d popsp
+ 77b: 00 breakpoint
+ 77c: 03 .byte 3
+ 77d: 08 load
+ 77e: 3a config
+ 77f: 0b nop
+ 780: 3b pushpc
+ 781: 0b nop
+ 782: 49 storesp 100
+ 783: 13 addsp 12
+ 784: 38 neqbranch
+ 785: 0a flip
+ 786: 00 breakpoint
+ 787: 00 breakpoint
+ 788: 0f .byte 15
+ 789: 0f .byte 15
+ 78a: 00 breakpoint
+ 78b: 0b nop
+ 78c: 0b nop
+ 78d: 49 storesp 100
+ 78e: 13 addsp 12
+ 78f: 00 breakpoint
+ 790: 00 breakpoint
+ 791: 10 addsp 0
+ 792: 13 addsp 12
+ 793: 01 .byte 1
+ 794: 01 .byte 1
+ 795: 13 addsp 12
+ 796: 03 .byte 3
+ 797: 0e .byte 14
+ 798: 0b nop
+ 799: 05 add
+ 79a: 3a config
+ 79b: 0b nop
+ 79c: 3b pushpc
+ 79d: 0b nop
+ 79e: 00 breakpoint
+ 79f: 00 breakpoint
+ 7a0: 11 addsp 4
+ 7a1: 15 addsp 20
+ 7a2: 00 breakpoint
+ 7a3: 27 ulessthanorequal
+ 7a4: 0c store
+ 7a5: 00 breakpoint
+ 7a6: 00 breakpoint
+ 7a7: 12 addsp 8
+ 7a8: 0d popsp
+ 7a9: 00 breakpoint
+ 7aa: 03 .byte 3
+ 7ab: 0e .byte 14
+ 7ac: 3a config
+ 7ad: 0b nop
+ 7ae: 3b pushpc
+ 7af: 05 add
+ 7b0: 49 storesp 100
+ 7b1: 13 addsp 12
+ 7b2: 38 neqbranch
+ 7b3: 0a flip
+ 7b4: 00 breakpoint
+ 7b5: 00 breakpoint
+ 7b6: 13 addsp 12
+ 7b7: 15 addsp 20
+ 7b8: 01 .byte 1
+ 7b9: 01 .byte 1
+ 7ba: 13 addsp 12
+ 7bb: 27 ulessthanorequal
+ 7bc: 0c store
+ 7bd: 49 storesp 100
+ 7be: 13 addsp 12
+ 7bf: 00 breakpoint
+ 7c0: 00 breakpoint
+ 7c1: 14 addsp 16
+ 7c2: 05 add
+ 7c3: 00 breakpoint
+ 7c4: 49 storesp 100
+ 7c5: 13 addsp 12
+ 7c6: 00 breakpoint
+ 7c7: 00 breakpoint
+ 7c8: 15 addsp 20
+ 7c9: 26 ulessthan
+ 7ca: 00 breakpoint
+ 7cb: 49 storesp 100
+ 7cc: 13 addsp 12
+ 7cd: 00 breakpoint
+ 7ce: 00 breakpoint
+ 7cf: 16 addsp 24
+ 7d0: 13 addsp 12
+ 7d1: 01 .byte 1
+ 7d2: 01 .byte 1
+ 7d3: 13 addsp 12
+ 7d4: 03 .byte 3
+ 7d5: 0e .byte 14
+ 7d6: 0b nop
+ 7d7: 0b nop
+ 7d8: 3a config
+ 7d9: 0b nop
+ 7da: 3b pushpc
+ 7db: 05 add
+ 7dc: 00 breakpoint
+ 7dd: 00 breakpoint
+ 7de: 17 addsp 28
+ 7df: 13 addsp 12
+ 7e0: 01 .byte 1
+ 7e1: 01 .byte 1
+ 7e2: 13 addsp 12
+ 7e3: 0b nop
+ 7e4: 0b nop
+ 7e5: 3a config
+ 7e6: 0b nop
+ 7e7: 3b pushpc
+ 7e8: 05 add
+ 7e9: 00 breakpoint
+ 7ea: 00 breakpoint
+ 7eb: 18 addsp 32
+ 7ec: 17 addsp 28
+ 7ed: 01 .byte 1
+ 7ee: 01 .byte 1
+ 7ef: 13 addsp 12
+ 7f0: 0b nop
+ 7f1: 0b nop
+ 7f2: 3a config
+ 7f3: 0b nop
+ 7f4: 3b pushpc
+ 7f5: 05 add
+ 7f6: 00 breakpoint
+ 7f7: 00 breakpoint
+ 7f8: 19 addsp 36
+ 7f9: 0d popsp
+ 7fa: 00 breakpoint
+ 7fb: 03 .byte 3
+ 7fc: 0e .byte 14
+ 7fd: 3a config
+ 7fe: 0b nop
+ 7ff: 3b pushpc
+ 800: 05 add
+ 801: 49 storesp 100
+ 802: 13 addsp 12
+ 803: 00 breakpoint
+ 804: 00 breakpoint
+ 805: 1a addsp 40
+ 806: 15 addsp 20
+ 807: 01 .byte 1
+ 808: 01 .byte 1
+ 809: 13 addsp 12
+ 80a: 27 ulessthanorequal
+ 80b: 0c store
+ 80c: 00 breakpoint
+ 80d: 00 breakpoint
+ 80e: 1b addsp 44
+ 80f: 34 storeb
+ 810: 00 breakpoint
+ 811: 03 .byte 3
+ 812: 0e .byte 14
+ 813: 3a config
+ 814: 0b nop
+ 815: 3b pushpc
+ 816: 0b nop
+ 817: 49 storesp 100
+ 818: 13 addsp 12
+ 819: 3f callpcrel
+ 81a: 0c store
+ 81b: 02 pushsp
+ 81c: 0a flip
+ 81d: 00 breakpoint
+ 81e: 00 breakpoint
+ 81f: 1c addsp 48
+ 820: 34 storeb
+ 821: 00 breakpoint
+ 822: 03 .byte 3
+ 823: 0e .byte 14
+ 824: 3a config
+ 825: 0b nop
+ 826: 3b pushpc
+ 827: 0b nop
+ 828: 49 storesp 100
+ 829: 13 addsp 12
+ 82a: 02 pushsp
+ 82b: 0a flip
+ 82c: 00 breakpoint
+ ...
+
+0000082f <.Ldebug_abbrev0>:
+ 82f: 01 .byte 1
+ 830: 11 addsp 4
+ 831: 01 .byte 1
+ 832: 10 addsp 0
+ 833: 06 and
+ 834: 12 addsp 8
+ 835: 01 .byte 1
+ 836: 11 addsp 4
+ 837: 01 .byte 1
+ 838: 25 lessthanorequal
+ 839: 0e .byte 14
+ 83a: 13 addsp 12
+ 83b: 0b nop
+ 83c: 03 .byte 3
+ 83d: 0e .byte 14
+ 83e: 1b addsp 44
+ 83f: 0e .byte 14
+ 840: 00 breakpoint
+ 841: 00 breakpoint
+ 842: 02 pushsp
+ 843: 24 lessthan
+ 844: 00 breakpoint
+ 845: 03 .byte 3
+ 846: 0e .byte 14
+ 847: 0b nop
+ 848: 0b nop
+ 849: 3e halfmult
+ 84a: 0b nop
+ 84b: 00 breakpoint
+ 84c: 00 breakpoint
+ 84d: 03 .byte 3
+ 84e: 24 lessthan
+ 84f: 00 breakpoint
+ 850: 03 .byte 3
+ 851: 08 load
+ 852: 0b nop
+ 853: 0b nop
+ 854: 3e halfmult
+ 855: 0b nop
+ 856: 00 breakpoint
+ 857: 00 breakpoint
+ 858: 04 poppc
+ 859: 0f .byte 15
+ 85a: 00 breakpoint
+ 85b: 0b nop
+ 85c: 0b nop
+ 85d: 00 breakpoint
+ 85e: 00 breakpoint
+ 85f: 05 add
+ 860: 0f .byte 15
+ 861: 00 breakpoint
+ 862: 0b nop
+ 863: 0b nop
+ 864: 49 storesp 100
+ 865: 13 addsp 12
+ 866: 00 breakpoint
+ 867: 00 breakpoint
+ 868: 06 and
+ 869: 16 addsp 24
+ 86a: 00 breakpoint
+ 86b: 03 .byte 3
+ 86c: 0e .byte 14
+ 86d: 3a config
+ 86e: 0b nop
+ 86f: 3b pushpc
+ 870: 0b nop
+ 871: 49 storesp 100
+ 872: 13 addsp 12
+ 873: 00 breakpoint
+ 874: 00 breakpoint
+ 875: 07 or
+ 876: 2e eq
+ 877: 01 .byte 1
+ 878: 01 .byte 1
+ 879: 13 addsp 12
+ 87a: 3f callpcrel
+ 87b: 0c store
+ 87c: 03 .byte 3
+ 87d: 0e .byte 14
+ 87e: 3a config
+ 87f: 0b nop
+ 880: 3b pushpc
+ 881: 0b nop
+ 882: 27 ulessthanorequal
+ 883: 0c store
+ 884: 49 storesp 100
+ 885: 13 addsp 12
+ 886: 11 addsp 4
+ 887: 01 .byte 1
+ 888: 12 addsp 8
+ 889: 01 .byte 1
+ 88a: 40 storesp 64
+ 88b: 0a flip
+ 88c: 00 breakpoint
+ 88d: 00 breakpoint
+ 88e: 08 load
+ 88f: 05 add
+ 890: 00 breakpoint
+ 891: 03 .byte 3
+ 892: 08 load
+ 893: 3a config
+ 894: 0b nop
+ 895: 3b pushpc
+ 896: 0b nop
+ 897: 49 storesp 100
+ 898: 13 addsp 12
+ 899: 02 pushsp
+ 89a: 0a flip
+ 89b: 00 breakpoint
+ 89c: 00 breakpoint
+ 89d: 09 not
+ 89e: 34 storeb
+ 89f: 00 breakpoint
+ 8a0: 03 .byte 3
+ 8a1: 08 load
+ 8a2: 3a config
+ 8a3: 0b nop
+ 8a4: 3b pushpc
+ 8a5: 0b nop
+ 8a6: 49 storesp 100
+ 8a7: 13 addsp 12
+ 8a8: 02 pushsp
+ 8a9: 0a flip
+ 8aa: 00 breakpoint
+ 8ab: 00 breakpoint
+ 8ac: 0a flip
+ 8ad: 34 storeb
+ 8ae: 00 breakpoint
+ 8af: 03 .byte 3
+ 8b0: 08 load
+ 8b1: 3a config
+ 8b2: 0b nop
+ 8b3: 3b pushpc
+ 8b4: 0b nop
+ 8b5: 49 storesp 100
+ 8b6: 13 addsp 12
+ 8b7: 00 breakpoint
+ 8b8: 00 breakpoint
+ 8b9: 0b nop
+ 8ba: 34 storeb
+ 8bb: 00 breakpoint
+ 8bc: 03 .byte 3
+ 8bd: 0e .byte 14
+ 8be: 3a config
+ 8bf: 0b nop
+ 8c0: 3b pushpc
+ 8c1: 0b nop
+ 8c2: 49 storesp 100
+ 8c3: 13 addsp 12
+ 8c4: 02 pushsp
+ 8c5: 0a flip
+ 8c6: 00 breakpoint
+ ...
+
+000008c9 <.Ldebug_abbrev0>:
+ 8c9: 01 .byte 1
+ 8ca: 11 addsp 4
+ 8cb: 01 .byte 1
+ 8cc: 10 addsp 0
+ 8cd: 06 and
+ 8ce: 12 addsp 8
+ 8cf: 01 .byte 1
+ 8d0: 11 addsp 4
+ 8d1: 01 .byte 1
+ 8d2: 25 lessthanorequal
+ 8d3: 0e .byte 14
+ 8d4: 13 addsp 12
+ 8d5: 0b nop
+ 8d6: 03 .byte 3
+ 8d7: 0e .byte 14
+ 8d8: 1b addsp 44
+ 8d9: 0e .byte 14
+ 8da: 00 breakpoint
+ 8db: 00 breakpoint
+ 8dc: 02 pushsp
+ 8dd: 24 lessthan
+ 8de: 00 breakpoint
+ 8df: 03 .byte 3
+ 8e0: 0e .byte 14
+ 8e1: 0b nop
+ 8e2: 0b nop
+ 8e3: 3e halfmult
+ 8e4: 0b nop
+ 8e5: 00 breakpoint
+ 8e6: 00 breakpoint
+ 8e7: 03 .byte 3
+ 8e8: 24 lessthan
+ 8e9: 00 breakpoint
+ 8ea: 03 .byte 3
+ 8eb: 08 load
+ 8ec: 0b nop
+ 8ed: 0b nop
+ 8ee: 3e halfmult
+ 8ef: 0b nop
+ 8f0: 00 breakpoint
+ 8f1: 00 breakpoint
+ 8f2: 04 poppc
+ 8f3: 0f .byte 15
+ 8f4: 00 breakpoint
+ 8f5: 0b nop
+ 8f6: 0b nop
+ 8f7: 49 storesp 100
+ 8f8: 13 addsp 12
+ 8f9: 00 breakpoint
+ 8fa: 00 breakpoint
+ 8fb: 05 add
+ 8fc: 26 ulessthan
+ 8fd: 00 breakpoint
+ 8fe: 49 storesp 100
+ 8ff: 13 addsp 12
+ 900: 00 breakpoint
+ 901: 00 breakpoint
+ 902: 06 and
+ 903: 16 addsp 24
+ 904: 00 breakpoint
+ 905: 03 .byte 3
+ 906: 0e .byte 14
+ 907: 3a config
+ 908: 0b nop
+ 909: 3b pushpc
+ 90a: 0b nop
+ 90b: 49 storesp 100
+ 90c: 13 addsp 12
+ 90d: 00 breakpoint
+ 90e: 00 breakpoint
+ 90f: 07 or
+ 910: 2e eq
+ 911: 01 .byte 1
+ 912: 01 .byte 1
+ 913: 13 addsp 12
+ 914: 3f callpcrel
+ 915: 0c store
+ 916: 03 .byte 3
+ 917: 0e .byte 14
+ 918: 3a config
+ 919: 0b nop
+ 91a: 3b pushpc
+ 91b: 0b nop
+ 91c: 27 ulessthanorequal
+ 91d: 0c store
+ 91e: 49 storesp 100
+ 91f: 13 addsp 12
+ 920: 11 addsp 4
+ 921: 01 .byte 1
+ 922: 12 addsp 8
+ 923: 01 .byte 1
+ 924: 40 storesp 64
+ 925: 0a flip
+ 926: 00 breakpoint
+ 927: 00 breakpoint
+ 928: 08 load
+ 929: 05 add
+ 92a: 00 breakpoint
+ 92b: 03 .byte 3
+ 92c: 08 load
+ 92d: 3a config
+ 92e: 0b nop
+ 92f: 3b pushpc
+ 930: 0b nop
+ 931: 49 storesp 100
+ 932: 13 addsp 12
+ 933: 02 pushsp
+ 934: 0a flip
+ 935: 00 breakpoint
+ 936: 00 breakpoint
+ 937: 09 not
+ 938: 34 storeb
+ 939: 00 breakpoint
+ 93a: 03 .byte 3
+ 93b: 0e .byte 14
+ 93c: 3a config
+ 93d: 0b nop
+ 93e: 3b pushpc
+ 93f: 0b nop
+ 940: 49 storesp 100
+ 941: 13 addsp 12
+ 942: 02 pushsp
+ 943: 0a flip
+ 944: 00 breakpoint
+ ...
+Disassembly of section .debug_line:
+
+00000000 <.Ldebug_line0>:
+ 0: 00 breakpoint
+ 1: 00 breakpoint
+ 2: 02 pushsp
+ 3: 69 loadsp 100
+ 4: 00 breakpoint
+ 5: 02 pushsp
+ 6: 00 breakpoint
+ 7: 00 breakpoint
+ 8: 01 .byte 1
+ 9: 2f neq
+ a: 01 .byte 1
+ b: 01 .byte 1
+ c: f6 im -10
+ d: f5 im -11
+ e: 0a flip
+ f: 00 breakpoint
+ 10: 01 .byte 1
+ 11: 01 .byte 1
+ 12: 01 .byte 1
+ 13: 01 .byte 1
+ 14: 00 breakpoint
+ 15: 00 breakpoint
+ 16: 00 breakpoint
+ 17: 01 .byte 1
+ 18: 2e eq
+ 19: 2e eq
+ 1a: 2f neq
+ 1b: 2e eq
+ 1c: 2e eq
+ 1d: 2f neq
+ 1e: 2e eq
+ 1f: 2e eq
+ 20: 2f neq
+ 21: 2e eq
+ 22: 2e eq
+ 23: 2f neq
+ 24: 67 loadsp 92
+ 25: 63 loadsp 76
+ 26: 63 loadsp 76
+ 27: 2f neq
+ 28: 6c loadsp 112
+ 29: 69 loadsp 100
+ 2a: 62 loadsp 72
+ 2b: 67 loadsp 92
+ 2c: 6c loadsp 112
+ 2d: 6f loadsp 124
+ 2e: 73 loadsp 12
+ 2f: 73 loadsp 12
+ 30: 2f neq
+ 31: 7a loadsp 40
+ 32: 70 loadsp 0
+ 33: 75 loadsp 20
+ 34: 00 breakpoint
+ 35: 2f neq
+ 36: 68 loadsp 96
+ 37: 6f loadsp 124
+ 38: 6d loadsp 116
+ 39: 65 loadsp 84
+ 3a: 2f neq
+ 3b: 6f loadsp 124
+ 3c: 79 loadsp 36
+ 3d: 76 loadsp 24
+ 3e: 69 loadsp 100
+ 3f: 6e loadsp 120
+ 40: 64 loadsp 80
+ 41: 2f neq
+ 42: 74 loadsp 16
+ 43: 6f loadsp 124
+ 44: 6f loadsp 124
+ 45: 6c loadsp 112
+ 46: 63 loadsp 76
+ 47: 68 loadsp 96
+ 48: 61 loadsp 68
+ 49: 69 loadsp 100
+ 4a: 6e loadsp 120
+ 4b: 2f neq
+ 4c: 74 loadsp 16
+ 4d: 6f loadsp 124
+ 4e: 6f loadsp 124
+ 4f: 6c loadsp 112
+ 50: 63 loadsp 76
+ 51: 68 loadsp 96
+ 52: 61 loadsp 68
+ 53: 69 loadsp 100
+ 54: 6e loadsp 120
+ 55: 2f neq
+ 56: 67 loadsp 92
+ 57: 63 loadsp 76
+ 58: 63 loadsp 76
+ 59: 2f neq
+ 5a: 6e loadsp 120
+ 5b: 65 loadsp 84
+ 5c: 77 loadsp 28
+ 5d: 6c loadsp 112
+ 5e: 69 loadsp 100
+ 5f: 62 loadsp 72
+ 60: 2f neq
+ 61: 6c loadsp 112
+ 62: 69 loadsp 100
+ 63: 62 loadsp 72
+ 64: 63 loadsp 76
+ 65: 2f neq
+ 66: 69 loadsp 100
+ 67: 6e loadsp 120
+ 68: 63 loadsp 76
+ 69: 6c loadsp 112
+ 6a: 75 loadsp 20
+ 6b: 64 loadsp 80
+ 6c: 65 loadsp 84
+ 6d: 00 breakpoint
+ 6e: 2f neq
+ 6f: 68 loadsp 96
+ 70: 6f loadsp 124
+ 71: 6d loadsp 116
+ 72: 65 loadsp 84
+ 73: 2f neq
+ 74: 6f loadsp 124
+ 75: 79 loadsp 36
+ 76: 76 loadsp 24
+ 77: 69 loadsp 100
+ 78: 6e loadsp 120
+ 79: 64 loadsp 80
+ 7a: 2f neq
+ 7b: 74 loadsp 16
+ 7c: 6f loadsp 124
+ 7d: 6f loadsp 124
+ 7e: 6c loadsp 112
+ 7f: 63 loadsp 76
+ 80: 68 loadsp 96
+ 81: 61 loadsp 68
+ 82: 69 loadsp 100
+ 83: 6e loadsp 120
+ 84: 2f neq
+ 85: 74 loadsp 16
+ 86: 6f loadsp 124
+ 87: 6f loadsp 124
+ 88: 6c loadsp 112
+ 89: 63 loadsp 76
+ 8a: 68 loadsp 96
+ 8b: 61 loadsp 68
+ 8c: 69 loadsp 100
+ 8d: 6e loadsp 120
+ 8e: 2f neq
+ 8f: 67 loadsp 92
+ 90: 63 loadsp 76
+ 91: 63 loadsp 76
+ 92: 62 loadsp 72
+ 93: 75 loadsp 20
+ 94: 69 loadsp 100
+ 95: 6c loadsp 112
+ 96: 64 loadsp 80
+ 97: 2f neq
+ 98: 67 loadsp 92
+ 99: 63 loadsp 76
+ 9a: 63 loadsp 76
+ 9b: 2f neq
+ 9c: 69 loadsp 100
+ 9d: 6e loadsp 120
+ 9e: 63 loadsp 76
+ 9f: 6c loadsp 112
+ a0: 75 loadsp 20
+ a1: 64 loadsp 80
+ a2: 65 loadsp 84
+ a3: 00 breakpoint
+ a4: 00 breakpoint
+ a5: 73 loadsp 12
+ a6: 74 loadsp 16
+ a7: 64 loadsp 80
+ a8: 64 loadsp 80
+ a9: 65 loadsp 84
+ aa: 66 loadsp 88
+ ab: 2e eq
+ ac: 68 loadsp 96
+ ad: 00 breakpoint
+ ae: 03 .byte 3
+ af: 00 breakpoint
+ b0: 00 breakpoint
+ b1: 73 loadsp 12
+ b2: 74 loadsp 16
+ b3: 64 loadsp 80
+ b4: 61 loadsp 68
+ b5: 72 loadsp 8
+ b6: 67 loadsp 92
+ b7: 2e eq
+ b8: 68 loadsp 96
+ b9: 00 breakpoint
+ ba: 03 .byte 3
+ bb: 00 breakpoint
+ bc: 00 breakpoint
+ bd: 73 loadsp 12
+ be: 79 loadsp 36
+ bf: 73 loadsp 12
+ c0: 2f neq
+ c1: 5f storesp 60
+ c2: 74 loadsp 16
+ c3: 79 loadsp 36
+ c4: 70 loadsp 0
+ c5: 65 loadsp 84
+ c6: 73 loadsp 12
+ c7: 2e eq
+ c8: 68 loadsp 96
+ c9: 00 breakpoint
+ ca: 02 pushsp
+ cb: 00 breakpoint
+ cc: 00 breakpoint
+ cd: 73 loadsp 12
+ ce: 79 loadsp 36
+ cf: 73 loadsp 12
+ d0: 2f neq
+ d1: 72 loadsp 8
+ d2: 65 loadsp 84
+ d3: 65 loadsp 84
+ d4: 6e loadsp 120
+ d5: 74 loadsp 16
+ d6: 2e eq
+ d7: 68 loadsp 96
+ d8: 00 breakpoint
+ d9: 02 pushsp
+ da: 00 breakpoint
+ db: 00 breakpoint
+ dc: 73 loadsp 12
+ dd: 79 loadsp 36
+ de: 73 loadsp 12
+ df: 2f neq
+ e0: 74 loadsp 16
+ e1: 79 loadsp 36
+ e2: 70 loadsp 0
+ e3: 65 loadsp 84
+ e4: 73 loadsp 12
+ e5: 2e eq
+ e6: 68 loadsp 96
+ e7: 00 breakpoint
+ e8: 02 pushsp
+ e9: 00 breakpoint
+ ea: 00 breakpoint
+ eb: 6d loadsp 116
+ ec: 61 loadsp 68
+ ed: 63 loadsp 76
+ ee: 68 loadsp 96
+ ef: 69 loadsp 100
+ f0: 6e loadsp 120
+ f1: 65 loadsp 84
+ f2: 2f neq
+ f3: 74 loadsp 16
+ f4: 79 loadsp 36
+ f5: 70 loadsp 0
+ f6: 65 loadsp 84
+ f7: 73 loadsp 12
+ f8: 2e eq
+ f9: 68 loadsp 96
+ fa: 00 breakpoint
+ fb: 02 pushsp
+ fc: 00 breakpoint
+ fd: 00 breakpoint
+ fe: 73 loadsp 12
+ ff: 74 loadsp 16
+ 100: 64 loadsp 80
+ 101: 69 loadsp 100
+ 102: 6f loadsp 124
+ 103: 2e eq
+ 104: 68 loadsp 96
+ 105: 00 breakpoint
+ 106: 02 pushsp
+ 107: 00 breakpoint
+ 108: 00 breakpoint
+ 109: 65 loadsp 84
+ 10a: 72 loadsp 8
+ 10b: 72 loadsp 8
+ 10c: 6e loadsp 120
+ 10d: 6f loadsp 124
+ 10e: 2e eq
+ 10f: 68 loadsp 96
+ 110: 00 breakpoint
+ 111: 02 pushsp
+ 112: 00 breakpoint
+ 113: 00 breakpoint
+ 114: 74 loadsp 16
+ 115: 69 loadsp 100
+ 116: 6d loadsp 116
+ 117: 65 loadsp 84
+ 118: 2e eq
+ 119: 68 loadsp 96
+ 11a: 00 breakpoint
+ 11b: 02 pushsp
+ 11c: 00 breakpoint
+ 11d: 00 breakpoint
+ 11e: 73 loadsp 12
+ 11f: 79 loadsp 36
+ 120: 73 loadsp 12
+ 121: 2f neq
+ 122: 73 loadsp 12
+ 123: 74 loadsp 16
+ 124: 61 loadsp 68
+ 125: 74 loadsp 16
+ 126: 2e eq
+ 127: 68 loadsp 96
+ 128: 00 breakpoint
+ 129: 02 pushsp
+ 12a: 00 breakpoint
+ 12b: 00 breakpoint
+ 12c: 63 loadsp 76
+ 12d: 72 loadsp 8
+ 12e: 74 loadsp 16
+ 12f: 5f storesp 60
+ 130: 69 loadsp 100
+ 131: 6f loadsp 124
+ 132: 2e eq
+ 133: 63 loadsp 76
+ 134: 00 breakpoint
+ 135: 01 .byte 1
+ 136: 00 breakpoint
+ 137: 00 breakpoint
+ 138: 00 breakpoint
+ 139: 00 breakpoint
+ 13a: 05 add
+ 13b: 02 pushsp
+ 13c: 00 breakpoint
+ 13d: 00 breakpoint
+ 13e: 00 breakpoint
+ 13f: 00 breakpoint
+ 140: 00 breakpoint
+ 141: 01 .byte 1
+ 142: 01 .byte 1
+ 143: 00 breakpoint
+ 144: 05 add
+ 145: 02 pushsp
+ 146: 00 breakpoint
+ 147: 00 breakpoint
+ 148: 00 breakpoint
+ 149: 00 breakpoint
+ 14a: 04 poppc
+ 14b: 0b nop
+ 14c: 2b ashiftleft
+ 14d: 00 breakpoint
+ 14e: 05 add
+ 14f: 02 pushsp
+ 150: 00 breakpoint
+ 151: 00 breakpoint
+ 152: 00 breakpoint
+ 153: 00 breakpoint
+ 154: 18 addsp 32
+ 155: 00 breakpoint
+ 156: 05 add
+ 157: 02 pushsp
+ 158: 00 breakpoint
+ 159: 00 breakpoint
+ 15a: 00 breakpoint
+ 15b: 00 breakpoint
+ 15c: 15 addsp 20
+ 15d: 00 breakpoint
+ 15e: 05 add
+ 15f: 02 pushsp
+ 160: 00 breakpoint
+ 161: 00 breakpoint
+ 162: 00 breakpoint
+ 163: 00 breakpoint
+ 164: 16 addsp 24
+ 165: 00 breakpoint
+ 166: 05 add
+ 167: 02 pushsp
+ 168: 00 breakpoint
+ 169: 00 breakpoint
+ 16a: 00 breakpoint
+ 16b: 00 breakpoint
+ 16c: 17 addsp 28
+ 16d: 00 breakpoint
+ 16e: 05 add
+ 16f: 02 pushsp
+ 170: 00 breakpoint
+ 171: 00 breakpoint
+ 172: 00 breakpoint
+ 173: 00 breakpoint
+ 174: 00 breakpoint
+ 175: 01 .byte 1
+ 176: 01 .byte 1
+ 177: 00 breakpoint
+ 178: 05 add
+ 179: 02 pushsp
+ 17a: 00 breakpoint
+ 17b: 00 breakpoint
+ 17c: 00 breakpoint
+ 17d: 00 breakpoint
+ 17e: 04 poppc
+ 17f: 0b nop
+ 180: 3f callpcrel
+ 181: 00 breakpoint
+ 182: 05 add
+ 183: 02 pushsp
+ 184: 00 breakpoint
+ 185: 00 breakpoint
+ 186: 00 breakpoint
+ 187: 00 breakpoint
+ 188: 16 addsp 24
+ 189: 00 breakpoint
+ 18a: 05 add
+ 18b: 02 pushsp
+ 18c: 00 breakpoint
+ 18d: 00 breakpoint
+ 18e: 00 breakpoint
+ 18f: 00 breakpoint
+ 190: 15 addsp 20
+ 191: 00 breakpoint
+ 192: 05 add
+ 193: 02 pushsp
+ 194: 00 breakpoint
+ 195: 00 breakpoint
+ 196: 00 breakpoint
+ 197: 00 breakpoint
+ 198: 00 breakpoint
+ 199: 01 .byte 1
+ 19a: 01 .byte 1
+ 19b: 00 breakpoint
+ 19c: 05 add
+ 19d: 02 pushsp
+ 19e: 00 breakpoint
+ 19f: 00 breakpoint
+ 1a0: 04 poppc
+ 1a1: 5f storesp 60
+ 1a2: 04 poppc
+ 1a3: 0b nop
+ 1a4: 48 storesp 96
+ 1a5: 00 breakpoint
+ 1a6: 05 add
+ 1a7: 02 pushsp
+ 1a8: 00 breakpoint
+ 1a9: 00 breakpoint
+ 1aa: 04 poppc
+ 1ab: 5f storesp 60
+ 1ac: 15 addsp 20
+ 1ad: 00 breakpoint
+ 1ae: 05 add
+ 1af: 02 pushsp
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+ 1b1: 00 breakpoint
+ 1b2: 04 poppc
+ 1b3: 66 loadsp 88
+ 1b4: 16 addsp 24
+ 1b5: 00 breakpoint
+ 1b6: 05 add
+ 1b7: 02 pushsp
+ 1b8: 00 breakpoint
+ 1b9: 00 breakpoint
+ 1ba: 04 poppc
+ 1bb: 6d loadsp 116
+ 1bc: 1d addsp 52
+ 1bd: 00 breakpoint
+ 1be: 05 add
+ 1bf: 02 pushsp
+ 1c0: 00 breakpoint
+ 1c1: 00 breakpoint
+ 1c2: 04 poppc
+ 1c3: 77 loadsp 28
+ 1c4: 15 addsp 20
+ 1c5: 00 breakpoint
+ 1c6: 05 add
+ 1c7: 02 pushsp
+ 1c8: 00 breakpoint
+ 1c9: 00 breakpoint
+ 1ca: 04 poppc
+ 1cb: 7e loadsp 56
+ 1cc: 15 addsp 20
+ 1cd: 00 breakpoint
+ 1ce: 05 add
+ 1cf: 02 pushsp
+ 1d0: 00 breakpoint
+ 1d1: 00 breakpoint
+ 1d2: 04 poppc
+ 1d3: 85 im 5
+ 1d4: 1c addsp 48
+ 1d5: 00 breakpoint
+ 1d6: 05 add
+ 1d7: 02 pushsp
+ 1d8: 00 breakpoint
+ 1d9: 00 breakpoint
+ 1da: 04 poppc
+ 1db: 86 im 6
+ 1dc: 10 addsp 0
+ 1dd: 00 breakpoint
+ 1de: 05 add
+ 1df: 02 pushsp
+ 1e0: 00 breakpoint
+ 1e1: 00 breakpoint
+ 1e2: 04 poppc
+ 1e3: 92 im 18
+ 1e4: 15 addsp 20
+ 1e5: 00 breakpoint
+ 1e6: 05 add
+ 1e7: 02 pushsp
+ 1e8: 00 breakpoint
+ 1e9: 00 breakpoint
+ 1ea: 04 poppc
+ 1eb: 9b im 27
+ 1ec: 15 addsp 20
+ 1ed: 00 breakpoint
+ 1ee: 05 add
+ 1ef: 02 pushsp
+ 1f0: 00 breakpoint
+ 1f1: 00 breakpoint
+ 1f2: 04 poppc
+ 1f3: a4 im 36
+ 1f4: 16 addsp 24
+ 1f5: 00 breakpoint
+ 1f6: 05 add
+ 1f7: 02 pushsp
+ 1f8: 00 breakpoint
+ 1f9: 00 breakpoint
+ 1fa: 04 poppc
+ 1fb: a5 im 37
+ 1fc: 03 .byte 3
+ 1fd: 70 loadsp 0
+ 1fe: 01 .byte 1
+ 1ff: 00 breakpoint
+ 200: 05 add
+ 201: 02 pushsp
+ 202: 00 breakpoint
+ 203: 00 breakpoint
+ 204: 04 poppc
+ 205: b1 im 49
+ 206: 15 addsp 20
+ 207: 00 breakpoint
+ 208: 05 add
+ 209: 02 pushsp
+ 20a: 00 breakpoint
+ 20b: 00 breakpoint
+ 20c: 04 poppc
+ 20d: ba im 58
+ 20e: 15 addsp 20
+ 20f: 00 breakpoint
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+
+00000287 <.Ldebug_line0>:
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+0000049d <.Ldebug_line0>:
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+ ad6: 01 .byte 1
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+ ad9: 0e .byte 14
+ ada: 0a flip
+ adb: 00 breakpoint
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+ ade: 01 .byte 1
+ adf: 01 .byte 1
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+ ae3: 01 .byte 1
+ ...
+
+00000ae6 <.Ldebug_line0>:
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+ af5: 00 breakpoint
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+ b0d: 67 loadsp 92
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+ b22: 00 breakpoint
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+ b5b: 00 breakpoint
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+ b73: 74 loadsp 16
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+ ba2: 5f storesp 60
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+ bb4: 2e eq
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+ bb6: 00 breakpoint
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+ bb9: 00 breakpoint
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+ bc3: 2e eq
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+ bc5: 00 breakpoint
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+ bc8: 00 breakpoint
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+ bd2: 79 loadsp 36
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+ bd6: 2e eq
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+ bd8: 00 breakpoint
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+ be1: 2e eq
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+ be3: 00 breakpoint
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+ c08: 00 breakpoint
+ c09: 00 breakpoint
+ c0a: 01 .byte 1
+ c0b: 01 .byte 1
+ c0c: 00 breakpoint
+ c0d: 00 breakpoint
+ c0e: 00 breakpoint
+ c0f: 16 addsp 24
+ c10: 00 breakpoint
+ c11: 02 pushsp
+ c12: 00 breakpoint
+ c13: 00 breakpoint
+ c14: 00 breakpoint
+ c15: 10 addsp 0
+ c16: 01 .byte 1
+ c17: 01 .byte 1
+ c18: fb im -5
+ c19: 0e .byte 14
+ c1a: 0a flip
+ c1b: 00 breakpoint
+ c1c: 01 .byte 1
+ c1d: 01 .byte 1
+ c1e: 01 .byte 1
+ c1f: 01 .byte 1
+ c20: 00 breakpoint
+ c21: 00 breakpoint
+ c22: 00 breakpoint
+ c23: 01 .byte 1
+ ...
+
+00000c26 <.Ldebug_line0>:
+ c26: 00 breakpoint
+ c27: 00 breakpoint
+ c28: 01 .byte 1
+ c29: 92 im 18
+ c2a: 00 breakpoint
+ c2b: 02 pushsp
+ c2c: 00 breakpoint
+ c2d: 00 breakpoint
+ c2e: 01 .byte 1
+ c2f: 08 load
+ c30: 01 .byte 1
+ c31: 01 .byte 1
+ c32: f6 im -10
+ c33: f5 im -11
+ c34: 0a flip
+ c35: 00 breakpoint
+ c36: 01 .byte 1
+ c37: 01 .byte 1
+ c38: 01 .byte 1
+ c39: 01 .byte 1
+ c3a: 00 breakpoint
+ c3b: 00 breakpoint
+ c3c: 00 breakpoint
+ c3d: 01 .byte 1
+ c3e: 2e eq
+ c3f: 2e eq
+ c40: 2f neq
+ c41: 2e eq
+ c42: 2e eq
+ c43: 2f neq
+ c44: 2e eq
+ c45: 2e eq
+ c46: 2f neq
+ c47: 2e eq
+ c48: 2e eq
+ c49: 2f neq
+ c4a: 2e eq
+ c4b: 2e eq
+ c4c: 2f neq
+ c4d: 67 loadsp 92
+ c4e: 63 loadsp 76
+ c4f: 63 loadsp 76
+ c50: 2f neq
+ c51: 6e loadsp 120
+ c52: 65 loadsp 84
+ c53: 77 loadsp 28
+ c54: 6c loadsp 112
+ c55: 69 loadsp 100
+ c56: 62 loadsp 72
+ c57: 2f neq
+ c58: 6c loadsp 112
+ c59: 69 loadsp 100
+ c5a: 62 loadsp 72
+ c5b: 63 loadsp 76
+ c5c: 2f neq
+ c5d: 73 loadsp 12
+ c5e: 74 loadsp 16
+ c5f: 64 loadsp 80
+ c60: 6c loadsp 112
+ c61: 69 loadsp 100
+ c62: 62 loadsp 72
+ c63: 00 breakpoint
+ c64: 2f neq
+ c65: 68 loadsp 96
+ c66: 6f loadsp 124
+ c67: 6d loadsp 116
+ c68: 65 loadsp 84
+ c69: 2f neq
+ c6a: 6f loadsp 124
+ c6b: 79 loadsp 36
+ c6c: 76 loadsp 24
+ c6d: 69 loadsp 100
+ c6e: 6e loadsp 120
+ c6f: 64 loadsp 80
+ c70: 2f neq
+ c71: 74 loadsp 16
+ c72: 6f loadsp 124
+ c73: 6f loadsp 124
+ c74: 6c loadsp 112
+ c75: 63 loadsp 76
+ c76: 68 loadsp 96
+ c77: 61 loadsp 68
+ c78: 69 loadsp 100
+ c79: 6e loadsp 120
+ c7a: 2f neq
+ c7b: 74 loadsp 16
+ c7c: 6f loadsp 124
+ c7d: 6f loadsp 124
+ c7e: 6c loadsp 112
+ c7f: 63 loadsp 76
+ c80: 68 loadsp 96
+ c81: 61 loadsp 68
+ c82: 69 loadsp 100
+ c83: 6e loadsp 120
+ c84: 2f neq
+ c85: 67 loadsp 92
+ c86: 63 loadsp 76
+ c87: 63 loadsp 76
+ c88: 2f neq
+ c89: 6e loadsp 120
+ c8a: 65 loadsp 84
+ c8b: 77 loadsp 28
+ c8c: 6c loadsp 112
+ c8d: 69 loadsp 100
+ c8e: 62 loadsp 72
+ c8f: 2f neq
+ c90: 6c loadsp 112
+ c91: 69 loadsp 100
+ c92: 62 loadsp 72
+ c93: 63 loadsp 76
+ c94: 2f neq
+ c95: 69 loadsp 100
+ c96: 6e loadsp 120
+ c97: 63 loadsp 76
+ c98: 6c loadsp 112
+ c99: 75 loadsp 20
+ c9a: 64 loadsp 80
+ c9b: 65 loadsp 84
+ c9c: 00 breakpoint
+ c9d: 2f neq
+ c9e: 68 loadsp 96
+ c9f: 6f loadsp 124
+ ca0: 6d loadsp 116
+ ca1: 65 loadsp 84
+ ca2: 2f neq
+ ca3: 6f loadsp 124
+ ca4: 79 loadsp 36
+ ca5: 76 loadsp 24
+ ca6: 69 loadsp 100
+ ca7: 6e loadsp 120
+ ca8: 64 loadsp 80
+ ca9: 2f neq
+ caa: 74 loadsp 16
+ cab: 6f loadsp 124
+ cac: 6f loadsp 124
+ cad: 6c loadsp 112
+ cae: 63 loadsp 76
+ caf: 68 loadsp 96
+ cb0: 61 loadsp 68
+ cb1: 69 loadsp 100
+ cb2: 6e loadsp 120
+ cb3: 2f neq
+ cb4: 74 loadsp 16
+ cb5: 6f loadsp 124
+ cb6: 6f loadsp 124
+ cb7: 6c loadsp 112
+ cb8: 63 loadsp 76
+ cb9: 68 loadsp 96
+ cba: 61 loadsp 68
+ cbb: 69 loadsp 100
+ cbc: 6e loadsp 120
+ cbd: 2f neq
+ cbe: 67 loadsp 92
+ cbf: 63 loadsp 76
+ cc0: 63 loadsp 76
+ cc1: 62 loadsp 72
+ cc2: 75 loadsp 20
+ cc3: 69 loadsp 100
+ cc4: 6c loadsp 112
+ cc5: 64 loadsp 80
+ cc6: 2f neq
+ cc7: 67 loadsp 92
+ cc8: 63 loadsp 76
+ cc9: 63 loadsp 76
+ cca: 2f neq
+ ccb: 69 loadsp 100
+ ccc: 6e loadsp 120
+ ccd: 63 loadsp 76
+ cce: 6c loadsp 112
+ ccf: 75 loadsp 20
+ cd0: 64 loadsp 80
+ cd1: 65 loadsp 84
+ cd2: 00 breakpoint
+ cd3: 00 breakpoint
+ cd4: 73 loadsp 12
+ cd5: 74 loadsp 16
+ cd6: 64 loadsp 80
+ cd7: 64 loadsp 80
+ cd8: 65 loadsp 84
+ cd9: 66 loadsp 88
+ cda: 2e eq
+ cdb: 68 loadsp 96
+ cdc: 00 breakpoint
+ cdd: 03 .byte 3
+ cde: 00 breakpoint
+ cdf: 00 breakpoint
+ ce0: 73 loadsp 12
+ ce1: 79 loadsp 36
+ ce2: 73 loadsp 12
+ ce3: 2f neq
+ ce4: 5f storesp 60
+ ce5: 74 loadsp 16
+ ce6: 79 loadsp 36
+ ce7: 70 loadsp 0
+ ce8: 65 loadsp 84
+ ce9: 73 loadsp 12
+ cea: 2e eq
+ ceb: 68 loadsp 96
+ cec: 00 breakpoint
+ ced: 02 pushsp
+ cee: 00 breakpoint
+ cef: 00 breakpoint
+ cf0: 73 loadsp 12
+ cf1: 79 loadsp 36
+ cf2: 73 loadsp 12
+ cf3: 2f neq
+ cf4: 72 loadsp 8
+ cf5: 65 loadsp 84
+ cf6: 65 loadsp 84
+ cf7: 6e loadsp 120
+ cf8: 74 loadsp 16
+ cf9: 2e eq
+ cfa: 68 loadsp 96
+ cfb: 00 breakpoint
+ cfc: 02 pushsp
+ cfd: 00 breakpoint
+ cfe: 00 breakpoint
+ cff: 73 loadsp 12
+ d00: 74 loadsp 16
+ d01: 64 loadsp 80
+ d02: 6c loadsp 112
+ d03: 69 loadsp 100
+ d04: 62 loadsp 72
+ d05: 2e eq
+ d06: 68 loadsp 96
+ d07: 00 breakpoint
+ d08: 02 pushsp
+ d09: 00 breakpoint
+ d0a: 00 breakpoint
+ d0b: 73 loadsp 12
+ d0c: 79 loadsp 36
+ d0d: 73 loadsp 12
+ d0e: 2f neq
+ d0f: 74 loadsp 16
+ d10: 79 loadsp 36
+ d11: 70 loadsp 0
+ d12: 65 loadsp 84
+ d13: 73 loadsp 12
+ d14: 2e eq
+ d15: 68 loadsp 96
+ d16: 00 breakpoint
+ d17: 02 pushsp
+ d18: 00 breakpoint
+ d19: 00 breakpoint
+ d1a: 6d loadsp 116
+ d1b: 61 loadsp 68
+ d1c: 63 loadsp 76
+ d1d: 68 loadsp 96
+ d1e: 69 loadsp 100
+ d1f: 6e loadsp 120
+ d20: 65 loadsp 84
+ d21: 2f neq
+ d22: 74 loadsp 16
+ d23: 79 loadsp 36
+ d24: 70 loadsp 0
+ d25: 65 loadsp 84
+ d26: 73 loadsp 12
+ d27: 2e eq
+ d28: 68 loadsp 96
+ d29: 00 breakpoint
+ d2a: 02 pushsp
+ d2b: 00 breakpoint
+ d2c: 00 breakpoint
+ d2d: 65 loadsp 84
+ d2e: 78 loadsp 32
+ d2f: 69 loadsp 100
+ d30: 74 loadsp 16
+ d31: 2e eq
+ d32: 63 loadsp 76
+ d33: 00 breakpoint
+ d34: 01 .byte 1
+ d35: 00 breakpoint
+ d36: 00 breakpoint
+ d37: 00 breakpoint
+ d38: 00 breakpoint
+ d39: 05 add
+ d3a: 02 pushsp
+ d3b: 00 breakpoint
+ d3c: 00 breakpoint
+ d3d: 07 or
+ d3e: 86 im 6
+ d3f: 04 poppc
+ d40: 07 or
+ d41: 50 storesp 0
+ d42: 00 breakpoint
+ d43: 05 add
+ d44: 02 pushsp
+ d45: 00 breakpoint
+ d46: 00 breakpoint
+ d47: 07 or
+ d48: 8a im 10
+ d49: 2c ashiftright
+ d4a: 00 breakpoint
+ d4b: 05 add
+ d4c: 02 pushsp
+ d4d: 00 breakpoint
+ d4e: 00 breakpoint
+ d4f: 07 or
+ d50: 94 im 20
+ d51: 1f addsp 60
+ d52: 00 breakpoint
+ d53: 05 add
+ d54: 02 pushsp
+ d55: 00 breakpoint
+ d56: 00 breakpoint
+ d57: 07 or
+ d58: 9a im 26
+ d59: 0c store
+ d5a: 00 breakpoint
+ d5b: 05 add
+ d5c: 02 pushsp
+ d5d: 00 breakpoint
+ d5e: 00 breakpoint
+ d5f: 07 or
+ d60: 9d im 29
+ d61: 16 addsp 24
+ d62: 00 breakpoint
+ d63: 05 add
+ d64: 02 pushsp
+ d65: 00 breakpoint
+ d66: 00 breakpoint
+ d67: 07 or
+ d68: bc im 60
+ d69: 15 addsp 20
+ d6a: 00 breakpoint
+ d6b: 05 add
+ d6c: 02 pushsp
+ d6d: 00 breakpoint
+ d6e: 00 breakpoint
+ d6f: 07 or
+ d70: c8 im -56
+ d71: 15 addsp 20
+ d72: 00 breakpoint
+ d73: 05 add
+ d74: 02 pushsp
+ d75: 00 breakpoint
+ d76: 00 breakpoint
+ d77: 07 or
+ d78: d5 im -43
+ d79: 12 addsp 8
+ d7a: 00 breakpoint
+ d7b: 05 add
+ d7c: 02 pushsp
+ d7d: 00 breakpoint
+ d7e: 00 breakpoint
+ d7f: 07 or
+ d80: e7 im -25
+ d81: 1a addsp 40
+ d82: 00 breakpoint
+ d83: 05 add
+ d84: 02 pushsp
+ d85: 00 breakpoint
+ d86: 00 breakpoint
+ d87: 07 or
+ d88: f2 im -14
+ d89: 18 addsp 32
+ d8a: 00 breakpoint
+ d8b: 05 add
+ d8c: 02 pushsp
+ d8d: 00 breakpoint
+ d8e: 00 breakpoint
+ d8f: 07 or
+ d90: f7 im -9
+ d91: 16 addsp 24
+ d92: 00 breakpoint
+ d93: 05 add
+ d94: 02 pushsp
+ d95: 00 breakpoint
+ d96: 00 breakpoint
+ d97: 07 or
+ d98: fc im -4
+ d99: 0c store
+ d9a: 00 breakpoint
+ d9b: 05 add
+ d9c: 02 pushsp
+ d9d: 00 breakpoint
+ d9e: 00 breakpoint
+ d9f: 08 load
+ da0: 01 .byte 1
+ da1: 10 addsp 0
+ da2: 00 breakpoint
+ da3: 05 add
+ da4: 02 pushsp
+ da5: 00 breakpoint
+ da6: 00 breakpoint
+ da7: 08 load
+ da8: 1b addsp 44
+ da9: 1f addsp 60
+ daa: 00 breakpoint
+ dab: 05 add
+ dac: 02 pushsp
+ dad: 00 breakpoint
+ dae: 00 breakpoint
+ daf: 08 load
+ db0: 23 storeh
+ db1: 15 addsp 20
+ db2: 00 breakpoint
+ db3: 05 add
+ db4: 02 pushsp
+ db5: 00 breakpoint
+ db6: 00 breakpoint
+ db7: 08 load
+ db8: 28 swap
+ db9: 00 breakpoint
+ dba: 01 .byte 1
+ dbb: 01 .byte 1
+ dbc: 00 breakpoint
+ dbd: 00 breakpoint
+ dbe: 00 breakpoint
+ dbf: 16 addsp 24
+ dc0: 00 breakpoint
+ dc1: 02 pushsp
+ dc2: 00 breakpoint
+ dc3: 00 breakpoint
+ dc4: 00 breakpoint
+ dc5: 10 addsp 0
+ dc6: 01 .byte 1
+ dc7: 01 .byte 1
+ dc8: fb im -5
+ dc9: 0e .byte 14
+ dca: 0a flip
+ dcb: 00 breakpoint
+ dcc: 01 .byte 1
+ dcd: 01 .byte 1
+ dce: 01 .byte 1
+ dcf: 01 .byte 1
+ dd0: 00 breakpoint
+ dd1: 00 breakpoint
+ dd2: 00 breakpoint
+ dd3: 01 .byte 1
+ ...
+
+00000dd6 <.Ldebug_line0>:
+ dd6: 00 breakpoint
+ dd7: 00 breakpoint
+ dd8: 01 .byte 1
+ dd9: 33 loadb
+ dda: 00 breakpoint
+ ddb: 02 pushsp
+ ddc: 00 breakpoint
+ ddd: 00 breakpoint
+ dde: 01 .byte 1
+ ddf: 23 storeh
+ de0: 01 .byte 1
+ de1: 01 .byte 1
+ de2: f6 im -10
+ de3: f5 im -11
+ de4: 0a flip
+ de5: 00 breakpoint
+ de6: 01 .byte 1
+ de7: 01 .byte 1
+ de8: 01 .byte 1
+ de9: 01 .byte 1
+ dea: 00 breakpoint
+ deb: 00 breakpoint
+ dec: 00 breakpoint
+ ded: 01 .byte 1
+ dee: 2e eq
+ def: 2e eq
+ df0: 2f neq
+ df1: 2e eq
+ df2: 2e eq
+ df3: 2f neq
+ df4: 2e eq
+ df5: 2e eq
+ df6: 2f neq
+ df7: 2e eq
+ df8: 2e eq
+ df9: 2f neq
+ dfa: 2e eq
+ dfb: 2e eq
+ dfc: 2f neq
+ dfd: 67 loadsp 92
+ dfe: 63 loadsp 76
+ dff: 63 loadsp 76
+ e00: 2f neq
+ e01: 6e loadsp 120
+ e02: 65 loadsp 84
+ e03: 77 loadsp 28
+ e04: 6c loadsp 112
+ e05: 69 loadsp 100
+ e06: 62 loadsp 72
+ e07: 2f neq
+ e08: 6c loadsp 112
+ e09: 69 loadsp 100
+ e0a: 62 loadsp 72
+ e0b: 63 loadsp 76
+ e0c: 2f neq
+ e0d: 72 loadsp 8
+ e0e: 65 loadsp 84
+ e0f: 65 loadsp 84
+ e10: 6e loadsp 120
+ e11: 74 loadsp 16
+ e12: 00 breakpoint
+ e13: 2f neq
+ e14: 68 loadsp 96
+ e15: 6f loadsp 124
+ e16: 6d loadsp 116
+ e17: 65 loadsp 84
+ e18: 2f neq
+ e19: 6f loadsp 124
+ e1a: 79 loadsp 36
+ e1b: 76 loadsp 24
+ e1c: 69 loadsp 100
+ e1d: 6e loadsp 120
+ e1e: 64 loadsp 80
+ e1f: 2f neq
+ e20: 74 loadsp 16
+ e21: 6f loadsp 124
+ e22: 6f loadsp 124
+ e23: 6c loadsp 112
+ e24: 63 loadsp 76
+ e25: 68 loadsp 96
+ e26: 61 loadsp 68
+ e27: 69 loadsp 100
+ e28: 6e loadsp 120
+ e29: 2f neq
+ e2a: 74 loadsp 16
+ e2b: 6f loadsp 124
+ e2c: 6f loadsp 124
+ e2d: 6c loadsp 112
+ e2e: 63 loadsp 76
+ e2f: 68 loadsp 96
+ e30: 61 loadsp 68
+ e31: 69 loadsp 100
+ e32: 6e loadsp 120
+ e33: 2f neq
+ e34: 67 loadsp 92
+ e35: 63 loadsp 76
+ e36: 63 loadsp 76
+ e37: 2f neq
+ e38: 6e loadsp 120
+ e39: 65 loadsp 84
+ e3a: 77 loadsp 28
+ e3b: 6c loadsp 112
+ e3c: 69 loadsp 100
+ e3d: 62 loadsp 72
+ e3e: 2f neq
+ e3f: 6c loadsp 112
+ e40: 69 loadsp 100
+ e41: 62 loadsp 72
+ e42: 63 loadsp 76
+ e43: 2f neq
+ e44: 69 loadsp 100
+ e45: 6e loadsp 120
+ e46: 63 loadsp 76
+ e47: 6c loadsp 112
+ e48: 75 loadsp 20
+ e49: 64 loadsp 80
+ e4a: 65 loadsp 84
+ e4b: 2f neq
+ e4c: 6d loadsp 116
+ e4d: 61 loadsp 68
+ e4e: 63 loadsp 76
+ e4f: 68 loadsp 96
+ e50: 69 loadsp 100
+ e51: 6e loadsp 120
+ e52: 65 loadsp 84
+ e53: 00 breakpoint
+ e54: 2f neq
+ e55: 68 loadsp 96
+ e56: 6f loadsp 124
+ e57: 6d loadsp 116
+ e58: 65 loadsp 84
+ e59: 2f neq
+ e5a: 6f loadsp 124
+ e5b: 79 loadsp 36
+ e5c: 76 loadsp 24
+ e5d: 69 loadsp 100
+ e5e: 6e loadsp 120
+ e5f: 64 loadsp 80
+ e60: 2f neq
+ e61: 74 loadsp 16
+ e62: 6f loadsp 124
+ e63: 6f loadsp 124
+ e64: 6c loadsp 112
+ e65: 63 loadsp 76
+ e66: 68 loadsp 96
+ e67: 61 loadsp 68
+ e68: 69 loadsp 100
+ e69: 6e loadsp 120
+ e6a: 2f neq
+ e6b: 74 loadsp 16
+ e6c: 6f loadsp 124
+ e6d: 6f loadsp 124
+ e6e: 6c loadsp 112
+ e6f: 63 loadsp 76
+ e70: 68 loadsp 96
+ e71: 61 loadsp 68
+ e72: 69 loadsp 100
+ e73: 6e loadsp 120
+ e74: 2f neq
+ e75: 67 loadsp 92
+ e76: 63 loadsp 76
+ e77: 63 loadsp 76
+ e78: 2f neq
+ e79: 6e loadsp 120
+ e7a: 65 loadsp 84
+ e7b: 77 loadsp 28
+ e7c: 6c loadsp 112
+ e7d: 69 loadsp 100
+ e7e: 62 loadsp 72
+ e7f: 2f neq
+ e80: 6c loadsp 112
+ e81: 69 loadsp 100
+ e82: 62 loadsp 72
+ e83: 63 loadsp 76
+ e84: 2f neq
+ e85: 69 loadsp 100
+ e86: 6e loadsp 120
+ e87: 63 loadsp 76
+ e88: 6c loadsp 112
+ e89: 75 loadsp 20
+ e8a: 64 loadsp 80
+ e8b: 65 loadsp 84
+ e8c: 2f neq
+ e8d: 73 loadsp 12
+ e8e: 79 loadsp 36
+ e8f: 73 loadsp 12
+ e90: 00 breakpoint
+ e91: 2f neq
+ e92: 68 loadsp 96
+ e93: 6f loadsp 124
+ e94: 6d loadsp 116
+ e95: 65 loadsp 84
+ e96: 2f neq
+ e97: 6f loadsp 124
+ e98: 79 loadsp 36
+ e99: 76 loadsp 24
+ e9a: 69 loadsp 100
+ e9b: 6e loadsp 120
+ e9c: 64 loadsp 80
+ e9d: 2f neq
+ e9e: 74 loadsp 16
+ e9f: 6f loadsp 124
+ ea0: 6f loadsp 124
+ ea1: 6c loadsp 112
+ ea2: 63 loadsp 76
+ ea3: 68 loadsp 96
+ ea4: 61 loadsp 68
+ ea5: 69 loadsp 100
+ ea6: 6e loadsp 120
+ ea7: 2f neq
+ ea8: 74 loadsp 16
+ ea9: 6f loadsp 124
+ eaa: 6f loadsp 124
+ eab: 6c loadsp 112
+ eac: 63 loadsp 76
+ ead: 68 loadsp 96
+ eae: 61 loadsp 68
+ eaf: 69 loadsp 100
+ eb0: 6e loadsp 120
+ eb1: 2f neq
+ eb2: 67 loadsp 92
+ eb3: 63 loadsp 76
+ eb4: 63 loadsp 76
+ eb5: 62 loadsp 72
+ eb6: 75 loadsp 20
+ eb7: 69 loadsp 100
+ eb8: 6c loadsp 112
+ eb9: 64 loadsp 80
+ eba: 2f neq
+ ebb: 67 loadsp 92
+ ebc: 63 loadsp 76
+ ebd: 63 loadsp 76
+ ebe: 2f neq
+ ebf: 69 loadsp 100
+ ec0: 6e loadsp 120
+ ec1: 63 loadsp 76
+ ec2: 6c loadsp 112
+ ec3: 75 loadsp 20
+ ec4: 64 loadsp 80
+ ec5: 65 loadsp 84
+ ec6: 00 breakpoint
+ ec7: 00 breakpoint
+ ec8: 5f storesp 60
+ ec9: 74 loadsp 16
+ eca: 79 loadsp 36
+ ecb: 70 loadsp 0
+ ecc: 65 loadsp 84
+ ecd: 73 loadsp 12
+ ece: 2e eq
+ ecf: 68 loadsp 96
+ ed0: 00 breakpoint
+ ed1: 03 .byte 3
+ ed2: 00 breakpoint
+ ed3: 00 breakpoint
+ ed4: 73 loadsp 12
+ ed5: 74 loadsp 16
+ ed6: 64 loadsp 80
+ ed7: 64 loadsp 80
+ ed8: 65 loadsp 84
+ ed9: 66 loadsp 88
+ eda: 2e eq
+ edb: 68 loadsp 96
+ edc: 00 breakpoint
+ edd: 04 poppc
+ ede: 00 breakpoint
+ edf: 00 breakpoint
+ ee0: 72 loadsp 8
+ ee1: 65 loadsp 84
+ ee2: 65 loadsp 84
+ ee3: 6e loadsp 120
+ ee4: 74 loadsp 16
+ ee5: 2e eq
+ ee6: 68 loadsp 96
+ ee7: 00 breakpoint
+ ee8: 03 .byte 3
+ ee9: 00 breakpoint
+ eea: 00 breakpoint
+ eeb: 74 loadsp 16
+ eec: 79 loadsp 36
+ eed: 70 loadsp 0
+ eee: 65 loadsp 84
+ eef: 73 loadsp 12
+ ef0: 2e eq
+ ef1: 68 loadsp 96
+ ef2: 00 breakpoint
+ ef3: 02 pushsp
+ ef4: 00 breakpoint
+ ef5: 00 breakpoint
+ ef6: 69 loadsp 100
+ ef7: 6d loadsp 116
+ ef8: 70 loadsp 0
+ ef9: 75 loadsp 20
+ efa: 72 loadsp 8
+ efb: 65 loadsp 84
+ efc: 2e eq
+ efd: 63 loadsp 76
+ efe: 00 breakpoint
+ eff: 01 .byte 1
+ f00: 00 breakpoint
+ f01: 00 breakpoint
+ f02: 00 breakpoint
+ f03: 00 breakpoint
+ f04: 05 add
+ f05: 02 pushsp
+ f06: 00 breakpoint
+ f07: 00 breakpoint
+ f08: 00 breakpoint
+ f09: 00 breakpoint
+ f0a: 00 breakpoint
+ f0b: 01 .byte 1
+ f0c: 01 .byte 1
+ f0d: 00 breakpoint
+ f0e: 00 breakpoint
+ f0f: 00 breakpoint
+ f10: 16 addsp 24
+ f11: 00 breakpoint
+ f12: 02 pushsp
+ f13: 00 breakpoint
+ f14: 00 breakpoint
+ f15: 00 breakpoint
+ f16: 10 addsp 0
+ f17: 01 .byte 1
+ f18: 01 .byte 1
+ f19: fb im -5
+ f1a: 0e .byte 14
+ f1b: 0a flip
+ f1c: 00 breakpoint
+ f1d: 01 .byte 1
+ f1e: 01 .byte 1
+ f1f: 01 .byte 1
+ f20: 01 .byte 1
+ f21: 00 breakpoint
+ f22: 00 breakpoint
+ f23: 00 breakpoint
+ f24: 01 .byte 1
+ ...
+
+00000f27 <.Ldebug_line0>:
+ f27: 00 breakpoint
+ f28: 00 breakpoint
+ f29: 01 .byte 1
+ f2a: 84 im 4
+ f2b: 00 breakpoint
+ f2c: 02 pushsp
+ f2d: 00 breakpoint
+ f2e: 00 breakpoint
+ f2f: 00 breakpoint
+ f30: d8 im -40
+ f31: 01 .byte 1
+ f32: 01 .byte 1
+ f33: f6 im -10
+ f34: f5 im -11
+ f35: 0a flip
+ f36: 00 breakpoint
+ f37: 01 .byte 1
+ f38: 01 .byte 1
+ f39: 01 .byte 1
+ f3a: 01 .byte 1
+ f3b: 00 breakpoint
+ f3c: 00 breakpoint
+ f3d: 00 breakpoint
+ f3e: 01 .byte 1
+ f3f: 2e eq
+ f40: 2e eq
+ f41: 2f neq
+ f42: 2e eq
+ f43: 2e eq
+ f44: 2f neq
+ f45: 2e eq
+ f46: 2e eq
+ f47: 2f neq
+ f48: 2e eq
+ f49: 2e eq
+ f4a: 2f neq
+ f4b: 2e eq
+ f4c: 2e eq
+ f4d: 2f neq
+ f4e: 67 loadsp 92
+ f4f: 63 loadsp 76
+ f50: 63 loadsp 76
+ f51: 2f neq
+ f52: 6e loadsp 120
+ f53: 65 loadsp 84
+ f54: 77 loadsp 28
+ f55: 6c loadsp 112
+ f56: 69 loadsp 100
+ f57: 62 loadsp 72
+ f58: 2f neq
+ f59: 6c loadsp 112
+ f5a: 69 loadsp 100
+ f5b: 62 loadsp 72
+ f5c: 63 loadsp 76
+ f5d: 2f neq
+ f5e: 73 loadsp 12
+ f5f: 74 loadsp 16
+ f60: 72 loadsp 8
+ f61: 69 loadsp 100
+ f62: 6e loadsp 120
+ f63: 67 loadsp 92
+ f64: 00 breakpoint
+ f65: 2f neq
+ f66: 68 loadsp 96
+ f67: 6f loadsp 124
+ f68: 6d loadsp 116
+ f69: 65 loadsp 84
+ f6a: 2f neq
+ f6b: 6f loadsp 124
+ f6c: 79 loadsp 36
+ f6d: 76 loadsp 24
+ f6e: 69 loadsp 100
+ f6f: 6e loadsp 120
+ f70: 64 loadsp 80
+ f71: 2f neq
+ f72: 74 loadsp 16
+ f73: 6f loadsp 124
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+ f75: 6c loadsp 112
+ f76: 63 loadsp 76
+ f77: 68 loadsp 96
+ f78: 61 loadsp 68
+ f79: 69 loadsp 100
+ f7a: 6e loadsp 120
+ f7b: 2f neq
+ f7c: 74 loadsp 16
+ f7d: 6f loadsp 124
+ f7e: 6f loadsp 124
+ f7f: 6c loadsp 112
+ f80: 63 loadsp 76
+ f81: 68 loadsp 96
+ f82: 61 loadsp 68
+ f83: 69 loadsp 100
+ f84: 6e loadsp 120
+ f85: 2f neq
+ f86: 67 loadsp 92
+ f87: 63 loadsp 76
+ f88: 63 loadsp 76
+ f89: 2f neq
+ f8a: 6e loadsp 120
+ f8b: 65 loadsp 84
+ f8c: 77 loadsp 28
+ f8d: 6c loadsp 112
+ f8e: 69 loadsp 100
+ f8f: 62 loadsp 72
+ f90: 2f neq
+ f91: 6c loadsp 112
+ f92: 69 loadsp 100
+ f93: 62 loadsp 72
+ f94: 63 loadsp 76
+ f95: 2f neq
+ f96: 69 loadsp 100
+ f97: 6e loadsp 120
+ f98: 63 loadsp 76
+ f99: 6c loadsp 112
+ f9a: 75 loadsp 20
+ f9b: 64 loadsp 80
+ f9c: 65 loadsp 84
+ f9d: 2f neq
+ f9e: 73 loadsp 12
+ f9f: 79 loadsp 36
+ fa0: 73 loadsp 12
+ fa1: 00 breakpoint
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+ fa3: 68 loadsp 96
+ fa4: 6f loadsp 124
+ fa5: 6d loadsp 116
+ fa6: 65 loadsp 84
+ fa7: 2f neq
+ fa8: 6f loadsp 124
+ fa9: 79 loadsp 36
+ faa: 76 loadsp 24
+ fab: 69 loadsp 100
+ fac: 6e loadsp 120
+ fad: 64 loadsp 80
+ fae: 2f neq
+ faf: 74 loadsp 16
+ fb0: 6f loadsp 124
+ fb1: 6f loadsp 124
+ fb2: 6c loadsp 112
+ fb3: 63 loadsp 76
+ fb4: 68 loadsp 96
+ fb5: 61 loadsp 68
+ fb6: 69 loadsp 100
+ fb7: 6e loadsp 120
+ fb8: 2f neq
+ fb9: 74 loadsp 16
+ fba: 6f loadsp 124
+ fbb: 6f loadsp 124
+ fbc: 6c loadsp 112
+ fbd: 63 loadsp 76
+ fbe: 68 loadsp 96
+ fbf: 61 loadsp 68
+ fc0: 69 loadsp 100
+ fc1: 6e loadsp 120
+ fc2: 2f neq
+ fc3: 67 loadsp 92
+ fc4: 63 loadsp 76
+ fc5: 63 loadsp 76
+ fc6: 62 loadsp 72
+ fc7: 75 loadsp 20
+ fc8: 69 loadsp 100
+ fc9: 6c loadsp 112
+ fca: 64 loadsp 80
+ fcb: 2f neq
+ fcc: 67 loadsp 92
+ fcd: 63 loadsp 76
+ fce: 63 loadsp 76
+ fcf: 2f neq
+ fd0: 69 loadsp 100
+ fd1: 6e loadsp 120
+ fd2: 63 loadsp 76
+ fd3: 6c loadsp 112
+ fd4: 75 loadsp 20
+ fd5: 64 loadsp 80
+ fd6: 65 loadsp 84
+ fd7: 00 breakpoint
+ fd8: 00 breakpoint
+ fd9: 5f storesp 60
+ fda: 74 loadsp 16
+ fdb: 79 loadsp 36
+ fdc: 70 loadsp 0
+ fdd: 65 loadsp 84
+ fde: 73 loadsp 12
+ fdf: 2e eq
+ fe0: 68 loadsp 96
+ fe1: 00 breakpoint
+ fe2: 02 pushsp
+ fe3: 00 breakpoint
+ fe4: 00 breakpoint
+ fe5: 73 loadsp 12
+ fe6: 74 loadsp 16
+ fe7: 64 loadsp 80
+ fe8: 64 loadsp 80
+ fe9: 65 loadsp 84
+ fea: 66 loadsp 88
+ feb: 2e eq
+ fec: 68 loadsp 96
+ fed: 00 breakpoint
+ fee: 03 .byte 3
+ fef: 00 breakpoint
+ ff0: 00 breakpoint
+ ff1: 72 loadsp 8
+ ff2: 65 loadsp 84
+ ff3: 65 loadsp 84
+ ff4: 6e loadsp 120
+ ff5: 74 loadsp 16
+ ff6: 2e eq
+ ff7: 68 loadsp 96
+ ff8: 00 breakpoint
+ ff9: 02 pushsp
+ ffa: 00 breakpoint
+ ffb: 00 breakpoint
+ ffc: 6d loadsp 116
+ ffd: 65 loadsp 84
+ ffe: 6d loadsp 116
+ fff: 73 loadsp 12
+ 1000: 65 loadsp 84
+ 1001: 74 loadsp 16
+ 1002: 2e eq
+ 1003: 63 loadsp 76
+ 1004: 00 breakpoint
+ 1005: 01 .byte 1
+ 1006: 00 breakpoint
+ 1007: 00 breakpoint
+ 1008: 00 breakpoint
+ 1009: 00 breakpoint
+ 100a: 05 add
+ 100b: 02 pushsp
+ 100c: 00 breakpoint
+ 100d: 00 breakpoint
+ 100e: 00 breakpoint
+ 100f: 00 breakpoint
+ 1010: 04 poppc
+ 1011: 04 poppc
+ 1012: 42 storesp 72
+ 1013: 00 breakpoint
+ 1014: 05 add
+ 1015: 02 pushsp
+ 1016: 00 breakpoint
+ 1017: 00 breakpoint
+ 1018: 00 breakpoint
+ 1019: 00 breakpoint
+ 101a: 1f addsp 60
+ 101b: 00 breakpoint
+ 101c: 05 add
+ 101d: 02 pushsp
+ 101e: 00 breakpoint
+ 101f: 00 breakpoint
+ 1020: 00 breakpoint
+ 1021: 00 breakpoint
+ 1022: 18 addsp 32
+ 1023: 00 breakpoint
+ 1024: 05 add
+ 1025: 02 pushsp
+ 1026: 00 breakpoint
+ 1027: 00 breakpoint
+ 1028: 00 breakpoint
+ 1029: 00 breakpoint
+ 102a: 17 addsp 28
+ 102b: 00 breakpoint
+ 102c: 05 add
+ 102d: 02 pushsp
+ 102e: 00 breakpoint
+ 102f: 00 breakpoint
+ 1030: 00 breakpoint
+ 1031: 00 breakpoint
+ 1032: 3b pushpc
+ 1033: 00 breakpoint
+ 1034: 05 add
+ 1035: 02 pushsp
+ 1036: 00 breakpoint
+ 1037: 00 breakpoint
+ 1038: 00 breakpoint
+ 1039: 00 breakpoint
+ 103a: 19 addsp 36
+ 103b: 00 breakpoint
+ 103c: 05 add
+ 103d: 02 pushsp
+ 103e: 00 breakpoint
+ 103f: 00 breakpoint
+ 1040: 00 breakpoint
+ 1041: 00 breakpoint
+ 1042: 03 .byte 3
+ 1043: 57 storesp 28
+ 1044: 01 .byte 1
+ 1045: 00 breakpoint
+ 1046: 05 add
+ 1047: 02 pushsp
+ 1048: 00 breakpoint
+ 1049: 00 breakpoint
+ 104a: 00 breakpoint
+ 104b: 00 breakpoint
+ 104c: 1a addsp 40
+ 104d: 00 breakpoint
+ 104e: 05 add
+ 104f: 02 pushsp
+ 1050: 00 breakpoint
+ 1051: 00 breakpoint
+ 1052: 00 breakpoint
+ 1053: 00 breakpoint
+ 1054: 15 addsp 20
+ 1055: 00 breakpoint
+ 1056: 05 add
+ 1057: 02 pushsp
+ 1058: 00 breakpoint
+ 1059: 00 breakpoint
+ 105a: 00 breakpoint
+ 105b: 00 breakpoint
+ 105c: 23 storeh
+ 105d: 00 breakpoint
+ 105e: 05 add
+ 105f: 02 pushsp
+ 1060: 00 breakpoint
+ 1061: 00 breakpoint
+ 1062: 00 breakpoint
+ 1063: 00 breakpoint
+ 1064: 10 addsp 0
+ 1065: 00 breakpoint
+ 1066: 05 add
+ 1067: 02 pushsp
+ 1068: 00 breakpoint
+ 1069: 00 breakpoint
+ 106a: 00 breakpoint
+ 106b: 00 breakpoint
+ 106c: 15 addsp 20
+ 106d: 00 breakpoint
+ 106e: 05 add
+ 106f: 02 pushsp
+ 1070: 00 breakpoint
+ 1071: 00 breakpoint
+ 1072: 00 breakpoint
+ 1073: 00 breakpoint
+ 1074: 15 addsp 20
+ 1075: 00 breakpoint
+ 1076: 05 add
+ 1077: 02 pushsp
+ 1078: 00 breakpoint
+ 1079: 00 breakpoint
+ 107a: 00 breakpoint
+ 107b: 00 breakpoint
+ 107c: 15 addsp 20
+ 107d: 00 breakpoint
+ 107e: 05 add
+ 107f: 02 pushsp
+ 1080: 00 breakpoint
+ 1081: 00 breakpoint
+ 1082: 00 breakpoint
+ 1083: 00 breakpoint
+ 1084: 15 addsp 20
+ 1085: 00 breakpoint
+ 1086: 05 add
+ 1087: 02 pushsp
+ 1088: 00 breakpoint
+ 1089: 00 breakpoint
+ 108a: 00 breakpoint
+ 108b: 00 breakpoint
+ 108c: 1a addsp 40
+ 108d: 00 breakpoint
+ 108e: 05 add
+ 108f: 02 pushsp
+ 1090: 00 breakpoint
+ 1091: 00 breakpoint
+ 1092: 00 breakpoint
+ 1093: 00 breakpoint
+ 1094: 13 addsp 12
+ 1095: 00 breakpoint
+ 1096: 05 add
+ 1097: 02 pushsp
+ 1098: 00 breakpoint
+ 1099: 00 breakpoint
+ 109a: 00 breakpoint
+ 109b: 00 breakpoint
+ 109c: 15 addsp 20
+ 109d: 00 breakpoint
+ 109e: 05 add
+ 109f: 02 pushsp
+ 10a0: 00 breakpoint
+ 10a1: 00 breakpoint
+ 10a2: 00 breakpoint
+ 10a3: 00 breakpoint
+ 10a4: 17 addsp 28
+ 10a5: 00 breakpoint
+ 10a6: 05 add
+ 10a7: 02 pushsp
+ 10a8: 00 breakpoint
+ 10a9: 00 breakpoint
+ 10aa: 00 breakpoint
+ 10ab: 00 breakpoint
+ 10ac: 00 breakpoint
+ 10ad: 01 .byte 1
+ 10ae: 01 .byte 1
+ 10af: 00 breakpoint
+ 10b0: 00 breakpoint
+ 10b1: 00 breakpoint
+ 10b2: 16 addsp 24
+ 10b3: 00 breakpoint
+ 10b4: 02 pushsp
+ 10b5: 00 breakpoint
+ 10b6: 00 breakpoint
+ 10b7: 00 breakpoint
+ 10b8: 10 addsp 0
+ 10b9: 01 .byte 1
+ 10ba: 01 .byte 1
+ 10bb: fb im -5
+ 10bc: 0e .byte 14
+ 10bd: 0a flip
+ 10be: 00 breakpoint
+ 10bf: 01 .byte 1
+ 10c0: 01 .byte 1
+ 10c1: 01 .byte 1
+ 10c2: 01 .byte 1
+ 10c3: 00 breakpoint
+ 10c4: 00 breakpoint
+ 10c5: 00 breakpoint
+ 10c6: 01 .byte 1
+ ...
+
+000010c9 <.Ldebug_line0>:
+ 10c9: 00 breakpoint
+ 10ca: 00 breakpoint
+ 10cb: 01 .byte 1
+ 10cc: 32 xor
+ 10cd: 00 breakpoint
+ 10ce: 02 pushsp
+ 10cf: 00 breakpoint
+ 10d0: 00 breakpoint
+ 10d1: 00 breakpoint
+ 10d2: d8 im -40
+ 10d3: 01 .byte 1
+ 10d4: 01 .byte 1
+ 10d5: f6 im -10
+ 10d6: f5 im -11
+ 10d7: 0a flip
+ 10d8: 00 breakpoint
+ 10d9: 01 .byte 1
+ 10da: 01 .byte 1
+ 10db: 01 .byte 1
+ 10dc: 01 .byte 1
+ 10dd: 00 breakpoint
+ 10de: 00 breakpoint
+ 10df: 00 breakpoint
+ 10e0: 01 .byte 1
+ 10e1: 2e eq
+ 10e2: 2e eq
+ 10e3: 2f neq
+ 10e4: 2e eq
+ 10e5: 2e eq
+ 10e6: 2f neq
+ 10e7: 2e eq
+ 10e8: 2e eq
+ 10e9: 2f neq
+ 10ea: 2e eq
+ 10eb: 2e eq
+ 10ec: 2f neq
+ 10ed: 2e eq
+ 10ee: 2e eq
+ 10ef: 2f neq
+ 10f0: 67 loadsp 92
+ 10f1: 63 loadsp 76
+ 10f2: 63 loadsp 76
+ 10f3: 2f neq
+ 10f4: 6e loadsp 120
+ 10f5: 65 loadsp 84
+ 10f6: 77 loadsp 28
+ 10f7: 6c loadsp 112
+ 10f8: 69 loadsp 100
+ 10f9: 62 loadsp 72
+ 10fa: 2f neq
+ 10fb: 6c loadsp 112
+ 10fc: 69 loadsp 100
+ 10fd: 62 loadsp 72
+ 10fe: 63 loadsp 76
+ 10ff: 2f neq
+ 1100: 73 loadsp 12
+ 1101: 74 loadsp 16
+ 1102: 72 loadsp 8
+ 1103: 69 loadsp 100
+ 1104: 6e loadsp 120
+ 1105: 67 loadsp 92
+ 1106: 00 breakpoint
+ 1107: 2f neq
+ 1108: 68 loadsp 96
+ 1109: 6f loadsp 124
+ 110a: 6d loadsp 116
+ 110b: 65 loadsp 84
+ 110c: 2f neq
+ 110d: 6f loadsp 124
+ 110e: 79 loadsp 36
+ 110f: 76 loadsp 24
+ 1110: 69 loadsp 100
+ 1111: 6e loadsp 120
+ 1112: 64 loadsp 80
+ 1113: 2f neq
+ 1114: 74 loadsp 16
+ 1115: 6f loadsp 124
+ 1116: 6f loadsp 124
+ 1117: 6c loadsp 112
+ 1118: 63 loadsp 76
+ 1119: 68 loadsp 96
+ 111a: 61 loadsp 68
+ 111b: 69 loadsp 100
+ 111c: 6e loadsp 120
+ 111d: 2f neq
+ 111e: 74 loadsp 16
+ 111f: 6f loadsp 124
+ 1120: 6f loadsp 124
+ 1121: 6c loadsp 112
+ 1122: 63 loadsp 76
+ 1123: 68 loadsp 96
+ 1124: 61 loadsp 68
+ 1125: 69 loadsp 100
+ 1126: 6e loadsp 120
+ 1127: 2f neq
+ 1128: 67 loadsp 92
+ 1129: 63 loadsp 76
+ 112a: 63 loadsp 76
+ 112b: 2f neq
+ 112c: 6e loadsp 120
+ 112d: 65 loadsp 84
+ 112e: 77 loadsp 28
+ 112f: 6c loadsp 112
+ 1130: 69 loadsp 100
+ 1131: 62 loadsp 72
+ 1132: 2f neq
+ 1133: 6c loadsp 112
+ 1134: 69 loadsp 100
+ 1135: 62 loadsp 72
+ 1136: 63 loadsp 76
+ 1137: 2f neq
+ 1138: 69 loadsp 100
+ 1139: 6e loadsp 120
+ 113a: 63 loadsp 76
+ 113b: 6c loadsp 112
+ 113c: 75 loadsp 20
+ 113d: 64 loadsp 80
+ 113e: 65 loadsp 84
+ 113f: 2f neq
+ 1140: 73 loadsp 12
+ 1141: 79 loadsp 36
+ 1142: 73 loadsp 12
+ 1143: 00 breakpoint
+ 1144: 2f neq
+ 1145: 68 loadsp 96
+ 1146: 6f loadsp 124
+ 1147: 6d loadsp 116
+ 1148: 65 loadsp 84
+ 1149: 2f neq
+ 114a: 6f loadsp 124
+ 114b: 79 loadsp 36
+ 114c: 76 loadsp 24
+ 114d: 69 loadsp 100
+ 114e: 6e loadsp 120
+ 114f: 64 loadsp 80
+ 1150: 2f neq
+ 1151: 74 loadsp 16
+ 1152: 6f loadsp 124
+ 1153: 6f loadsp 124
+ 1154: 6c loadsp 112
+ 1155: 63 loadsp 76
+ 1156: 68 loadsp 96
+ 1157: 61 loadsp 68
+ 1158: 69 loadsp 100
+ 1159: 6e loadsp 120
+ 115a: 2f neq
+ 115b: 74 loadsp 16
+ 115c: 6f loadsp 124
+ 115d: 6f loadsp 124
+ 115e: 6c loadsp 112
+ 115f: 63 loadsp 76
+ 1160: 68 loadsp 96
+ 1161: 61 loadsp 68
+ 1162: 69 loadsp 100
+ 1163: 6e loadsp 120
+ 1164: 2f neq
+ 1165: 67 loadsp 92
+ 1166: 63 loadsp 76
+ 1167: 63 loadsp 76
+ 1168: 62 loadsp 72
+ 1169: 75 loadsp 20
+ 116a: 69 loadsp 100
+ 116b: 6c loadsp 112
+ 116c: 64 loadsp 80
+ 116d: 2f neq
+ 116e: 67 loadsp 92
+ 116f: 63 loadsp 76
+ 1170: 63 loadsp 76
+ 1171: 2f neq
+ 1172: 69 loadsp 100
+ 1173: 6e loadsp 120
+ 1174: 63 loadsp 76
+ 1175: 6c loadsp 112
+ 1176: 75 loadsp 20
+ 1177: 64 loadsp 80
+ 1178: 65 loadsp 84
+ 1179: 00 breakpoint
+ 117a: 00 breakpoint
+ 117b: 5f storesp 60
+ 117c: 74 loadsp 16
+ 117d: 79 loadsp 36
+ 117e: 70 loadsp 0
+ 117f: 65 loadsp 84
+ 1180: 73 loadsp 12
+ 1181: 2e eq
+ 1182: 68 loadsp 96
+ 1183: 00 breakpoint
+ 1184: 02 pushsp
+ 1185: 00 breakpoint
+ 1186: 00 breakpoint
+ 1187: 73 loadsp 12
+ 1188: 74 loadsp 16
+ 1189: 64 loadsp 80
+ 118a: 64 loadsp 80
+ 118b: 65 loadsp 84
+ 118c: 66 loadsp 88
+ 118d: 2e eq
+ 118e: 68 loadsp 96
+ 118f: 00 breakpoint
+ 1190: 03 .byte 3
+ 1191: 00 breakpoint
+ 1192: 00 breakpoint
+ 1193: 72 loadsp 8
+ 1194: 65 loadsp 84
+ 1195: 65 loadsp 84
+ 1196: 6e loadsp 120
+ 1197: 74 loadsp 16
+ 1198: 2e eq
+ 1199: 68 loadsp 96
+ 119a: 00 breakpoint
+ 119b: 02 pushsp
+ 119c: 00 breakpoint
+ 119d: 00 breakpoint
+ 119e: 73 loadsp 12
+ 119f: 74 loadsp 16
+ 11a0: 72 loadsp 8
+ 11a1: 6c loadsp 112
+ 11a2: 65 loadsp 84
+ 11a3: 6e loadsp 120
+ 11a4: 2e eq
+ 11a5: 63 loadsp 76
+ 11a6: 00 breakpoint
+ 11a7: 01 .byte 1
+ 11a8: 00 breakpoint
+ 11a9: 00 breakpoint
+ 11aa: 00 breakpoint
+ 11ab: 00 breakpoint
+ 11ac: 05 add
+ 11ad: 02 pushsp
+ 11ae: 00 breakpoint
+ 11af: 00 breakpoint
+ 11b0: 00 breakpoint
+ 11b1: 00 breakpoint
+ 11b2: 04 poppc
+ 11b3: 04 poppc
+ 11b4: 4e storesp 120
+ 11b5: 00 breakpoint
+ 11b6: 05 add
+ 11b7: 02 pushsp
+ 11b8: 00 breakpoint
+ 11b9: 00 breakpoint
+ 11ba: 00 breakpoint
+ 11bb: 00 breakpoint
+ 11bc: 1d addsp 52
+ 11bd: 00 breakpoint
+ 11be: 05 add
+ 11bf: 02 pushsp
+ 11c0: 00 breakpoint
+ 11c1: 00 breakpoint
+ 11c2: 00 breakpoint
+ 11c3: 00 breakpoint
+ 11c4: 17 addsp 28
+ 11c5: 00 breakpoint
+ 11c6: 05 add
+ 11c7: 02 pushsp
+ 11c8: 00 breakpoint
+ 11c9: 00 breakpoint
+ 11ca: 00 breakpoint
+ 11cb: 00 breakpoint
+ 11cc: 18 addsp 32
+ 11cd: 00 breakpoint
+ 11ce: 05 add
+ 11cf: 02 pushsp
+ 11d0: 00 breakpoint
+ 11d1: 00 breakpoint
+ 11d2: 00 breakpoint
+ 11d3: 00 breakpoint
+ 11d4: 16 addsp 24
+ 11d5: 00 breakpoint
+ 11d6: 05 add
+ 11d7: 02 pushsp
+ 11d8: 00 breakpoint
+ 11d9: 00 breakpoint
+ 11da: 00 breakpoint
+ 11db: 00 breakpoint
+ 11dc: 18 addsp 32
+ 11dd: 00 breakpoint
+ 11de: 05 add
+ 11df: 02 pushsp
+ 11e0: 00 breakpoint
+ 11e1: 00 breakpoint
+ 11e2: 00 breakpoint
+ 11e3: 00 breakpoint
+ 11e4: 18 addsp 32
+ 11e5: 00 breakpoint
+ 11e6: 05 add
+ 11e7: 02 pushsp
+ 11e8: 00 breakpoint
+ 11e9: 00 breakpoint
+ 11ea: 00 breakpoint
+ 11eb: 00 breakpoint
+ 11ec: 15 addsp 20
+ 11ed: 00 breakpoint
+ 11ee: 05 add
+ 11ef: 02 pushsp
+ 11f0: 00 breakpoint
+ 11f1: 00 breakpoint
+ 11f2: 00 breakpoint
+ 11f3: 00 breakpoint
+ 11f4: 16 addsp 24
+ 11f5: 00 breakpoint
+ 11f6: 05 add
+ 11f7: 02 pushsp
+ 11f8: 00 breakpoint
+ 11f9: 00 breakpoint
+ 11fa: 00 breakpoint
+ 11fb: 00 breakpoint
+ 11fc: 00 breakpoint
+ 11fd: 01 .byte 1
+ 11fe: 01 .byte 1
+ 11ff: 00 breakpoint
+ 1200: 00 breakpoint
+ 1201: 00 breakpoint
+ 1202: 16 addsp 24
+ 1203: 00 breakpoint
+ 1204: 02 pushsp
+ 1205: 00 breakpoint
+ 1206: 00 breakpoint
+ 1207: 00 breakpoint
+ 1208: 10 addsp 0
+ 1209: 01 .byte 1
+ 120a: 01 .byte 1
+ 120b: fb im -5
+ 120c: 0e .byte 14
+ 120d: 0a flip
+ 120e: 00 breakpoint
+ 120f: 01 .byte 1
+ 1210: 01 .byte 1
+ 1211: 01 .byte 1
+ 1212: 01 .byte 1
+ 1213: 00 breakpoint
+ 1214: 00 breakpoint
+ 1215: 00 breakpoint
+ 1216: 01 .byte 1
+ ...
+Disassembly of section .debug_frame:
+
+00000000 <.Lframe0>:
+ 0: 00 breakpoint
+ 1: 00 breakpoint
+ 2: 00 breakpoint
+ 3: 10 addsp 0
+ 4: ff im -1
+ 5: ff im -1
+ 6: ff im -1
+ 7: ff im -1
+ 8: 01 .byte 1
+ 9: 00 breakpoint
+ a: 01 .byte 1
+ b: 7c loadsp 48
+ c: 24 lessthan
+ d: 0c store
+ e: 20 .byte 32
+ f: 04 poppc
+ 10: a4 im 36
+ 11: 01 .byte 1
+ 12: 00 breakpoint
+ 13: 00 breakpoint
+ 14: 00 breakpoint
+ 15: 00 breakpoint
+ 16: 00 breakpoint
+ 17: 1c addsp 48
+ ...
+ 20: 00 breakpoint
+ 21: 00 breakpoint
+ 22: 00 breakpoint
+ 23: 29 mult
+ 24: 04 poppc
+ 25: 00 breakpoint
+ 26: 00 breakpoint
+ 27: 00 breakpoint
+ 28: 03 .byte 3
+ 29: 0e .byte 14
+ 2a: 10 addsp 0
+ 2b: 04 poppc
+ 2c: 00 breakpoint
+ 2d: 00 breakpoint
+ 2e: 00 breakpoint
+ 2f: 25 lessthanorequal
+ 30: 0e .byte 14
+ 31: 04 poppc
+ 32: 00 breakpoint
+ 33: 00 breakpoint
+ 34: 00 breakpoint
+ 35: 00 breakpoint
+ 36: 00 breakpoint
+ 37: 1c addsp 48
+ ...
+ 40: 00 breakpoint
+ 41: 00 breakpoint
+ 42: 00 breakpoint
+ 43: 25 lessthanorequal
+ 44: 04 poppc
+ 45: 00 breakpoint
+ 46: 00 breakpoint
+ 47: 00 breakpoint
+ 48: 03 .byte 3
+ 49: 0e .byte 14
+ 4a: 0c store
+ 4b: 04 poppc
+ 4c: 00 breakpoint
+ 4d: 00 breakpoint
+ 4e: 00 breakpoint
+ 4f: 21 .byte 33
+ 50: 0e .byte 14
+ 51: 04 poppc
+ 52: 00 breakpoint
+ 53: 00 breakpoint
+ 54: 00 breakpoint
+ 55: 00 breakpoint
+ 56: 00 breakpoint
+ 57: 0c store
+ 58: 00 breakpoint
+ 59: 00 breakpoint
+ 5a: 00 breakpoint
+ 5b: 00 breakpoint
+ 5c: 00 breakpoint
+ 5d: 00 breakpoint
+ 5e: 04 poppc
+ 5f: 5f storesp 60
+ 60: 00 breakpoint
+ 61: 00 breakpoint
+ 62: 00 breakpoint
+ 63: 85 im 5
+ 64: 00 breakpoint
+ 65: 00 breakpoint
+ 66: 00 breakpoint
+ 67: 1c addsp 48
+ ...
+ 70: 00 breakpoint
+ 71: 00 breakpoint
+ 72: 00 breakpoint
+ 73: 6c loadsp 112
+ 74: 04 poppc
+ 75: 00 breakpoint
+ 76: 00 breakpoint
+ 77: 00 breakpoint
+ 78: 03 .byte 3
+ 79: 0e .byte 14
+ 7a: 40 storesp 64
+ 7b: 04 poppc
+ 7c: 00 breakpoint
+ 7d: 00 breakpoint
+ 7e: 00 breakpoint
+ 7f: 5b storesp 44
+ 80: 0e .byte 14
+ 81: 04 poppc
+ ...
+
+00000084 <.Lframe0>:
+ 84: 00 breakpoint
+ 85: 00 breakpoint
+ 86: 00 breakpoint
+ 87: 10 addsp 0
+ 88: ff im -1
+ 89: ff im -1
+ 8a: ff im -1
+ 8b: ff im -1
+ 8c: 01 .byte 1
+ 8d: 00 breakpoint
+ 8e: 01 .byte 1
+ 8f: 7c loadsp 48
+ 90: 24 lessthan
+ 91: 0c store
+ 92: 20 .byte 32
+ 93: 04 poppc
+ 94: a4 im 36
+ 95: 01 .byte 1
+ 96: 00 breakpoint
+ 97: 00 breakpoint
+ 98: 00 breakpoint
+ 99: 00 breakpoint
+ 9a: 00 breakpoint
+ 9b: 14 addsp 16
+ 9c: 00 breakpoint
+ 9d: 00 breakpoint
+ 9e: 00 breakpoint
+ 9f: 84 im 4
+ a0: 00 breakpoint
+ a1: 00 breakpoint
+ a2: 05 add
+ a3: 24 lessthan
+ a4: 00 breakpoint
+ a5: 00 breakpoint
+ a6: 00 breakpoint
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+ ...
+
+000000b0 <.Lframe0>:
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+ de: 00 breakpoint
+ df: 4d storesp 116
+ e0: 0e .byte 14
+ e1: 04 poppc
+ ...
+
+000000e4 <.Lframe0>:
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+ 111: 00 breakpoint
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+ 1a6: 1c addsp 48
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+ 1d3: 00 breakpoint
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+ 1d6: 1c addsp 48
+ 1d7: 04 poppc
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+ 1d9: 00 breakpoint
+ 1da: 00 breakpoint
+ 1db: 3f callpcrel
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+ 1f2: 00 breakpoint
+ 1f3: 00 breakpoint
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+ 1f6: 20 .byte 32
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+ 216: 1c addsp 48
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+ 234: 03 .byte 3
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+ 236: 18 addsp 32
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+ 244: 00 breakpoint
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+ 248: 00 breakpoint
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+ 24f: 58 storesp 32
+ 250: 04 poppc
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+ 252: 00 breakpoint
+ 253: 00 breakpoint
+ 254: 03 .byte 3
+ 255: 0e .byte 14
+ 256: 64 loadsp 80
+ 257: 04 poppc
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+ 259: 00 breakpoint
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+ 25b: 21 .byte 33
+ 25c: 0e .byte 14
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+ 26f: 66 loadsp 88
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+ 274: 03 .byte 3
+ 275: 0e .byte 14
+ 276: 64 loadsp 80
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+ 278: 00 breakpoint
+ 279: 00 breakpoint
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+ 27b: 4f storesp 124
+ 27c: 0e .byte 14
+ 27d: 04 poppc
+ 27e: 00 breakpoint
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+ 280: 00 breakpoint
+ 281: 00 breakpoint
+ 282: 00 breakpoint
+ 283: 1c addsp 48
+ 284: 00 breakpoint
+ 285: 00 breakpoint
+ 286: 00 breakpoint
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+ 288: 00 breakpoint
+ 289: 00 breakpoint
+ 28a: 00 breakpoint
+ 28b: 00 breakpoint
+ 28c: 00 breakpoint
+ 28d: 00 breakpoint
+ 28e: 00 breakpoint
+ 28f: 3c syscall
+ 290: 04 poppc
+ 291: 00 breakpoint
+ 292: 00 breakpoint
+ 293: 00 breakpoint
+ 294: 03 .byte 3
+ 295: 0e .byte 14
+ 296: 18 addsp 32
+ 297: 04 poppc
+ 298: 00 breakpoint
+ 299: 00 breakpoint
+ 29a: 00 breakpoint
+ 29b: 14 addsp 16
+ 29c: 0e .byte 14
+ 29d: 04 poppc
+ ...
+
+000002a0 <.Lframe0>:
+ 2a0: 00 breakpoint
+ 2a1: 00 breakpoint
+ 2a2: 00 breakpoint
+ 2a3: 10 addsp 0
+ 2a4: ff im -1
+ 2a5: ff im -1
+ 2a6: ff im -1
+ 2a7: ff im -1
+ 2a8: 01 .byte 1
+ 2a9: 00 breakpoint
+ 2aa: 01 .byte 1
+ 2ab: 7c loadsp 48
+ 2ac: 24 lessthan
+ 2ad: 0c store
+ 2ae: 20 .byte 32
+ 2af: 04 poppc
+ 2b0: a4 im 36
+ 2b1: 01 .byte 1
+ 2b2: 00 breakpoint
+ 2b3: 00 breakpoint
+ 2b4: 00 breakpoint
+ 2b5: 00 breakpoint
+ 2b6: 00 breakpoint
+ 2b7: 0c store
+ 2b8: 00 breakpoint
+ 2b9: 00 breakpoint
+ 2ba: 02 pushsp
+ 2bb: a0 im 32
+ 2bc: 00 breakpoint
+ 2bd: 00 breakpoint
+ 2be: 00 breakpoint
+ 2bf: 00 breakpoint
+ 2c0: 00 breakpoint
+ 2c1: 00 breakpoint
+ 2c2: 00 breakpoint
+ 2c3: 09 not
+
+000002c4 <.Lframe0>:
+ 2c4: 00 breakpoint
+ 2c5: 00 breakpoint
+ 2c6: 00 breakpoint
+ 2c7: 10 addsp 0
+ 2c8: ff im -1
+ 2c9: ff im -1
+ 2ca: ff im -1
+ 2cb: ff im -1
+ 2cc: 01 .byte 1
+ 2cd: 00 breakpoint
+ 2ce: 01 .byte 1
+ 2cf: 7c loadsp 48
+ 2d0: 24 lessthan
+ 2d1: 0c store
+ 2d2: 20 .byte 32
+ 2d3: 04 poppc
+ 2d4: a4 im 36
+ 2d5: 01 .byte 1
+ 2d6: 00 breakpoint
+ 2d7: 00 breakpoint
+ 2d8: 00 breakpoint
+ 2d9: 00 breakpoint
+ 2da: 00 breakpoint
+ 2db: 14 addsp 16
+ 2dc: 00 breakpoint
+ 2dd: 00 breakpoint
+ 2de: 02 pushsp
+ 2df: c4 im -60
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+ 2e8: 04 poppc
+ 2e9: 00 breakpoint
+ 2ea: 00 breakpoint
+ 2eb: 00 breakpoint
+ 2ec: 03 .byte 3
+ 2ed: 0e .byte 14
+ 2ee: 2c ashiftright
+ ...
+
+000002f0 <.Lframe0>:
+ 2f0: 00 breakpoint
+ 2f1: 00 breakpoint
+ 2f2: 00 breakpoint
+ 2f3: 10 addsp 0
+ 2f4: ff im -1
+ 2f5: ff im -1
+ 2f6: ff im -1
+ 2f7: ff im -1
+ 2f8: 01 .byte 1
+ 2f9: 00 breakpoint
+ 2fa: 01 .byte 1
+ 2fb: 7c loadsp 48
+ 2fc: 24 lessthan
+ 2fd: 0c store
+ 2fe: 20 .byte 32
+ 2ff: 04 poppc
+ 300: a4 im 36
+ 301: 01 .byte 1
+ 302: 00 breakpoint
+ 303: 00 breakpoint
+ 304: 00 breakpoint
+ 305: 00 breakpoint
+ 306: 00 breakpoint
+ 307: 1c addsp 48
+ 308: 00 breakpoint
+ 309: 00 breakpoint
+ 30a: 02 pushsp
+ 30b: f0 im -16
+ 30c: 00 breakpoint
+ 30d: 00 breakpoint
+ 30e: 00 breakpoint
+ 30f: 00 breakpoint
+ 310: 00 breakpoint
+ 311: 00 breakpoint
+ 312: 00 breakpoint
+ 313: b2 im 50
+ 314: 04 poppc
+ 315: 00 breakpoint
+ 316: 00 breakpoint
+ 317: 00 breakpoint
+ 318: 03 .byte 3
+ 319: 0e .byte 14
+ 31a: 18 addsp 32
+ 31b: 04 poppc
+ 31c: 00 breakpoint
+ 31d: 00 breakpoint
+ 31e: 00 breakpoint
+ 31f: 4b storesp 108
+ 320: 0e .byte 14
+ 321: 04 poppc
+ ...
+
+00000324 <.Lframe0>:
+ 324: 00 breakpoint
+ 325: 00 breakpoint
+ 326: 00 breakpoint
+ 327: 10 addsp 0
+ 328: ff im -1
+ 329: ff im -1
+ 32a: ff im -1
+ 32b: ff im -1
+ 32c: 01 .byte 1
+ 32d: 00 breakpoint
+ 32e: 01 .byte 1
+ 32f: 7c loadsp 48
+ 330: 24 lessthan
+ 331: 0c store
+ 332: 20 .byte 32
+ 333: 04 poppc
+ 334: a4 im 36
+ 335: 01 .byte 1
+ 336: 00 breakpoint
+ 337: 00 breakpoint
+ 338: 00 breakpoint
+ 339: 00 breakpoint
+ 33a: 00 breakpoint
+ 33b: 1c addsp 48
+ 33c: 00 breakpoint
+ 33d: 00 breakpoint
+ 33e: 03 .byte 3
+ 33f: 24 lessthan
+ 340: 00 breakpoint
+ 341: 00 breakpoint
+ 342: 00 breakpoint
+ 343: 00 breakpoint
+ 344: 00 breakpoint
+ 345: 00 breakpoint
+ 346: 00 breakpoint
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+ 348: 04 poppc
+ 349: 00 breakpoint
+ 34a: 00 breakpoint
+ 34b: 00 breakpoint
+ 34c: 03 .byte 3
+ 34d: 0e .byte 14
+ 34e: 14 addsp 16
+ 34f: 04 poppc
+ 350: 00 breakpoint
+ 351: 00 breakpoint
+ 352: 00 breakpoint
+ 353: 6f loadsp 124
+ 354: 0e .byte 14
+ 355: 04 poppc
+ ...
+Disassembly of section .debug_str:
+
+00000000 <.debug_str>:
+ 0: 5f storesp 60
+ 1: 63 loadsp 76
+ 2: 70 loadsp 0
+ 3: 75 loadsp 20
+ 4: 5f storesp 60
+ 5: 63 loadsp 76
+ 6: 6f loadsp 124
+ 7: 6e loadsp 120
+ 8: 66 loadsp 88
+ 9: 69 loadsp 100
+ a: 67 loadsp 92
+ b: 00 breakpoint
+ c: 6c loadsp 112
+ d: 6f loadsp 124
+ e: 6e loadsp 120
+ f: 67 loadsp 92
+ 10: 20 .byte 32
+ 11: 6c loadsp 112
+ 12: 6f loadsp 124
+ 13: 6e loadsp 120
+ 14: 67 loadsp 92
+ 15: 20 .byte 32
+ 16: 75 loadsp 20
+ 17: 6e loadsp 120
+ 18: 73 loadsp 12
+ 19: 69 loadsp 100
+ 1a: 67 loadsp 92
+ 1b: 6e loadsp 120
+ 1c: 65 loadsp 84
+ 1d: 64 loadsp 80
+ 1e: 20 .byte 32
+ 1f: 69 loadsp 100
+ 20: 6e loadsp 120
+ 21: 74 loadsp 16
+ 22: 00 breakpoint
+ 23: 6c loadsp 112
+ 24: 6f loadsp 124
+ 25: 6e loadsp 120
+ 26: 67 loadsp 92
+ 27: 20 .byte 32
+ 28: 6c loadsp 112
+ 29: 6f loadsp 124
+ 2a: 6e loadsp 120
+ 2b: 67 loadsp 92
+ 2c: 20 .byte 32
+ 2d: 69 loadsp 100
+ 2e: 6e loadsp 120
+ 2f: 74 loadsp 16
+ 30: 00 breakpoint
+ 31: 54 storesp 16
+ 32: 49 storesp 100
+ 33: 4d storesp 116
+ 34: 45 storesp 84
+ 35: 52 storesp 8
+ 36: 00 breakpoint
+ 37: 6f loadsp 124
+ 38: 75 loadsp 20
+ 39: 74 loadsp 16
+ 3a: 62 loadsp 72
+ 3b: 79 loadsp 36
+ 3c: 74 loadsp 16
+ 3d: 65 loadsp 84
+ 3e: 00 breakpoint
+ 3f: 5f storesp 60
+ 40: 72 loadsp 8
+ 41: 65 loadsp 84
+ 42: 61 loadsp 68
+ 43: 64 loadsp 80
+ 44: 43 storesp 76
+ 45: 79 loadsp 36
+ 46: 63 loadsp 76
+ 47: 6c loadsp 112
+ 48: 65 loadsp 84
+ 49: 73 loadsp 12
+ 4a: 00 breakpoint
+ 4b: 73 loadsp 12
+ 4c: 68 loadsp 96
+ 4d: 6f loadsp 124
+ 4e: 72 loadsp 8
+ 4f: 74 loadsp 16
+ 50: 20 .byte 32
+ 51: 75 loadsp 20
+ 52: 6e loadsp 120
+ 53: 73 loadsp 12
+ 54: 69 loadsp 100
+ 55: 67 loadsp 92
+ 56: 6e loadsp 120
+ 57: 65 loadsp 84
+ 58: 64 loadsp 80
+ 59: 20 .byte 32
+ 5a: 69 loadsp 100
+ 5b: 6e loadsp 120
+ 5c: 74 loadsp 16
+ 5d: 00 breakpoint
+ 5e: 47 storesp 92
+ 5f: 4e storesp 120
+ 60: 55 storesp 20
+ 61: 20 .byte 32
+ 62: 43 storesp 76
+ 63: 20 .byte 32
+ 64: 33 loadb
+ 65: 2e eq
+ 66: 34 storeb
+ 67: 2e eq
+ 68: 32 xor
+ 69: 00 breakpoint
+ 6a: 5f storesp 60
+ 6b: 68 loadsp 96
+ 6c: 61 loadsp 68
+ 6d: 72 loadsp 8
+ 6e: 64 loadsp 80
+ 6f: 77 loadsp 28
+ 70: 61 loadsp 68
+ 71: 72 loadsp 8
+ 72: 65 loadsp 84
+ 73: 00 breakpoint
+ 74: 2e eq
+ 75: 2e eq
+ 76: 2f neq
+ 77: 2e eq
+ 78: 2e eq
+ 79: 2f neq
+ 7a: 2e eq
+ 7b: 2e eq
+ 7c: 2f neq
+ 7d: 2e eq
+ 7e: 2e eq
+ 7f: 2f neq
+ 80: 67 loadsp 92
+ 81: 63 loadsp 76
+ 82: 63 loadsp 76
+ 83: 2f neq
+ 84: 6c loadsp 112
+ 85: 69 loadsp 100
+ 86: 62 loadsp 72
+ 87: 67 loadsp 92
+ 88: 6c loadsp 112
+ 89: 6f loadsp 124
+ 8a: 73 loadsp 12
+ 8b: 73 loadsp 12
+ 8c: 2f neq
+ 8d: 7a loadsp 40
+ 8e: 70 loadsp 0
+ 8f: 75 loadsp 20
+ 90: 2f neq
+ 91: 63 loadsp 76
+ 92: 72 loadsp 8
+ 93: 74 loadsp 16
+ 94: 5f storesp 60
+ 95: 69 loadsp 100
+ 96: 6f loadsp 124
+ 97: 2e eq
+ 98: 63 loadsp 76
+ 99: 00 breakpoint
+ 9a: 75 loadsp 20
+ 9b: 6e loadsp 120
+ 9c: 73 loadsp 12
+ 9d: 69 loadsp 100
+ 9e: 67 loadsp 92
+ 9f: 6e loadsp 120
+ a0: 65 loadsp 84
+ a1: 64 loadsp 80
+ a2: 20 .byte 32
+ a3: 63 loadsp 76
+ a4: 68 loadsp 96
+ a5: 61 loadsp 68
+ a6: 72 loadsp 8
+ a7: 00 breakpoint
+ a8: 73 loadsp 12
+ a9: 68 loadsp 96
+ aa: 6f loadsp 124
+ ab: 72 loadsp 8
+ ac: 74 loadsp 16
+ ad: 20 .byte 32
+ ae: 69 loadsp 100
+ af: 6e loadsp 120
+ b0: 74 loadsp 16
+ b1: 00 breakpoint
+ b2: 69 loadsp 100
+ b3: 6e loadsp 120
+ b4: 62 loadsp 72
+ b5: 79 loadsp 36
+ b6: 74 loadsp 16
+ b7: 65 loadsp 84
+ b8: 00 breakpoint
+ b9: 55 storesp 20
+ ba: 41 storesp 68
+ bb: 52 storesp 8
+ bc: 54 storesp 16
+ bd: 00 breakpoint
+ be: 2f neq
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+ c0: 6f loadsp 124
+ c1: 6d loadsp 116
+ c2: 65 loadsp 84
+ c3: 2f neq
+ c4: 6f loadsp 124
+ c5: 79 loadsp 36
+ c6: 76 loadsp 24
+ c7: 69 loadsp 100
+ c8: 6e loadsp 120
+ c9: 64 loadsp 80
+ ca: 2f neq
+ cb: 74 loadsp 16
+ cc: 6f loadsp 124
+ cd: 6f loadsp 124
+ ce: 6c loadsp 112
+ cf: 63 loadsp 76
+ d0: 68 loadsp 96
+ d1: 61 loadsp 68
+ d2: 69 loadsp 100
+ d3: 6e loadsp 120
+ d4: 2f neq
+ d5: 74 loadsp 16
+ d6: 6f loadsp 124
+ d7: 6f loadsp 124
+ d8: 6c loadsp 112
+ d9: 63 loadsp 76
+ da: 68 loadsp 96
+ db: 61 loadsp 68
+ dc: 69 loadsp 100
+ dd: 6e loadsp 120
+ de: 2f neq
+ df: 67 loadsp 92
+ e0: 63 loadsp 76
+ e1: 63 loadsp 76
+ e2: 62 loadsp 72
+ e3: 75 loadsp 20
+ e4: 69 loadsp 100
+ e5: 6c loadsp 112
+ e6: 64 loadsp 80
+ e7: 2f neq
+ e8: 7a loadsp 40
+ e9: 70 loadsp 0
+ ea: 75 loadsp 20
+ eb: 2d call
+ ec: 65 loadsp 84
+ ed: 6c loadsp 112
+ ee: 66 loadsp 88
+ ef: 2f neq
+ f0: 6c loadsp 112
+ f1: 69 loadsp 100
+ f2: 62 loadsp 72
+ f3: 67 loadsp 92
+ f4: 6c loadsp 112
+ f5: 6f loadsp 124
+ f6: 73 loadsp 12
+ f7: 73 loadsp 12
+ f8: 2f neq
+ f9: 7a loadsp 40
+ fa: 70 loadsp 0
+ fb: 75 loadsp 20
+ fc: 00 breakpoint
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+ ff: 6e loadsp 120
+ 100: 69 loadsp 100
+ 101: 74 loadsp 16
+ 102: 49 storesp 100
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+ 104: 00 breakpoint
+ 105: 63 loadsp 76
+ 106: 6c loadsp 112
+ 107: 6f loadsp 124
+ 108: 63 loadsp 76
+ 109: 6b loadsp 108
+ 10a: 00 breakpoint
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+ 10c: 6f loadsp 124
+ 10d: 75 loadsp 20
+ 10e: 6e loadsp 120
+ 10f: 74 loadsp 16
+ 110: 65 loadsp 84
+ 111: 72 loadsp 8
+ 112: 00 breakpoint
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+ 114: 63 loadsp 76
+ 115: 79 loadsp 36
+ 116: 67 loadsp 92
+ 117: 64 loadsp 80
+ 118: 72 loadsp 8
+ 119: 69 loadsp 100
+ 11a: 76 loadsp 24
+ 11b: 65 loadsp 84
+ 11c: 2f neq
+ 11d: 64 loadsp 80
+ 11e: 2f neq
+ 11f: 52 storesp 8
+ 120: 65 loadsp 84
+ 121: 73 loadsp 12
+ 122: 65 loadsp 84
+ 123: 61 loadsp 68
+ 124: 72 loadsp 8
+ 125: 63 loadsp 76
+ 126: 68 loadsp 96
+ 127: 2f neq
+ 128: 43 storesp 76
+ 129: 6f loadsp 124
+ 12a: 6d loadsp 116
+ 12b: 70 loadsp 0
+ 12c: 75 loadsp 20
+ 12d: 74 loadsp 16
+ 12e: 65 loadsp 84
+ 12f: 72 loadsp 8
+ 130: 5f storesp 60
+ 131: 53 storesp 12
+ 132: 63 loadsp 76
+ 133: 69 loadsp 100
+ 134: 65 loadsp 84
+ 135: 6e loadsp 120
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+ 137: 65 loadsp 84
+ 138: 2f neq
+ 139: 50 storesp 0
+ 13a: 72 loadsp 8
+ 13b: 6f loadsp 124
+ 13c: 6a loadsp 104
+ 13d: 65 loadsp 84
+ 13e: 63 loadsp 76
+ 13f: 74 loadsp 16
+ 140: 73 loadsp 12
+ 141: 2f neq
+ 142: 50 storesp 0
+ 143: 72 loadsp 8
+ 144: 61 loadsp 68
+ 145: 63 loadsp 76
+ 146: 74 loadsp 16
+ 147: 69 loadsp 100
+ 148: 63 loadsp 76
+ 149: 65 loadsp 84
+ 14a: 2f neq
+ 14b: 7a loadsp 40
+ 14c: 70 loadsp 0
+ 14d: 75 loadsp 20
+ 14e: 2f neq
+ 14f: 70 loadsp 0
+ 150: 73 loadsp 12
+ 151: 73 loadsp 12
+ 152: 2f neq
+ 153: 70 loadsp 0
+ 154: 73 loadsp 12
+ 155: 73 loadsp 12
+ 156: 2f neq
+ 157: 53 storesp 12
+ 158: 57 storesp 28
+ 159: 2f neq
+ 15a: 6f loadsp 124
+ 15b: 6e loadsp 120
+ 15c: 62 loadsp 72
+ 15d: 6f loadsp 124
+ 15e: 61 loadsp 68
+ 15f: 72 loadsp 8
+ 160: 64 loadsp 80
+ 161: 2f neq
+ 162: 48 storesp 96
+ 163: 65 loadsp 84
+ 164: 61 loadsp 68
+ 165: 72 loadsp 8
+ 166: 74 loadsp 16
+ 167: 62 loadsp 72
+ 168: 65 loadsp 84
+ 169: 61 loadsp 68
+ 16a: 74 loadsp 16
+ 16b: 44 storesp 80
+ 16c: 65 loadsp 84
+ 16d: 6c loadsp 112
+ 16e: 61 loadsp 68
+ 16f: 79 loadsp 36
+ 170: 2f neq
+ 171: 68 loadsp 96
+ 172: 65 loadsp 84
+ 173: 61 loadsp 68
+ 174: 72 loadsp 8
+ 175: 74 loadsp 16
+ 176: 62 loadsp 72
+ 177: 65 loadsp 84
+ 178: 61 loadsp 68
+ 179: 74 loadsp 16
+ 17a: 64 loadsp 80
+ 17b: 65 loadsp 84
+ 17c: 6c loadsp 112
+ 17d: 61 loadsp 68
+ 17e: 79 loadsp 36
+ 17f: 2e eq
+ 180: 63 loadsp 76
+ 181: 00 breakpoint
+ 182: 61 loadsp 68
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+ 184: 69 loadsp 100
+ 185: 67 loadsp 92
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+ 189: 5f storesp 60
+ 18a: 64 loadsp 80
+ 18b: 73 loadsp 12
+ 18c: 74 loadsp 16
+ 18d: 00 breakpoint
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+ 194: 00 breakpoint
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+ 196: 68 loadsp 96
+ 197: 6f loadsp 124
+ 198: 6d loadsp 116
+ 199: 65 loadsp 84
+ 19a: 2f neq
+ 19b: 6f loadsp 124
+ 19c: 79 loadsp 36
+ 19d: 76 loadsp 24
+ 19e: 69 loadsp 100
+ 19f: 6e loadsp 120
+ 1a0: 64 loadsp 80
+ 1a1: 2f neq
+ 1a2: 74 loadsp 16
+ 1a3: 6f loadsp 124
+ 1a4: 6f loadsp 124
+ 1a5: 6c loadsp 112
+ 1a6: 63 loadsp 76
+ 1a7: 68 loadsp 96
+ 1a8: 61 loadsp 68
+ 1a9: 69 loadsp 100
+ 1aa: 6e loadsp 120
+ 1ab: 2f neq
+ 1ac: 74 loadsp 16
+ 1ad: 6f loadsp 124
+ 1ae: 6f loadsp 124
+ 1af: 6c loadsp 112
+ 1b0: 63 loadsp 76
+ 1b1: 68 loadsp 96
+ 1b2: 61 loadsp 68
+ 1b3: 69 loadsp 100
+ 1b4: 6e loadsp 120
+ 1b5: 2f neq
+ 1b6: 67 loadsp 92
+ 1b7: 63 loadsp 76
+ 1b8: 63 loadsp 76
+ 1b9: 62 loadsp 72
+ 1ba: 75 loadsp 20
+ 1bb: 69 loadsp 100
+ 1bc: 6c loadsp 112
+ 1bd: 64 loadsp 80
+ 1be: 2f neq
+ 1bf: 7a loadsp 40
+ 1c0: 70 loadsp 0
+ 1c1: 75 loadsp 20
+ 1c2: 2d call
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+ 1c4: 6c loadsp 112
+ 1c5: 66 loadsp 88
+ 1c6: 2f neq
+ 1c7: 6e loadsp 120
+ 1c8: 65 loadsp 84
+ 1c9: 77 loadsp 28
+ 1ca: 6c loadsp 112
+ 1cb: 69 loadsp 100
+ 1cc: 62 loadsp 72
+ 1cd: 2f neq
+ 1ce: 6c loadsp 112
+ 1cf: 69 loadsp 100
+ 1d0: 62 loadsp 72
+ 1d1: 63 loadsp 76
+ 1d2: 2f neq
+ 1d3: 73 loadsp 12
+ 1d4: 74 loadsp 16
+ 1d5: 72 loadsp 8
+ 1d6: 69 loadsp 100
+ 1d7: 6e loadsp 120
+ 1d8: 67 loadsp 92
+ 1d9: 00 breakpoint
+ 1da: 61 loadsp 68
+ 1db: 6c loadsp 112
+ 1dc: 69 loadsp 100
+ 1dd: 67 loadsp 92
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+ 1e1: 5f storesp 60
+ 1e2: 73 loadsp 12
+ 1e3: 72 loadsp 8
+ 1e4: 63 loadsp 76
+ 1e5: 00 breakpoint
+ 1e6: 73 loadsp 12
+ 1e7: 72 loadsp 8
+ 1e8: 63 loadsp 76
+ 1e9: 30 neg
+ 1ea: 00 breakpoint
+ 1eb: 2e eq
+ 1ec: 2e eq
+ 1ed: 2f neq
+ 1ee: 2e eq
+ 1ef: 2e eq
+ 1f0: 2f neq
+ 1f1: 2e eq
+ 1f2: 2e eq
+ 1f3: 2f neq
+ 1f4: 2e eq
+ 1f5: 2e eq
+ 1f6: 2f neq
+ 1f7: 2e eq
+ 1f8: 2e eq
+ 1f9: 2f neq
+ 1fa: 67 loadsp 92
+ 1fb: 63 loadsp 76
+ 1fc: 63 loadsp 76
+ 1fd: 2f neq
+ 1fe: 6e loadsp 120
+ 1ff: 65 loadsp 84
+ 200: 77 loadsp 28
+ 201: 6c loadsp 112
+ 202: 69 loadsp 100
+ 203: 62 loadsp 72
+ 204: 2f neq
+ 205: 6c loadsp 112
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+ 207: 62 loadsp 72
+ 208: 63 loadsp 76
+ 209: 2f neq
+ 20a: 73 loadsp 12
+ 20b: 74 loadsp 16
+ 20c: 72 loadsp 8
+ 20d: 69 loadsp 100
+ 20e: 6e loadsp 120
+ 20f: 67 loadsp 92
+ 210: 2f neq
+ 211: 6d loadsp 116
+ 212: 65 loadsp 84
+ 213: 6d loadsp 116
+ 214: 63 loadsp 76
+ 215: 70 loadsp 0
+ 216: 79 loadsp 36
+ 217: 2e eq
+ 218: 63 loadsp 76
+ 219: 00 breakpoint
+ 21a: 64 loadsp 80
+ 21b: 73 loadsp 12
+ 21c: 74 loadsp 16
+ 21d: 30 neg
+ 21e: 00 breakpoint
+ 21f: 6d loadsp 116
+ 220: 65 loadsp 84
+ 221: 6d loadsp 116
+ 222: 63 loadsp 76
+ 223: 70 loadsp 0
+ 224: 79 loadsp 36
+ 225: 00 breakpoint
+ 226: 6c loadsp 112
+ 227: 65 loadsp 84
+ 228: 6e loadsp 120
+ 229: 30 neg
+ 22a: 00 breakpoint
+ 22b: 69 loadsp 100
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+ 22d: 61 loadsp 68
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+ 22f: 74 loadsp 16
+ 230: 79 loadsp 36
+ 231: 00 breakpoint
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+ 233: 75 loadsp 20
+ 234: 73 loadsp 12
+ 235: 65 loadsp 84
+ 236: 5f storesp 60
+ 237: 73 loadsp 12
+ 238: 79 loadsp 36
+ 239: 73 loadsp 12
+ 23a: 63 loadsp 76
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+ 23c: 6c loadsp 112
+ 23d: 6c loadsp 112
+ 23e: 00 breakpoint
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+ 240: 69 loadsp 100
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+ 243: 75 loadsp 20
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+ 249: 74 loadsp 16
+ 24a: 00 breakpoint
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+ 24d: 74 loadsp 16
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+ 251: 69 loadsp 100
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+ 253: 65 loadsp 84
+ 254: 00 breakpoint
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+ 25a: 74 loadsp 16
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+ 25e: 00 breakpoint
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+ 263: 00 breakpoint
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+ 266: 78 loadsp 32
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+ 269: 00 breakpoint
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+ 270: 64 loadsp 80
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+ 272: 00 breakpoint
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+ 274: 70 loadsp 0
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+ 27b: 00 breakpoint
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+ 28a: 00 breakpoint
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+ 292: 00 breakpoint
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+ 29a: 00 breakpoint
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+ 2a3: 33 loadb
+ 2a4: 00 breakpoint
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+ 2af: 00 breakpoint
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+ 2b5: 00 breakpoint
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+ 2be: 31 sub
+ 2bf: 00 breakpoint
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+ 2c8: 32 xor
+ 2c9: 00 breakpoint
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+ 2d0: 00 breakpoint
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+ 2d6: 00 breakpoint
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+ 2da: 65 loadsp 84
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+ 2dc: 00 breakpoint
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+ 2e8: 00 breakpoint
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+ 2ee: 00 breakpoint
+ 2ef: 2e eq
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+ 2f5: 2e eq
+ 2f6: 2e eq
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+ 2f9: 2e eq
+ 2fa: 2f neq
+ 2fb: 67 loadsp 92
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+ 2fd: 63 loadsp 76
+ 2fe: 2f neq
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+ 301: 62 loadsp 72
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+ 305: 73 loadsp 12
+ 306: 73 loadsp 12
+ 307: 2f neq
+ 308: 7a loadsp 40
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+ 30a: 75 loadsp 20
+ 30b: 2f neq
+ 30c: 73 loadsp 12
+ 30d: 79 loadsp 36
+ 30e: 73 loadsp 12
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+ 310: 61 loadsp 68
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+ 314: 2e eq
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+ 316: 00 breakpoint
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+ 31a: 5f storesp 60
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+ 31f: 00 breakpoint
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+ 326: 00 breakpoint
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+ 32b: 00 breakpoint
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+ 335: 00 breakpoint
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+ 33a: 62 loadsp 72
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+ 340: 00 breakpoint
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+ 346: 00 breakpoint
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+ 34d: 00 breakpoint
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+ 355: 00 breakpoint
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+ 35e: 34 storeb
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+ 36a: 00 breakpoint
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+ 374: 00 breakpoint
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+ 37d: 00 breakpoint
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+ 385: 00 breakpoint
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+ 38d: 00 breakpoint
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+ 393: 00 breakpoint
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+ 39a: 00 breakpoint
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+ 3a0: 74 loadsp 16
+ 3a1: 00 breakpoint
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+ 3b9: 00 breakpoint
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+ 3be: 00 breakpoint
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+ 3c5: 00 breakpoint
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+ 3ce: 00 breakpoint
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+ 3d9: 00 breakpoint
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+ 3e3: 00 breakpoint
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+ 3eb: 5f storesp 60
+ 3ec: 65 loadsp 84
+ 3ed: 72 loadsp 8
+ 3ee: 72 loadsp 8
+ 3ef: 6e loadsp 120
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+ 3f1: 00 breakpoint
+ 3f2: 5f storesp 60
+ 3f3: 5f storesp 60
+ 3f4: 73 loadsp 12
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+ 3fc: 00 breakpoint
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+ 404: 00 breakpoint
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+ 411: 00 breakpoint
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+ 414: 36 mod
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+ 41b: 00 breakpoint
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+ 421: 00 breakpoint
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+ 42a: 00 breakpoint
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+ 439: 00 breakpoint
+ 43a: 5f storesp 60
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+ 448: 00 breakpoint
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+ 452: 00 breakpoint
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+ 45a: 00 breakpoint
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+ 46b: 00 breakpoint
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+ 470: 00 breakpoint
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+ 477: 00 breakpoint
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+ 47f: 00 breakpoint
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+ 493: 00 breakpoint
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+ 4a4: 00 breakpoint
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+ 4a7: 34 storeb
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+ 4bd: 00 breakpoint
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+ 4c8: 00 breakpoint
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+ 4d6: 00 breakpoint
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+ 4e4: 00 breakpoint
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+ 4f3: 00 breakpoint
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+ 500: 00 breakpoint
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+ 509: 00 breakpoint
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+ 513: 00 breakpoint
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+ 526: 00 breakpoint
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+ 535: 00 breakpoint
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+ 54f: 00 breakpoint
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+ 554: 00 breakpoint
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+ 560: 00 breakpoint
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+ 5dc: 2e eq
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+ 5e2: 67 loadsp 92
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+ 5e9: 6c loadsp 112
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+ 5f1: 2f neq
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+ 6b7: 2d call
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+ 712: 64 loadsp 80
+ 713: 34 storeb
+ 714: 38 neqbranch
+ 715: 00 breakpoint
+ 716: 5f storesp 60
+ 717: 5f storesp 60
+ 718: 74 loadsp 16
+ 719: 6d loadsp 116
+ 71a: 5f storesp 60
+ 71b: 79 loadsp 36
+ 71c: 64 loadsp 80
+ 71d: 61 loadsp 68
+ 71e: 79 loadsp 36
+ 71f: 00 breakpoint
+ 720: 5f storesp 60
+ 721: 61 loadsp 68
+ 722: 74 loadsp 16
+ 723: 65 loadsp 84
+ 724: 78 loadsp 32
+ 725: 69 loadsp 100
+ 726: 74 loadsp 16
+ 727: 00 breakpoint
+ 728: 5f storesp 60
+ 729: 73 loadsp 12
+ 72a: 65 loadsp 84
+ 72b: 65 loadsp 84
+ 72c: 6b loadsp 108
+ 72d: 00 breakpoint
+ 72e: 5f storesp 60
+ 72f: 72 loadsp 8
+ 730: 65 loadsp 84
+ 731: 73 loadsp 12
+ 732: 75 loadsp 20
+ 733: 6c loadsp 112
+ 734: 74 loadsp 16
+ 735: 00 breakpoint
+ 736: 5f storesp 60
+ 737: 5f storesp 60
+ 738: 74 loadsp 16
+ 739: 6d loadsp 116
+ 73a: 5f storesp 60
+ 73b: 6d loadsp 116
+ 73c: 6f loadsp 124
+ 73d: 6e loadsp 120
+ 73e: 00 breakpoint
+ 73f: 5f storesp 60
+ 740: 69 loadsp 100
+ 741: 6e loadsp 120
+ 742: 63 loadsp 76
+ 743: 00 breakpoint
+ 744: 5f storesp 60
+ 745: 69 loadsp 100
+ 746: 6e loadsp 120
+ 747: 64 loadsp 80
+ 748: 00 breakpoint
+ 749: 5f storesp 60
+ 74a: 77 loadsp 28
+ 74b: 63 loadsp 76
+ 74c: 74 loadsp 16
+ 74d: 6f loadsp 124
+ 74e: 6d loadsp 116
+ 74f: 62 loadsp 72
+ 750: 5f storesp 60
+ 751: 73 loadsp 12
+ 752: 74 loadsp 16
+ 753: 61 loadsp 68
+ 754: 74 loadsp 16
+ 755: 65 loadsp 84
+ 756: 00 breakpoint
+ 757: 5f storesp 60
+ 758: 70 loadsp 0
+ 759: 35 div
+ 75a: 73 loadsp 12
+ 75b: 00 breakpoint
+ 75c: 5f storesp 60
+ 75d: 73 loadsp 12
+ 75e: 69 loadsp 100
+ 75f: 67 loadsp 92
+ 760: 6e loadsp 120
+ 761: 00 breakpoint
+ 762: 5f storesp 60
+ 763: 72 loadsp 8
+ 764: 61 loadsp 68
+ 765: 6e loadsp 120
+ 766: 64 loadsp 80
+ 767: 5f storesp 60
+ 768: 6e loadsp 120
+ 769: 65 loadsp 84
+ 76a: 78 loadsp 32
+ 76b: 74 loadsp 16
+ 76c: 00 breakpoint
+ 76d: 5f storesp 60
+ 76e: 73 loadsp 12
+ 76f: 74 loadsp 16
+ 770: 64 loadsp 80
+ 771: 69 loadsp 100
+ 772: 6e loadsp 120
+ 773: 00 breakpoint
+ 774: 5f storesp 60
+ 775: 63 loadsp 76
+ 776: 75 loadsp 20
+ 777: 72 loadsp 8
+ 778: 72 loadsp 8
+ 779: 65 loadsp 84
+ 77a: 6e loadsp 120
+ 77b: 74 loadsp 16
+ 77c: 5f storesp 60
+ 77d: 6c loadsp 112
+ 77e: 6f loadsp 124
+ 77f: 63 loadsp 76
+ 780: 61 loadsp 68
+ 781: 6c loadsp 112
+ 782: 65 loadsp 84
+ 783: 00 breakpoint
+ 784: 5f storesp 60
+ 785: 72 loadsp 8
+ 786: 65 loadsp 84
+ 787: 65 loadsp 84
+ 788: 6e loadsp 120
+ 789: 74 loadsp 16
+ 78a: 00 breakpoint
+ 78b: 5f storesp 60
+ 78c: 77 loadsp 28
+ 78d: 63 loadsp 76
+ 78e: 72 loadsp 8
+ 78f: 74 loadsp 16
+ 790: 6f loadsp 124
+ 791: 6d loadsp 116
+ 792: 62 loadsp 72
+ 793: 5f storesp 60
+ 794: 73 loadsp 12
+ 795: 74 loadsp 16
+ 796: 61 loadsp 68
+ 797: 74 loadsp 16
+ 798: 65 loadsp 84
+ 799: 00 breakpoint
+ 79a: 5f storesp 60
+ 79b: 66 loadsp 88
+ 79c: 6c loadsp 112
+ 79d: 61 loadsp 68
+ 79e: 67 loadsp 92
+ 79f: 73 loadsp 12
+ 7a0: 00 breakpoint
+ 7a1: 5f storesp 60
+ 7a2: 75 loadsp 20
+ 7a3: 62 loadsp 72
+ 7a4: 75 loadsp 20
+ 7a5: 66 loadsp 88
+ 7a6: 00 breakpoint
+ 7a7: 5f storesp 60
+ 7a8: 61 loadsp 68
+ 7a9: 73 loadsp 12
+ 7aa: 63 loadsp 76
+ 7ab: 74 loadsp 16
+ 7ac: 69 loadsp 100
+ 7ad: 6d loadsp 116
+ 7ae: 65 loadsp 84
+ 7af: 5f storesp 60
+ 7b0: 62 loadsp 72
+ 7b1: 75 loadsp 20
+ 7b2: 66 loadsp 88
+ 7b3: 00 breakpoint
+ 7b4: 5f storesp 60
+ 7b5: 5f storesp 60
+ 7b6: 73 loadsp 12
+ 7b7: 46 storesp 88
+ 7b8: 49 storesp 100
+ 7b9: 4c storesp 112
+ 7ba: 45 storesp 84
+ 7bb: 00 breakpoint
+ 7bc: 2f neq
+ 7bd: 68 loadsp 96
+ 7be: 6f loadsp 124
+ 7bf: 6d loadsp 116
+ 7c0: 65 loadsp 84
+ 7c1: 2f neq
+ 7c2: 6f loadsp 124
+ 7c3: 79 loadsp 36
+ 7c4: 76 loadsp 24
+ 7c5: 69 loadsp 100
+ 7c6: 6e loadsp 120
+ 7c7: 64 loadsp 80
+ 7c8: 2f neq
+ 7c9: 74 loadsp 16
+ 7ca: 6f loadsp 124
+ 7cb: 6f loadsp 124
+ 7cc: 6c loadsp 112
+ 7cd: 63 loadsp 76
+ 7ce: 68 loadsp 96
+ 7cf: 61 loadsp 68
+ 7d0: 69 loadsp 100
+ 7d1: 6e loadsp 120
+ 7d2: 2f neq
+ 7d3: 74 loadsp 16
+ 7d4: 6f loadsp 124
+ 7d5: 6f loadsp 124
+ 7d6: 6c loadsp 112
+ 7d7: 63 loadsp 76
+ 7d8: 68 loadsp 96
+ 7d9: 61 loadsp 68
+ 7da: 69 loadsp 100
+ 7db: 6e loadsp 120
+ 7dc: 2f neq
+ 7dd: 67 loadsp 92
+ 7de: 63 loadsp 76
+ 7df: 63 loadsp 76
+ 7e0: 62 loadsp 72
+ 7e1: 75 loadsp 20
+ 7e2: 69 loadsp 100
+ 7e3: 6c loadsp 112
+ 7e4: 64 loadsp 80
+ 7e5: 2f neq
+ 7e6: 7a loadsp 40
+ 7e7: 70 loadsp 0
+ 7e8: 75 loadsp 20
+ 7e9: 2d call
+ 7ea: 65 loadsp 84
+ 7eb: 6c loadsp 112
+ 7ec: 66 loadsp 88
+ 7ed: 2f neq
+ 7ee: 6e loadsp 120
+ 7ef: 65 loadsp 84
+ 7f0: 77 loadsp 28
+ 7f1: 6c loadsp 112
+ 7f2: 69 loadsp 100
+ 7f3: 62 loadsp 72
+ 7f4: 2f neq
+ 7f5: 6c loadsp 112
+ 7f6: 69 loadsp 100
+ 7f7: 62 loadsp 72
+ 7f8: 63 loadsp 76
+ 7f9: 2f neq
+ 7fa: 73 loadsp 12
+ 7fb: 74 loadsp 16
+ 7fc: 64 loadsp 80
+ 7fd: 6c loadsp 112
+ 7fe: 69 loadsp 100
+ 7ff: 62 loadsp 72
+ 800: 00 breakpoint
+ 801: 2e eq
+ 802: 2e eq
+ 803: 2f neq
+ 804: 2e eq
+ 805: 2e eq
+ 806: 2f neq
+ 807: 2e eq
+ 808: 2e eq
+ 809: 2f neq
+ 80a: 2e eq
+ 80b: 2e eq
+ 80c: 2f neq
+ 80d: 2e eq
+ 80e: 2e eq
+ 80f: 2f neq
+ 810: 67 loadsp 92
+ 811: 63 loadsp 76
+ 812: 63 loadsp 76
+ 813: 2f neq
+ 814: 6e loadsp 120
+ 815: 65 loadsp 84
+ 816: 77 loadsp 28
+ 817: 6c loadsp 112
+ 818: 69 loadsp 100
+ 819: 62 loadsp 72
+ 81a: 2f neq
+ 81b: 6c loadsp 112
+ 81c: 69 loadsp 100
+ 81d: 62 loadsp 72
+ 81e: 63 loadsp 76
+ 81f: 2f neq
+ 820: 73 loadsp 12
+ 821: 74 loadsp 16
+ 822: 64 loadsp 80
+ 823: 6c loadsp 112
+ 824: 69 loadsp 100
+ 825: 62 loadsp 72
+ 826: 2f neq
+ 827: 65 loadsp 84
+ 828: 78 loadsp 32
+ 829: 69 loadsp 100
+ 82a: 74 loadsp 16
+ 82b: 2e eq
+ 82c: 63 loadsp 76
+ 82d: 00 breakpoint
+ 82e: 63 loadsp 76
+ 82f: 6f loadsp 124
+ 830: 64 loadsp 80
+ 831: 65 loadsp 84
+ 832: 00 breakpoint
+ 833: 69 loadsp 100
+ 834: 6d loadsp 116
+ 835: 70 loadsp 0
+ 836: 75 loadsp 20
+ 837: 72 loadsp 8
+ 838: 65 loadsp 84
+ 839: 5f storesp 60
+ 83a: 64 loadsp 80
+ 83b: 61 loadsp 68
+ 83c: 74 loadsp 16
+ 83d: 61 loadsp 68
+ 83e: 00 breakpoint
+ 83f: 2e eq
+ 840: 2e eq
+ 841: 2f neq
+ 842: 2e eq
+ 843: 2e eq
+ 844: 2f neq
+ 845: 2e eq
+ 846: 2e eq
+ 847: 2f neq
+ 848: 2e eq
+ 849: 2e eq
+ 84a: 2f neq
+ 84b: 2e eq
+ 84c: 2e eq
+ 84d: 2f neq
+ 84e: 67 loadsp 92
+ 84f: 63 loadsp 76
+ 850: 63 loadsp 76
+ 851: 2f neq
+ 852: 6e loadsp 120
+ 853: 65 loadsp 84
+ 854: 77 loadsp 28
+ 855: 6c loadsp 112
+ 856: 69 loadsp 100
+ 857: 62 loadsp 72
+ 858: 2f neq
+ 859: 6c loadsp 112
+ 85a: 69 loadsp 100
+ 85b: 62 loadsp 72
+ 85c: 63 loadsp 76
+ 85d: 2f neq
+ 85e: 72 loadsp 8
+ 85f: 65 loadsp 84
+ 860: 65 loadsp 84
+ 861: 6e loadsp 120
+ 862: 74 loadsp 16
+ 863: 2f neq
+ 864: 69 loadsp 100
+ 865: 6d loadsp 116
+ 866: 70 loadsp 0
+ 867: 75 loadsp 20
+ 868: 72 loadsp 8
+ 869: 65 loadsp 84
+ 86a: 2e eq
+ 86b: 63 loadsp 76
+ 86c: 00 breakpoint
+ 86d: 2f neq
+ 86e: 68 loadsp 96
+ 86f: 6f loadsp 124
+ 870: 6d loadsp 116
+ 871: 65 loadsp 84
+ 872: 2f neq
+ 873: 6f loadsp 124
+ 874: 79 loadsp 36
+ 875: 76 loadsp 24
+ 876: 69 loadsp 100
+ 877: 6e loadsp 120
+ 878: 64 loadsp 80
+ 879: 2f neq
+ 87a: 74 loadsp 16
+ 87b: 6f loadsp 124
+ 87c: 6f loadsp 124
+ 87d: 6c loadsp 112
+ 87e: 63 loadsp 76
+ 87f: 68 loadsp 96
+ 880: 61 loadsp 68
+ 881: 69 loadsp 100
+ 882: 6e loadsp 120
+ 883: 2f neq
+ 884: 74 loadsp 16
+ 885: 6f loadsp 124
+ 886: 6f loadsp 124
+ 887: 6c loadsp 112
+ 888: 63 loadsp 76
+ 889: 68 loadsp 96
+ 88a: 61 loadsp 68
+ 88b: 69 loadsp 100
+ 88c: 6e loadsp 120
+ 88d: 2f neq
+ 88e: 67 loadsp 92
+ 88f: 63 loadsp 76
+ 890: 63 loadsp 76
+ 891: 62 loadsp 72
+ 892: 75 loadsp 20
+ 893: 69 loadsp 100
+ 894: 6c loadsp 112
+ 895: 64 loadsp 80
+ 896: 2f neq
+ 897: 7a loadsp 40
+ 898: 70 loadsp 0
+ 899: 75 loadsp 20
+ 89a: 2d call
+ 89b: 65 loadsp 84
+ 89c: 6c loadsp 112
+ 89d: 66 loadsp 88
+ 89e: 2f neq
+ 89f: 6e loadsp 120
+ 8a0: 65 loadsp 84
+ 8a1: 77 loadsp 28
+ 8a2: 6c loadsp 112
+ 8a3: 69 loadsp 100
+ 8a4: 62 loadsp 72
+ 8a5: 2f neq
+ 8a6: 6c loadsp 112
+ 8a7: 69 loadsp 100
+ 8a8: 62 loadsp 72
+ 8a9: 63 loadsp 76
+ 8aa: 2f neq
+ 8ab: 72 loadsp 8
+ 8ac: 65 loadsp 84
+ 8ad: 65 loadsp 84
+ 8ae: 6e loadsp 120
+ 8af: 74 loadsp 16
+ 8b0: 00 breakpoint
+ 8b1: 61 loadsp 68
+ 8b2: 6c loadsp 112
+ 8b3: 69 loadsp 100
+ 8b4: 67 loadsp 92
+ 8b5: 6e loadsp 120
+ 8b6: 65 loadsp 84
+ 8b7: 64 loadsp 80
+ 8b8: 5f storesp 60
+ 8b9: 61 loadsp 68
+ 8ba: 64 loadsp 80
+ 8bb: 64 loadsp 80
+ 8bc: 72 loadsp 8
+ 8bd: 00 breakpoint
+ 8be: 2e eq
+ 8bf: 2e eq
+ 8c0: 2f neq
+ 8c1: 2e eq
+ 8c2: 2e eq
+ 8c3: 2f neq
+ 8c4: 2e eq
+ 8c5: 2e eq
+ 8c6: 2f neq
+ 8c7: 2e eq
+ 8c8: 2e eq
+ 8c9: 2f neq
+ 8ca: 2e eq
+ 8cb: 2e eq
+ 8cc: 2f neq
+ 8cd: 67 loadsp 92
+ 8ce: 63 loadsp 76
+ 8cf: 63 loadsp 76
+ 8d0: 2f neq
+ 8d1: 6e loadsp 120
+ 8d2: 65 loadsp 84
+ 8d3: 77 loadsp 28
+ 8d4: 6c loadsp 112
+ 8d5: 69 loadsp 100
+ 8d6: 62 loadsp 72
+ 8d7: 2f neq
+ 8d8: 6c loadsp 112
+ 8d9: 69 loadsp 100
+ 8da: 62 loadsp 72
+ 8db: 63 loadsp 76
+ 8dc: 2f neq
+ 8dd: 73 loadsp 12
+ 8de: 74 loadsp 16
+ 8df: 72 loadsp 8
+ 8e0: 69 loadsp 100
+ 8e1: 6e loadsp 120
+ 8e2: 67 loadsp 92
+ 8e3: 2f neq
+ 8e4: 6d loadsp 116
+ 8e5: 65 loadsp 84
+ 8e6: 6d loadsp 116
+ 8e7: 73 loadsp 12
+ 8e8: 65 loadsp 84
+ 8e9: 74 loadsp 16
+ 8ea: 2e eq
+ 8eb: 63 loadsp 76
+ 8ec: 00 breakpoint
+ 8ed: 62 loadsp 72
+ 8ee: 75 loadsp 20
+ 8ef: 66 loadsp 88
+ 8f0: 66 loadsp 88
+ 8f1: 65 loadsp 84
+ 8f2: 72 loadsp 8
+ 8f3: 00 breakpoint
+ 8f4: 2e eq
+ 8f5: 2e eq
+ 8f6: 2f neq
+ 8f7: 2e eq
+ 8f8: 2e eq
+ 8f9: 2f neq
+ 8fa: 2e eq
+ 8fb: 2e eq
+ 8fc: 2f neq
+ 8fd: 2e eq
+ 8fe: 2e eq
+ 8ff: 2f neq
+ 900: 2e eq
+ 901: 2e eq
+ 902: 2f neq
+ 903: 67 loadsp 92
+ 904: 63 loadsp 76
+ 905: 63 loadsp 76
+ 906: 2f neq
+ 907: 6e loadsp 120
+ 908: 65 loadsp 84
+ 909: 77 loadsp 28
+ 90a: 6c loadsp 112
+ 90b: 69 loadsp 100
+ 90c: 62 loadsp 72
+ 90d: 2f neq
+ 90e: 6c loadsp 112
+ 90f: 69 loadsp 100
+ 910: 62 loadsp 72
+ 911: 63 loadsp 76
+ 912: 2f neq
+ 913: 73 loadsp 12
+ 914: 74 loadsp 16
+ 915: 72 loadsp 8
+ 916: 69 loadsp 100
+ 917: 6e loadsp 120
+ 918: 67 loadsp 92
+ 919: 2f neq
+ 91a: 73 loadsp 12
+ 91b: 74 loadsp 16
+ 91c: 72 loadsp 8
+ 91d: 6c loadsp 112
+ 91e: 65 loadsp 84
+ 91f: 6e loadsp 120
+ 920: 2e eq
+ 921: 63 loadsp 76
+ 922: 00 breakpoint
+ 923: 73 loadsp 12
+ 924: 74 loadsp 16
+ 925: 61 loadsp 68
+ 926: 72 loadsp 8
+ 927: 74 loadsp 16
+ ...
+Disassembly of section .debug_ranges:
+
+00000000 <.Ldebug_ranges0>:
+ ...