URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/axi4_lib/sim/tests
- from Rev 29 to Rev 31
- ↔ Reverse comparison
Rev 29 → Rev 31
/debug_axi4_memory/init_test.do
0,0 → 1,34
# ------------------------------------ |
# |
# ------------------------------------ |
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global env |
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set env(ROOT_DIR) ../../../../.. |
set env(PROJECT_DIR) ../../.. |
set env(SIM_TARGET) fpga |
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# load sim procedures |
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do |
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radix -hexadecimal |
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make_lib work 1 |
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sim_compile_all packages |
sim_compile_all sim |
sim_compile_all axi4_lib |
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# simulation $root |
vlog $env(PROJECT_DIR)/sim/src/tb_axi4_memory.sv |
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# compile test last |
vlog ./the_test.sv |
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# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top |
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# run the sim |
sim_run_test |
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/debug_axi4_memory/sim.do
0,0 → 1,21
# |
# |
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quit -sim |
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# vsim opt_tb_top |
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vsim -novopt -f ./sim.f work.tb_top |
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
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# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
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# # log all signals |
# log -r * |
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# run -all |
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/debug_axi4_memory/sim.f
0,0 → 1,14
# |
# |
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+nowarn8887 |
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-novopt |
-t 1ps |
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-L work |
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/debug_axi4_memory/the_test.sv
0,0 → 1,143
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
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`timescale 1ps/1ps |
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module |
the_test( |
input tb_clk, |
input tb_rst |
); |
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// -------------------------------------------------------------------- |
// |
localparam A = tb_top.A; |
localparam N = tb_top.N; |
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// -------------------------------------------------------------------- |
// |
import axi4_transaction_pkg::*; |
axi4_payload_class payload_h; |
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// -------------------------------------------------------------------- |
// |
logic [(8*N)-1:0] data[]; |
logic [1:0] resp; |
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task run_the_test; |
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// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
// -------------------------------------------------------------------- |
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tb_top.tb.timeout_stop(10us); |
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// -------------------------------------------------------------------- |
wait(~tb_rst); |
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// -------------------------------------------------------------------- |
#100ns; |
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// force tb_top.axi4_s.bready = 1; |
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data = new[16]; |
data[0] = 64'habba_beef_cafe_1a7e; |
tb_top.bfm.basic_write(32'h1234_0000, 0, data, resp); |
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// -------------------------------------------------------------------- |
#100ns; |
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repeat(5) |
begin |
tb_top.bfm.basic_random_write_burst(resp); |
end |
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// -------------------------------------------------------------------- |
#100ns; |
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repeat(5) |
begin |
tb_top.bfm.basic_random_read_burst(data, resp); |
end |
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// // -------------------------------------------------------------------- |
// #100ns; |
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// repeat(5) |
// begin |
// tb_top.bfm.basic_read(32'h1234_0000, 3, data, resp); |
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// foreach(data[i]) |
// $display("^^^ %16.t | %d | 0x%016x |", $time, i, data[i]); |
// end |
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// tb_top.bfm.basic_read(32'habcd_0000, 0, data, resp); |
// $display("^^^ %16.t | 0x%016x |", $time, data[0]); |
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// // -------------------------------------------------------------------- |
// tb_top.bfm.basic_read(32'habcd_0000, 0, data, resp); |
// $display("^^^ %16.t | 0x%016x |", $time, data[0]); |
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// // -------------------------------------------------------------------- |
// #100ns; |
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// repeat(5) |
// begin |
// tb_top.bfm.basic_random_write(32'habcd_0000, 0, resp); |
// end |
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// // -------------------------------------------------------------------- |
// #100ns; |
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// repeat(5) |
// begin |
// tb_top.bfm.basic_random_write(32'habcd_0000, 3, resp); |
// end |
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// -------------------------------------------------------------------- |
#100ns; |
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// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
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endtask |
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endmodule |
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/debug_axi4_memory/wip.do
0,0 → 1,15
# |
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# vlog -f ../../libs/packages_verilog/tb_lib.f |
vlog -f ../../libs/sim_verilog/axi4_bfm.f |
vlog -f ../../libs/sim_verilog/axi4_models.f |
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vlog -f ../../libs/axi4_lib_verilog/axi4_base.f |
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# simulation $root |
vlog ../../src/tb_axi4_memory.sv |
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# compile test last |
vlog ./the_test.sv |
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/tb_axi4_to_axis_basic_dma/init_test.do
0,0 → 1,34
# ------------------------------------ |
# |
# ------------------------------------ |
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global env |
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# setup environment |
do ../../../../scripts/sim_env.do |
set env(SIM_TARGET) fpga |
set env(SIM_TB) tb_axi4_to_axis_basic_dma |
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radix -hexadecimal |
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make_lib work 1 |
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sim_compile_all tb_packages |
sim_compile_all bfm_packages |
sim_compile_all axi4_lib |
sim_compile_all qaz_lib |
sim_compile_all sim |
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# compile simulation files |
vlog -f ./$env(SIM_TB).f |
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# simulation $root |
vlog ./$env(SIM_TB)_pkg.sv |
vlog ./$env(SIM_TB).sv |
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# compile test last |
vlog ./the_test.sv |
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# run the sim |
sim_run_test |
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/tb_axi4_to_axis_basic_dma/sim.do
0,0 → 1,13
# |
# |
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quit -sim |
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vsim -novopt work.tb_top |
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# log all signals |
log -r * |
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# run -all |
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/tb_axi4_to_axis_basic_dma/tb_axi4_to_axis_basic_dma.f
0,0 → 1,12
# |
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${LIB_BASE_DIR}/axi4_stream_lib/sim/src/axis_bfm_pkg.sv |
${LIB_BASE_DIR}/axi4_lib/sim/src/axi4_models/axi4_memory_pkg.sv |
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${PROJECT_DIR}/sim/src/tb_axi4_to_axis_agent_class_pkg.sv |
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${PROJECT_DIR}/src/axi4_to_axis_basic_dma.sv |
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./${SIM_TB}_pkg.sv |
./${SIM_TB}.sv |
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/tb_axi4_to_axis_basic_dma/tb_axi4_to_axis_basic_dma.sv
0,0 → 1,115
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
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module tb_top(); |
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// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_200mhz; |
wire tb_clk = clk_200mhz; |
wire tb_rst; |
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tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); |
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// -------------------------------------------------------------------- |
// |
wire tb_rst_s; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst_s; |
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sync_reset |
sync_reset_i(aclk, tb_rst, tb_rst_s); |
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// -------------------------------------------------------------------- |
// |
import tb_axi4_to_axis_basic_dma_pkg::*; |
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// -------------------------------------------------------------------- |
// |
axi4_if #(.A(A), .N(N), .I(I)) axi4_m(.*); |
axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*); |
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// -------------------------------------------------------------------- |
// |
logic dma_enable = 0; |
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axi4_to_axis_basic_dma |
#( |
.A(A), |
.N(N), |
.I(I), |
.BASE_ADDRESS(BASE_ADDRESS), |
.BUFFER_SIZE(BUFFER_SIZE), |
.BURST_LENGTH(BURST_LENGTH), |
.MAX_BURSTS(MAX_BURSTS), |
.BYTES_PER_TUSER(BYTES_PER_TUSER) |
) |
dut(.*); |
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// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
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// -------------------------------------------------------------------- |
// |
axi4_checker #(.A(A), .N(N), .MAXWAITS(64)) |
axi4_checker_i(.axi4_in(axi4_m)); |
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// -------------------------------------------------------------------- |
// |
axis_checker #(.N(N), .I(I), .D(D), .U(U)) |
axis_checker_i(.axis_in(axis_out)); |
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// -------------------------------------------------------------------- |
// |
tb_axi4_to_axis_basic_dma_class a_h; |
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initial |
a_h = new(axi4_m, axis_out); |
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// -------------------------------------------------------------------- |
// |
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// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
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// -------------------------------------------------------------------- |
// debug wires |
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// -------------------------------------------------------------------- |
// test |
the_test test(tb_clk, tb_rst); |
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initial |
begin |
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test.run_the_test(); |
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$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
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$display("^^^---------------------------------"); |
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$stop(); |
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end |
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endmodule |
/tb_axi4_to_axis_basic_dma/tb_axi4_to_axis_basic_dma_pkg.sv
0,0 → 1,58
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
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package tb_axi4_to_axis_basic_dma_pkg; |
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// -------------------------------------------------------------------- |
// |
import tb_axi4_to_axis_agent_class_pkg::*; |
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// -------------------------------------------------------------------- |
// |
localparam BASE_ADDRESS = 32'h0000_0000; // must be on 4K boundry |
localparam BUFFER_SIZE = 'h800; |
localparam BURST_LENGTH = 8'h08; |
localparam MAX_BURSTS = 4; |
localparam BYTES_PER_TUSER = 2; // bytes per tuser bit. Set to 0 for transfer based. |
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localparam N = 8; // data bus width in bytes |
localparam A = 32; // address bus width |
localparam I = 1; // ID width |
localparam D = 1; // TDEST width |
localparam U = N / BYTES_PER_TUSER; // TUSER width |
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// -------------------------------------------------------------------- |
// |
class tb_axi4_to_axis_basic_dma_class |
extends tb_axi4_to_axis_agent_class #(N, A, I, D, U); |
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//-------------------------------------------------------------------- |
// |
function new |
( |
virtual axi4_if #(.A(A), .N(N), .I(I)) axi4_m, |
virtual axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out |
); |
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super.new(.axi4_m(axi4_m), .axis_out(axis_out)); |
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endfunction: new |
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// -------------------------------------------------------------------- |
// |
endclass: tb_axi4_to_axis_basic_dma_class |
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// -------------------------------------------------------------------- |
// |
endpackage: tb_axi4_to_axis_basic_dma_pkg |
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/tb_axi4_to_axis_basic_dma/the_test.sv
0,0 → 1,69
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
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`timescale 1ps/1ps |
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module |
the_test( |
input tb_clk, |
input tb_rst |
); |
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// -------------------------------------------------------------------- |
// |
import tb_axi4_to_axis_basic_dma_pkg::*; |
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// -------------------------------------------------------------------- |
// |
task run_the_test; |
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// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.", $time); |
$display("^^^---------------------------------"); |
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// -------------------------------------------------------------------- |
tb_top.tb.timeout_stop(50us); |
// tb_top.a_h.m_h.counting_fill(0,'h800); |
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// -------------------------------------------------------------------- |
wait(tb_top.aresetn); |
#200ns; |
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// -------------------------------------------------------------------- |
tb_top.a_h.random_transaction(BASE_ADDRESS, BUFFER_SIZE); |
force tb_top.dma_enable = 1; |
repeat(2) tb_top.a_h.wait_for_sof(); |
tb_top.a_h.compare(); |
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// -------------------------------------------------------------------- |
release tb_top.dma_enable; |
force tb_top.tb_rst = 1; |
#200ns; |
release tb_top.tb_rst; |
#200ns; |
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// -------------------------------------------------------------------- |
tb_top.a_h.random_transaction(BASE_ADDRESS, BUFFER_SIZE); |
force tb_top.dma_enable = 1; |
repeat(2) tb_top.a_h.wait_for_sof(); |
tb_top.a_h.compare(); |
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// -------------------------------------------------------------------- |
#200ns; |
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// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
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endtask |
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endmodule |
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/tb_axi4_to_axis_basic_dma/wip.do
0,0 → 1,11
# |
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vlog -f ./tb_axi4_to_axis_basic_dma.f |
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# simulation $root |
vlog ./tb_axi4_to_axis_basic_dma.sv |
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# compile test last |
vlog ./the_test.sv |
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