URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
Compare Revisions
- This comparison shows the changes necessary to convert path
/qaz_libs/trunk/basal/sim/tests
- from Rev 44 to Rev 50
- ↔ Reverse comparison
Rev 44 → Rev 50
/tb_tiny_async_fifo/tb_tiny_async_fifo.sv
File deleted
/tb_tiny_async_fifo/wip.do
File deleted
/tb_tiny_async_fifo/init_test.do
File deleted
/tb_tiny_async_fifo/the_test.sv
File deleted
/tb_tiny_async_fifo/sim.do
File deleted
/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv
File deleted
/tb_tiny_sync_fifo/wip.do
File deleted
/tb_tiny_sync_fifo/init_test.do
File deleted
/tb_tiny_sync_fifo/the_test.sv
File deleted
/tb_tiny_sync_fifo/sim.do
File deleted
/legacy/tb_tiny_async_fifo/init_test.do
0,0 → 1,33
# ------------------------------------ |
# |
# ------------------------------------ |
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global env |
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set env(ROOT_DIR) ../../../../.. |
set env(PROJECT_DIR) ../../.. |
set env(SIM_TARGET) fpga |
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# load sim procedures |
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do |
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radix -hexadecimal |
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make_lib work 1 |
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sim_compile_all async_fifo |
sim_compile_all sim |
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# simulation $root |
vlog $env(PROJECT_DIR)/sim/src/tb_tiny_async_fifo.sv |
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# compile test last |
vlog ./the_test.sv |
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# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top |
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# run the sim |
sim_run_test |
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/legacy/tb_tiny_async_fifo/sim.do
0,0 → 1,21
# |
# |
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quit -sim |
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# vsim opt_tb_top |
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vsim -novopt work.tb_top |
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
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# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
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# # log all signals |
# log -r * |
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# run -all |
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/legacy/tb_tiny_async_fifo/tb_tiny_async_fifo.sv
0,0 → 1,122
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
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module tb_top(); |
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// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_200mhz; |
wire tb_clk = clk_200mhz; |
wire tb_rst; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst; |
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tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); |
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// wire clk_100mhz; |
// tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz); |
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// -------------------------------------------------------------------- |
// |
localparam W = 8; |
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fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst); |
fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst); |
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// -------------------------------------------------------------------- |
// |
tiny_async_fifo |
dut(.*); |
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// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
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// -------------------------------------------------------------------- |
// |
// import fifo_bfm_pkg::*; |
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// fifo_bfm_class bfm = new(source, sink); |
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// initial |
// bfm.init("", BOTH); |
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// -------------------------------------------------------------------- |
// |
import fifo_agent_pkg::*; |
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fifo_agent_class bfm = new(source, sink); |
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initial |
begin |
bfm.init(); |
bfm.start_q(); |
end |
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// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
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// -------------------------------------------------------------------- |
// debug wires |
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// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
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initial |
begin |
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test.run_the_test(); |
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$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
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$display("^^^---------------------------------"); |
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$stop(); |
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end |
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endmodule |
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/legacy/tb_tiny_async_fifo/the_test.sv
0,0 → 1,77
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
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`timescale 1ps/1ps |
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module |
the_test( |
input tb_clk, |
input tb_rst |
); |
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// -------------------------------------------------------------------- |
// |
int data; |
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// -------------------------------------------------------------------- |
// |
task run_the_test; |
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// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
// -------------------------------------------------------------------- |
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tb_top.tb.timeout_stop(1000ms); |
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// -------------------------------------------------------------------- |
wait(~tb_rst); |
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// -------------------------------------------------------------------- |
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repeat(20) @(posedge tb_clk); |
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repeat(100) tb_top.bfm.queue_random(); |
repeat(500) @(posedge tb_clk); |
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// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
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endtask |
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endmodule |
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/legacy/tb_tiny_async_fifo/wip.do
0,0 → 1,13
# |
|
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vlog -f ../../libs/async_fifo_verilog/tiny_async_fifo.f |
# vlog -f ../../libs/sim_verilog/fifo_bfm.f |
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# simulation $root |
vlog ../../src/tb_tiny_async_fifo.sv |
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# compile test last |
vlog ./the_test.sv |
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/legacy/tb_tiny_sync_fifo/init_test.do
0,0 → 1,33
# ------------------------------------ |
# |
# ------------------------------------ |
|
global env |
|
set env(ROOT_DIR) ../../../../.. |
set env(PROJECT_DIR) ../../.. |
set env(SIM_TARGET) fpga |
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# load sim procedures |
do $env(ROOT_DIR)/qaz_libs/scripts/sim_procs.do |
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radix -hexadecimal |
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make_lib work 1 |
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sim_compile_all sync_fifo |
sim_compile_all sim |
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# simulation $root |
vlog $env(PROJECT_DIR)/sim/src/tb_tiny_sync_fifo.sv |
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# compile test last |
vlog ./the_test.sv |
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# vopt work.glbl tb_top -L secureip -L simprims_ver -L unisims_ver -f opt_tb_top.f -o opt_tb_top |
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# run the sim |
sim_run_test |
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/legacy/tb_tiny_sync_fifo/sim.do
0,0 → 1,21
# |
# |
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quit -sim |
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# vsim opt_tb_top |
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vsim -novopt work.tb_top |
# vsim -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
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# vsim -voptargs="+acc=rn+/tb_top/dut" -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
# vsim -pli "C:/Xilinx/Vivado/2015.4/lib/win64.o/libxil_vsim.dll" -novopt -L secureip -L simprims_ver -L unisims_ver work.glbl work.tb_top |
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# # log all signals |
# log -r * |
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# run -all |
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/legacy/tb_tiny_sync_fifo/tb_tiny_sync_fifo.sv
0,0 → 1,122
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
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module tb_top(); |
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// -------------------------------------------------------------------- |
// test bench clock & reset |
wire clk_200mhz; |
wire tb_clk = clk_200mhz; |
wire tb_rst; |
wire aclk = tb_clk; |
wire aresetn = ~tb_rst; |
|
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst); |
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// wire clk_100mhz; |
// tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz); |
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// -------------------------------------------------------------------- |
// |
localparam W = 8; |
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fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst); |
fifo_read_if #(.W(W)) sink(clk_200mhz, tb_rst); |
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// -------------------------------------------------------------------- |
// |
tiny_sync_fifo |
dut(.*); |
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// -------------------------------------------------------------------- |
// sim models |
// | | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ |
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
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// -------------------------------------------------------------------- |
// |
// import fifo_bfm_pkg::*; |
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// fifo_bfm_class bfm = new(source, sink); |
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// initial |
// bfm.init("", BOTH); |
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// -------------------------------------------------------------------- |
// |
import fifo_agent_pkg::*; |
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fifo_agent_class bfm = new(source, sink); |
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initial |
begin |
bfm.init(); |
bfm.start_q(); |
end |
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// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' |
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\ |
// | | | | | | | | | | | | | | | | | |
// sim models |
// -------------------------------------------------------------------- |
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// -------------------------------------------------------------------- |
// debug wires |
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// -------------------------------------------------------------------- |
// test |
the_test test( tb_clk, tb_rst ); |
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initial |
begin |
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test.run_the_test(); |
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$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench done.", $time); |
$display("^^^---------------------------------"); |
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$display("^^^---------------------------------"); |
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$stop(); |
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end |
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endmodule |
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/legacy/tb_tiny_sync_fifo/the_test.sv
0,0 → 1,88
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2015 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
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`timescale 1ps/1ps |
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module |
the_test( |
input tb_clk, |
input tb_rst |
); |
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// -------------------------------------------------------------------- |
// |
int data; |
|
|
// -------------------------------------------------------------------- |
// |
task run_the_test; |
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// -------------------------------------------------------------------- |
// insert test below |
// -------------------------------------------------------------------- |
$display("^^^---------------------------------"); |
$display("^^^ %16.t | Testbench begun.\n", $time); |
$display("^^^---------------------------------"); |
// -------------------------------------------------------------------- |
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tb_top.tb.timeout_stop(1000ms); |
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// -------------------------------------------------------------------- |
wait(~tb_rst); |
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// -------------------------------------------------------------------- |
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repeat(10) @(posedge tb_clk); |
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repeat(100) tb_top.bfm.queue_random(); |
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// tb_top.bfm.write(8'h22, 0); |
// tb_top.bfm.write(8'haa, 0); |
// tb_top.bfm.read(10); |
// tb_top.bfm.write(8'hff, 5); |
// tb_top.bfm.read(0); |
// tb_top.bfm.read(0); |
// tb_top.bfm.write(8'h11, 1); |
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repeat(1000) @(posedge tb_clk); |
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// -------------------------------------------------------------------- |
// insert test above |
// -------------------------------------------------------------------- |
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endtask |
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endmodule |
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/legacy/tb_tiny_sync_fifo/wip.do
0,0 → 1,13
# |
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vlog -f ../../libs/FPGA_verilog/tiny_fifo.f |
vlog -f ../../libs/sim_verilog/fifo_bfm.f |
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# simulation $root |
vlog ../../src/tb_tiny_sync_fifo.sv |
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# compile test last |
vlog ./the_test.sv |
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