URL
https://opencores.org/ocsvn/quark/quark/trunk
Subversion Repositories quark
Compare Revisions
- This comparison shows the changes necessary to convert path
/quark
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/Quantum.wcfg
0,0 → 1,251
<?xml version="1.0" encoding="UTF-8"?> |
<wave_config> |
<wave_state> |
</wave_state> |
<db_ref_list> |
<db_ref path="/home/miguel/Desktop/Quantum/Quantum_TB_isim_beh.wdb" id="1" type="auto"> |
<top_modules> |
<top_module name="glbl" /> |
<top_module name="quantum_tb" /> |
<top_module name="std_logic_1164" /> |
<top_module name="std_logic_arith" /> |
<top_module name="std_logic_unsigned" /> |
<top_module name="vl_types" /> |
</top_modules> |
</db_ref> |
</db_ref_list> |
<WVObjectSize size="5" /> |
<wvobject fp_name="group5" type="group"> |
<obj_property name="label">Quantum</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
<wvobject fp_name="/quantum_tb/clock" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">clock</obj_property> |
<obj_property name="ObjectShortName">clock</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/reset" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">reset</obj_property> |
<obj_property name="ObjectShortName">reset</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/gpio1" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">gpio1[7:0]</obj_property> |
<obj_property name="ObjectShortName">gpio1[7:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
</wvobject> |
<wvobject fp_name="group6" type="group"> |
<obj_property name="label">ControlUnit</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/BusDataIn" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">BusDataIn[0:7]</obj_property> |
<obj_property name="ObjectShortName">BusDataIn[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/WritePC" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">WritePC</obj_property> |
<obj_property name="ObjectShortName">WritePC</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/IncrementPC" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">IncrementPC</obj_property> |
<obj_property name="ObjectShortName">IncrementPC</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/REGA" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">REGA[0:7]</obj_property> |
<obj_property name="ObjectShortName">REGA[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/REGB" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">REGB[0:7]</obj_property> |
<obj_property name="ObjectShortName">REGB[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/REGC" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">REGC[0:7]</obj_property> |
<obj_property name="ObjectShortName">REGC[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/REGX" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">REGX[0:7]</obj_property> |
<obj_property name="ObjectShortName">REGX[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/REGY" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">REGY[0:7]</obj_property> |
<obj_property name="ObjectShortName">REGY[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/REGZ" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">REGZ[0:7]</obj_property> |
<obj_property name="ObjectShortName">REGZ[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/FetchTemporalReg1" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">FetchTemporalReg1[0:7]</obj_property> |
<obj_property name="ObjectShortName">FetchTemporalReg1[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/FetchTemporalReg2" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">FetchTemporalReg2[0:7]</obj_property> |
<obj_property name="ObjectShortName">FetchTemporalReg2[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/FetchTemporalReg3" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">FetchTemporalReg3[0:7]</obj_property> |
<obj_property name="ObjectShortName">FetchTemporalReg3[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/FetchState" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">FetchState[0:7]</obj_property> |
<obj_property name="ObjectShortName">FetchState[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/NumberOfBytesToRead" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">NumberOfBytesToRead[0:1]</obj_property> |
<obj_property name="ObjectShortName">NumberOfBytesToRead[0:1]</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/CounterOfBytesToRead" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">CounterOfBytesToRead[0:1]</obj_property> |
<obj_property name="ObjectShortName">CounterOfBytesToRead[0:1]</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/Opcode" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">Opcode[0:7]</obj_property> |
<obj_property name="ObjectShortName">Opcode[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/InstExecuteState" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">InstExecuteState[0:7]</obj_property> |
<obj_property name="ObjectShortName">InstExecuteState[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/AluInputData" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">AluInputData[0:7]</obj_property> |
<obj_property name="ObjectShortName">AluInputData[0:7]</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/PCIsNotLocked" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">PCIsNotLocked</obj_property> |
<obj_property name="ObjectShortName">PCIsNotLocked</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/DecodeState" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">DecodeState[0:7]</obj_property> |
<obj_property name="ObjectShortName">DecodeState[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/DecodeIsBusy" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">DecodeIsBusy</obj_property> |
<obj_property name="ObjectShortName">DecodeIsBusy</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/RequestDecode" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">RequestDecode</obj_property> |
<obj_property name="ObjectShortName">RequestDecode</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/ExecuteIsBusy" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">ExecuteIsBusy</obj_property> |
<obj_property name="ObjectShortName">ExecuteIsBusy</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/ExecuteCode" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">ExecuteCode[0:15]</obj_property> |
<obj_property name="ObjectShortName">ExecuteCode[0:15]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/RequestExecute" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">RequestExecute</obj_property> |
<obj_property name="ObjectShortName">RequestExecute</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/LockPC" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">LockPC</obj_property> |
<obj_property name="ObjectShortName">LockPC</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/PCIsNotLocked" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">PCIsNotLocked</obj_property> |
<obj_property name="ObjectShortName">PCIsNotLocked</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/RequestUnlockPC" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">RequestUnlockPC</obj_property> |
<obj_property name="ObjectShortName">RequestUnlockPC</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/InstExecuteState" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">InstExecuteState[0:7]</obj_property> |
<obj_property name="ObjectShortName">InstExecuteState[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/AluInput1" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">AluInput1[0:7]</obj_property> |
<obj_property name="ObjectShortName">AluInput1[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/ControlUnit/AluInput2" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">AluInput2[0:7]</obj_property> |
<obj_property name="ObjectShortName">AluInput2[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
</wvobject> |
<wvobject fp_name="group26" type="group"> |
<obj_property name="label">PCUnit</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
<wvobject fp_name="/quantum_tb/uut/PCUnit/TemporalPC" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">TemporalPC[0:7]</obj_property> |
<obj_property name="ObjectShortName">TemporalPC[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/PCUnit/ProgramCounter" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">ProgramCounter[0:7]</obj_property> |
<obj_property name="ObjectShortName">ProgramCounter[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/PCUnit/DataWrite" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">DataWrite[0:7]</obj_property> |
<obj_property name="ObjectShortName">DataWrite[0:7]</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/PCUnit/WritePC" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">WritePC</obj_property> |
<obj_property name="ObjectShortName">WritePC</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/PCUnit/IncrementPC" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">IncrementPC</obj_property> |
<obj_property name="ObjectShortName">IncrementPC</obj_property> |
</wvobject> |
</wvobject> |
<wvobject fp_name="group32" type="group"> |
<obj_property name="label">RomUnit</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
<wvobject fp_name="/quantum_tb/uut/RomUnit/address" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">address[7:0]</obj_property> |
<obj_property name="ObjectShortName">address[7:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/RomUnit/datain" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">datain[7:0]</obj_property> |
<obj_property name="ObjectShortName">datain[7:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/RomUnit/dataout" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">dataout[7:0]</obj_property> |
<obj_property name="ObjectShortName">dataout[7:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/RomUnit/writeenable" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">writeenable</obj_property> |
<obj_property name="ObjectShortName">writeenable</obj_property> |
</wvobject> |
</wvobject> |
<wvobject fp_name="group34" type="group"> |
<obj_property name="label">ALU</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
<wvobject fp_name="/quantum_tb/uut/AluUnit/AluInput2" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">AluInput2[0:7]</obj_property> |
<obj_property name="ObjectShortName">AluInput2[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/AluUnit/AluInput1" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">AluInput1[0:7]</obj_property> |
<obj_property name="ObjectShortName">AluInput1[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/AluUnit/AluInstruction" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">AluInstruction[0:7]</obj_property> |
<obj_property name="ObjectShortName">AluInstruction[0:7]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/quantum_tb/uut/AluUnit/AluResult" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">AluResult[0:15]</obj_property> |
<obj_property name="ObjectShortName">AluResult[0:15]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
</wvobject> |
</wave_config> |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/ControlUnit/ExecuteUnit/ExecuteUnit.v
0,0 → 1,262
//////////////////////////////////////////////// |
// @file ExecuteUnit.v |
// @brief Execute Unit for Quantum Processor |
// @date 9/28/2014 |
//////////////////////////////////////////////// |
|
`include "ExecuteUnit.vh" |
`include "../../Alu/Alu.vh" |
|
module ExecuteUnit ( |
input Clock, |
input Reset, |
input RequestExecute, |
input [0:15] AluResult, |
input [0:15] ExecuteCode, |
input [0:7] FetchTemporalReg1, |
input [0:7] FetchTemporalReg2, |
input [0:7] FetchTemporalReg3, |
output reg [0:7] REGA, |
output reg [0:7] REGB, |
output reg [0:7] REGC, |
output reg [0:7] REGX, |
output reg [0:7] REGY, |
output reg [0:7] REGZ, |
output reg [0:7] AluInput1, |
output reg [0:7] AluInput2, |
output reg [0:7] AluInstruction, |
output reg [0:7] BusDataOut, |
output reg [0:7] NewPC, |
output reg WritePC, |
output reg ExecuteIsBusy, |
output reg RequestUnlockPC, |
output reg WriteEnable |
); |
|
reg [0:7] InstExecuteState; |
|
always@(posedge Clock, negedge Reset) begin |
if (Reset == 1'b0) begin |
AluInput1 <= 8'h00; |
AluInput2 <= 8'h00; |
AluInstruction <= 8'h00; |
REGA <= 8'h00; |
REGB <= 8'h00; |
REGC <= 8'h00; |
REGX <= 8'h00; |
REGY <= 8'h00; |
REGZ <= 8'h00; |
WritePC <= 1'b0; |
ExecuteIsBusy <= 1'b1; |
RequestUnlockPC <= 1'b0; |
WriteEnable <= 1'b0; |
BusDataOut <= 8'h00; |
InstExecuteState <= 8'h00; |
end else begin |
WritePC <= 1'b0; |
|
if (RequestExecute == 1'b1) begin |
ExecuteIsBusy <= 1'b1; |
|
case (ExecuteCode) |
`idle: begin |
InstExecuteState <= 8'h00; |
end |
`ldr_rega_data: begin |
REGA <= FetchTemporalReg2; |
ExecuteIsBusy <= 1'b0; |
end |
`ldr_regb_data: begin |
REGB <= FetchTemporalReg2; |
ExecuteIsBusy <= 1'b0; |
end |
`ldr_regc_data: begin |
REGC <= FetchTemporalReg2; |
ExecuteIsBusy <= 1'b0; |
end |
`ldr_regx_data: begin |
REGX <= FetchTemporalReg2; |
ExecuteIsBusy <= 1'b0; |
end |
`ldr_regy_data: begin |
REGY <= FetchTemporalReg2; |
ExecuteIsBusy <= 1'b0; |
end |
`ldr_regz_data: begin |
REGZ <= FetchTemporalReg2; |
ExecuteIsBusy <= 1'b0; |
end |
`ldm_addr_data: begin |
case (InstExecuteState) |
8'h00: begin |
BusDataOut <= FetchTemporalReg2; |
InstExecuteState <= 8'h01; |
end |
|
8'h01: begin |
WriteEnable <= 1'b1; |
InstExecuteState <= 8'h02; |
end |
|
8'h02: begin |
WriteEnable <= 1'b0; |
InstExecuteState <= 8'h00; |
end |
endcase |
end |
|
`addrr_rega_regx: begin |
case (InstExecuteState) |
8'h00: begin |
AluInput1 <= REGA; |
AluInput2 <= REGX; |
AluInstruction <= `Add; |
InstExecuteState <= 8'h01; |
end |
|
8'h01: begin |
InstExecuteState <= 8'h02; |
end |
|
8'h02: begin |
AluInstruction <= `Idle; |
REGA <= AluResult[8:15]; |
ExecuteIsBusy <= 1'b0; |
InstExecuteState <= 8'h00; |
end |
endcase |
end |
|
`addrr_regb_regx: begin |
case (InstExecuteState) |
8'h00: begin |
AluInput1 <= REGB; |
AluInput2 <= REGX; |
AluInstruction <= `Add; |
InstExecuteState <= 8'h01; |
end |
|
8'h01: begin |
InstExecuteState <= 8'h02; |
end |
|
8'h02: begin |
AluInstruction <= `Idle; |
REGB <= AluResult[8:15]; |
ExecuteIsBusy <= 1'b0; |
InstExecuteState <= 8'h00; |
end |
endcase |
end |
|
`addrr_regc_regx: begin |
case (InstExecuteState) |
8'h00: begin |
AluInput1 <= REGC; |
AluInput2 <= REGX; |
AluInstruction <= `Add; |
InstExecuteState <= 8'h01; |
end |
|
8'h01: begin |
InstExecuteState <= 8'h02; |
end |
|
8'h02: begin |
AluInstruction <= `Idle; |
REGC <= AluResult[8:15]; |
ExecuteIsBusy <= 1'b0; |
InstExecuteState <= 8'h00; |
end |
endcase |
end |
|
`breqrr_rega_regy: begin |
NewPC <= FetchTemporalReg3; |
|
case (InstExecuteState) |
8'h00: begin |
if (REGA == REGY) begin |
ExecuteIsBusy <= 1'b0; |
InstExecuteState <= 8'h01; |
RequestUnlockPC <= 1'b1; |
end else begin |
WritePC <= 1'b1; |
InstExecuteState <= 8'h01; |
end |
end |
|
8'h01: begin |
InstExecuteState <= 8'h02; |
end |
|
8'h02: begin |
RequestUnlockPC <= 1'b0; |
ExecuteIsBusy <= 1'b0; |
InstExecuteState <= 8'h00; |
end |
endcase |
end |
|
`breqrr_regb_regy: begin |
NewPC <= FetchTemporalReg3; |
|
case (InstExecuteState) |
8'h00: begin |
if (REGB == REGY) begin |
ExecuteIsBusy <= 1'b0; |
InstExecuteState <= 8'h01; |
RequestUnlockPC <= 1'b1; |
end else begin |
WritePC <= 1'b1; |
InstExecuteState <= 8'h01; |
end |
end |
|
8'h01: begin |
InstExecuteState <= 8'h02; |
end |
|
8'h02: begin |
RequestUnlockPC <= 1'b0; |
ExecuteIsBusy <= 1'b0; |
InstExecuteState <= 8'h00; |
end |
endcase |
end |
|
`jmpr_regz: begin |
NewPC <= REGZ; |
|
case (InstExecuteState) |
8'h00: begin // JUMP TO ADDRESS |
WritePC <= 1'b1; |
InstExecuteState <= 8'h01; |
end |
|
8'h01: begin // WAIT FOR MEMORY TO GET VALUE |
InstExecuteState <= 8'h02; |
end |
|
8'h02: begin // RESET STATE MACHINE |
RequestUnlockPC <= 1'b0; |
ExecuteIsBusy <= 1'b0; |
InstExecuteState <= 8'h00; |
end |
endcase |
end |
|
default: begin |
InstExecuteState <= 8'h00; |
end |
endcase |
end else begin |
InstExecuteState <= 8'h00; |
end |
end |
end |
endmodule |
|
//////////////////////////////////////////////// |
// EOF |
//////////////////////////////////////////////// |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/ControlUnit/ExecuteUnit/ExecuteUnit.vh
0,0 → 1,107
//////////////////////////////////////////////// |
// @file ExecuteUnit.vh |
// @brief Execute Unit Definitions |
// @date 9/28/2014 |
//////////////////////////////////////////////// |
|
`ifndef _EXECUTEUNIT_VH_ |
`define _EXECUTEUNIT_VH_ |
|
/* |
**************************** |
* Define Execution codes |
**************************** |
*/ |
|
`define idle 16'h0000 |
`define ldr_rega_data 16'h0001 |
`define ldr_regb_data 16'h0002 |
`define ldr_regc_data 16'h0003 |
`define ldr_regx_data 16'h0004 |
`define ldr_regy_data 16'h0005 |
`define ldr_regz_data 16'h0006 |
`define ldm_addr_data 16'h0007 |
`define addrr_rega_rega 16'h0008 |
`define addrr_rega_regb 16'h0009 |
`define addrr_rega_regc 16'h000A |
`define addrr_rega_regx 16'h000B |
`define addrr_rega_regy 16'h000C |
`define addrr_rega_regz 16'h000D |
`define addrr_regb_rega 16'h000E |
`define addrr_regb_regb 16'h000F |
`define addrr_regb_regc 16'h0010 |
`define addrr_regb_regx 16'h0011 |
`define addrr_regb_regy 16'h0012 |
`define addrr_regb_regz 16'h0013 |
`define addrr_regc_rega 16'h0014 |
`define addrr_regc_regb 16'h0015 |
`define addrr_regc_regc 16'h0016 |
`define addrr_regc_regx 16'h0017 |
`define addrr_regc_regy 16'h0018 |
`define addrr_regc_regz 16'h0019 |
`define addrr_regx_rega 16'h001A |
`define addrr_regx_regb 16'h001B |
`define addrr_regx_regc 16'h001C |
`define addrr_regx_regx 16'h001D |
`define addrr_regx_regy 16'h001E |
`define addrr_regx_regz 16'h001F |
`define addrr_regy_rega 16'h0020 |
`define addrr_regy_regb 16'h0021 |
`define addrr_regy_regc 16'h0022 |
`define addrr_regy_regx 16'h0023 |
`define addrr_regy_regy 16'h0024 |
`define addrr_regy_regz 16'h0025 |
`define addrr_regz_rega 16'h0026 |
`define addrr_regz_regb 16'h0027 |
`define addrr_regz_regc 16'h0028 |
`define addrr_regz_regx 16'h0029 |
`define addrr_regz_regy 16'h002A |
`define addrr_regz_regz 16'h002B |
`define addrm_rega_addr 16'h002C |
`define addrm_regb_addr 16'h002D |
`define addrm_regc_addr 16'h002E |
`define addrm_regx_addr 16'h002F |
`define addrm_regy_addr 16'h0030 |
`define addrm_regz_addr 16'h0031 |
`define addmr_addr_rega 16'h0032 |
`define addmr_addr_regb 16'h0033 |
`define addmr_addr_regc 16'h0034 |
`define addmr_addr_regx 16'h0035 |
`define addmr_addr_regy 16'h0036 |
`define addmr_addr_regz 16'h0037 |
`define addmm_addr_addr 16'h0038 |
`define breqrr_rega_regb 16'h0039 |
`define breqrr_rega_regc 16'h003A |
`define breqrr_rega_regx 16'h003B |
`define breqrr_rega_regy 16'h003C |
`define breqrr_rega_regz 16'h003D |
`define breqrr_regb_rega 16'h003E |
`define breqrr_regb_regc 16'h003F |
`define breqrr_regb_regx 16'h0040 |
`define breqrr_regb_regy 16'h0041 |
`define breqrr_regb_regz 16'h0042 |
`define breqrr_regc_rega 16'h0043 |
`define breqrr_regc_regb 16'h0044 |
`define breqrr_regc_regx 16'h0045 |
`define breqrr_regc_regy 16'h0046 |
`define breqrr_regc_regz 16'h0047 |
`define breqrm_rega_addr 16'h0048 |
`define breqrm_regb_addr 16'h0049 |
`define breqrm_regc_addr 16'h004A |
`define breqrm_regx_addr 16'h004B |
`define breqrm_regy_addr 16'h004C |
`define breqrm_regz_addr 16'h004D |
`define breqmm_addr_addr 16'h004E |
`define jmpr_rega 16'h004F |
`define jmpr_regb 16'h0050 |
`define jmpr_regc 16'h0051 |
`define jmpr_regx 16'h0052 |
`define jmpr_regy 16'h0053 |
`define jmpr_regz 16'h0054 |
`define jmpm_addr 16'h0055 |
|
`endif |
|
//////////////////////////////////////////////// |
// EOF |
//////////////////////////////////////////////// |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/ControlUnit/DecodeUnit/DecodeUnit.vh
0,0 → 1,39
//////////////////////////////////////////////// |
// @file DecodeUnit.vh |
// @brief Decode Unit Definitions |
// @date 9/28/2014 |
//////////////////////////////////////////////// |
|
`ifndef _DECODEUNIT_VH_ |
`define _DECODEUNIT_VH_ |
|
/* |
**************************** |
* Define Decode SM States. |
**************************** |
*/ |
|
`define Decode 8'h00 |
`define RequestExecute 8'h01 |
`define WaitExecute 8'h02 |
`define WaitRequest 8'h03 |
`define ResetDecodeSM 8'h04 |
|
/* |
**************************** |
* Define Registers |
**************************** |
*/ |
|
`define rega 8'h00 |
`define regb 8'h01 |
`define regc 8'h02 |
`define regx 8'h03 |
`define regy 8'h04 |
`define regz 8'h05 |
|
`endif |
|
//////////////////////////////////////////////// |
// EOF |
//////////////////////////////////////////////// |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/ControlUnit/DecodeUnit/DecodeUnit.v
0,0 → 1,266
//////////////////////////////////////////////// |
// @file DecodeUnit.v |
// @brief Decode Unit for Quantum Processor |
// @date 9/28/2014 |
//////////////////////////////////////////////// |
|
`include "DecodeUnit.vh" |
`include "../ExecuteUnit/ExecuteUnit.vh" |
`include "../FetchUnit/FetchUnit.vh" |
|
module DecodeUnit ( |
input Clock, |
input Reset, |
input RequestDecode, |
input ExecuteIsBusy, |
input [0:7] Opcode, |
input [0:7] FetchTemporalReg1, |
input [0:7] FetchTemporalReg2, |
input [0:7] FetchTemporalReg3, |
output reg [0:15] ExecuteCode, |
output reg DecodeIsBusy, |
output reg RequestExecute, |
output reg MemoryIsCorrupted |
); |
|
reg [0:7] DecodeState; |
|
always@(posedge Clock, negedge Reset) begin |
if (Reset == 1'b0) begin |
DecodeIsBusy <= 1'b1; |
RequestExecute <= 1'b0; |
MemoryIsCorrupted <= 1'b0; |
ExecuteCode <= `idle; |
DecodeState <= `Decode; |
end else begin |
DecodeIsBusy <= 1'b1; |
|
case(DecodeState) |
`Decode: begin |
if (RequestDecode == 1'b1) begin |
DecodeState <= `RequestExecute; |
|
////////////////////////////////////////////////// |
///// Load Instructions |
////////////////////////////////////////////////// |
if ((Opcode == `ldr) && (FetchTemporalReg1 == `rega)) begin |
ExecuteCode <= `ldr_rega_data; |
end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regb)) begin |
ExecuteCode <= `ldr_regb_data; |
end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regc)) begin |
ExecuteCode <= `ldr_regc_data; |
end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regx)) begin |
ExecuteCode <= `ldr_regx_data; |
end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regy)) begin |
ExecuteCode <= `ldr_regy_data; |
end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regz)) begin |
ExecuteCode <= `ldr_regz_data; |
end else if (Opcode == `ldm) begin |
ExecuteCode <= `ldm_addr_data; |
|
////////////////////////////////////////////////// |
///// Addition operations |
////////////////////////////////////////////////// |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `rega)) begin |
ExecuteCode <= `addrr_rega_rega; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regb)) begin |
ExecuteCode <= `addrr_rega_regb; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regc)) begin |
ExecuteCode <= `addrr_rega_regc; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regx)) begin |
ExecuteCode <= `addrr_rega_regx; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regy)) begin |
ExecuteCode <= `addrr_rega_regy; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regz)) begin |
ExecuteCode <= `addrr_rega_regz; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `rega)) begin |
ExecuteCode <= `addrr_regb_rega; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regb)) begin |
ExecuteCode <= `addrr_regb_regb; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regc)) begin |
ExecuteCode <= `addrr_regb_regc; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regx)) begin |
ExecuteCode <= `addrr_regb_regx; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regy)) begin |
ExecuteCode <= `addrr_regb_regy; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regz)) begin |
ExecuteCode <= `addrr_regb_regz; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `rega)) begin |
ExecuteCode <= `addrr_regc_rega; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regb)) begin |
ExecuteCode <= `addrr_regc_regb; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regc)) begin |
ExecuteCode <= `addrr_regc_regc; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regx)) begin |
ExecuteCode <= `addrr_regc_regx; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regy)) begin |
ExecuteCode <= `addrr_regc_regy; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regz)) begin |
ExecuteCode <= `addrr_regc_regz; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `rega)) begin |
ExecuteCode <= `addrr_regx_rega; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regb)) begin |
ExecuteCode <= `addrr_regx_regb; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regc)) begin |
ExecuteCode <= `addrr_regx_regc; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regx)) begin |
ExecuteCode <= `addrr_regx_regx; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regy)) begin |
ExecuteCode <= `addrr_regx_regy; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regz)) begin |
ExecuteCode <= `addrr_regx_regz; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `rega)) begin |
ExecuteCode <= `addrr_regy_rega; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regb)) begin |
ExecuteCode <= `addrr_regy_regb; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regc)) begin |
ExecuteCode <= `addrr_regy_regc; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regx)) begin |
ExecuteCode <= `addrr_regy_regx; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regy)) begin |
ExecuteCode <= `addrr_regy_regy; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regz)) begin |
ExecuteCode <= `addrr_regy_regz; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `rega)) begin |
ExecuteCode <= `addrr_regz_rega; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regb)) begin |
ExecuteCode <= `addrr_regz_regb; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regc)) begin |
ExecuteCode <= `addrr_regz_regc; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regx)) begin |
ExecuteCode <= `addrr_regz_regx; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regy)) begin |
ExecuteCode <= `addrr_regz_regy; |
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regz)) begin |
ExecuteCode <= `addrr_regz_regz; |
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `rega)) begin |
ExecuteCode <= `addrm_rega_addr; |
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regb)) begin |
ExecuteCode <= `addrm_regb_addr; |
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regc)) begin |
ExecuteCode <= `addrm_regc_addr; |
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regx)) begin |
ExecuteCode <= `addrm_regx_addr; |
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regy)) begin |
ExecuteCode <= `addrm_regy_addr; |
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regz)) begin |
ExecuteCode <= `addrm_regz_addr; |
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `rega)) begin |
ExecuteCode <= `addmr_addr_rega; |
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regb)) begin |
ExecuteCode <= `addmr_addr_regb; |
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regc)) begin |
ExecuteCode <= `addmr_addr_regc; |
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regx)) begin |
ExecuteCode <= `addmr_addr_regx; |
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regy)) begin |
ExecuteCode <= `addmr_addr_regy; |
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regz)) begin |
ExecuteCode <= `addmr_addr_regz; |
end else if (Opcode == `addmm) begin |
ExecuteCode <= `addmm_addr_addr; |
|
////////////////////////////////////////////////// |
///// Branch Instructions |
////////////////////////////////////////////////// |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regb)) begin |
ExecuteCode <= `breqrr_rega_regb; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regc)) begin |
ExecuteCode <= `breqrr_rega_regc; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regx)) begin |
ExecuteCode <= `breqrr_rega_regx; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regy)) begin |
ExecuteCode <= `breqrr_rega_regy; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regz)) begin |
ExecuteCode <= `breqrr_rega_regz; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `rega)) begin |
ExecuteCode <= `breqrr_regb_rega; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regc)) begin |
ExecuteCode <= `breqrr_regb_regc; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regx)) begin |
ExecuteCode <= `breqrr_regb_regx; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regy)) begin |
ExecuteCode <= `breqrr_regb_regy; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regz)) begin |
ExecuteCode <= `breqrr_regb_regz; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `rega)) begin |
ExecuteCode <= `breqrr_regc_rega; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regb)) begin |
ExecuteCode <= `breqrr_regc_regb; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regx)) begin |
ExecuteCode <= `breqrr_regc_regx; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regy)) begin |
ExecuteCode <= `breqrr_regc_regy; |
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regz)) begin |
ExecuteCode <= `breqrr_regc_regz; |
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `rega)) begin |
ExecuteCode <= `breqrm_rega_addr; |
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regb)) begin |
ExecuteCode <= `breqrm_regb_addr; |
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regc)) begin |
ExecuteCode <= `breqrm_regc_addr; |
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regx)) begin |
ExecuteCode <= `breqrm_regx_addr; |
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regy)) begin |
ExecuteCode <= `breqrm_regy_addr; |
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regz)) begin |
ExecuteCode <= `breqrm_regz_addr; |
end else if (Opcode == `breqmm) begin |
ExecuteCode <= `breqmm_addr_addr; |
|
////////////////////////////////////////////////// |
///// Jump Instructions |
////////////////////////////////////////////////// |
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `rega)) begin |
ExecuteCode <= `jmpr_rega; |
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regb)) begin |
ExecuteCode <= `jmpr_regb; |
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regc)) begin |
ExecuteCode <= `jmpr_regc; |
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regx)) begin |
ExecuteCode <= `jmpr_regx; |
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regy)) begin |
ExecuteCode <= `jmpr_regy; |
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regz)) begin |
ExecuteCode <= `jmpr_regz; |
end else if (Opcode == `jmpm) begin |
ExecuteCode <= `jmpm_addr; |
end else begin |
ExecuteCode <= `idle; |
MemoryIsCorrupted <= 1'b0; |
DecodeState <= `Decode; |
end |
end |
end |
|
`RequestExecute: begin |
RequestExecute <= 1'b1; |
DecodeState <= `WaitRequest; |
end |
|
`WaitRequest: begin |
DecodeState <= `WaitExecute; |
end |
|
`WaitExecute: begin |
if (ExecuteIsBusy == 1'b0) begin |
DecodeState <= `ResetDecodeSM; |
RequestExecute <= 1'b0; |
DecodeIsBusy <= 1'b0; |
ExecuteCode <= `idle; |
end |
end |
|
`ResetDecodeSM: begin |
if (RequestDecode == 1'b0) begin |
DecodeState <= `Decode; |
end |
end |
endcase |
end |
end |
endmodule |
|
//////////////////////////////////////////////// |
// EOF |
//////////////////////////////////////////////// |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/ControlUnit/ControlUnit.v
0,0 → 1,105
//////////////////////////////////////////////// |
// @file ControlUnit.v |
// @brief Control Unit of Quantum Processor |
// @date 9/28/2014 |
//////////////////////////////////////////////// |
|
module ControlUnit ( |
input Clock, |
input Reset, |
input [0:7] BusDataIn, |
input [0:15] AluResult, |
output IncrementPC, |
output WritePC, |
output WriteEnable, |
output [0:7] BusDataOut, |
output [0:7] NewPC, |
output [0:7] AluInstruction, |
output [0:7] AluInput1, |
output [0:7] AluInput2, |
output [0:7] REGA, |
output [0:7] REGB, |
output [0:7] REGC, |
output [0:7] REGX, |
output [0:7] REGY, |
output [0:7] REGZ |
); |
|
wire [0:15] ExecuteCode; |
wire [0:7] Opcode; |
wire [0:7] FetchTemporalReg1; |
wire [0:7] FetchTemporalReg2; |
wire [0:7] FetchTemporalReg3; |
wire RequestDecode; |
wire DecodeIsBusy; |
wire LockPC; |
wire PCIsNotLocked; |
wire IncrementPC1; |
wire ExecuteIsBusy; |
wire RequestExecute; |
wire MemoryIsCorrupted; |
wire RequestUnlockPC; |
|
FetchUnit FetchUnit( |
.Clock (Clock), |
.Reset (Reset), |
.DecodeIsBusy (DecodeIsBusy), |
.RequestUnlockPC (RequestUnlockPC), |
.BusDataIn (BusDataIn), |
.Opcode (Opcode), |
.FetchTemporalReg1 (FetchTemporalReg1), |
.FetchTemporalReg2 (FetchTemporalReg2), |
.FetchTemporalReg3 (FetchTemporalReg3), |
.RequestDecode (RequestDecode), |
.LockPC (LockPC), |
.PCIsNotLocked (PCIsNotLocked), |
.IncrementPC (IncrementPC1) |
); |
|
DecodeUnit DecodeUnit( |
.Clock (Clock), |
.Reset (Reset), |
.RequestDecode (RequestDecode), |
.ExecuteIsBusy (ExecuteIsBusy), |
.Opcode (Opcode), |
.FetchTemporalReg1 (FetchTemporalReg1), |
.FetchTemporalReg2 (FetchTemporalReg2), |
.FetchTemporalReg3 (FetchTemporalReg3), |
.ExecuteCode (ExecuteCode), |
.DecodeIsBusy (DecodeIsBusy), |
.RequestExecute (RequestExecute), |
.MemoryIsCorrupted (MemoryIsCorrupted) |
); |
|
ExecuteUnit ExecuteUnit( |
.Clock (Clock), |
.Reset (Reset), |
.RequestExecute (RequestExecute), |
.AluResult (AluResult), |
.ExecuteCode (ExecuteCode), |
.FetchTemporalReg1 (FetchTemporalReg1), |
.FetchTemporalReg2 (FetchTemporalReg2), |
.FetchTemporalReg3 (FetchTemporalReg3), |
.REGA (REGA), |
.REGB (REGB), |
.REGC (REGC), |
.REGX (REGX), |
.REGY (REGY), |
.REGZ (REGZ), |
.AluInput1 (AluInput1), |
.AluInput2 (AluInput2), |
.AluInstruction (AluInstruction), |
.BusDataOut (BusDataOut), |
.NewPC (NewPC), |
.WritePC (WritePC), |
.ExecuteIsBusy (ExecuteIsBusy), |
.RequestUnlockPC (RequestUnlockPC), |
.WriteEnable (WriteEnable) |
); |
|
assign IncrementPC = PCIsNotLocked & IncrementPC1; |
endmodule |
|
//////////////////////////////////////////////// |
// EOF |
//////////////////////////////////////////////// |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/ControlUnit/FetchUnit/FetchUnit.vh
0,0 → 1,59
//////////////////////////////////////////////// |
// @file FetchUnit.vh |
// @brief Fetch Unit Definitions |
// @date 9/28/2014 |
//////////////////////////////////////////////// |
|
`ifndef _FETCHUNIT_VH_ |
`define _FETCHUNIT_VH_ |
|
/* |
**************************** |
* Define Fetch SM States. |
**************************** |
*/ |
|
`define GetOpcode 8'h00 |
`define WaitNumberOfBytesToRead 8'h01 |
`define ReadData1 8'h02 |
`define WaitPCIncrement1 8'h03 |
`define WaitMemory1 8'h04 |
`define SaveData1 8'h05 |
`define ReadData2 8'h06 |
`define WaitPCIncrement2 8'h07 |
`define WaitMemory2 8'h08 |
`define SaveData2 8'h09 |
`define ReadData3 8'h0A |
`define WaitPCIncrement3 8'h0B |
`define WaitMemory3 8'h0C |
`define SaveData3 8'h0D |
`define RequestDecode 8'h0E |
`define WaitDecode 8'h0F |
`define IncrementPC 8'h10 |
`define WaitIncrementPC 8'h11 |
`define ResetFetchSM 8'h12 |
|
/* |
**************************** |
* Define Opcodes |
**************************** |
*/ |
|
`define nop 8'h00 |
`define ldr 8'h01 |
`define ldm 8'h02 |
`define addrr 8'h03 |
`define addrm 8'h04 |
`define addmr 8'h05 |
`define addmm 8'h06 |
`define breqrr 8'h07 |
`define breqrm 8'h08 |
`define breqmm 8'h09 |
`define jmpr 8'h0A |
`define jmpm 8'h0B |
|
`endif // _FETCHUNIT_VH_ |
|
//////////////////////////////////////////////// |
// EOF |
//////////////////////////////////////////////// |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/ControlUnit/FetchUnit/FetchUnit.v
0,0 → 1,231
//////////////////////////////////////////////// |
// @file FetchUnit.v |
// @brief Fetch Control for Quantum Processor |
// @date 9/28/2014 |
//////////////////////////////////////////////// |
|
`include "FetchUnit.vh" |
|
module FetchUnit ( |
input Clock, |
input Reset, |
input DecodeIsBusy, |
input RequestUnlockPC, |
input [0:7] BusDataIn, |
output reg [0:7] Opcode, |
output reg [0:7] FetchTemporalReg1, |
output reg [0:7] FetchTemporalReg2, |
output reg [0:7] FetchTemporalReg3, |
output reg RequestDecode, |
output reg LockPC, |
output reg PCIsNotLocked, |
output reg IncrementPC |
); |
|
reg [0:1] CounterOfBytesToRead; |
reg [0:1] NumberOfBytesToRead; |
reg [0:7] FetchState; |
|
always@(posedge Clock, negedge Reset) begin |
if (Reset == 1'b0) begin |
RequestDecode <= 1'b0; |
CounterOfBytesToRead <= 2'b00; |
NumberOfBytesToRead <= 2'b00; |
Opcode <= `nop; |
FetchTemporalReg1 <= 8'h00; |
FetchTemporalReg2 <= 8'h00; |
FetchTemporalReg3 <= 8'h00; |
LockPC <= 1'b0; |
PCIsNotLocked <= 1'b1; |
IncrementPC <= 1'b0; |
FetchState <= `GetOpcode; |
end else begin |
IncrementPC <= 1'b0; |
|
case (FetchState) |
`GetOpcode: begin |
LockPC <= 1'b0; |
PCIsNotLocked <= 1'b1; |
CounterOfBytesToRead <= 2'b00; |
FetchState <= `WaitNumberOfBytesToRead; |
Opcode <= BusDataIn; |
|
case (BusDataIn) |
`ldr: begin |
NumberOfBytesToRead <= 2'b10; |
end |
`ldm: begin |
NumberOfBytesToRead <= 2'b10; |
end |
`addrr: begin |
NumberOfBytesToRead <= 2'b10; |
end |
`addrm: begin |
NumberOfBytesToRead <= 2'b10; |
end |
`addmr: begin |
NumberOfBytesToRead <= 2'b10; |
end |
`addmm: begin |
NumberOfBytesToRead <= 2'b10; |
end |
`breqrr: begin |
LockPC <= 1'b1; |
NumberOfBytesToRead <= 2'b11; |
end |
`breqrm: begin |
LockPC <= 1'b1; |
NumberOfBytesToRead <= 2'b11; |
end |
`breqmm: begin |
LockPC <= 1'b1; |
NumberOfBytesToRead <= 2'b11; |
end |
`jmpr: begin |
LockPC <= 1'b1; |
NumberOfBytesToRead <= 2'b10; |
end |
`jmpm: begin |
LockPC <= 1'b1; |
NumberOfBytesToRead <= 2'b10; |
end |
default: begin |
NumberOfBytesToRead <= 2'b00; |
FetchState <= `GetOpcode; |
Opcode <= `nop; |
end |
endcase |
end |
|
`WaitNumberOfBytesToRead: begin |
FetchState <= `ReadData1; |
end |
|
////////////////////////////////////////////////// |
///// READ DATA 1 |
////////////////////////////////////////////////// |
`ReadData1: begin |
FetchState <= `WaitPCIncrement1; |
CounterOfBytesToRead <= 2'b00; |
|
if (CounterOfBytesToRead < NumberOfBytesToRead) begin |
CounterOfBytesToRead <= CounterOfBytesToRead + 1; |
IncrementPC <= 1'b1; |
end else begin |
FetchState <= `RequestDecode; |
end |
end |
|
`WaitPCIncrement1: begin |
FetchState <= `WaitMemory1; |
end |
|
`WaitMemory1: begin |
FetchState <= `SaveData1; |
end |
|
`SaveData1: begin |
FetchTemporalReg1 <= BusDataIn; |
FetchState <= `ReadData2; |
end |
|
////////////////////////////////////////////////// |
///// READ DATA 2 |
////////////////////////////////////////////////// |
`ReadData2: begin |
FetchState <= `WaitPCIncrement2; |
CounterOfBytesToRead <= 2'b00; |
|
if (CounterOfBytesToRead < NumberOfBytesToRead) begin |
CounterOfBytesToRead <= CounterOfBytesToRead + 1; |
IncrementPC <= 1'b1; |
end else begin |
FetchState <= `RequestDecode; |
end |
end |
|
`WaitPCIncrement2: begin |
FetchState <= `WaitMemory2; |
end |
|
`WaitMemory2: begin |
FetchState <= `SaveData2; |
end |
|
`SaveData2: begin |
FetchTemporalReg2 <= BusDataIn; |
FetchState <= `ReadData3; |
end |
|
////////////////////////////////////////////////// |
///// READ DATA 3 |
////////////////////////////////////////////////// |
`ReadData3: begin |
FetchState <= `WaitPCIncrement3; |
CounterOfBytesToRead <= 2'b00; |
|
if (CounterOfBytesToRead < NumberOfBytesToRead) begin |
CounterOfBytesToRead <= CounterOfBytesToRead + 1; |
IncrementPC <= 1'b1; |
end else begin |
FetchState <= `RequestDecode; |
end |
end |
|
`WaitPCIncrement3: begin |
FetchState <= `WaitMemory3; |
end |
|
`WaitMemory3: begin |
FetchState <= `SaveData3; |
end |
|
`SaveData3: begin |
FetchTemporalReg3 <= BusDataIn; |
FetchState <= `RequestDecode; |
end |
|
////////////////////////////////////////////////// |
///// Request Decode |
////////////////////////////////////////////////// |
`RequestDecode: begin |
RequestDecode <= 1'b1; |
CounterOfBytesToRead <= 8'h00; |
FetchState <= `WaitDecode; |
|
if (LockPC == 1'b1) begin |
PCIsNotLocked <= 1'b0; |
end |
end |
|
`WaitDecode: begin |
if (DecodeIsBusy == 1'b0) begin |
FetchState <= `IncrementPC; |
end |
end |
|
`IncrementPC: begin |
RequestDecode <= 1'b0; |
IncrementPC <= 1'b1; |
FetchState <= `WaitIncrementPC; |
|
if (RequestUnlockPC == 1'b1) begin |
PCIsNotLocked <= 1'b1; |
end |
end |
|
`WaitIncrementPC: begin |
FetchState <= `ResetFetchSM; |
end |
|
`ResetFetchSM: begin |
FetchState <= `GetOpcode; |
end |
endcase |
end |
end |
endmodule |
|
//////////////////////////////////////////////// |
// EOF |
//////////////////////////////////////////////// |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/Alu/AluTestBench.v
0,0 → 1,65
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 22:11:23 09/06/2014 |
// Design Name: ModAlu |
// Module Name: C:/Quantum/ALU/ALU_TB.v |
// Project Name: Quantum |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: ModAlu |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module ALU_TB; |
|
// Inputs |
reg Clock; |
reg Reset; |
reg [0:7] Mnemonic; |
reg [0:7] Data0; |
reg [0:7] Data1; |
|
// Outputs |
wire [0:15] Result; |
|
// Instantiate the Unit Under Test (UUT) |
ModAlu uut ( |
.Clock(Clock), |
.Reset(Reset), |
.Mnemonic(Mnemonic), |
.Data0(Data0), |
.Data1(Data1), |
.Result(Result) |
); |
|
always@(*) begin |
#10; |
Clock = ~Clock; |
end |
|
initial begin |
// Initialize Inputs |
Reset = 0; |
Mnemonic = 0; |
Data0 = 0; |
Data1 = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
|
// Add stimulus here |
|
end |
endmodule |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/Alu/Alu.v
0,0 → 1,57
//////////////////////////////////////////////// |
// @file ALU.v |
// @brief ALU design for Quantum processor |
// @date 9/6/2014 |
//////////////////////////////////////////////// |
|
`include "Alu.vh" |
|
module ModAlu ( |
input Clock, |
input Reset, |
input [0:7] AluInstruction, |
input [0:7] AluInput1, |
input [0:7] AluInput2, |
output reg [0:15] AluResult |
); |
|
always@(posedge Clock, negedge Reset) begin |
if (Reset == 1'b0) begin |
AluResult <= 16'h00; |
end else begin |
case (AluInstruction) |
`Idle: begin |
AluResult <= AluResult; |
end |
`And: begin |
AluResult <= AluInput2 & AluInput1; |
end |
`Or: begin |
AluResult <= AluInput2 | AluInput1; |
end |
`XNOr: begin |
AluResult <= AluInput2 ^~ AluInput1; |
end |
`XOr: begin |
AluResult <= AluInput2 ^ AluInput1; |
end |
`Not: begin |
AluResult <= {AluInput2, AluInput1}; |
end |
`Add: begin |
AluResult <= AluInput2 + AluInput1; |
end |
`Sub: begin |
AluResult <= AluInput2 - AluInput1; |
end |
default: begin |
AluResult <= AluResult; |
end |
endcase |
end |
end |
endmodule |
|
//////////////////////////////////////////////// |
// EOF |
//////////////////////////////////////////////// |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/Alu/Alu.vh
0,0 → 1,19
`ifndef _ALU8X16_VH_ |
`define _ALU8X16_VH_ |
|
/* |
**************************** |
* Alu Instrunctions |
**************************** |
*/ |
|
`define Idle 8'h00 |
`define And 8'h01 |
`define Or 8'h02 |
`define XNOr 8'h03 |
`define XOr 8'h04 |
`define Not 8'h05 |
`define Add 8'h06 |
`define Sub 8'h07 |
|
`endif |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/contador0-999.vhd
0,0 → 1,145
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
entity contador is port( |
clk, rst: in std_logic; |
DECO: out std_logic_vector(6 downto 0); |
AP: out std_logic; |
barrido: out std_logic_vector(2 downto 0)); |
end contador; |
|
architecture cont of contador is |
type states is (state0, state1, state2); |
signal state: states; |
signal cnt1, cnt2: std_logic_vector(31 downto 0); |
signal contU, contD, contC: std_logic_vector(3 downto 0); |
signal temp1, temp2: std_logic; |
signal p1, p2, p3: std_logic; |
signal MUX: std_logic_vector(3 downto 0); |
signal barr: std_logic_vector(2 downto 0); |
begin |
|
divisor1: process(clk,rst) |
begin |
if (rst='1') then |
temp1 <= '0'; |
cnt1 <= conv_std_logic_vector(0,32); |
elsif(clk'event and clk='1') then |
if (cnt1=conv_std_logic_vector(25000000,32)) then |
temp1 <= not temp1; |
cnt1 <= conv_std_logic_vector(0,32); |
else |
cnt1 <= cnt1 + 1; |
end if; |
end if; |
end process; |
|
divisor2: process(clk,rst) |
begin |
if (rst='1') then |
temp2 <= '0'; |
cnt2 <= conv_std_logic_vector(0,32); |
elsif(clk'event and clk='1') then |
if (cnt2=conv_std_logic_vector(125000,32)) then |
temp2 <= not temp2; |
cnt2 <= conv_std_logic_vector(0,32); |
else |
cnt2 <= cnt2 + 1; |
end if; |
end if; |
end process; |
|
contador1: process(temp1,rst) |
begin |
if (rst='1') then |
contU <= conv_std_logic_vector(0,4); |
elsif(temp1'event and temp1='1') then |
if contU < 9 then |
contU <= contU + 1; |
p1 <= '0'; |
elsif contU = 9 then |
contU <= conv_std_logic_vector(0,4); |
p1 <= '1'; |
end if; |
end if; |
end process; |
|
contador2: process(p1,rst) |
begin |
if (rst='1') then |
contD <= conv_std_logic_vector(0,4); |
elsif(p1'event and p1='1') then |
if contD < 9 then |
contD <= contD + 1; |
p2 <= '0'; |
elsif contD = 9 then |
contD <= conv_std_logic_vector(0,4); |
p2 <= '1'; |
end if; |
end if; |
end process; |
|
contador3: process(p2,rst) |
begin |
if (rst='1') then |
contC <= conv_std_logic_vector(0,4); |
elsif(p2'event and p2='1') then |
if contC < 9 then |
contC <= contC + 1; |
p3 <= '0'; |
elsif contC = 9 then |
contC <= conv_std_logic_vector(0,4); |
p3 <= '1'; |
end if; |
end if; |
end process; |
|
BD: process(temp2,rst) |
begin |
if (rst='1') then |
barrido <= conv_std_logic_vector(0,3); |
barr <= conv_std_logic_vector(0,3); |
state <= state0; |
elsif(temp2'event and temp2='1') then |
case state is |
when state0 => |
barrido <= "110"; |
barr <= "110"; |
state <= state1; |
when state1 => |
barrido <= "101"; |
barr <= "101"; |
state <= state2; |
when state2 => |
barrido <= "011"; |
barr <= "011"; |
state <= state0; |
end case; |
end if; |
end process; |
|
--MUX |
|
MUX <= contU when barr = "110" else |
contD when barr = "101" else |
contC when barr = "011"; |
|
--DECO |
|
DECO <= "1000000" when mux = "0000" else |
"1111001" when mux = "0001" else |
"0100100" when mux = "0010" else |
"0110000" when mux = "0011" else |
"0011001" when mux = "0100" else |
"0010010" when mux = "0101" else |
"0000010" when mux = "0110" else |
"1111000" when mux = "0111" else |
"0000000" when mux = "1000" else |
"0011000" when mux = "1001" else |
"0000110"; |
|
--AP |
AP <= '1'; |
end cont; |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/Quantum.bmm
--- trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/contador.ucf (nonexistent)
+++ trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/contador.ucf (revision 3)
@@ -0,0 +1,13 @@
+NET clk LOC=B8;
+NET rst LOC=G18;
+NET barrido<0> LOC=F17;
+NET barrido<1> LOC=H17;
+NET barrido<2> LOC=C18;
+NET AP LOC = F15;
+NET DECO<0> LOC=L18;
+NET DECO<1> LOC=F18;
+NET DECO<2> LOC=D17;
+NET DECO<3> LOC=D16;
+NET DECO<4> LOC=G14;
+NET DECO<5> LOC=J17;
+NET DECO<6> LOC=H14;
\ No newline at end of file
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/ProgramCounter/ProgramCounter.v
0,0 → 1,32
module ProgramCounter( |
input Clock, |
input Reset, |
input IncrementPC, |
input WritePC, |
input [0:7] NewPC, |
output [0:7] ProgramCounter |
); |
|
reg [0:7] TemporalPC; |
|
always@(posedge Clock, negedge Reset) begin |
if (Reset == 1'b0) begin |
TemporalPC <= 8'h00; |
end else begin |
case (WritePC) |
1'b0: begin |
if (TemporalPC < 8'hFF) begin |
TemporalPC <= TemporalPC + IncrementPC; |
end else begin |
TemporalPC <= 8'h00; |
end |
end |
1'b1: begin |
TemporalPC <= NewPC; |
end |
endcase |
end |
end |
|
assign ProgramCounter = TemporalPC; |
endmodule |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/Memory/RomMemory.vhd
0,0 → 1,312
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
entity ROM is port( |
Clock: in std_logic; |
Reset: in std_logic; |
WriteEnable: in std_logic; |
DataOut: out std_logic_vector(7 downto 0); |
DataIn: in std_logic_vector(7 downto 0); |
Address: in std_logic_vector(7 downto 0) |
); |
end ROM; |
|
architecture ArchRom of ROM is |
--**************************** |
--* Define Opcodes |
--**************************** |
|
constant nop: std_logic_vector(7 downto 0) := x"00"; |
constant ldr: std_logic_vector(7 downto 0) := x"01"; |
constant ldm: std_logic_vector(7 downto 0) := x"02"; |
constant addrr: std_logic_vector(7 downto 0) := x"03"; |
constant addrm: std_logic_vector(7 downto 0) := x"04"; |
constant addmr: std_logic_vector(7 downto 0) := x"05"; |
constant addmm: std_logic_vector(7 downto 0) := x"06"; |
constant breqrr: std_logic_vector(7 downto 0) := x"07"; |
constant breqrm: std_logic_vector(7 downto 0) := x"08"; |
constant breqmm: std_logic_vector(7 downto 0) := x"09"; |
constant jmpr: std_logic_vector(7 downto 0) := x"0A"; |
constant jmpm: std_logic_vector(7 downto 0) := x"0B"; |
|
--**************************** |
--* Define Registers |
--**************************** |
|
constant rega: std_logic_vector(7 downto 0) := x"00"; |
constant regb: std_logic_vector(7 downto 0) := x"01"; |
constant regc: std_logic_vector(7 downto 0) := x"02"; |
constant regx: std_logic_vector(7 downto 0) := x"03"; |
constant regy: std_logic_vector(7 downto 0) := x"04"; |
constant regz: std_logic_vector(7 downto 0) := x"05"; |
|
--**************************** |
--* Define Asm Labels |
--**************************** |
|
constant LoopLabel: std_logic_vector(7 downto 0) := x"12"; |
|
type ROMA is array(0 to 255) of std_logic_vector(7 downto 0); |
signal ROM1: ROMA:=( |
--################################## |
--## PROGRAM 1 |
--################################## |
|
ldr, rega, x"00", |
ldr, regb, x"00", |
ldr, regc, x"00", |
ldr, regx, x"01", |
ldr, regy, x"ff", |
ldr, regz, LoopLabel, |
|
--LoopLabel: |
addrr, rega, regx, |
breqrr, rega, regy, LoopLabel, |
ldr, rega, x"00", |
addrr, regb, regx, |
breqrr, regb, regy, LoopLabel, |
ldr, regb, x"00", |
addrr, regc, regx, |
jmpr, regz, |
|
|
--adda, x"01", |
--brnea, x"FF", x"00", |
--lda, x"00", |
--addb, x"01", |
--brneb, x"FF", x"00", |
--addc, x"01", |
--ldgpc, |
--ldb, x"00", |
--jmp, x"00", |
|
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00"), |
(x"00") |
); |
attribute ramstyle : string; |
--attribute ramstyle of ROM1 : signal is "M512"; |
begin |
process(Clock, Reset) begin |
if (Reset = '0') then |
DataOut <= x"00"; |
elsif rising_edge(Clock) then |
if (WriteEnable = '1') then |
ROM1 (conv_integer(Address)) <= DataIn; |
else |
DataOut <= ROM1(conv_integer(Address)); |
end if; |
end if; |
end process; |
end ArchRom; |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/Pinout/Nexys2_1200K.ucf
0,0 → 1,24
######################################### |
## NEXYS 2 - 1200K DIGILENT PLATFORM |
######################################### |
|
NET Clock LOC = B8; |
NET Reset LOC = G18; |
|
NET Gpio1<0> LOC = J14; |
NET Gpio1<1> LOC = J15; |
NET Gpio1<2> LOC = K15; |
NET Gpio1<3> LOC = K14; |
NET Gpio1<4> LOC = E16; |
NET Gpio1<5> LOC = P16; |
NET Gpio1<6> LOC = E4; |
NET Gpio1<7> LOC = P4; |
|
#NET Switch<0> LOC = G18; |
#NET Switch<1> LOC = H18; |
#NET Switch<2> LOC = K18; |
#NET Switch<3> LOC = K17; |
#NET Switch<4> LOC = L14; |
#NET Switch<5> LOC = L13; |
#NET Switch<6> LOC = N17; |
#NET Switch<7> LOC = R17; |
/trunk/ENG06_HDLConstruction/01_OldArchitecture_ReferenceOnly/Quantum.v
0,0 → 1,69
module Quantum ( |
input Clock, |
input Reset, |
output [7:0] Gpio1 |
); |
|
wire WriteEnable; |
wire WritePC; |
wire IncrementPC; |
wire [0:7] BusDataIn; |
wire [0:7] BusDataOut; |
wire [0:7] AluResult; |
wire [0:7] ProgramCounter; |
wire [0:1] AluRegMux1; |
wire [0:1] AluRegMux2; |
wire [0:7] AluInstruction; |
wire [0:7] REGA; |
wire [0:7] REGB; |
wire [0:7] REGC; |
wire [0:7] REGX; |
wire [0:7] REGY; |
wire [0:7] REGZ; |
wire [0:7] AluInput1; |
wire [0:7] AluInput2; |
wire [0:7] NewPC; |
|
ControlUnit ControlUnit ( |
.Clock (Clock), |
.Reset (Reset), |
.BusDataIn (BusDataIn), |
.AluResult (AluResult), |
.BusDataOut (BusDataOut), |
.IncrementPC (IncrementPC), |
.WritePC (WritePC), |
.NewPC (NewPC), |
.AluInput1 (AluInput1), |
.AluInput2 (AluInput2), |
.AluInstruction (AluInstruction), |
.REGC (Gpio1), |
.WriteEnable (WriteEnable) |
); |
|
ProgramCounter PCUnit ( |
.Clock (Clock), |
.Reset (Reset), |
.IncrementPC (IncrementPC), |
.WritePC (WritePC), |
.NewPC (NewPC), |
.ProgramCounter (ProgramCounter) |
); |
|
ModAlu AluUnit ( |
.Clock (Clock), |
.Reset (Reset), |
.AluInstruction (AluInstruction), |
.AluInput1 (AluInput1), |
.AluInput2 (AluInput2), |
.AluResult (AluResult) |
); |
|
ROM RomUnit ( |
.Clock (Clock), |
.Reset (Reset), |
.WriteEnable (WriteEnable), |
.DataOut (BusDataIn), |
.DataIn (BusDataOut), |
.Address (ProgramCounter) |
); |
endmodule |
/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/DIV_tb.m
0,0 → 1,18
function DIV_tb() |
div_alu = 0; |
div_real = 0; |
|
for y = 1:65535 |
for x = 1:65535 |
div_alu = DIV(x,y); |
div_real = fix(x/y); |
|
if (div_alu ~= div_real) |
disp(strcat('not ok! div_alu = ',num2str(div_alu),'; div_real = ',num2str(div_real))); |
return; |
else |
disp(strcat('opcode ok! div_alu = ',num2str(div_alu),'; div_real = ',num2str(div_real))); |
end |
end |
end |
end |
/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/MUL.m
0,0 → 1,7
function X = MUL(D1,D2) |
X = 0; |
|
for loop = 0:(D2 - 1) |
X = X + D1; |
end |
end |
/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/MOD.m
0,0 → 1,17
function [R,zero] = MOD(N,D) |
R = 0; |
X = 0; |
zero = 0; |
|
if (D == 0) |
zero = 1; |
return; |
end |
|
while N >= D |
N = N - D; |
X = X + 1; |
end |
|
R = N; |
end |
/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/01_MatlabAlgorithmDesign/DIV.m
0,0 → 1,37
|
function [answer,zero] = DIV(dividend,divisor) |
denom = divisor; |
current = 1; |
answer = 0; |
zero = 0; |
|
if (divisor == 0) |
zero = 1; |
return; |
end |
|
% METHOD 1 |
%while (dividend >= divisor) |
% dividend = dividend - divisor; |
% answer = answer + 1; |
%end |
% |
|
while (denom <= dividend) |
denom = fix(bitsll(denom, 1)); |
current = fix(bitsll(current, 1)); |
end |
|
denom = fix(bitsra(denom, 1)); |
current = fix(bitsra(current, 1)); |
|
while (current~=0) |
if (dividend >= denom) |
dividend = int16(dividend - denom); |
answer = bitor(answer, current); |
end |
|
current = fix(bitsra(current, 1)); |
denom = fix(bitsra(denom, 1)); |
end |
end |
/trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/~$divide.docx
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/~$divide.docx
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Quark.docx
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Quark.docx
===================================================================
--- trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Quark.docx (nonexistent)
+++ trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Quark.docx (revision 3)
trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Quark.docx
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Divide.docx
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Divide.docx
===================================================================
--- trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Divide.docx (nonexistent)
+++ trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Divide.docx (revision 3)
trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/SysReq_Divide.docx
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/02_VerilogAlgorithmDesign/alu_8bit.v
===================================================================
--- trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/02_VerilogAlgorithmDesign/alu_8bit.v (nonexistent)
+++ trunk/ENG04_RequirementsAnalysis/03_InternalRequirements/02_VerilogAlgorithmDesign/alu_8bit.v (revision 3)
@@ -0,0 +1,197 @@
+`timescale 1ns / 1ps
+
+module ALU_8bit(
+ clk,
+ rst,
+ en,
+ ready,
+ opcode,
+ reg_in_1,
+ reg_in_2,
+ reg_out,
+ reg_bank
+ );
+
+ input wire clk;
+ input wire rst;
+ input wire en;
+ input wire [7:0] opcode;
+ input wire [7:0] reg_in_1;
+ input wire [7:0] reg_in_2;
+
+ output reg ready;
+ output reg [7:0] reg_out;
+
+ /* ALU flags steps registers
+ N
+ Set when the result of the operation was Negative.
+ Z
+ Set when the result of the operation was Zero.
+ C
+ Set when the operation resulted in a Carry.
+ V
+ Set when the operation caused oVerflow.
+
+ A carry occurs if the result of an add, subtract, or compare is greater than or equal to 232, or as the result of an inline barrel shifter operation in a move or logical instruction.
+ Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 231, or less than -231.
+ */
+ `define N 0:0
+ `define Z 1:1
+ `define C 2:2
+ `define V 3:3
+ output reg [3:0] reg_bank;
+
+ reg [15:0] reg_out_temp;
+
+ /* ROL and ROR steps and registers */
+ `define R_FIRST_STEP 1'b0
+ `define R_SECOND_STEP 1'b1
+ reg rotation_step;
+
+ /* math steps and registers */
+ `define M_FIRST_STEP 2'b00
+ `define M_SECOND_STEP 2'b01
+ `define M_THIRD_STEP 2'b10
+ reg [1:0] math_step;
+ reg [7:0] dividend;
+ reg [7:0] denom;
+ reg [7:0] current;
+ reg [7:0] temp_result;
+
+ always@(posedge clk) begin
+ if (rst == 1'b1) begin
+ reg_out_temp <= 16'b0000;
+ reg_out <= 8'h00;
+ ready <= 1'b0;
+ rotation_step <= `R_FIRST_STEP;
+ reg_bank <= 4'b0000;
+ math_step <= `M_FIRST_STEP;
+ current <= 8'h01;
+ temp_result <= 8'h00;
+ dividend <= 8'h00;
+ denom <= 8'h00;
+ end else if (en == 1'b1) begin
+ ready <= 1'b0;
+
+ case(opcode)
+ 8'h00:begin /* SUM(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 + reg_in_2]*/
+ reg_out <= reg_in_1 + reg_in_2;
+ ready <= 1'b1;
+ end
+
+ 8'h01:begin /* SUB(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 - reg_in_2]*/
+ reg_out <= reg_in_1 - reg_in_2;
+
+ if (reg_in_2 > reg_in_1) begin
+ ready <= 1'b1;
+ end
+
+ if (reg_in_2 == reg_in_1) begin
+ ready <= 1'b1;
+ end
+
+ ready <= 1'b1;
+ end
+
+ 8'h02:begin /* MUL(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 * reg_in_2]*/
+
+ end
+
+ 8'h03:begin /* DIV(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 / reg_in_2]*/
+ case(math_step)
+ `M_FIRST_STEP:begin
+ dividend <= reg_in_1;
+ denom <= reg_in_2;
+ math_step <= `M_SECOND_STEP;
+ end
+
+ `M_SECOND_STEP:begin /* shift left to find first bit with value 1 */
+ if (denom <= dividend) begin
+ denom <= denom << 1;
+ current <= current << 1;
+ end else begin
+ denom <= denom >> 1; /* shift right reg_in_2 to align it with reg_in_1 */
+ current <= current >> 1;
+ math_step <= `M_THIRD_STEP;
+ end
+ end
+
+ `M_THIRD_STEP:begin
+ if (current != 0) begin
+ if (dividend >= denom) begin
+ dividend <= dividend - denom;
+ temp_result <= temp_result | current;
+ end
+
+ denom <= denom >> 1;
+ current <= current >> 1;
+ end else begin
+ reg_out <= temp_result;
+ current <= 8'h01;
+ temp_result <= 8'h00;
+ math_step <= `M_FIRST_STEP;
+ ready <= 1'b1;
+ end
+ end
+ endcase
+ end
+
+ 8'h04:begin /* MOD(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 % reg_in_2]*/
+
+ end
+
+ 8'h05:begin /* AND(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 & reg_in_2]*/
+ reg_out <= reg_in_1 & reg_in_2;
+ ready <= 1'b1;
+ end
+
+ 8'h06:begin /* OR(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 | reg_in_2]*/
+ reg_out <= reg_in_1 | reg_in_2;
+ ready <= 1'b1;
+ end
+
+ 8'h07:begin /* NOT(reg_out) reg_in_1 [reg_out = ~reg_in_1]*/
+ reg_out <= ~reg_in_1;
+ ready <= 1'b1;
+ end
+
+ 8'h08:begin /* XOR(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 ^ reg_in_2]*/
+ reg_out <= reg_in_1 ^ reg_in_2;
+ ready <= 1'b1;
+ end
+
+ 8'h09:begin /* SHL(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 << reg_in_2]*/
+ reg_out <= reg_in_1 << reg_in_2;
+ ready <= 1'b1;
+ end
+
+ 8'h0A:begin /* SHR(reg_out) reg_in_1,reg_in_2 [reg_out = reg_in_1 >> reg_in_2]*/
+ reg_out <= reg_in_1 >> reg_in_2;
+ ready <= 1'b1;ready <= 1'b1;
+ end
+
+ 8'h0B:begin /* ROL(reg_out) reg_in_1,reg_in_2 [reg_out = ??]*/
+ if (rotation_step == `R_FIRST_STEP) begin
+ reg_out_temp <= reg_in_1 << (reg_in_2 & 8'h07);
+ rotation_step <= `R_SECOND_STEP;
+ end else begin
+ reg_out <= reg_out_temp[15:8] | reg_out_temp[7:0];
+ ready <= 1'b1;
+ rotation_step <= `R_FIRST_STEP;
+ end
+ end
+
+ 8'h0C:begin /* ROR(reg_out) reg_in_1,reg_in_2 [reg_out = ??]*/
+ if (rotation_step == `R_FIRST_STEP) begin
+ reg_out_temp <= {reg_in_1[7:0],8'b00} >> (reg_in_2 & 8'h07);
+ rotation_step <= `R_SECOND_STEP;
+ end else begin
+ reg_out <= reg_out_temp[15:8] | reg_out_temp[7:0];
+ ready <= 1'b1;
+ rotation_step <= `R_FIRST_STEP;
+ end
+ end
+ endcase
+ end
+ end
+endmodule
Index: trunk/ENG04_RequirementsAnalysis/02_ExternalRequirements/wbspec_b4.pdf
===================================================================
--- trunk/ENG04_RequirementsAnalysis/02_ExternalRequirements/wbspec_b4.pdf (nonexistent)
+++ trunk/ENG04_RequirementsAnalysis/02_ExternalRequirements/wbspec_b4.pdf (revision 3)
@@ -0,0 +1,14797 @@
+%PDF-1.4
+%äüöß
+2 0 obj
+<>
+stream
+xœŒ½ËŽt=’¸§ˆu
+ÞI ð]ªî´ëA³´š‘Ô‹
+ £Í¼þdÐÝÜÍÉÌ’Ð@uò7;<¼8ýÆó½¾Òóÿ{ü¿Ï×óõ•Ÿmµ¯öœ5}Íçÿü/Ïÿëžÿýñ¯Ïϯ%Mý½?kß(ü¾‘eåôýÿûóÿü?Žÿð?ÿÛ£õ¯ñ¬e|·ÞVæ7¹´þöD«}~·DPÿöøó?èÃëšþÆÏúó_m}Xê|þõÿyþ»IÏÒŸý¯ÿéO¯ôʯòª¤?½Ú«ÿñùO¯ñiÌ×zýÓëÏüç¿þÇÇ?ÿõñ¯BûýF÷ýÊ©})a~¦©„üã7<8Êþ³þñÍÙ>m¥ÿpï¿ä÷úüôçÏÿüûý_ÿòúçýßÿ%½¾‘)}ÿ‘?ÿ!•o™T?2©ýñåOß,åO©ÿ&‘ÿ–íJãó_?øÆ+mšñå’ß=Ÿßÿ’>D"¦üúûß{ùò=ôõxùôOMò>£TýMøçϘû?ü%ý{y²4÷ ¥¿üþNïå?þã¿|ÿO~}3~¿ðyá¿|^KÁYßvØ#þSZZú^Px«*SÚÒL¯ïŽ~3æ´yË/´öTH·^»9z»K;Ö¾gY^é—‡§U¿—ÒOïûÚ÷è¤Ï£Ò~ÉWšñ]>{¢ŒñUž#ÏïIýõMØ>;Ó7Æç?ŽýÔöÙ7.?žÿ÷ûñïþû>ÿò?žÿú¿Ø`Ÿ_÷¦y}/4Ö÷ÖÜ„ô¤ýõIÕÅ›>¨ýï=(íÿû¢2Ú7CÍÏÛüîö,ßÿá[ò¿þÃãóæ¿ý¼‰Fº¦ôý[¯ãû‰ïOëÙÛgþöÔ_¾[u·ê÷À}äæn{ýðþíñigïù›ão[äïVú–Ö7®½¾%¤Uvkêæ–L–×gìúžïß^Ÿ¡éu‰äw+S«í罶¬¯òõéõg±~Xæ§UûÖ›üvUY_ùÃÚ_Ÿw}õÝÏ—H~ã¾9[–w}ô-·ä·¬OVâߤ—ß%ySýï’v«ù»4¼söѱP2VQúT0veIüäÝÊARçÆZÕûŽñO„Ï[ÝïUlö¥%+£í¿“ÿs+Üc³íUÐ|Mô÷yÿ–3–¢}B½{É“?«ïÓÚJ{¦—JʼËúü¼SoUK{E6}úgVúVÒú^ƒÖÎ÷FmʱÑgK«é³Ñ*ÄXm½çž©½Sª²Øjü¬Íïm+»òÛ6PÆú1 ö®ü’})=~íµ‰}™ô½Œp&°tuÈRTή{*»þ"R¨¿·R˜[EdUm·êA¤Pþ@÷\v]¥¢kúM£Pþ@Û^ÂS—RÝ~Ð(¢¶çLWô”×$ ª° +iûV&Ý{ÅWIw-éD6-?T5ô—)ǽŒtN™JÀ$þ†žýÖ¥Ðc·ÆEe`ˆÛ“ œv«_Tüd÷ÍU‡Ïµo"…Bø½ÕöÚÂC~Ùv)ÔÅ?à¹w\S—±"…Bø6á¹Ñ"‘=ul¶©§KÚ/ š¶‡ ËÚJô¶&¾»¼©püðÁÄDè² ÿ}¨ÿýwé˜~ž$¿ §ñв¿
+(¢K¶ø;ûT7º×é8TÇEe`ˆ3¸p»¨°Ì邞ЃÝr§Á®–Ð.ùF/ÁZpÛng0Þµþ`\¬Ü¸ðMÅZ‚Àҵƕ
+’CÅ@œÁƒì¨~Ð l‚Íƒæ ’Zû;6Ý/=u ,¦À SLLÀ›ÆLt²õ¨6]9ˆ
+a†¦ ÍÑN
+–¡X,~ÂÅY.&ê<ˆè€ rؽ§¥Ë&/ýÙäæÛ E3OÝ0‡¡‰Ï=l˜ž\ømÛ§û¹…ßv·‚7@g¶a\Ôßk¨]k+1¢65jn¯Ô=O#á‰é0*ó•ÑÛÐÁÒ`3+!þ†‡[§y™|a¦2sâÒa±#`ûf²*˜Ê:
+q1B>+:ú.ð-˜ÊìDˆ;øtuÒEÀ͇ñ<=£fF¦Sâþ°šéo§1 ˆšÉÕÜ{OOõÀMðsÜZÛ?ÛÛµçé®õ¯ †øQòçzh9•!ÎàÀå¢:À™Àî-ö«Õ¢oq·m…bqˆõ:~Ÿ_ˆ»],&žø_ý¢ VqQ[fîiÊ2 sÙ»H·|~ñÌyG”–[nÚÚ'ÜßÿöÝóíZôÝïßúþM$»zE9óÞx2@]þuÞ–×C&¿<Ž_Ûß˲ærQçÒ÷¶ €Y|#}´x?õ¢Q „?Àí´ÀqÊM]¬y)ÔÅß¡óg#•ÎúÒèÜRpÝ`¼ß!]oâý±ê%qéöÚìM‡¾Ð2•uâ>XÓÞ2íÖM†kêJ÷—8;©\^ª7¸¼öù\ejŠ¨*à’ôPZÚ’3dÇ°JRkbÏRÉj3 UC‹%‹J
+KQÉ©¿uz^Ñ~&mI?÷Ä–Š>?ð÷ ÿ¾Ñ^Q)ª«¶ïîSvÝ^H÷•¬:gjKä0:ÆʳÈYym9U¾å¥jZ–Ém/‘¹¼\¿ï(½éþ‹¶boôñ
+¨1hìáe;z†Ö¢Vƾx@G,½ZZÈÔÒ„KçJP]W†´°Nöägö÷ßEW‚ìO¬ ù-é
+Z{/_Øñûkfë•<=9$¦¿4×Oe¸[Fдƒ³
+ÖªÊÇÚ|‘Û£ÏÊö›øŠú˜õݤÿXG]½;
+waL$,ƒÝ¸žÅy`”±^Š†«uk:Ó,b½È9ø¢3€V’ýýRv…ü†õ=¼¡¨é:Á¢<ÕÇt&¤p&è˜è© ½*§Bq]Š³9pú»°íÌ<8ø§Ï‡>;ÛYÕðìݲˆ¤žiº«E7ßÉÃßÍÆš¢aÌ~Ñ`Ú(ØçÉGÏNhoušáÂ@µ 9*gu%Ó°½Þ;IVt1…Õt_é8”®£Rµ%ã'o$ñ D{Ú]V:ïú[‹ZÍv[&CmY½b}à|0Ë¡ôý–Ãú×v«ëžª¤ö©Ò&Ÿ8°t<¦‡hÕb*‰1®°,Ô6[f©±æ‚K%ãIÛAë¢5I/&Nƒ¨«Yp]Mд/ÕЋÎݧ²&qNˆu&gÈÞ™li%õpbuÏ祑ÄE'V¶U/> ŸKX1zŽÚûe´vöÚo,™U–
+Ù[zîg=©f8çÙ ÎùžÕ”oên;%ã42+¥²/%sß¡gê>›«Î0l$h^²ádφS;@ì”,ü–”eÑHz«»pÁ&³9†)¿@Ûv·ÏDÿuX§‹<ð¡þ8,ðJ®ÙPëL5¶Ï’Z¾°‰ž®k)«õ܃݃
+>h]wÞ¹ë~–ᶀž Ó΃BžœÈ8_D[DϬ©~FJ4 lr‘Ä>‘*ì½ùT¯fïÒBšJvp7-/ÖÖ{-a©¦/ºýZæk™õÕÙj
++Ò´)Õ6è9ÑlS¨Kõ~‘ª¶-Ì“=î;¼áõd¿¹Ã2µ‰$sÔ¹dú;)GÖ=RŸ–kPÏ¿°¶±g¿”ŸOãŠÕ£¿a½{6ãˆ+)K•@Y1îÀúºRd‰Äßâ–5 3:sÐ(PD7HÇlºNø0~ÓPõ0Œë 2(„:è