URL
https://opencores.org/ocsvn/ram_wb/ram_wb/trunk
Subversion Repositories ram_wb
Compare Revisions
- This comparison shows the changes necessary to convert path
/ram_wb/trunk
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/rtl/verilog/ram_wb_sc_sw.v
0,0 → 1,22
module ram (dat_i, dat_o, adr_i, we_i, clk ); |
|
parameter dat_width = 32; |
parameter adr_width = 11; |
parameter mem_size = 2048; |
|
input [dat_width-1:0] dat_i; |
input [adr_width-1:0] adr_i; |
input we_i; |
output reg [dat_width-1:0] dat_o; |
input clk; |
|
reg [dat_width-1:0] ram [0:mem_size - 1] /* synthesis ram_style = no_rw_check */; |
|
always @ (posedge clk) |
begin |
dat_o <= ram[adr_i]; |
if (we_i) |
ram[adr_i] <= dat_i; |
end |
|
endmodule // ram |
rtl/verilog/ram_wb_sc_sw.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ram_wb.v
===================================================================
--- rtl/verilog/ram_wb.v (revision 7)
+++ rtl/verilog/ram_wb.v (revision 8)
@@ -31,9 +31,9 @@
ram
#
(
- .DATA_WIDTH(dat_width),
- .ADDR_WIDTH(adr_width),
- .MEM_SIZE(mem_size)
+ .dat_width(dat_width),
+ .adr_width(adr_width),
+ .mem_size(mem_size)
)
ram0
(