OpenCores
URL https://opencores.org/ocsvn/raptor64/raptor64/trunk

Subversion Repositories raptor64

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /raptor64/trunk/rtl
    from Rev 50 to Rev 52
    ↔ Reverse comparison
  •

Rev 50 → Rev 52

/verilog/WB64ToMIG32.v
0,0 → 1,381
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2011-2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
//
// WB2MIG32.v
// - 64 bit WISHBONE to 32 bit MIG bus bridge
// - supports
// constant address burst cycles
// incrementing address burst cycles
// classic bus cycles
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
//`define SUPPORT_INCADR 1
`define MAX_MEM 32'h07FF_FFFF
//
module WB64ToMIG32 (
input rst_i,
input clk_i,
 
// WISHBONE PORT
input [1:0] bte_i, // burst type extension
input [2:0] cti_i, // cycle type indicator
input cyc_i, // cycle in progress
input stb_i, // data strobe
output ack_o, // acknowledge
input we_i, // write cycle
input [7:0] sel_i, // byte lane selects
input [63:0] adr_i, // address
input [63:0] dat_i, // data
output reg [63:0] dat_o,
input [4:0] bl_i, // burst length
 
// MIG port
input calib_done,
input cmd_full,
output reg cmd_en,
output reg [2:0] cmd_instr,
output reg [5:0] cmd_bl,
output reg [29:0] cmd_byte_addr,
 
output reg rd_en,
input [31:0] rd_data,
input rd_empty,
 
output reg wr_en,
output reg [3:0] wr_mask,
output reg [31:0] wr_data,
input wr_empty,
input wr_full
);
parameter IDLE = 4'd1;
parameter BWRITE_001a = 4'd2;
parameter BWRITE_001b = 4'd3;
parameter BWRITE_010a = 4'd4;
parameter BWRITE_010b = 4'd5;
parameter BWRITE_010c = 4'd6;
parameter BWRITE_010d = 4'd7;
parameter BWRITE_CMD = 4'd8;
parameter BREAD_001a = 4'd9;
parameter BREAD_001b = 4'd10;
parameter BREAD_010a = 4'd11;
parameter BREAD_010b = 4'd12;
parameter BREAD_010c = 4'd13;
parameter BREAD_010d = 4'd14;
parameter NACK = 4'd15;
 
 
// Fill write FIFO then issue write command
reg [5:0] ctr; // burst length counter
reg [63:0] dato;
reg [3:0] state;
reg ack1;
 
wire cs = cyc_i && stb_i && (adr_i[59:32]==28'h0000001 || adr_i[63:36]==28'hE000000); // circuit select
assign ack_o = ack1 & cs; // Force ack_o low as soon as cyc_i or stb_i go low
 
always @(cs or adr_i or dato)
if (cs) begin
// The following test allows the startup code to determine how much memory is presnet.
// Otherwise, the code thinks there's more memory than there actually is, due to aliased
// addresses hit during the memory test.
if (adr_i[31:0]>`MAX_MEM)
dat_o <= 64'hDEADDEAD_DEADDEAD;
else
dat_o <= dato;
end
else
dat_o <= 64'h00000000_00000000; // Allow wire-or'ing data bus
 
reg [5:0] bl;
reg [63:0] prev_adr;
 
always @(posedge clk_i)
if (rst_i) begin
ack1 <= 1'b0;
ctr <= 6'd0;
state <= IDLE;
end
else begin
cmd_en <= 1'b0; // Forces cmd_en to be just a 1-cycle pulse
wr_en <= 1'b0;
case(state)
IDLE:
if (cs & calib_done) begin
ctr <= 6'd0;
cmd_byte_addr <= {adr_i[29:2],2'b00};
if (cti_i==3'b001)
cmd_bl <= {bl_i,1'b1};
else begin
if (sel_i[3:0]==4'h0 || sel_i[7:4]==4'h0)
cmd_bl <= 6'd0; // single access required
else
cmd_bl <= 6'd1; // double access required
end
cmd_instr <= we_i ? 3'b000 : 3'b001; // WRITE or READ
prev_adr <= adr_i;
 
// Write cycles
if (we_i) begin
case(cti_i)
3'b000,3'b111:
// Writing for a half-word or less ?
if (sel_i[3:0]==4'h0 || sel_i[7:4]==4'h0) begin
if (!wr_full) begin
ack1 <= 1'b1;
wr_en <= 1'b1;
// data will be reflected for sub-word writes
// the same data is on [31:0] as is on [63:32]
wr_data <= dat_i[31:0];
wr_mask <= ~(sel_i[7:4]|sel_i[3:0]);
state <= BWRITE_CMD;
end
end
// Writing 2 32 bit words
else begin
if (wr_empty)
state <= BWRITE_001a;
end
// Since we want to write a burst of numerous data, we wait until the
// write FIFO is empty. We could wait until the FIFO count is greater
// than the burst length.
3'b001:
if (wr_empty)
state <= BWRITE_001a;
`ifdef SUPPORT_INCADR
3'b010:
if (wr_empty)
state <= BWRITE_010a;
`endif
default: ;
endcase
end
// Read cycles
else begin
if (!cmd_full) begin
cmd_en <= 1'b1;
case(cti_i)
3'b000: state <= BREAD_001a;
3'b001: state <= BREAD_001a;
`ifdef SUPPORT_INCADR
3'b010: state <= BREAD_010a;
`endif
3'b111: state <= BREAD_001a;
default: ;
endcase
end
end
end
 
//---------------------------------------------------------
// Burst write
//---------------------------------------------------------
 
// Constant address burst:
BWRITE_001a:
begin
ack1 <= 1'b0;
if (stb_i) begin
wr_en <= 1'b1;
wr_data <= dat_i[31:0];
wr_mask <= ~sel_i[3:0];
ctr <= ctr + 6'd1;
state <= BWRITE_001b;
end
end
BWRITE_001b:
if (stb_i) begin
ack1 <= 1'b1;
wr_en <= 1'b1;
wr_data <= dat_i[63:32];
wr_mask <= ~sel_i[7:4];
ctr <= ctr + 6'd1;
if (ctr >= bl_i || cti_i==3'b000 || cti_i==3'b111 || !cyc_i)
state <= BWRITE_CMD;
else
state <= BWRITE_001a;
end
else
ack1 <= 1'b0;
 
`ifdef SUPPORT_INCADR
// Incrementing address burst:
// Write the first word
// Write subsequent words, checking for an address change
BWRITE_010a:
begin
ack1 <= 1'b0;
if (stb_i) begin
wr_en <= 1'b1;
wr_data <= dat_i[31:0];
wr_mask <= ~sel_i[3:0];
ctr <= ctr + 6'd1;
state <= BWRITE_010b;
end
end
BWRITE_010b:
if (stb_i) begin
ack1 <= 1'b1;
wr_en <= 1'b1;
wr_data <= dat_i[63:32];
wr_mask <= ~sel_i[7:4];
ctr <= ctr + 6'd1;
if (ctr >= bl_i || cti_i==3'b000 || cti_i==3'b111 || !cyc_i)
state <= BWRITE_CMD;
else
state <= BWRITE_010c;
end
else
ack1 <= 1'b0;
BWRITE_010c:
begin
ack1 <= 1'b0;
if (stb_i) begin
if (adr_i!=prev_adr) begin
prev_adr <= adr_i;
wr_en <= 1'b1;
wr_data <= dat_i[31:0];
wr_mask <= ~sel_i[3:0];
ctr <= ctr + 6'd1;
state <= BWRITE_010d;
end
end
end
BWRITE_010d:
if (stb_i) begin
ack1 <= 1'b1;
wr_en <= 1'b1;
wr_data <= dat_i[63:32];
wr_mask <= ~sel_i[7:4];
ctr <= ctr + 6'd1;
if (ctr >= bl_i || cti_i==3'b000 || cti_i==3'b111 || !cyc_i)
state <= BWRITE_CMD;
else
state <= BWRITE_010c;
end
else
ack1 <= 1'b0;
`endif
 
BWRITE_CMD:
begin
if (cyc_i==1'b0)
ack1 <= 1'b0;
if (!cmd_full) begin
cmd_en <= 1'b1;
state <= NACK;
end
end
 
//---------------------------------------------------------
// Burst read or single read
//---------------------------------------------------------
BREAD_001a:
begin
rd_en <= 1'b1;
ack1 <= 1'b0;
if (rd_en & !rd_empty) begin
dato <= {rd_data,rd_data};
ctr <= ctr + 6'd1;
if (sel_i[7:4]!=4'h0 && sel_i[3:0]!=4'h0 && cyc_i)
state <= BREAD_001b;
else begin
ack1 <= 1'b1;
state <= NACK;
end
end
end
BREAD_001b:
if (rd_en & !rd_empty) begin
dato[63:32] <= rd_data;
ack1 <= 1'b1;
ctr <= ctr + 6'd1;
if (ctr>={bl_i,1'b1} || !cyc_i || cti_i==3'b000 || cti_i==3'b111)
state <= NACK;
else
state <= BREAD_001a;
end
 
`ifdef SUPPORT_INCADR
BREAD_010a:
begin
rd_en <= 1'b1;
ack1 <= 1'b0;
if (rd_en & !rd_empty) begin
prev_adr <= adr_i;
dato <= {rd_data,rd_data};
ctr <= ctr + 6'd1;
state <= BREAD_010b;
end
end
BREAD_010b:
if (rd_en & !rd_empty) begin
rd_en <= 1'b0;
dato[63:32] <= rd_data;
ack1 <= 1'b1;
ctr <= ctr + 6'd1;
if (ctr>={bl_i,1'b1} || !cyc_i || cti_i==3'b000 || cti_i==3'b111)
state <= NACK;
else
state <= BREAD_010c;
end
BREAD_010c:
begin
ack1 <= 1'b0;
if (adr_i != prev_adr) begin
rd_en <= 1'b1;
if (rd_en & !rd_empty) begin
prev_adr <= adr_i;
dato <= {rd_data,rd_data};
ctr <= ctr + 6'd1;
state <= BREAD_010d;
end
end
end
BREAD_010d:
if (rd_en & !rd_empty) begin
rd_en <= 1'b0;
ack1 <= 1'b1;
dato[63:32] <= rd_data;
ctr <= ctr + 6'd1;
if (ctr >= bl_i || cti_i==3'b000 || cti_i==3'b111 || !cyc_i)
state <= NACK;
else
state <= BREAD_010c;
end
`endif
 
//---------------------------------------------------------
//---------------------------------------------------------
// If cyc_o went inactive during BWRITE_CMD (ack1==1'b0) then move
// to next state. cyc_i might have gone back to active as the next
// bus cycle could have started.
//
NACK:
if (!cyc_i || ack1==1'b0) begin
ack1 <= 1'b0;
rd_en <= 1'b0;
state <= IDLE;
end
endcase
end
endmodule
/verilog/Raptor64_opcodes.v
110,6 → 110,9
`define INSNKEY 6'd37
`define PCHI 6'd62
`define PCHISTORIC 6'd63
`define MFSEG 6'd42
`define MTSEG 6'd43
`define MFSEGI 6'd44
`define OMG 6'd50
`define CMG 6'd51
`define OMGI 6'd52
130,6 → 133,7
`define NOR 6'd13
`define XNOR 6'd14
`define ORC 6'd15
`define AVG 6'd19
`define MIN 6'd20
`define MAX 6'd21
`define MULU 6'd24
143,6 → 147,8
`define MOVPL 6'd32
`define MOVMI 6'd33
 
`define MTSEGI 6'd35
 
`define SHL 6'd40
`define SHRU 6'd41
`define ROL 6'd42
/verilog/Raptor64sc.v
32,6 → 32,7
//`define TLB 1
//`define SIMD 1
`define SEGMENTATION 1
`define SIMPLE_MMU 1
 
`define RESET_VECTOR 64'hFFFF_FFFF_FFFF_FFF0
 
52,8 → 53,7
`include "Raptor64_opcodes.v"
 
module Raptor64sc(rst_i, clk_i, nmi_i, irq_i, irq_no, bte_o, cti_o, bl_o, iocyc_o,
cyc_o, stb_o, ack_i, err_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr,
advanceI, advanceR, advanceX, advanceM1, advanceM2, advanceW, advanceT
cyc_o, stb_o, ack_i, err_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr
);
parameter IDLE = 5'd1;
parameter ICACT = 5'd2;
99,18 → 99,11
input sys_adv;
input [63:5] sys_adr;
 
output advanceI;
output advanceR;
output advanceX;
output advanceM1;
output advanceM2;
output advanceW;
output advanceT;
 
wire clk;
reg [3:0] state;
reg [5:0] fltctr;
wire fltdone = fltctr==6'd0;
reg inta;
reg bu_im; // interrupt mask
reg im1; // temporary interrupt mask for LM/SM
reg [7:0] ie_fuse; // interrupt enable fuse
128,10 → 121,7
reg [63:0] EPC [0:15]; // Exception return address
reg [63:0] IPC [0:15]; // Interrupt return address
`ifdef SEGMENTATION
reg [63:16] CS [0:15]; // Code segment
reg [63:16] DS [0:15]; // Data segment
reg [63:16] SS [0:15]; // Stack segment
reg [63:16] ES [0:15]; // BSS segment
reg [63:12] segs [0:255];
`endif
reg dStatusHWI,xStatusHWI,m1StatusHWI,m2StatusHWI;
reg dIm,xIm,m1Im,m2Im;
147,7 → 137,7
reg [63:0] mutex_gate;
reg [63:0] TBA; // Trap Base Address
reg [8:0] dextype,d1extype,xextype,m1extype,m2extype,wextype,textype;
reg [3:0] epat [0:255];
reg [3:0] epat [0:255]; // execution pattern table
reg [7:0] eptr;
reg [3:0] dAXC,d1AXC,xAXC,m1AXC,m2AXC,wAXC; // context active per pipeline stage
wire [3:0] AXC = (eptr==8'h00) ? 4'h0 : epat[eptr];
185,6 → 175,10
reg [63:13] BadVAddr;
reg [63:13] PageTableAddr;
reg [63:0] errorAddress;
wire mmu_ack;
wire [15:0] mmu_dato;
wire ack_i1 = ack_i | mmu_ack;
wire [63:0] dat_i1 = dat_i|{4{mmu_dato}};
 
wire [6:0] iOpcode = insn[31:25];
wire [6:0] iFunc = insn[6:0];
274,37 → 268,37
reg [31:0] data32;
reg [63:0] data64;
 
always @(sel_o or dat_i)
always @(sel_o or dat_i1)
case(sel_o)
8'b00000001: data8 <= #1 dat_i[ 7: 0];
8'b00000010: data8 <= #1 dat_i[15: 8];
8'b00000100: data8 <= #1 dat_i[23:16];
8'b00001000: data8 <= #1 dat_i[31:24];
8'b00010000: data8 <= #1 dat_i[39:32];
8'b00100000: data8 <= #1 dat_i[47:40];
8'b01000000: data8 <= #1 dat_i[55:48];
8'b10000000: data8 <= #1 dat_i[63:56];
8'b00000001: data8 <= #1 dat_i1[ 7: 0];
8'b00000010: data8 <= #1 dat_i1[15: 8];
8'b00000100: data8 <= #1 dat_i1[23:16];
8'b00001000: data8 <= #1 dat_i1[31:24];
8'b00010000: data8 <= #1 dat_i1[39:32];
8'b00100000: data8 <= #1 dat_i1[47:40];
8'b01000000: data8 <= #1 dat_i1[55:48];
8'b10000000: data8 <= #1 dat_i1[63:56];
default: data8 <= 8'h00;
endcase
 
always @(sel_o or dat_i)
always @(sel_o or dat_i1)
case(sel_o)
8'b00000011: data16 <= #1 dat_i[15: 0];
8'b00001100: data16 <= #1 dat_i[31:16];
8'b00110000: data16 <= #1 dat_i[47:32];
8'b11000000: data16 <= #1 dat_i[63:48];
8'b00000011: data16 <= #1 dat_i1[15: 0];
8'b00001100: data16 <= #1 dat_i1[31:16];
8'b00110000: data16 <= #1 dat_i1[47:32];
8'b11000000: data16 <= #1 dat_i1[63:48];
default: data16 <= #1 16'hDEAD;
endcase
 
always @(sel_o or dat_i)
always @(sel_o or dat_i1)
case(sel_o)
8'b00001111: data32 <= #1 dat_i[31: 0];
8'b11110000: data32 <= #1 dat_i[63:32];
8'b00001111: data32 <= #1 dat_i1[31: 0];
8'b11110000: data32 <= #1 dat_i1[63:32];
default: data32 <= #1 32'hDEADDEAD;
endcase
 
always @(sel_o or dat_i)
data64 <= #1 dat_i;
always @(sel_o or dat_i1)
data64 <= #1 dat_i1;
 
assign KernelMode = StatusEXL[xAXC]|StatusHWI;
 
319,30 → 313,19
//-----------------------------------------------------------------------------
// Segmentation
//
// If the upper nybble of the address is 'F' then segmentation is not applied.
// This allows for bootstrapping and operating system use. Also when in kernel
// mode the lowest 64k of memory is unsegmented to allow easier access to
// operating system variables.
//
// Otherwise: the CS register is always in use for code addresses.
// Which segment is used for data addresses depends on the upper nybble of
// the address.
// Paradoxically, it's less expensive to provide an array of 16 segment
// registers as opposed to several independent registers. The 16 registers
// are lower cost than the independent CS,DS,ES, and SS registers were.
//-----------------------------------------------------------------------------
`ifdef SEGMENTATION
wire [63:0] spc; // segmented PC
reg [63:0] sea; // segmented effective address
assign spc = pc[63:60]==4'hF ? pc : {CS[AXC][63:16] + pc[59:16],pc[15:0]};
always @(ea or KernelMode)
if (KernelMode && ea[63:16]==48'h0)
sea <= ea;
else
case(ea[63:60])
4'hF: sea <= ea;
4'hE: sea <= {SS[xAXC][63:16] + ea[59:16],ea[15:0]};
4'hD: sea <= {ES[xAXC][63:16] + ea[59:16],ea[15:0]};
default:
sea <= {DS[xAXC][63:16] + ea[59:16],ea[15:0]};
endcase
wire [63:0] sea; // segmented effective address
assign spc = {segs[{pc[63:60], AXC}][63:12] + pc[59:12],pc[11:0]};
assign sea = {segs[{ea[63:60],xAXC}][63:12] + ea[59:12],ea[11:0]};
initial begin
for (n = 0; n < 256; n = n + 1)
segs[n] = 52'd0;
end
`else
wire [63:0] spc = pc;
wire [63:0] sea = ea;
349,6 → 332,33
`endif
 
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
`ifdef SIMPLE_MMU
SimpleMMU ummu1
(
.num(3'd0),
.rst_i(rst_i),
.clk_i(clk),
.dma_i(1'b0),
.kernel_mode(KernelMode),
.cyc_i(iocyc_o),
.stb_i(stb_o),
.ack_o(mmu_ack),
.we_i(we_o),
.adr_i(adr_o[23:0]),
.dat_i(dat_o[15:0]),
.dat_o(mmu_dato),
.rclk(~clk),
.pc_i(spc[27:0]),
.pc_o(ppc[27:0]),
.ea_i(sea[27:0]),
.ea_o(pea[27:0])
);
assign pea[63:28]=sea[63:28];
assign ppc[63:28]=spc[63:28];
`endif
 
//-----------------------------------------------------------------------------
// TLB
// The TLB contains 64 entries, that are 8 way set associative.
// The TLB is dual ported and shared between the instruction and data streams.
396,9 → 406,11
);
 
`else
`ifndef SIMPLE_MMU
assign ppc = spc;
assign pea = sea;
`endif
`endif
 
//-----------------------------------------------------------------------------
// Clock control
479,7 → 491,7
.adr(icadr[13:0]),
.d(err_i ? bevect : dat_i),
.rclk(~clk),
.pc(pc[13:0]),
.pc(ppc[13:0]),
.insn(insnbundle)
);
 
506,7 → 518,7
end
 
wire [64:14] tgout;
assign tgout = {tvalid[pc[13:6]],tmem[pc[13:6]]};
assign tgout = {tvalid[ppc[13:6]],tmem[ppc[13:6]]};
assign ihit = (tgout=={1'b1,ppc[63:14]});
assign ibufrdy = ibufadr[63:2]==ppc[63:2];
 
1095,6 → 1107,7
wire lti = $signed(a) < $signed(imm);
wire ltu = a < b;
wire ltui = a < imm;
wire [7:0] segndx = xFunc6==`MFSEG ? {xIR[9:6],xAXC} : {a[63:60],xAXC};
 
always @(xOpcode or xFunc or xFunc5 or a or b or c or imm or xpc or aeqz or xFunc6 or
sqrt_out or cntlzo or cntloo or tick or AXC or scale or
1170,12 → 1183,6
`PageTableAddr: xData1 = {PageTableAddr,13'd0};
`BadVAddr: xData1 = {BadVAddr,13'd0};
`endif
`ifdef SEGMENTATION
`CS: xData1 = {CS[xAXC],16'h0};
`DS: xData1 = {DS[xAXC],16'h0};
`ES: xData1 = {ES[xAXC],16'b0};
`SS: xData1 = {SS[xAXC],16'h0};
`endif
`ASID: xData1 = ASID;
`Tick: xData1 = tick;
`EPC: xData1 = EPC[xAXC];
1192,6 → 1199,10
`PCHISTORIC: xData1 = pchistoric;
default: xData1 = 64'd0;
endcase
`ifdef SEGMENTATION
`MFSEG,`MFSEGI: xData1 = segs[segndx];
`MTSEG: xData1 = a;
`endif
`OMG: xData1 = mutex_gate[a[5:0]];
`CMG: xData1 = mutex_gate[a[5:0]];
`OMGI: begin
1219,6 → 1230,9
`MODS: xData1 = div_r;
`BCD_MUL: xData1 = bcdmulo;
`MFEP: xData1 = epat[a[7:0]];
`ifdef SEGMENTATION
`MTSEGI: xData1 = b;
`endif
default: xData1 = 64'd0;
endcase
`ifdef SIMD
1536,7 → 1550,7
wire m2ForwardingActive = (m2Rt==dRa || m2Rt==dRb || m2Rt==dRc) & !m2Rtz;
wire m1ForwardingActive = (m1Rt==dRa || m1Rt==dRb || m1Rt==dRc) & !m1Rtz;
wire xForwardingActive = (xRt==dRa || xRt==dRb || xRt==dRc) & !xRtz;
wire memCycleActive = ((iocyc_o & !(ack_i|err_i)) || (cyc_o & !(ack_i|err_i)));
wire memCycleActive = ((iocyc_o & !(ack_i1|err_i)) || (cyc_o & !(ack_i1|err_i)));
wire StallI = 1'b0;
 
// Stall on SWC allows rsf flag to be loaded for the next instruction
1558,9 → 1572,9
 
assign advanceT = (state==RUN) && !StallT;
assign advanceW = advanceT & !StallW;
assign advanceM2 = advanceW && (cyc_o ? (ack_i|err_i) : 1'b1) && !StallM2;
assign advanceM2 = advanceW && (cyc_o ? (ack_i1|err_i) : 1'b1) && !StallM2;
assign advanceM1 = advanceM2 &
(iocyc_o ? (ack_i|err_i) : 1'b1) &
(iocyc_o ? (ack_i1|err_i) : 1'b1) &
((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
!StallM1
;
1801,6 → 1815,7
wData <= 64'd0;
m1Data <= 64'd0;
m2Data <= 64'd0;
wData <= 64'd0;
icaccess <= 1'b0;
dcaccess <= 1'b0;
wFip <= 1'b0;
1809,6 → 1824,7
xFip <= 1'b0;
dFip <= 1'b0;
dirqf <= 1'b0;
inta <= 1'b0;
dNmi <= 1'b0;
xNmi <= 1'b0;
m1Nmi <= 1'b0;
1857,11 → 1873,12
// Initialize program counters
// Initialize data tags to zero.
// Initialize execution pattern register to zero.
// Initialize segment registers to zero.
//---------------------------------------------------------
case(state)
RESET:
begin
pc <= `RESET_VECTOR;
$display("Resetting %h",adr_o[14:6]);
adr_o[14:6] <= adr_o[14:6]+9'd1;
if (adr_o[14:6]==9'h1FF) begin
dtinit <= 1'b0;
1869,6 → 1886,9
end
epat[a[7:0]] <= b[3:0]; /// b=0, to make this line the same as MTEP
a[7:0] <= a[7:0] + 8'h1;
wIR[9:6] <= a[7:4];
wAXC <= wAXC + 4'd1;
segs[{wIR[9:6],wAXC}] <= wData; // same line as in WB stage, wData =0
end
RUN:
begin
1876,6 → 1896,7
ie_fuse <= {ie_fuse[6:0],ie_fuse[0]}; // shift counter
 
tick <= tick + 64'd1;
$display("tick: %d", tick[31:0]);
 
prev_nmi <= nmi_i;
if (!prev_nmi & nmi_i)
2303,6 → 2324,7
`RR:
case(xFunc6)
`MTEP: epat[a[7:0]] <= b[3:0];
`MTSEGI: m1IR[9:6] <= a[63:60];
default: ;
endcase
// JMP and CALL change the program counter immediately in the IF stage.
3294,12 → 3316,6
case(wFunc6)
`MTSPR:
case(wIR[11:6])
`ifdef SEGMENTATION
`CS: CS[wAXC][63:16] <= wData[63:16];
`DS: DS[wAXC][63:16] <= wData[63:16];
`ES: ES[wAXC][63:16] <= wData[63:16];
`SS: SS[wAXC][63:16] <= wData[63:16];
`endif
`IPC: begin
$display("mtspr IPC[%d]=%h",wAXC,wData);
IPC[wAXC] <= wData;
3307,7 → 3323,18
`EPC: EPC[wAXC] <= wData;
default: ;
endcase
`ifdef SEGMENTATION
`MTSEG: segs[{wIR[9:6],wAXC}] <= wData[63:12];
`endif
endcase
`RR:
case(wFunc6)
`ifdef SEGMENTATION
`MTSEGI: segs[{wIR[9:6],wAXC}] <= wData[63:12];
`endif
default: ;
endcase
default: ;
endcase
if (wclkoff)
clk_en <= 1'b0;
3435,6 → 3462,7
cstate <= ICACT1;
end
else begin
$display("Fetching %h", {ppc[31:2],2'b00});
cti_o <= 3'b000;
bl_o <= 5'd0;
adr_o <= {ppc[63:2],2'b00};
3468,6 → 3496,7
insnbuf <= syscall509;
else
insnbuf <= adr_o[2] ? dat_i[63:32] : dat_i[31:0];
$display("Fetched: %h", adr_o[2] ? dat_i[63:32] : dat_i[31:0]);
cti_o <= 3'b000; // back to non-burst mode
cyc_o <= 1'b0;
stb_o <= 1'b0;
/verilog/SimpleMMU.v
0,0 → 1,215
`timescale 1ns / 1ps
//=============================================================================
// __
// \\__/ o\ (C) 2011,2012 Robert Finch
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// SimpleMMU.v
// - maps 128MB into 512 256kB blocks
// - supports 32 tasks per mmu
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// 20 block RAMs // 106 LUTs // 42 FF's // 190 MHz
//=============================================================================
//
module SimpleMMU(num, rst_i, clk_i, dma_i, kernel_mode, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o, rclk, pc_i, pc_o, ea_i, ea_o);
parameter pIOAddress = 24'hDC4000;
input [2:0] num; // mmu number
input rst_i; // core reset
input clk_i; // clock
input dma_i; // 1=DMA cycle is active
input kernel_mode; // 1=processor is in kernel mode
input cyc_i; // bus cycle active
input stb_i; // data transfer strobe
output ack_o; // data transfer acknowledge
input we_i; // write enable
input [23:0] adr_i; // I/O register address
input [15:0] dat_i; // data input
output [15:0] dat_o; // data output
reg [15:0] dat_o;
input rclk; // read clock (~clk)
input [27:0] pc_i; // program counter / instruction pointer input
output [27:0] pc_o; // mapped version of program counter
reg [27:0] pc_o;
input [27:0] ea_i; // effective data address input
output [27:0] ea_o; // effective data address mapped
reg [27:0] ea_o;
 
reg map_enable;
reg forceHi;
reg su; // 1= system
reg [3:0] fuse;
reg ofuse3;
reg [7:0] accessKey;
reg [7:0] operateKey;
reg [2:0] kvmmu;
reg ack1, ack2;
 
always @(posedge clk_i)
begin
ack1 <= cs;
ack2 <= ack1 & cs;
end
assign ack_o = cs ? (we_i ? 1'b1 : ack2) : 1'b0;
 
wire cs = cyc_i && stb_i && (adr_i[23:12]==pIOAddress[23:12]);
wire [7:0] oKey =
dma_i ? 8'd1 :
su ? 8'd0 :
operateKey
;
reg [13:0] rmrad;
reg [13:0] rmra;
reg [13:0] rmrb;
wire [13:0] mwa = {accessKey[4:0],adr_i[9:1]};
wire [13:0] mrad = {accessKey[4:0],adr_i[9:1]};
wire [13:0] mra = {oKey[4:0],pc_i[26:18]};
wire [13:0] mrb = {oKey[4:0],ea_i[26:18]};
wire [9:0] mro0,mro1,mro2;
 
always @(posedge clk_i) rmrad <= mrad;
always @(posedge rclk) rmra <= mra;
always @(posedge rclk) rmrb <= mrb;
wire thisMMU = kvmmu==accessKey[7:5];
 
wire pe_stb;
wire pe_km;
edge_det u1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(stb_i), .pe(pe_stb), .ne(), .ee() );
edge_det u2 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(kernel_mode), .pe(pe_km), .ne(), .ee() );
 
mapram u3
(
.wclk(clk_i),
.wr(cs & we_i & su & ~adr_i[10] & thisMMU),
.wa(mwa),
.i(dat_i[9:0]),
.rclk(~clk_i),
.ra0(mrad),
.ra1(mra),
.ra2(mrb),
.o0(mro0),
.o1(mro1),
.o2(mro2)
);
 
always @(posedge clk_i)
if (rst_i) begin
map_enable <= 1'b0;
kvmmu <= 3'd0;
su <= 1'b1;
fuse <= 4'hF;
ofuse3 <= 1'b1;
accessKey <= 8'h00;
operateKey <= 8'h00;
end
else begin
ofuse3 <= fuse[3];
if (!fuse[3] && !dma_i && pe_stb)
fuse <= fuse - 4'd1;
if (fuse[3] & !ofuse3)
su <= 1'b0;
else if (pe_km)
su <= 1'b1;
 
if (cs) begin
if (we_i) begin
if (su) begin
casex(adr_i[10:0])
// 11'b0xxxxxxxxxx: if (thisMMU) map[mwa] <= dat_i[9:0];
11'h40x: if (oKey==8'h00 && (adr_i[2:0]==num))
kvmmu <= dat_i[2:0];
11'h412: fuse <= dat_i[2:0];
11'h414: accessKey <= dat_i[7:0];
11'h416: operateKey <= dat_i[7:0];
11'h418: map_enable <= dat_i[0];
endcase
end
end
else begin
if ((adr_i[2:0]==num) && oKey==8'd0 && adr_i[10:4]==7'b1000000)
dat_o <= {5'd0,kvmmu};
else if (thisMMU)
casex(adr_i[10:0])
11'b0xxxxxxxxxx: dat_o <= mro0;
11'h410: dat_o <= su;
11'h412: dat_o <= fuse;
11'h414: dat_o <= accessKey;
11'h416: dat_o <= operateKey;
11'h418: dat_o <= map_enable;
default: dat_o <= 16'h0000;
endcase
else
dat_o <= 16'h0000;
end
end
else
dat_o <= 16'h0000;
end
 
always @(pc_i) pc_o[17:0] <= pc_i[17:0];
always @(ea_i) ea_o[17:0] <= ea_i[17:0];
 
always @(rmra or oKey or kvmmu or mro1 or cs or map_enable)
begin
if (!map_enable)
pc_o[27:18] <= pc_i[27:18];
else if (kvmmu==oKey[7:5])
pc_o[27:18] <= mro1;
else
pc_o[27:18] <= 10'h000;
end
 
always @(rmrb or oKey or kvmmu or mro2 or cs or cyc_i or ea_i or map_enable)
begin
if (cyc_i|~map_enable) // I/O cycles are not mapped
ea_o[27:18] <= ea_i[27:18];
else if (kvmmu==oKey[7:5])
ea_o[27:18] <= mro2;
else
ea_o[27:18] <= 10'h000;
end
 
endmodule
 
module mapram(wclk, wr, wa, i, rclk, ra0, ra1, ra2, o0, o1, o2);
input wclk;
input wr;
input [13:0] wa;
input [9:0] i;
input rclk;
input [13:0] ra0;
input [13:0] ra1;
input [13:0] ra2;
output [9:0] o0;
output [9:0] o1;
output [9:0] o2;
 
reg [9:0] map [0:16383];
reg [13:0] rra0,rra1,rra2;
 
always @(posedge wclk)
if (wr) map[wa] <= i;
always @(posedge rclk) rra0 <= ra0;
always @(posedge rclk) rra1 <= ra1;
always @(posedge rclk) rra2 <= ra2;
 
assign o0 = map[rra0];
assign o1 = map[rra1];
assign o2 = map[rra2];
 
endmodule
/verilog/Raptor64_tb2.v
0,0 → 1,903
module Raptor64_tb2();
parameter IDLE = 8'd1;
parameter DOCMD = 8'd2;
 
reg clk;
reg rst;
reg nmi;
wire sys_iocyc;
wire sys_cyc;
wire sys_stb;
wire sys_we;
wire [7:0] sys_sel;
wire [63:0] sys_adr;
wire [63:0] sys_dbo;
wire [63:0] sys_dbi;
wire sys_ack;
wire sys_err = 1'b0;
reg [7:0] cnt;
wire wr_empty = 1'b1;
wire wr_full;
reg [63:0] romout;
wire stk_ack;
wire scr_ack;
wire br_ack;
wire [63:0] br_dato;
wire [63:0] stk_dato;
wire [63:0] scr_dato;
wire [15:0] tc_dato;
wire [15:0] pic_dato;
wire tc_ack;
wire pic_ack;
reg pulse1000Hz,pulse100Hz;
wire [7:0] config_rec;
reg [7:0] config_reco;
//wire sm_ack;
wire [7:0] sm_dato;
wire [8:0] vecno;
wire [2:0] cpu_cti;
 
wire uart_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_0A);
wire rast_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDA_01);
wire AC97_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_10);
wire spr_ack = sys_iocyc && sys_stb && (sys_adr[23:16]==8'hD8);
wire Led_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_06);
wire dt_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_04);
wire p100ack = sys_iocyc && sys_stb && (sys_adr[23:0]==24'hDCFFFC);
wire p1000ack = sys_iocyc && sys_stb && (sys_adr[23:0]==24'hDCFFFD);
wire config_rec_ack = sys_iocyc && sys_stb && sys_adr[23:3]==21'b1101_1100_1111_1111_1111_0;
wire perr_ack = sys_iocyc && sys_stb && sys_adr[23:0]==24'hDCFFFE;
wire tmp_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC03);
wire sm_ack = sys_iocyc && sys_stb && (sys_adr[23:16]==8'hDB);
wire mmu_ack = sys_iocyc && sys_stb && (sys_adr[23:12]==12'hDC4);
 
//assign ram_ack = sys_cyc && sys_stb && (sys_adr[63:32]==32'd1);
 
assign config_rec = 8'b0000_0111;
 
always @(config_rec_ack)
config_reco <= config_rec_ack ? config_rec : 8'd0;
 
wire cs_ram = sys_cyc && sys_stb && (sys_adr[63:32]==32'd1);
reg [63:0] sysram [0:16000];
always @(posedge clk)
if (cs_ram & sys_we) begin
$display("Wrote ram[%h]=%h", sys_adr, sys_dbo);
sysram[sys_adr[15:3]] <= sys_dbo;
end
wire [63:0] ramo = cs_ram ? sysram[sys_adr[15:3]] : 64'd0;
reg ack1,ack2,ack3,ack4,ack5,ack6,ack7,ack8;
always @(posedge clk)
begin
ack1 <= cs_ram;
ack2 <= ack1 & cs_ram;
ack3 <= ack2 & cs_ram;
ack4 <= ack3 & cs_ram;
ack5 <= ack4 & cs_ram;
ack6 <= ack5 & cs_ram;
ack7 <= ack6 & cs_ram;
ack8 <= ack7 & cs_ram;
end
wire ram_ack = cs_ram & ack8;
 
assign sys_ack = br_ack|stk_ack|scr_ack|tc_ack|pic_ack|ram_ack|uart_ack|rast_ack|
AC97_ack|spr_ack|Led_ack|dt_ack|
p100ack|p1000ack|config_rec_ack|tmp_ack|perr_ack|sm_ack|mmu_ack;
initial begin
clk = 1;
pulse1000Hz = 0;
pulse100Hz = 0;
rst = 0;
nmi = 0;
#100 rst = 1;
#100 rst = 0;
#800 nmi = 1;
#100 nmi = 0;
end
 
always #20 clk = ~clk; // 25 MHz
always #29930 pulse1000Hz = 1;
always #130 pulse1000Hz = 0;
always #299030 pulse100Hz = 1;
always #130 pulse100Hz = 0;
 
 
reg pulse1000HzB,pulse100HzB;
always @(posedge clk)
if (rst) begin
pulse1000HzB <= 1'b0;
pulse100HzB <= 1'b0;
end
else begin
if (pulse1000Hz)
pulse1000HzB <= 1'b1;
else begin
if (p1000ack)
pulse1000HzB <= 1'b0;
end
if (pulse100Hz)
pulse100HzB <= 1'b1;
else begin
if (p100ack)
pulse100HzB <= 1'b0;
end
end
 
sema_mem usm
(
.rst_i(rst),
.clk_i(clk),
.cyc_i(sys_iocyc),
.stb_i(sys_stb),
.ack_o(sm_ack),
.we_i(sys_we),
.adr_i(sys_adr[23:0]),
.dat_i(sys_dbo[7:0]),
.dat_o(sm_dato)
);
 
 
rtfTextController tc1
(
.rst_i(rst),
.clk_i(clk),
.cyc_i(sys_iocyc),
.stb_i(sys_stb),
.ack_o(tc_ack),
.we_i(sys_we),
.sel_i(sys_sel[1:0]|sys_sel[3:2]|sys_sel[5:4]|sys_sel[7:6]),
.adr_i(sys_adr),
.dat_i(sys_dbo[15:0]),
.dat_o(tc_dato),
.lp(),
.curpos(),
.vclk(),
.hsync(),
.vsync(),
.blank(),
.border(),
.rgbIn(),
.rgbOut()
);
 
scratchmem u_sc
(
.clk_i(clk),
.cyc_i(sys_cyc),
.stb_i(sys_stb),
.ack_o(scr_ack),
.we_i(sys_we),
.sel_i(sys_sel),
.adr_i(sys_adr),
.dat_i(sys_dbo),
.dat_o(scr_dato)
);
 
stkmem u_stk
(
.clk_i(clk),
.cyc_i(sys_cyc),
.stb_i(sys_stb),
.ack_o(stk_ack),
.we_i(sys_we),
.adr_i(sys_adr),
.dat_i(sys_dbo),
.dat_o(stk_dato)
);
 
bootrom u_br
(
.clk_i(clk),
.cti_i(cpu_cti),
.cyc_i(sys_cyc),
.stb_i(sys_stb),
.ack_o(br_ack),
.adr_i(sys_adr),
.dat_o(br_dato)
);
 
 
RaptorPIC u_pic
(
.rst_i(rst), // reset
.clk_i(clk), // system clock
.cyc_i(sys_iocyc), // cycle valid
.stb_i(sys_stb), // strobe
.ack_o(pic_ack), // transfer acknowledge
.we_i(sys_we), // write
.sel_i(sys_sel[1:0]|sys_sel[3:2]|sys_sel[5:4]|sys_sel[7:6]), // byte select
.adr_i(sys_adr), // address
.dat_i(sys_dbo[15:0]),
.dat_o(pic_dato),
.vol_o(), // volatile register selected
.i1(),
.i2(pulse1000HzB),
.i3(pulse100HzB),
.i4(), .i5(), .i6(), .i7(),
.i8(), .i9(), .i10(), .i11(), .i12(), .i13(), .i14(),
.i15(),
.irqo(cpu_irq), // normally connected to the processor irq
.nmii(nmi), // nmi input connected to nmi requester
.nmio(cpu_nmi), // normally connected to the nmi of cpu
.vecno(vecno)
);
 
 
 
reg [63:0] keybdout;
always @(sys_adr)
if (sys_adr==24'hDC_0000) begin
$display ("keyboard=FF");
keybdout <= 64'hFFFF_FFFF_FFFF_FFFF;
end
else
keybdout <= 64'd0;
always @(sys_adr)
case(sys_adr)// | 64'hFFFF_FFFF_FFFF_0000)
64'hFFFFFFFFFFFFE800: romout <= 64'h000030000000000A;
64'hFFFFFFFFFFFFE808: romout <= 64'h0BEFFFEFFF800000;
64'hFFFFFFFFFFFFE810: romout <= 64'hFFE920C7FFFFFA66;
64'hFFFFFFFFFFFFE818: romout <= 64'h0000000004031FFF;
64'hFFFFFFFFFFFFE820: romout <= 64'h001050A3000000CE;
64'hFFFFFFFFFFFFE828: romout <= 64'h1080600041462018;
64'hFFFFFFFFFFFFE830: romout <= 64'h001058A300000020;
64'hFFFFFFFFFFFFE838: romout <= 64'h1080400041662018;
64'hFFFFFFFFFFFFE840: romout <= 64'h0002210804000416;
64'hFFFFFFFFFFFFE848: romout <= 64'h0000000000DBE218;
64'hFFFFFFFFFFFFE850: romout <= 64'hFFEBD10806000414;
64'hFFFFFFFFFFFFE858: romout <= 64'h0C7FFFFFAE131FFF;
64'hFFFFFFFFFFFFE860: romout <= 64'h0010618800000416;
64'hFFFFFFFFFFFFE868: romout <= 64'h0A1FFFFE90062000;
64'hFFFFFFFFFFFFE870: romout <= 64'hFFEF94E1FFFFFFFF;
64'hFFFFFFFFFFFFE878: romout <= 64'h00802000AA831FFF;
64'hFFFFFFFFFFFFE880: romout <= 64'h50C842F840000129;
64'hFFFFFFFFFFFFE888: romout <= 64'h008400008A9285D9;
64'hFFFFFFFFFFFFE890: romout <= 64'h72EA6008400009A9;
64'hFFFFFFFFFFFFE898: romout <= 64'h00840000929287FB;
64'hFFFFFFFFFFFFE8A0: romout <= 64'hFFF2440840000A29;
64'hFFFFFFFFFFFFE8A8: romout <= 64'h2F80000002A33FFF;
64'hFFFFFFFFFFFFE8B0: romout <= 64'h00000C3FBC000018;
64'hFFFFFFFFFFFFE8B8: romout <= 64'h0A2FFFFE8F09FD00;
64'hFFFFFFFFFFFFE8C0: romout <= 64'h0003210082000000;
64'hFFFFFFFFFFFFE8C8: romout <= 64'h0C7FFFFFA58BE100;
64'hFFFFFFFFFFFFE8D0: romout <= 64'hFFFE282884000001;
64'hFFFFFFFFFFFFE8D8: romout <= 64'h27740000003BE007;
64'hFFFFFFFFFFFFE8E0: romout <= 64'h000000DFBE000018;
64'hFFFFFFFFFFFFE8E8: romout <= 64'h37800000000DE000;
64'hFFFFFFFFFFFFE8F0: romout <= 64'h6F57206F6C6C6548;
64'hFFFFFFFFFFFFE8F8: romout <= 64'h0000000021646C72;
64'hFFFFFFFFFFFFE900: romout <= 64'h3436726F74706152;
64'hFFFFFFFFFFFFE908: romout <= 64'h206D657473797320;
64'hFFFFFFFFFFFFE910: romout <= 64'h676E697472617473;
64'hFFFFFFFFFFFFE918: romout <= 64'h000000002E2E2E2E;
64'hFFFFFFFFFFFFE920: romout <= 64'h703FC8A1FFFF8007;
64'hFFFFFFFFFFFFE928: romout <= 64'h0DFBE0000009200F;
64'hFFFFFFFFFFFFE930: romout <= 64'h0000003FBC000008;
64'hFFFFFFFFFFFFE938: romout <= 64'h0A1FFDC0A0067E18;
64'hFFFFFFFFFFFFE940: romout <= 64'h0000060046000001;
64'hFFFFFFFFFFFFE948: romout <= 64'h2F8C000000814318;
64'hFFFFFFFFFFFFE950: romout <= 64'h0000011F86000000;
64'hFFFFFFFFFFFFE958: romout <= 64'h0DFBE00000880108;
64'hFFFFFFFFFFFFE960: romout <= 64'h0000203FBC000010;
64'hFFFFFFFFFFFFE968: romout <= 64'h19F8600000067E10;
64'hFFFFFFFFFFFFE970: romout <= 64'h000004A3FFDC0A00;
64'hFFFFFFFFFFFFE978: romout <= 64'h0508400004080310;
64'hFFFFFFFFFFFFE980: romout <= 64'h000002F881FFFFA8;
64'hFFFFFFFFFFFFE988: romout <= 64'h11F8600000090308;
64'hFFFFFFFFFFFFE990: romout <= 64'h0000411F84000008;
64'hFFFFFFFFFFFFE998: romout <= 64'h1800000045037EF8;
64'hFFFFFFFFFFFFE9A0: romout <= 64'h0000058000000451;
64'hFFFFFFFFFFFFE9A8: romout <= 64'h1800200041A28400;
64'hFFFFFFFFFFFFE9B0: romout <= 64'h000060DFBE000000;
64'hFFFFFFFFFFFFE9B8: romout <= 64'h27F000000070FEF0;
64'hFFFFFFFFFFFFE9C0: romout <= 64'h00003D2802000450;
64'hFFFFFFFFFFFFE9C8: romout <= 64'h0A30000044014108;
64'hFFFFFFFFFFFFE9D0: romout <= 64'h700000E300000000;
64'hFFFFFFFFFFFFE9D8: romout <= 64'h24801DC000282017;
64'hFFFFFFFFFFFFE9E0: romout <= 64'h000005A8C2200010;
64'hFFFFFFFFFFFFE9E8: romout <= 64'h0504200000F0A108;
64'hFFFFFFFFFFFFE9F0: romout <= 64'h0011458002000450;
64'hFFFFFFFFFFFFE9F8: romout <= 64'h2F8440001094A010;
64'hFFFFFFFFFFFFEA00: romout <= 64'h00003C2884000001;
64'hFFFFFFFFFFFFEA08: romout <= 64'h1800400045114210;
64'hFFFFFFFFFFFFEA10: romout <= 64'h0000627700000007;
64'hFFFFFFFFFFFFEA18: romout <= 64'h0DFBE0000000BEF0;
64'hFFFFFFFFFFFFEA20: romout <= 64'h000001800200041A;
64'hFFFFFFFFFFFFEA28: romout <= 64'h03FBC00001037EF8;
64'hFFFFFFFFFFFFEA30: romout <= 64'h0011467F00000006;
64'hFFFFFFFFFFFFEA38: romout <= 64'h128020004504A010;
64'hFFFFFFFFFFFFEA40: romout <= 64'h000002F844000148;
64'hFFFFFFFFFFFFEA48: romout <= 64'h1A8C410000528C00;
64'hFFFFFFFFFFFFEA50: romout <= 64'h00003C2884000001;
64'hFFFFFFFFFFFFEA58: romout <= 64'h1800400045114210;
64'hFFFFFFFFFFFFEA60: romout <= 64'h0000427700000006;
64'hFFFFFFFFFFFFEA68: romout <= 64'h0A1FFFFFFFF37EF8;
64'hFFFFFFFFFFFFEA70: romout <= 64'h0000427700000006;
64'hFFFFFFFFFFFFEA78: romout <= 64'h1280200045137EF8;
64'hFFFFFFFFFFFFEA80: romout <= 64'h0002A12804000450;
64'hFFFFFFFFFFFFEA88: romout <= 64'h0A100000001BE110;
64'hFFFFFFFFFFFFEA90: romout <= 64'h400028DFBE000000;
64'hFFFFFFFFFFFFEA98: romout <= 64'h0DFBE00000004108;
64'hFFFFFFFFFFFFEAA0: romout <= 64'h0000083FBC000010;
64'hFFFFFFFFFFFFEAA8: romout <= 64'h0A2FFDC00009FD00;
64'hFFFFFFFFFFFFEAB0: romout <= 64'h0000060082000000;
64'hFFFFFFFFFFFFEAB8: romout <= 64'h20080000002BE100;
64'hFFFFFFFFFFFFEAC0: romout <= 64'h00106850420000FF;
64'hFFFFFFFFFFFFEAC8: romout <= 64'h2F8800000C840010;
64'hFFFFFFFFFFFFEAD0: romout <= 64'hFFED4AC04514000D;
64'hFFFFFFFFFFFFEAD8: romout <= 64'h2774000000231FFF;
64'hFFFFFFFFFFFFEAE0: romout <= 64'h000060DFBE000010;
64'hFFFFFFFFFFFFEAE8: romout <= 64'h27F400000030FEF0;
64'hFFFFFFFFFFFFEAF0: romout <= 64'h0000051802000400;
64'hFFFFFFFFFFFFEAF8: romout <= 64'h1980200040008108;
64'hFFFFFFFFFFFFEB00: romout <= 64'h000378A2FFD00000;
64'hFFFFFFFFFFFFEB08: romout <= 64'h0284200000142208;
64'hFFFFFFFFFFFFEB10: romout <= 64'hFC000188820000DE;
64'hFFFFFFFFFFFFEB18: romout <= 64'h1180200040042007;
64'hFFFFFFFFFFFFEB20: romout <= 64'h400100504200007F;
64'hFFFFFFFFFFFFEB28: romout <= 64'h0C7FFFFFACEB2100;
64'hFFFFFFFFFFFFEB30: romout <= 64'h0000627740000003;
64'hFFFFFFFFFFFFEB38: romout <= 64'h03FBC00002037EF8;
64'hFFFFFFFFFFFFEB40: romout <= 64'hFFED0A7F40000007;
64'hFFFFFFFFFFFFEB48: romout <= 64'h0284201000031FFF;
64'hFFFFFFFFFFFFEB50: romout <= 64'h0000050844000000;
64'hFFFFFFFFFFFFEB58: romout <= 64'h188440000000A210;
64'hFFFFFFFFFFFFEB60: romout <= 64'h0003211804000408;
64'hFFFFFFFFFFFFEB68: romout <= 64'h10806000414BE110;
64'hFFFFFFFFFFFFEB70: romout <= 64'h0010218886000000;
64'hFFFFFFFFFFFFEB78: romout <= 64'h2774000000766008;
64'hFFFFFFFFFFFFEB80: romout <= 64'h0000A0DFBE000020;
64'hFFFFFFFFFFFFEB88: romout <= 64'h27F4000000F0FEF0;
64'hFFFFFFFFFFFFEB90: romout <= 64'h000C00A100000554;
64'hFFFFFFFFFFFFEB98: romout <= 64'h0104420001828800;
64'hFFFFFFFFFFFFEBA0: romout <= 64'hA4A4A41004400009;
64'hFFFFFFFFFFFFEBA8: romout <= 64'h0A300200000284A4;
64'hFFFFFFFFFFFFEBB0: romout <= 64'h000000E300000001;
64'hFFFFFFFFFFFFEBB8: romout <= 64'h028C600000464308;
64'hFFFFFFFFFFFFEBC0: romout <= 64'h00003EF805FFFFAF;
64'hFFFFFFFFFFFFEBC8: romout <= 64'h0DFBE0000289DD00;
64'hFFFFFFFFFFFFEBD0: romout <= 64'h00003C3FBC000028;
64'hFFFFFFFFFFFFEBD8: romout <= 64'h0A3FFDA00009FD00;
64'hFFFFFFFFFFFFEBE0: romout <= 64'h00000908C2000000;
64'hFFFFFFFFFFFFEBE8: romout <= 64'h0104420001842310;
64'hFFFFFFFFFFFFEBF0: romout <= 64'h001050A100000020;
64'hFFFFFFFFFFFFEBF8: romout <= 64'h0C7FFFFFB3242020;
64'hFFFFFFFFFFFFEC00: romout <= 64'h000000A3FFD00000;
64'hFFFFFFFFFFFFEC08: romout <= 64'h188C801000062308;
64'hFFFFFFFFFFFFEC10: romout <= 64'hFFFEBC28C6000002;
64'hFFFFFFFFFFFFEC18: romout <= 64'h2774000000FBE017;
64'hFFFFFFFFFFFFEC20: romout <= 64'h0000A0DFBE000028;
64'hFFFFFFFFFFFFEC28: romout <= 64'h27F4000000F0FEF0;
64'hFFFFFFFFFFFFEC30: romout <= 64'h000000A3FFDA0000;
64'hFFFFFFFFFFFFEC38: romout <= 64'h108C400000242308;
64'hFFFFFFFFFFFFEC40: romout <= 64'h8000141044200018;
64'hFFFFFFFFFFFFEC48: romout <= 64'h0A3FFD0000004208;
64'hFFFFFFFFFFFFEC50: romout <= 64'h000001A8C2400001;
64'hFFFFFFFFFFFFEC58: romout <= 64'h028C600000262320;
64'hFFFFFFFFFFFFEC60: romout <= 64'h680002F805FFFF8F;
64'hFFFFFFFFFFFFEC68: romout <= 64'h108C200000228FFF;
64'hFFFFFFFFFFFFEC70: romout <= 64'hFFEC843842000001;
64'hFFFFFFFFFFFFEC78: romout <= 64'h2774000000F31FFF;
64'hFFFFFFFFFFFFEC80: romout <= 64'h000060DFBE000028;
64'hFFFFFFFFFFFFEC88: romout <= 64'h27F000000070FEF0;
64'hFFFFFFFFFFFFEC90: romout <= 64'h000000A3FFDA0000;
64'hFFFFFFFFFFFFEC98: romout <= 64'h0108230001842310;
64'hFFFFFFFFFFFFECA0: romout <= 64'h40000018C6080000;
64'hFFFFFFFFFFFFECA8: romout <= 64'h0A1000000200A31F;
64'hFFFFFFFFFFFFECB0: romout <= 64'h00000988C2000000;
64'hFFFFFFFFFFFFECB8: romout <= 64'h2F80400000F0A318;
64'hFFFFFFFFFFFFECC0: romout <= 64'h0000627700000007;
64'hFFFFFFFFFFFFECC8: romout <= 64'h050420000FF37EF8;
64'hFFFFFFFFFFFFECD0: romout <= 64'h60016AA040180041;
64'hFFFFFFFFFFFFECD8: romout <= 64'h2B84018007AAC100;
64'hFFFFFFFFFFFFECE0: romout <= 64'h000182A040080061;
64'hFFFFFFFFFFFFECE8: romout <= 64'h058420001000C108;
64'hFFFFFFFFFFFFECF0: romout <= 64'h0003FCDFBE000000;
64'hFFFFFFFFFFFFECF8: romout <= 64'h2B84014001A14108;
64'hFFFFFFFFFFFFED00: romout <= 64'h000000284200003C;
64'hFFFFFFFFFFFFED08: romout <= 64'h1080200041637EF8;
64'hFFFFFFFFFFFFED10: romout <= 64'h680000504200007F;
64'hFFFFFFFFFFFFED18: romout <= 64'h208C400000028FFF;
64'hFFFFFFFFFFFFED20: romout <= 64'h0010601082200018;
64'hFFFFFFFFFFFFED28: romout <= 64'h0504200007F42008;
64'hFFFFFFFFFFFFED30: romout <= 64'h0000581082200003;
64'hFFFFFFFFFFFFED38: romout <= 64'h0188408000092310;
64'hFFFFFFFFFFFFED40: romout <= 64'h0000002883D00000;
64'hFFFFFFFFFFFFED48: romout <= 64'h2C84018000D37EF8;
64'hFFFFFFFFFFFFED50: romout <= 64'h0000018800000418;
64'hFFFFFFFFFFFFED58: romout <= 64'h2C84038009137EF8;
64'hFFFFFFFFFFFFED60: romout <= 64'h0000003FBC000008;
64'hFFFFFFFFFFFFED68: romout <= 64'h1080400041867E10;
64'hFFFFFFFFFFFFED70: romout <= 64'h000006C080100038;
64'hFFFFFFFFFFFFED78: romout <= 64'h188040004180A210;
64'hFFFFFFFFFFFFED80: romout <= 64'h0000211F84000000;
64'hFFFFFFFFFFFFED88: romout <= 64'h2C84034009037EF8;
64'hFFFFFFFFFFFFED90: romout <= 64'h0000003FBC000008;
64'hFFFFFFFFFFFFED98: romout <= 64'h1080400041667E10;
64'hFFFFFFFFFFFFEDA0: romout <= 64'h000006C0BFE00000;
64'hFFFFFFFFFFFFEDA8: romout <= 64'h188040004160E210;
64'hFFFFFFFFFFFFEDB0: romout <= 64'hC0024EF801FFFE8A;
64'hFFFFFFFFFFFFEDB8: romout <= 64'h03FBC000008B2100;
64'hFFFFFFFFFFFFEDC0: romout <= 64'h0010619F84000000;
64'hFFFFFFFFFFFFEDC8: romout <= 64'h2C0BFC0000042010;
64'hFFFFFFFFFFFFEDD0: romout <= 64'h0010603884000001;
64'hFFFFFFFFFFFFEDD8: romout <= 64'h2F801FFFD8A62010;
64'hFFFFFFFFFFFFEDE0: romout <= 64'h000022C840280092;
64'hFFFFFFFFFFFFEDE8: romout <= 64'h19F840000000FEF0;
64'hFFFFFFFFFFFFEDF0: romout <= 64'h4000790804000416;
64'hFFFFFFFFFFFFEDF8: romout <= 64'h02884000001B02FE;
64'hFFFFFFFFFFFFEE00: romout <= 64'hFFF0298804000416;
64'hFFFFFFFFFFFFEE08: romout <= 64'h2C840380094BE007;
64'hFFFFFFFFFFFFEE10: romout <= 64'h0000003FBC000008;
64'hFFFFFFFFFFFFEE18: romout <= 64'h1080400041867E10;
64'hFFFFFFFFFFFFEE20: romout <= 64'h001062F880000088;
64'hFFFFFFFFFFFFEE28: romout <= 64'h2F801FFFB0A62000;
64'hFFFFFFFFFFFFEE30: romout <= 64'hFFEA298800000416;
64'hFFFFFFFFFFFFEE38: romout <= 64'h03FBC000030BE007;
64'hFFFFFFFFFFFFEE40: romout <= 64'h8002667F4000001F;
64'hFFFFFFFFFFFFEE48: romout <= 64'h0C7FFFFFB42B2100;
64'hFFFFFFFFFFFFEE50: romout <= 64'h0010601002300009;
64'hFFFFFFFFFFFFEE58: romout <= 64'h2F8000001CA42008;
64'hFFFFFFFFFFFFEE60: romout <= 64'h001062C840600008;
64'hFFFFFFFFFFFFEE68: romout <= 64'h2F8800004C842010;
64'hFFFFFFFFFFFFEE70: romout <= 64'h0010603884000001;
64'hFFFFFFFFFFFFEE78: romout <= 64'h0C7FFFFFB4262010;
64'hFFFFFFFFFFFFEE80: romout <= 64'h0010601002300009;
64'hFFFFFFFFFFFFEE88: romout <= 64'h108C400000242008;
64'hFFFFFFFFFFFFEE90: romout <= 64'h00000988C4000000;
64'hFFFFFFFFFFFFEE98: romout <= 64'h028420000010A318;
64'hFFFFFFFFFFFFEEA0: romout <= 64'h000000A4FFDA0000;
64'hFFFFFFFFFFFFEEA8: romout <= 64'h2F84BFFFF4482428;
64'hFFFFFFFFFFFFEEB0: romout <= 64'hFFFFF8A200000020;
64'hFFFFFFFFFFFFEEB8: romout <= 64'h2F80000024A62317;
64'hFFFFFFFFFFFFEEC0: romout <= 64'h000026C04034000A;
64'hFFFFFFFFFFFFEEC8: romout <= 64'h0C7FFFFFB4204009;
64'hFFFFFFFFFFFFEED0: romout <= 64'h4000241002300009;
64'hFFFFFFFFFFFFEED8: romout <= 64'h0C7FFFFFB3204020;
64'hFFFFFFFFFFFFEEE0: romout <= 64'hFFEF058803D00000;
64'hFFFFFFFFFFFFEEE8: romout <= 64'h2774000001F31FFF;
64'hFFFFFFFFFFFFEEF0: romout <= 64'hFFEF44DFBE000030;
64'hFFFFFFFFFFFFEEF8: romout <= 64'h2774000001F31FFF;
64'hFFFFFFFFFFFFEF00: romout <= 64'h000080DFBE000030;
64'hFFFFFFFFFFFFEF08: romout <= 64'h27F400000070FEF0;
64'hFFFFFFFFFFFFEF10: romout <= 64'h000058A3FFDA0000;
64'hFFFFFFFFFFFFEF18: romout <= 64'h0284200000182308;
64'hFFFFFFFFFFFFEF20: romout <= 64'h00106248C2000016;
64'hFFFFFFFFFFFFEF28: romout <= 64'h0284200000142008;
64'hFFFFFFFFFFFFEF30: romout <= 64'h0000018802000418;
64'hFFFFFFFFFFFFEF38: romout <= 64'h2F8440002C682310;
64'hFFFFFFFFFFFFEF40: romout <= 64'h0010598800000418;
64'hFFFFFFFFFFFFEF48: romout <= 64'h0284200000142008;
64'hFFFFFFFFFFFFEF50: romout <= 64'h6800018802000416;
64'hFFFFFFFFFFFFEF58: romout <= 64'h208C400000228FFF;
64'hFFFFFFFFFFFFEF60: romout <= 64'h000006F844000146;
64'hFFFFFFFFFFFFEF68: romout <= 64'h188040004160E210;
64'hFFFFFFFFFFFFEF70: romout <= 64'h00005908C4000000;
64'hFFFFFFFFFFFFEF78: romout <= 64'h0104410000542308;
64'hFFFFFFFFFFFFEF80: romout <= 64'hFFEC2588C2000016;
64'hFFFFFFFFFFFFEF88: romout <= 64'h2774000000731FFF;
64'hFFFFFFFFFFFFEF90: romout <= 64'h000060DFBE000020;
64'hFFFFFFFFFFFFEF98: romout <= 64'h27F400000030DEF0;
64'hFFFFFFFFFFFFEFA0: romout <= 64'h0000001040200009;
64'hFFFFFFFFFFFFEFA8: romout <= 64'h028840000014A208;
64'hFFFFFFFFFFFFEFB0: romout <= 64'hFFED4AF840000088;
64'hFFFFFFFFFFFFEFB8: romout <= 64'h2F801FFFFAA31FFF;
64'hFFFFFFFFFFFFEFC0: romout <= 64'h0000627740000003;
64'hFFFFFFFFFFFFEFC8: romout <= 64'h03FBC00000837EF8;
64'hFFFFFFFFFFFFEFD0: romout <= 64'hFFEF959FBE000000;
64'hFFFFFFFFFFFFEFD8: romout <= 64'h11FBE00000031FFF;
64'hFFFFFFFFFFFFEFE0: romout <= 64'h0000402FBC000008;
64'hFFFFFFFFFFFFEFE8: romout <= 64'h19F820000000DEF0;
64'hFFFFFFFFFFFFEFF0: romout <= 64'h0000359FBE000008;
64'hFFFFFFFFFFFFEFF8: romout <= 64'h0C7FFFFFB5228400;
64'hFFFFFFFFFFFFF000: romout <= 64'hFFED48A10000000A;
64'hFFFFFFFFFFFFF008: romout <= 64'h11F8200000031FFF;
64'hFFFFFFFFFFFFF010: romout <= 64'h0000411FBE000008;
64'hFFFFFFFFFFFFF018: romout <= 64'h037BC00001037EF8;
64'hFFFFFFFFFFFFF020: romout <= 64'h0000019FBE000008;
64'hFFFFFFFFFFFFF028: romout <= 64'h0504200000F67E08;
64'hFFFFFFFFFFFFF030: romout <= 64'h4000E42042000030;
64'hFFFFFFFFFFFFF038: romout <= 64'h02042000007AC100;
64'hFFFFFFFFFFFFF040: romout <= 64'h000000C7FFFFFB52;
64'hFFFFFFFFFFFFF048: romout <= 64'h11FBE00000847E08;
64'hFFFFFFFFFFFFF050: romout <= 64'h000040DFBE000010;
64'hFFFFFFFFFFFFF058: romout <= 64'h27F400000010FEF0;
64'hFFFFFFFFFFFFF060: romout <= 64'hFFF0181842200004;
64'hFFFFFFFFFFFFF068: romout <= 64'h0184220000231FFF;
64'hFFFFFFFFFFFFF070: romout <= 64'h000004C7FFFFFC06;
64'hFFFFFFFFFFFFF078: romout <= 64'h0DFBE0000109DD00;
64'hFFFFFFFFFFFFF080: romout <= 64'h0000143FBC000018;
64'hFFFFFFFFFFFFF088: romout <= 64'h0A3000000079FD00;
64'hFFFFFFFFFFFFF090: romout <= 64'hFFF0541842400002;
64'hFFFFFFFFFFFFF098: romout <= 64'h2F80600000F31FFF;
64'hFFFFFFFFFFFFF0A0: romout <= 64'h0000627740000005;
64'hFFFFFFFFFFFFF0A8: romout <= 64'h0A10000003A37EF8;
64'hFFFFFFFFFFFFF0B0: romout <= 64'h400024C7FFFFFB52;
64'hFFFFFFFFFFFFF0B8: romout <= 64'h0C7FFFFFC2004200;
64'hFFFFFFFFFFFFF0C0: romout <= 64'h000080A300000007;
64'hFFFFFFFFFFFFF0C8: romout <= 64'h0C7FFFFFB5228400;
64'hFFFFFFFFFFFFF0D0: romout <= 64'hFFF0550082000000;
64'hFFFFFFFFFFFFF0D8: romout <= 64'h0288400000131FFF;
64'hFFFFFFFFFFFFF0E0: romout <= 64'hFFEFE6F807FFFF2F;
64'hFFFFFFFFFFFFF0E8: romout <= 64'h03FBC00003033FFF;
64'hFFFFFFFFFFFFF0F0: romout <= 64'h00002A7F000000FC;
64'hFFFFFFFFFFFFF0F8: romout <= 64'h0A80000001328800;
64'hFFFFFFFFFFFFF100: romout <= 64'h800000104430001C;
64'hFFFFFFFFFFFFF108: romout <= 64'h0194FE000000631F;
64'hFFFFFFFFFFFFF110: romout <= 64'h0000241908200001;
64'hFFFFFFFFFFFFF118: romout <= 64'h0194A20000104439;
64'hFFFFFFFFFFFFF120: romout <= 64'h0000001146500009;
64'hFFFFFFFFFFFFF128: romout <= 64'h2F811FFFF0F1C108;
64'hFFFFFFFFFFFFF130: romout <= 64'h0000001909800001;
64'hFFFFFFFFFFFFF138: romout <= 64'h0110C40000906532;
64'hFFFFFFFFFFFFF140: romout <= 64'h400024194B800001;
64'hFFFFFFFFFFFFF148: romout <= 64'h0100A20000904020;
64'hFFFFFFFFFFFFF150: romout <= 64'h0000C277000000FC;
64'hFFFFFFFFFFFFF158: romout <= 64'h03FBC00002037EF8;
64'hFFFFFFFFFFFFF160: romout <= 64'h00003E7F0000009C;
64'hFFFFFFFFFFFFF168: romout <= 64'h0504400000F2A000;
64'hFFFFFFFFFFFFF170: romout <= 64'h0000005884000030;
64'hFFFFFFFFFFFFF178: romout <= 64'h0190840000106217;
64'hFFFFFFFFFFFFF180: romout <= 64'h00002418CBC00000;
64'hFFFFFFFFFFFFF188: romout <= 64'h018C640000104429;
64'hFFFFFFFFFFFFF190: romout <= 64'h80000410C4300009;
64'hFFFFFFFFFFFFF198: romout <= 64'h2F811FFFECF06108;
64'hFFFFFFFFFFFFF1A0: romout <= 64'h8000241008100009;
64'hFFFFFFFFFFFFF1A8: romout <= 64'h2770000009C04018;
64'hFFFFFFFFFFFFF1B0: romout <= 64'h0000E0DFBE000020;
64'hFFFFFFFFFFFFF1B8: romout <= 64'h27F400007C40FEF0;
64'hFFFFFFFFFFFFF1C0: romout <= 64'hFFF0E81004B00009;
64'hFFFFFFFFFFFFF1C8: romout <= 64'h01004A0000931FFF;
64'hFFFFFFFFFFFFF1D0: romout <= 64'h000004C7FFFFFC56;
64'hFFFFFFFFFFFFF1D8: romout <= 64'h0A8000000072A400;
64'hFFFFFFFFFFFFF1E0: romout <= 64'h0000001A4E180000;
64'hFFFFFFFFFFFFF1E8: romout <= 64'h029CE0000040A738;
64'hFFFFFFFFFFFFF1F0: romout <= 64'hC0004050460000FF;
64'hFFFFFFFFFFFFF1F8: romout <= 64'h018424000016A758;
64'hFFFFFFFFFFFFF200: romout <= 64'h400026F811FFFF0F;
64'hFFFFFFFFFFFFF208: romout <= 64'h2F813FFFECF04010;
64'hFFFFFFFFFFFFF210: romout <= 64'hFFF1581014100009;
64'hFFFFFFFFFFFFF218: romout <= 64'h0A80000000331FFF;
64'hFFFFFFFFFFFFF220: romout <= 64'hC0004050460000FF;
64'hFFFFFFFFFFFFF228: romout <= 64'h018424000016A858;
64'hFFFFFFFFFFFFF230: romout <= 64'h000052F811FFFF8F;
64'hFFFFFFFFFFFFF238: romout <= 64'h277400007C460B00;
64'hFFFFFFFFFFFFF240: romout <= 64'hFFBFE0DFBE000038;
64'hFFFFFFFFFFFFF248: romout <= 64'h1800000041A2FBFF;
64'hFFFFFFFFFFFFF250: romout <= 64'h000090C7FFFFFBF9;
64'hFFFFFFFFFFFFF258: romout <= 64'h0C7FFFFFB5228400;
64'hFFFFFFFFFFFFF260: romout <= 64'h0FFFFCC7FFFFFA8A;
64'hFFFFFFFFFFFFF268: romout <= 64'h2C04018000DB0100;
64'hFFFFFFFFFFFFF270: romout <= 64'hFFFE28C7FFFFFB52;
64'hFFFFFFFFFFFFF278: romout <= 64'h18800000418BE007;
64'hFFFFFFFFFFFFF280: romout <= 64'hC00024C7FFFFFB42;
64'hFFFFFFFFFFFFF288: romout <= 64'h108C200000004100;
64'hFFFFFFFFFFFFF290: romout <= 64'hFFECF428C6000002;
64'hFFFFFFFFFFFFF298: romout <= 64'h2C84020002431FFF;
64'hFFFFFFFFFFFFF2A0: romout <= 64'h00000908C2000000;
64'hFFFFFFFFFFFFF2A8: romout <= 64'h0C7FFFFFB3D0A318;
64'hFFFFFFFFFFFFF2B0: romout <= 64'h000112C04130003A;
64'hFFFFFFFFFFFFF2B8: romout <= 64'h2C075500042B0106;
64'hFFFFFFFFFFFFF2C0: romout <= 64'h800132C04154004A;
64'hFFFFFFFFFFFFF2C8: romout <= 64'h2C04050003FB0109;
64'hFFFFFFFFFFFFF2D0: romout <= 64'hFFEEAAC040080043;
64'hFFFFFFFFFFFFF2D8: romout <= 64'h108C2000000BE007;
64'hFFFFFFFFFFFFF2E0: romout <= 64'hFFECF428C6000002;
64'hFFFFFFFFFFFFF2E8: romout <= 64'h2C87F64004C31FFF;
64'hFFFFFFFFFFFFF2F0: romout <= 64'h00000908C2000000;
64'hFFFFFFFFFFFFF2F8: romout <= 64'h0C7FFFFFB3D0A318;
64'hFFFFFFFFFFFFF300: romout <= 64'hFFEBD2C87F440053;
64'hFFFFFFFFFFFFF308: romout <= 64'h2F801FFFA2A31FFF;
64'hFFFFFFFFFFFFF310: romout <= 64'hFFEF94A1FFFFF320;
64'hFFFFFFFFFFFFF318: romout <= 64'h2F801FFF9AA31FFF;
64'hFFFFFFFFFFFFF320: romout <= 64'h70736944203D203F;
64'hFFFFFFFFFFFFF328: romout <= 64'h706C65682079616C;
64'hFFFFFFFFFFFFF330: romout <= 64'h203D20534C430A0D;
64'hFFFFFFFFFFFFF338: romout <= 64'h6373207261656C63;
64'hFFFFFFFFFFFFF340: romout <= 64'h203A0A0D6E656572;
64'hFFFFFFFFFFFFF348: romout <= 64'h6D2074696445203D;
64'hFFFFFFFFFFFFF350: romout <= 64'h79622079726F6D65;
64'hFFFFFFFFFFFFF358: romout <= 64'h3D204C0A0D736574;
64'hFFFFFFFFFFFFF360: romout <= 64'h31532064616F4C20;
64'hFFFFFFFFFFFFF368: romout <= 64'h0A0D656C69662039;
64'hFFFFFFFFFFFFF370: romout <= 64'h706D7544203D2044;
64'hFFFFFFFFFFFFF378: romout <= 64'h0D79726F6D656D20;
64'hFFFFFFFFFFFFF380: romout <= 64'h617473203D20420A;
64'hFFFFFFFFFFFFF388: romout <= 64'h20796E6974207472;
64'hFFFFFFFFFFFFF390: romout <= 64'h4A0A0D6369736162;
64'hFFFFFFFFFFFFF398: romout <= 64'h20706D754A203D20;
64'hFFFFFFFFFFFFF3A0: romout <= 64'h0D65646F63206F74;
64'hFFFFFFFFFFFFF3A8: romout <= 64'hFFFFFFFFFFFF000A;
64'hFFFFFFFFFFFFF3B0: romout <= 64'h0000003FBC000008;
64'hFFFFFFFFFFFFF3B8: romout <= 64'h108C200000067EF8;
64'hFFFFFFFFFFFFF3C0: romout <= 64'hFFECF428C6000002;
64'hFFFFFFFFFFFFF3C8: romout <= 64'h2C07FF0002031FFF;
64'hFFFFFFFFFFFFF3D0: romout <= 64'h00000038C6000002;
64'hFFFFFFFFFFFFF3D8: romout <= 64'h0DFBE00000847EF8;
64'hFFFFFFFFFFFFF3E0: romout <= 64'hFFF474C7FFFFFCEC;
64'hFFFFFFFFFFFFF3E8: romout <= 64'h0104050000931FFF;
64'hFFFFFFFFFFFFF3F0: romout <= 64'hFFF3B0A400000007;
64'hFFFFFFFFFFFFF3F8: romout <= 64'h0C7FFFFFD1D31FFF;
64'hFFFFFFFFFFFFF400: romout <= 64'h0000058142000000;
64'hFFFFFFFFFFFFF408: romout <= 64'h2F809FFFFAF0A528;
64'hFFFFFFFFFFFFF410: romout <= 64'hFFF3B2F801FFF1AA;
64'hFFFFFFFFFFFFF418: romout <= 64'h0C7FFFFFD1D31FFF;
64'hFFFFFFFFFFFFF420: romout <= 64'h0000001040300009;
64'hFFFFFFFFFFFFF428: romout <= 64'h2F801FFF12A343F8;
64'hFFFFFFFFFFFFF430: romout <= 64'hFFF474C7FFFFFCEC;
64'hFFFFFFFFFFFFF438: romout <= 64'h0104020000931FFF;
64'hFFFFFFFFFFFFF440: romout <= 64'hFFF0A8C7FFFFFBF9;
64'hFFFFFFFFFFFFF448: romout <= 64'h0C7FFFFFC2A31FFF;
64'hFFFFFFFFFFFFF450: romout <= 64'hFFF0A8C7FFFFFC2A;
64'hFFFFFFFFFFFFF458: romout <= 64'h0C7FFFFFC2A31FFF;
64'hFFFFFFFFFFFFF460: romout <= 64'hFFF0A8C7FFFFFC2A;
64'hFFFFFFFFFFFFF468: romout <= 64'h0C7FFFFFC2A31FFF;
64'hFFFFFFFFFFFFF470: romout <= 64'h000062F801FFEEAA;
64'hFFFFFFFFFFFFF478: romout <= 64'h27F4000000A0FEF0;
64'hFFFFFFFFFFFFF480: romout <= 64'h00003CA200000000;
64'hFFFFFFFFFFFFF488: romout <= 64'h108C200000029000;
64'hFFFFFFFFFFFFF490: romout <= 64'hFFECF428C6000002;
64'hFFFFFFFFFFFFF498: romout <= 64'h0C7FFFFFD3231FFF;
64'hFFFFFFFFFFFFF4A0: romout <= 64'h800002C0401BFFFF;
64'hFFFFFFFFFFFFF4A8: romout <= 64'h0504200000F06210;
64'hFFFFFFFFFFFFF4B0: romout <= 64'hFFFB3C1082200009;
64'hFFFFFFFFFFFFF4B8: romout <= 64'h01080100009BE027;
64'hFFFFFFFFFFFFF4C0: romout <= 64'h000062774000000A;
64'hFFFFFFFFFFFFF4C8: romout <= 64'h2A04054003037EF8;
64'hFFFFFFFFFFFFF4D0: romout <= 64'h0000C2B840100039;
64'hFFFFFFFFFFFFF4D8: romout <= 64'h0DFBE0000000E108;
64'hFFFFFFFFFFFFF4E0: romout <= 64'h60011AA040340041;
64'hFFFFFFFFFFFFF4E8: romout <= 64'h03842000041AE100;
64'hFFFFFFFFFFFFF4F0: romout <= 64'h000000284200000A;
64'hFFFFFFFFFFFFF4F8: romout <= 64'h2A04024006137EF8;
64'hFFFFFFFFFFFFF500: romout <= 64'h000186B840140066;
64'hFFFFFFFFFFFFF508: romout <= 64'h0284200000A0E108;
64'hFFFFFFFFFFFFF510: romout <= 64'hFFFFFCDFBE000000;
64'hFFFFFFFFFFFFF518: romout <= 64'h0DFBE000000287FF;
64'hFFFFFFFFFFFFF520: romout <= 64'hFFF782F80000008A;
64'hFFFFFFFFFFFFF528: romout <= 64'h2C84004000A31FFF;
64'hFFFFFFFFFFFFF530: romout <= 64'h500068C7FFFFFDE0;
64'hFFFFFFFFFFFFF538: romout <= 64'h2C87FF40053B01F4;
64'hFFFFFFFFFFFFF540: romout <= 64'h9000C0C7FFFFFDE0;
64'hFFFFFFFFFFFFF548: romout <= 64'h2987FE40039A01FF;
64'hFFFFFFFFFFFFF550: romout <= 64'hFFF7801040400009;
64'hFFFFFFFFFFFFF558: romout <= 64'h0C7FFFFFD3231FFF;
64'hFFFFFFFFFFFFF560: romout <= 64'hFFF7801040200009;
64'hFFFFFFFFFFFFF568: romout <= 64'h0C7FFFFFD3231FFF;
64'hFFFFFFFFFFFFF570: romout <= 64'h8000241884200000;
64'hFFFFFFFFFFFFF578: romout <= 64'h0108230000904208;
64'hFFFFFFFFFFFFF580: romout <= 64'h9000C6C13FA40030;
64'hFFFFFFFFFFFFF588: romout <= 64'h2C100B00032B0402;
64'hFFFFFFFFFFFFF590: romout <= 64'h5000D6C100A80033;
64'hFFFFFFFFFFFFF598: romout <= 64'h2C100B40037B04FE;
64'hFFFFFFFFFFFFF5A0: romout <= 64'h1000E6C100B40038;
64'hFFFFFFFFFFFFF5A8: romout <= 64'h2F801FFFC2AB0403;
64'hFFFFFFFFFFFFF5B0: romout <= 64'h00000450C60000FF;
64'hFFFFFFFFFFFFF5B8: romout <= 64'h0C7FFFFFDE00E318;
64'hFFFFFFFFFFFFF5C0: romout <= 64'h800000C7FFFFFD32;
64'hFFFFFFFFFFFFF5C8: romout <= 64'h0108220000906210;
64'hFFFFFFFFFFFFF5D0: romout <= 64'hFFF4C8C7FFFFFDE0;
64'hFFFFFFFFFFFFF5D8: romout <= 64'h0188420000031FFF;
64'hFFFFFFFFFFFFF5E0: romout <= 64'h0000001082200009;
64'hFFFFFFFFFFFFF5E8: romout <= 64'h0294A00000160510;
64'hFFFFFFFFFFFFF5F0: romout <= 64'hFFF782F807FFFE4F;
64'hFFFFFFFFFFFFF5F8: romout <= 64'h0C7FFFFFD3231FFF;
64'hFFFFFFFFFFFFF600: romout <= 64'h8000241884200000;
64'hFFFFFFFFFFFFF608: romout <= 64'h0C7FFFFFDE004208;
64'hFFFFFFFFFFFFF610: romout <= 64'h800000C7FFFFFD32;
64'hFFFFFFFFFFFFF618: romout <= 64'h0108220000906210;
64'hFFFFFFFFFFFFF620: romout <= 64'hFFF676F801FFF82A;
64'hFFFFFFFFFFFFF628: romout <= 64'h2F801FFFC8A31FFF;
64'hFFFFFFFFFFFFF630: romout <= 64'hFFF028C7FFFFFDA5;
64'hFFFFFFFFFFFFF638: romout <= 64'h0C7FFFFFDADBE007;
64'hFFFFFFFFFFFFF640: romout <= 64'hFFF6B6F801FFFB8A;
64'hFFFFFFFFFFFFF648: romout <= 64'h1980A00000031FFF;
64'hFFFFFFFFFFFFF650: romout <= 64'hFFF696F801FFDFAA;
64'hFFFFFFFFFFFFF658: romout <= 64'h1980A00000031FFF;
64'hFFFFFFFFFFFFF660: romout <= 64'hFFF676F801FFDF2A;
64'hFFFFFFFFFFFFF668: romout <= 64'h1980A00000031FFF;
64'hFFFFFFFFFFFFF670: romout <= 64'h000022F801FFDEAA;
64'hFFFFFFFFFFFFF678: romout <= 64'h19FBE0000000FEF0;
64'hFFFFFFFFFFFFF680: romout <= 64'hFFF4C8C7FFFFFDE0;
64'hFFFFFFFFFFFFF688: romout <= 64'h0104020000931FFF;
64'hFFFFFFFFFFFFF690: romout <= 64'h000022F8000004AA;
64'hFFFFFFFFFFFFF698: romout <= 64'h19FBE0000000FEF0;
64'hFFFFFFFFFFFFF6A0: romout <= 64'hFFF4C8C7FFFFFDE0;
64'hFFFFFFFFFFFFF6A8: romout <= 64'h0104020000931FFF;
64'hFFFFFFFFFFFFF6B0: romout <= 64'h000022F80000024A;
64'hFFFFFFFFFFFFF6B8: romout <= 64'h19FBE0000000FEF0;
64'hFFFFFFFFFFFFF6C0: romout <= 64'hFFF4C8C7FFFFFDE0;
64'hFFFFFFFFFFFFF6C8: romout <= 64'h0104020000931FFF;
64'hFFFFFFFFFFFFF6D0: romout <= 64'hFFF4C8C7FFFFFDE0;
64'hFFFFFFFFFFFFF6D8: romout <= 64'h0188420000031FFF;
64'hFFFFFFFFFFFFF6E0: romout <= 64'hFFF7801044200009;
64'hFFFFFFFFFFFFF6E8: romout <= 64'h0C7FFFFFD3231FFF;
64'hFFFFFFFFFFFFF6F0: romout <= 64'h8000241884200000;
64'hFFFFFFFFFFFFF6F8: romout <= 64'h0C7FFFFFDE004208;
64'hFFFFFFFFFFFFF700: romout <= 64'h800000C7FFFFFD32;
64'hFFFFFFFFFFFFF708: romout <= 64'h0108220000906210;
64'hFFFFFFFFFFFFF710: romout <= 64'hFFF4C8C7FFFFFDE0;
64'hFFFFFFFFFFFFF718: romout <= 64'h0188420000031FFF;
64'hFFFFFFFFFFFFF720: romout <= 64'hFFF7801082200009;
64'hFFFFFFFFFFFFF728: romout <= 64'h0C7FFFFFD3231FFF;
64'hFFFFFFFFFFFFF730: romout <= 64'h8000241884200000;
64'hFFFFFFFFFFFFF738: romout <= 64'h0C7FFFFFDE004208;
64'hFFFFFFFFFFFFF740: romout <= 64'h800000C7FFFFFD32;
64'hFFFFFFFFFFFFF748: romout <= 64'h0108220000906210;
64'hFFFFFFFFFFFFF750: romout <= 64'hFFF4C8C7FFFFFDE0;
64'hFFFFFFFFFFFFF758: romout <= 64'h0188420000031FFF;
64'hFFFFFFFFFFFFF760: romout <= 64'h0000281082200009;
64'hFFFFFFFFFFFFF768: romout <= 64'h0108050000904421;
64'hFFFFFFFFFFFFF770: romout <= 64'h0000211FBE000000;
64'hFFFFFFFFFFFFF778: romout <= 64'h0DFBE0000000BEF0;
64'hFFFFFFFFFFFFF780: romout <= 64'h0000003FBC000008;
64'hFFFFFFFFFFFFF788: romout <= 64'h0C7FFFFFA9E67EF8;
64'hFFFFFFFFFFFFF790: romout <= 64'hFFEA2AF841FF8D88;
64'hFFFFFFFFFFFFF798: romout <= 64'h2C07AB4000031FFF;
64'hFFFFFFFFFFFFF7A0: romout <= 64'hFFFD20C7FFFFFDEE;
64'hFFFFFFFFFFFFF7A8: romout <= 64'h11FBE000000BE107;
64'hFFFFFFFFFFFFF7B0: romout <= 64'h0000002FBC000008;
64'hFFFFFFFFFFFFF7B8: romout <= 64'h20003DC0A0137EF8;
64'hFFFFFFFFFFFFF7C0: romout <= 64'h0002A05042000001;
64'hFFFFFFFFFFFFF7C8: romout <= 64'h20003DC0A00BE100;
64'hFFFFFFFFFFFFF7D0: romout <= 64'h000000504200007F;
64'hFFFFFFFFFFFFF7D8: romout <= 64'h0CFFFFFFC9137EF8;
64'hFFFFFFFFFFFFF7E0: romout <= 64'h726F747061520A0D;
64'hFFFFFFFFFFFFF7E8: romout <= 64'h20796E6954203436;
64'hFFFFFFFFFFFFF7F0: romout <= 64'h3176204349534142;
64'hFFFFFFFFFFFFF7F8: romout <= 64'h202943280A0D302E;
64'hFFFFFFFFFFFFF800: romout <= 64'h6F52202032313032;
64'hFFFFFFFFFFFFF808: romout <= 64'h6E69462074726562;
64'hFFFFFFFFFFFFF810: romout <= 64'h0A0D000A0A0D6863;
64'hFFFFFFFFFFFFF818: romout <= 64'h616857000A0D4B4F;
64'hFFFFFFFFFFFFF820: romout <= 64'h726F53000A0D3F74;
64'hFFFFFFFFFFFFF828: romout <= 64'h6F43000A0D2E7972;
64'hFFFFFFFFFFFFF830: romout <= 64'h4C4620746361706D;
64'hFFFFFFFFFFFFF838: romout <= 64'h6461657220485341;
64'hFFFFFFFFFFFFF840: romout <= 64'h0A0D726F72726520;
64'hFFFFFFFFFFFFF848: romout <= 64'h207265626D754E00;
64'hFFFFFFFFFFFFF850: romout <= 64'h62206F6F74207369;
64'hFFFFFFFFFFFFF858: romout <= 64'h766944000A0D6769;
64'hFFFFFFFFFFFFF860: romout <= 64'h7962206E6F697369;
64'hFFFFFFFFFFFFF868: romout <= 64'h000A0D6F72657A20;
64'hFFFFFFFFFFFFF870: romout <= 64'h7620666F2074754F;
64'hFFFFFFFFFFFFF878: romout <= 64'h20656C6261697261;
64'hFFFFFFFFFFFFF880: romout <= 64'h000A0D6563617073;
64'hFFFFFFFFFFFFF888: romout <= 64'h6620736574796220;
64'hFFFFFFFFFFFFF890: romout <= 64'h0A0D000A0D656572;
64'hFFFFFFFFFFFFF898: romout <= 64'h000A0D7964616552;
64'hFFFFFFFFFFFFF8A0: romout <= 64'h6E69746365707845;
64'hFFFFFFFFFFFFF8A8: romout <= 64'h6D6D6F6320612067;
64'hFFFFFFFFFFFFF8B0: romout <= 64'h656E694C000A0D61;
64'hFFFFFFFFFFFFF8B8: romout <= 64'h207265626D756E20;
64'hFFFFFFFFFFFFF8C0: romout <= 64'h0D676962206F6F74;
64'hFFFFFFFFFFFFF8C8: romout <= 64'h746365707845000A;
64'hFFFFFFFFFFFFF8D0: romout <= 64'h6176206120676E69;
64'hFFFFFFFFFFFFF8D8: romout <= 64'h0A0D656C62616972;
64'hFFFFFFFFFFFFF8E0: romout <= 64'h64616220444E5200;
64'hFFFFFFFFFFFFF8E8: romout <= 64'h74656D6172617020;
64'hFFFFFFFFFFFFF8F0: romout <= 64'h535953000A0D7265;
64'hFFFFFFFFFFFFF8F8: romout <= 64'h6464612064616220;
64'hFFFFFFFFFFFFF900: romout <= 64'h49000A0D73736572;
64'hFFFFFFFFFFFFF908: romout <= 64'h707865205455504E;
64'hFFFFFFFFFFFFF910: romout <= 64'h6120676E69746365;
64'hFFFFFFFFFFFFF918: romout <= 64'h6C62616972617620;
64'hFFFFFFFFFFFFF920: romout <= 64'h5458454E000A0D65;
64'hFFFFFFFFFFFFF928: romout <= 64'h74756F6874697720;
64'hFFFFFFFFFFFFF930: romout <= 64'h4E000A0D524F4620;
64'hFFFFFFFFFFFFF938: romout <= 64'h6570786520545845;
64'hFFFFFFFFFFFFF940: romout <= 64'h206120676E697463;
64'hFFFFFFFFFFFFF948: romout <= 64'h2064656E69666564;
64'hFFFFFFFFFFFFF950: romout <= 64'h656C626169726176;
64'hFFFFFFFFFFFFF958: romout <= 64'h2F4F544F47000A0D;
64'hFFFFFFFFFFFFF960: romout <= 64'h6162204255534F47;
64'hFFFFFFFFFFFFF968: romout <= 64'h6E20656E696C2064;
64'hFFFFFFFFFFFFF970: romout <= 64'h000A0D7265626D75;
64'hFFFFFFFFFFFFF978: romout <= 64'h77204E5255544552;
64'hFFFFFFFFFFFFF980: romout <= 64'h472074756F687469;
64'hFFFFFFFFFFFFF988: romout <= 64'h50000A0D4255534F;
64'hFFFFFFFFFFFFF990: romout <= 64'h69206D6172676F72;
64'hFFFFFFFFFFFFF998: romout <= 64'h6962206F6F742073;
64'hFFFFFFFFFFFFF9A0: romout <= 64'h72747845000A0D67;
64'hFFFFFFFFFFFFF9A8: romout <= 64'h6361726168632061;
64'hFFFFFFFFFFFFF9B0: romout <= 64'h206E6F2073726574;
64'hFFFFFFFFFFFFF9B8: romout <= 64'h6E676920656E696C;
64'hFFFFFFFFFFFFF9C0: romout <= 64'h0D000A0D6465726F;
64'hFFFFFFFFFFFFF9C8: romout <= 64'h0D000A0A0D00520A;
64'hFFFFFFFFFFFFF9D0: romout <= 64'h0048000A0D004F0A;
64'hFFFFFFFFFFFFF9D8: romout <= 64'h000A0D0057000A0D;
64'hFFFFFFFFFFFFF9E0: romout <= 64'hFFFFFF000A0D0053;
64'hFFFFFFFFFFFFF9E8: romout <= 64'hFFFFFFFFFFFFFFFF;
64'hFFFFFFFFFFFFF9F0: romout <= 64'hAAAB541000800009;
64'hFFFFFFFFFFFFF9F8: romout <= 64'h05802AA5555F5554;
64'hFFFFFFFFFFFFFA00: romout <= 64'h0000019A02000000;
64'hFFFFFFFFFFFFFA08: romout <= 64'h0104430000646810;
64'hFFFFFFFFFFFFFA10: romout <= 64'h000022F8C00000A9;
64'hFFFFFFFFFFFFFA18: romout <= 64'h042060000000A840;
64'hFFFFFFFFFFFFFA20: romout <= 64'h800026F8C1FFFF00;
64'hFFFFFFFFFFFFFA28: romout <= 64'h0100080000904802;
64'hFFFFFFFFFFFFFA30: romout <= 64'hA955551A04000000;
64'hFFFFFFFFFFFFFA38: romout <= 64'h2F8C00001091021A;
64'hFFFFFFFFFFFFFA40: romout <= 64'h0000002210000008;
64'hFFFFFFFFFFFFFA48: romout <= 64'h2F8C1FFFF801081C;
64'hFFFFFFFFFFFFFA50: romout <= 64'h000026FA14000329;
64'hFFFFFFFFFFFFFA58: romout <= 64'h3AAAAD5552A04002;
64'hFFFFFFFFFFFFFA60: romout <= 64'h000000580355AAAA;
64'hFFFFFFFFFFFFFA68: romout <= 64'h11A0400000066808;
64'hFFFFFFFFFFFFFA70: romout <= 64'h0003241044300006;
64'hFFFFFFFFFFFFFA78: romout <= 64'h02210000008BE300;
64'hFFFFFFFFFFFFFA80: romout <= 64'hFFFC804207000000;
64'hFFFFFFFFFFFFFA88: romout <= 64'h01200B00009BE307;
64'hFFFFFFFFFFFFFA90: romout <= 64'h0000001000800009;
64'hFFFFFFFFFFFFFA98: romout <= 64'h0408755AAAA46810;
64'hFFFFFFFFFFFFFAA0: romout <= 64'h000022F8C00000A9;
64'hFFFFFFFFFFFFFAA8: romout <= 64'h0420700000008840;
64'hFFFFFFFFFFFFFAB0: romout <= 64'h000222F8C1FFFF20;
64'hFFFFFFFFFFFFFAB8: romout <= 64'h01216800014BE858;
64'hFFFFFFFFFFFFFAC0: romout <= 64'h000052FA14000048;
64'hFFFFFFFFFFFFFAC8: romout <= 64'h1981000040004852;
64'hFFFFFFFFFFFFFAD0: romout <= 64'h000020DFBE000000;
64'hFFFFFFFFFFFFFAD8: romout <= 64'h19F820000000FEF0;
64'hFFFFFFFFFFFFFAE0: romout <= 64'h8000060803DC0FF0;
64'hFFFFFFFFFFFFFAE8: romout <= 64'h2C840180002B01B4;
64'hFFFFFFFFFFFFFAF0: romout <= 64'h0002A8C7FFFFFAB9;
64'hFFFFFFFFFFFFFAF8: romout <= 64'h2C84014000FBE000;
64'hFFFFFFFFFFFFFB00: romout <= 64'h000000C7FFFFFA6D;
64'hFFFFFFFFFFFFFB08: romout <= 64'h02FBC00000847E08;
64'hFFFFFFFFFFFFFB10: romout <= 64'h0000800000000020;
64'hFFFFFFFFFFFFFB18: romout <= 64'h19803FF000000000;
64'hFFFFFFFFFFFFFB20: romout <= 64'h0000D19805FF0008;
64'hFFFFFFFFFFFFFB28: romout <= 64'h2F84000002902008;
64'hFFFFFFFFFFFFFB30: romout <= 64'h0010A00802000228;
64'hFFFFFFFFFFFFFB38: romout <= 64'h008800005A902010;
64'hFFFFFFFFFFFFFB40: romout <= 64'h40000C1884680001;
64'hFFFFFFFFFFFFFB48: romout <= 64'h1184400000004110;
64'hFFFFFFFFFFFFFB50: romout <= 64'h0014A45084000000;
64'hFFFFFFFFFFFFFB58: romout <= 64'h1184400000802200;
64'hFFFFFFFFFFFFFB60: romout <= 64'h0016A45084000000;
64'hFFFFFFFFFFFFFB68: romout <= 64'h0080000003402200;
64'hFFFFFFFFFFFFFB70: romout <= 64'hFC00000800000035;
64'hFFFFFFFFFFFFFB78: romout <= 64'h11805FF00084600F;
64'hFFFFFFFFFFFFFB80: romout <= 64'h0000000000000020;
64'hFFFFFFFFFFFFFB88: romout <= 64'h37800000000DE000;
64'hFFFFFFFFFFFFFFB0: romout <= 64'h000000CFFFFFFEC6;
64'hFFFFFFFFFFFFFFB8: romout <= 64'h37800000000DE000;
64'hFFFFFFFFFFFFFFC0: romout <= 64'h000000CFFFFFFEC6;
64'hFFFFFFFFFFFFFFC8: romout <= 64'h37800000000DE000;
64'hFFFFFFFFFFFFFFD0: romout <= 64'h000000CFFFFFFEB5;
64'hFFFFFFFFFFFFFFD8: romout <= 64'h37800000000DE000;
64'hFFFFFFFFFFFFFFE0: romout <= 64'h000000CFFFFFFEC5;
64'hFFFFFFFFFFFFFFE8: romout <= 64'h37800000000DE000;
64'hFFFFFFFFFFFFFFF0: romout <= 64'h000000CFFFFFFA00;
64'hFFFFFFFFFFFFFFF8: romout <= 64'h37800000000DE000;
default: romout <= 64'd0;
endcase
assign sys_dbi = br_dato|keybdout|stk_dato|scr_dato| {4{tc_dato}} | {4{pic_dato}} | {8{config_reco}} | ramo | {8{sm_dato}};
 
 
Raptor64sc u1
(
.rst_i(rst),
.clk_i(clk),
.nmi_i(cpu_nmi),
.irq_i(cpu_irq),
.irq_no(vecno),
.bte_o(),
.cti_o(cpu_cti),
.iocyc_o(sys_iocyc),
.cyc_o(sys_cyc),
.stb_o(sys_stb),
.ack_i(sys_ack),
.err_i(sys_err),
.we_o(sys_we),
.sel_o(sys_sel),
.adr_o(sys_adr),
.dat_i(sys_dbi),
.dat_o(sys_dbo),
 
.sys_adv(1'b0),
.sys_adr(59'd0)
);
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.