OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /raytrac/branches/fp
    from Rev 138 to Rev 139
    ↔ Reverse comparison
  •

Rev 138 → Rev 139

/sm.vhd
23,27 → 23,98
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
 
 
entity sm is
generic (
width :integer:= 32;
widthadmemblock : integer := 9
);
port (
clk,rst: in std_logic;
add_rd,add_wr:out std_logic_vector(widthadmemblock-1 downto 0);
iempty,ifull:in std_logic_vector;
rd,wr:out std_logic;
irq:out std_logic
clk,rst:in std_logic;
add0,add1:out std_logic_vector (8 downto 0);
iq:in std_logic_vector(31 downto 0);
read_memory,ird_ack:out std_logic;
ucsa:out std_logic(3 downto 0);
iempty , rfull, opq_empty : in std_logic;
);
end entity;
architecture sm_arch of arch is
 
architecture sm_arch of sm is
 
type macState is (IDLE,EXECUTING,FLUSHING);
signal state : macState;
constant rstMasterValue : std_logic:='0';
signal sadd0,sadd1:std_logic_vector (8 downto 0);
signal schunk0o,schunk0f,schunk1o,schunk1f: std_logic_vector (3 downto 0);
signal sadd0_now,sadd0_next,sadd0_reg:std_logic_vector(8 downto 0);
signal sadd1_now,sadd1_next,sadd1_reg:std_logic_vector(8 downto 0);
signal sadd0_adder_bit,sadd1_adder_bit,sena:std_logic;
begin
schunk0o(3 downto 0) <= iq(19 downto 16);
schunk0f(3 downto 0) <= iq(15 downto 12);
schunk1o(3 downto 0) <= iq(11 downto 8);
schunk1f(3 downto 0) <= iq(7 downto 4);
ucsa <= iq(3 downto 0);
sadd0_next <= sadd0_now+sadd0_adder_bit;
sadd1_next <= sadd1_now+sadd1_adder_bit;
sm_comb:
process (state)
begin
case state is
when IDLE =>
sadd0_now <= schunk0o(3 downto 0)&x"0";
sadd1_now <= schunk1o(3 downto 0)&x"0";
when others =>
sadd0_now <= sadd0_next;
sadd1_now <= sadd1_next;
end case;
end process;
 
 
sm_proc:
process (clk,rst)
begin
if rst=rstMasterValue then
state <= IDLE;
ird_ack <= '0';
elsif clk='1' and clk'event and sena='1' then
case state is
when IDLE =>
if rfull='0' and iempty='0' then
state <= EXECUTING;
read_memory <= '1';
end if;
when EXCUTING =>
if rfull='0' then
if sadd1_now=schunk1f&"11111" then
if sadd0_now=schunk0f&"11111" then
state <= FLUSHING;
end if;
end if;
end if;
when FLUSHING =>
if opq_empty='1' then
end if;
end case;
end if;
end process;
 
 
end architecture;
/fadd32.vhd
29,11 → 29,14
use lpm.all;
--! Esta entidad recibe dos n&uacutemeros en formato punto flotante IEEE 754, de precision simple y devuelve las mantissas signadas y corridas, y el exponente correspondiente al resultado antes de normalizarlo al formato float.
--!\nLas 2 mantissas y el exponente entran despues a la entidad add2 que suma las mantissas y entrega el resultado en formato IEEE 754.
entity fadd32 is
entity fadd32 is
generic (
propagation_chain : string := "ON"
);
port (
clk,dpc,ena : in std_logic;
clk,dpc,prop_in : in std_logic;
a32,b32 : in std_logic_vector (31 downto 0);
c32 : out std_logic_vector(31 downto 0)
c32,prop_out : out std_logic_vector(31 downto 0)
);
end fadd32;
architecture fadd32_arch of fadd32 is
67,12 → 70,25
signal s4sresult,s5result,s6result : std_logic_vector(25 downto 0); -- Signed mantissa result
signal s1ph,s6ph : std_logic_vector(26 downto 0);
signal s0a,s0b : std_logic_vector(31 downto 0); -- Float 32 bit
signal sxprop : std_logic_vector(7 downto 0);
begin
 
process (clk,ena)
propagation:
if propagation_chain="ON" generate
prop_out <= sxprop(7);
process (clk)
begin
if clk'event and clk='1' then
for i in 7 downto 1 loop
sxprop(i) <= sxprop(i-1);
end loop;
sxprop(0) <= prop_in;
end if;
end process;
end generate propagation ;
process (clk)
begin
if clk'event and clk='1' and ena='1' then
if clk'event and clk='1' then
--!Registro de entrada
s0a <= a32;
/fsqrt32.vhd
26,11 → 26,14
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sqrt32 is
generic (
propagation_chain : string := "ON"
);
port (
clk,ena : in std_logic;
clk,prop_in : in std_logic;
rd32 : in std_logic_vector(31 downto 0);
sq32 : out std_logic_vector(31 downto 0)
sq32,prop_out : out std_logic_vector(31 downto 0)
);
end sqrt32;
architecture sqrt32_arch of sqrt32 is
63,13 → 66,22
signal s0sgn : std_logic;
signal s0uexp,s0e129 : std_logic_vector(7 downto 0);
signal s0q : std_logic_vector(17 downto 0);
signal sxprop : std_logic;
begin
propagation:
if propagation_chain="ON" generate
prop_out <= sxprop;
process (clk)
begin
if clk'event and clk='1' then
sxprop <= prop_in;
end if;
end process;
end generate propagation ;
--! SNAN?
process (clk,ena)
process (clk)
begin
if clk'event and clk='1' and ena='1' then
if clk'event and clk='1' then
--!Carga de Operando.
s0sgn <= rd32(31);
/dpc.vhd
100,7 → 100,7
process (clk,ena)
begin
if clk'event and clk='1' and ena='1' then
for i 05 downto 0 loop
for i in 05 downto 0 loop
sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
end loop;
end if;
156,7 → 156,7
--! La entrada al inversor SIEMPRE viene con la salida de la raiz cuadrada
inv32blki <= sqr32blko;
 
--! La entrada de la ra�z cuadrada SIEMPRE viene con la salida del sumador 1.
sqr32blki <= sadd32blk(a1);
/fmul32.vhd
26,10 → 26,13
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fmul32 is
generic (
propagation_chain : string := "ON"
);
port (
clk,ena : in std_logic;
a32,b32 : in std_logic_vector(31 downto 0);
p32 : out std_logic_vector(31 downto 0)
clk,prop_in : in std_logic;
a32,b32 : in std_logic_vector(31 downto 0);
p32,prop_out : out std_logic_vector(31 downto 0)
);
end fmul32;
54,9 → 57,7
end component;
 
--Stage 0 signals
signal s0sga,s0sgb,s0zrs,s1sgr,s2sgr:std_logic;
signal s0exa,s0exb,s1exp,s2exp:std_logic_vector(7 downto 0);
signal s0exp : std_logic_vector(7 downto 0);
67,13 → 68,26
signal s1ac,s1umu:std_logic_vector(35 downto 0);
signal s2umu:std_logic_vector(24 downto 0);
signal sxprop : std_logic_vector(2 downto 0);
begin
propagation:
if propagation_chain="ON" generate
prop_out <= sxprop(2);
process (clk)
begin
if clk'event and clk='1' then
for i in 2 downto 1 loop
sxprop(i) <= sxprop(i-1);
end loop;
sxprop(0) <= prop_in;
end if;
end process;
end generate propagation ;
begin
 
process(clk,ena)
process(clk)
begin
if clk'event and clk='1' and ena='1' then
if clk'event and clk='1' then
--! Registro de entrada
s0sga <= a32(31);
s0sgb <= b32(31);
/finvr32.vhd
28,9 → 28,9
entity invr32 is
port (
clk,ena : in std_logic;
clk,prop_in : in std_logic;
dvd32: in std_logic_vector(31 downto 0);
qout32: out std_logic_vector(31 downto 0)
qout32,prop_out: out std_logic_vector(31 downto 0)
);
end invr32;
architecture invr32_arch of invr32 is
63,7 → 63,7
signal s0sgn : std_logic;
signal s0uexp,s0e129 : std_logic_vector(7 downto 0);
signal s0q : std_logic_vector(17 downto 0);
signal sxprop : std_logic;
begin
altsyncram_component : altsyncram
89,10 → 89,20
address_a => dvd32(22 downto 13),
q_a => s0q
);
propagation:
if propagation_chain="ON" generate
prop_out <= sxprop;
process (clk)
begin
if clk'event and clk='1' then
sxprop <= prop_in;
end if;
end process;
end generate propagation ;
--! SNAN?
process (clk,ena)
process (clk)
begin
if clk'event and clk='1' and ena='1' then
if clk'event and clk='1' then
--!Carga de Operando.
s0sgn <= dvd32(31);
s0uexp <= dvd32(30 downto 23);
/memblock.vhd
1,4 → 1,4
--! @file memblock.vhd
--! @file memblock.vhd
--! @brief Bloque de memoria.
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.