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    /raytrac/branches/fp
    from Rev 146 to Rev 147
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Rev 146 → Rev 147

/sm.vhd
37,19 → 37,9
--! Señales normales de secuencia.
clk,rst: in std_logic;
--! ENTRADAS DE CONTROL DE SINCRONIZACION.
--! Señales de sincronización de recursos.
--! Las siguientes entradas tienen relevancia y son sensibles en los estados EXECUTE_INSTRUCTION y VERMEER_EXECUTE.
--! ENTRADAS
--! Instruction Q, instruction.
--! Vector con las instrucción codficada
instrQq:in std_logic_vector(width-1 downto 0);
--! Señal de cola vacia.
instrQ_empty:in std_logic;
56,6 → 46,7
adda,addb:out std_logic_vector (widthadmemblock-1 downto 0);
sync_chain_0,instrRdAckd:out std_logic;
full_r: in std_logic; --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.
/im.vhd
0,0 → 1,107
--! @file im.vhd
--! @brief Maquina de Interrupciones. Circuito que detecta eventos que generan interrupciones para que el usuario externo del RayTrac detecte eventos como el final de una instrucción.
--! @author Julián Andrés Guarín Reyes
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- sm.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- raytrac is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
 
--!
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity im is
generic (
num_events : integer :=4;
cycles_to_wait : integer := 1023
);
port (
clk,rst: in std_logic;
rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
rfull_int: out std_logic_vector(num_events-1downto 0) --! full results queue related interruptions
);
end entity;
 
architecture im_arch of im is
 
type macState is (WAITING_FOR_AN_EVENT,FIRING_INTERRUPTIONS,SUSPEND);
signal state : macState;
constant rstMasterValue : std_logic:='0';
signal s_event_polling_chain : std_logic_vector(num_events-1 downto 0);
signal s_eoi_events : std_logic_vector(num_events-1 downto 0);
begin
 
 
sm_proc:
process (clk,rst,s_event_polling_chain,rfull_events,eoi_events)
variable tempo : integer range 0 to cycles_to_wait:=cycles_to_wait;
begin
if rst=rstMasterValue then
tempo := cycles_to_wait;
state <= WAITING_FOR_AN_EVENT;
s_event_polling_chain <= (others => '0');
s_eoi_events <= (others => '0');
rfull_int <= (others => '0');
eoi_int <= (others => '0');
elsif clk'event and clk='1' then
for i in num_events-1 downto 0 loop
if s_eoi_events(i)='0' then --! Hooking events
s_eoi_events(i) <= eoi_events(i);
else --! Event Hooked
s_eoi_events(i) <= not(s_event_polling_chain(i));
end if;
rfull_int(i) <= s_event_polling_chain(i) and rfull_events(i);
eoi_int(i) <= s_event_polling_chain(i) and s_eoi_events(i);
end loop;
case state is
when WAITING_FOR_AN_EVENT =>
for i in num_events-1 downto 0 loop
if rfull_events(i)='1' then
state <= FIRING_INTERRUPTIONS;
s_event_polling_chain(0) <= '1';
end if;
end loop;
when FIRING_INTERRUPTIONS =>
if s_event_polling_chain(num_events-1)='1' then
state <= SUSPEND;
tempo := cycles_to_wait;
end if;
for i in num_events-1 downto 1 loop
s_event_polling_chain(i) <= s_event_polling_chain(i-1);
end loop;
s_event_polling_chain(0) <= '0';
when SUSPEND =>
if tempo=0 then
state <= WAITING_FOR_AN_EVENT;
else
tempo:=tempo-1;
end if;
when others => null;
end case;
end if;
end process;
end architecture;
 
/dpc.vhd
38,6 → 38,8
fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
eoi_int : in std_logic; --! Sennal de interrupción de final de instrucción.
eoi_demuxed_int : out std_logic_vector (3 downto 0); --! Señal de interrupción de final de instrucción pero esta vez va asociada a la instruccón UCA.
sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalizaci&oacute;n.
fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
49,7 → 51,7
fifo32x23_r : out std_logic;
res567f,res13f : in std_logic; --! Entradas de la se&ntilde;al de full de las colas de resultados.
res2f,res0f : in std_logic;
resf : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operaci&oacute;n est&aacute; en curso.
resf : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operaci&oacute;n que est&aacute; en curso.
resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 8 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
);
end dpc;
225,14 → 227,18
fullQ:process(res0f,res13f,res2f,res567f,unary,crossprod,addsub)
begin
if unary='0' then
if crossprod='1' or addsub='1' then
if crossprod='1' or addsub='1' then
eoi_demuxed_int <= "00"&eoi_int&'0';
resf <= res13f;
else
eoi_demuxed_int <= '0'&eoi_int&"00";
resf <= res2f;
end if;
elsif crossprod='1' or addsub='1' then
eoi_demuxed_int <= eoi_int&"000";
resf <= res567f;
else
eoi_demuxed_int <= "000"&eoi_int;
resf <= res0f;
end if;
end process;
/memblock.vhd
36,15 → 36,14
);
port (
clk,ena,dpfifo_flush,normfifo_flush,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
dpfifo_empty, normfifo_empty, dpfifo_full, normfifo_full : out std_logic;
instrfifo_flush,instrfifo_rd,instrfifo_wr,resultfifo_flush,resultfifo_wr: in std_logic;
instrfifo_empty,instrfifo_full: out std_logic;
clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
instrfifo_rd,instrfifo_wr,resultfifo_wr: in std_logic;
instrfifo_empty: out std_logic;
ext_rd,ext_wr: in std_logic;
ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
ext_d: in std_logic_vector(width-1 downto 0);
--!sresultfifo_full,resultfifo_empty : out std_logic_vector(external_readable_blocks-1 downto 0);
resultfifo_full,resultfifo_empty : out std_logic_vector(external_readable_blocks-1 downto 0);
int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);
int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
62,6 → 61,7
type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
type vectorblock08 is array (07 downto 0) of std_logic_vector(width-1 downto 0);
type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
constant rstMasterValue : std_logic := '0';
component scfifo
generic (
92,6 → 92,7
);
end component;
component altsyncram
generic (
address_aclr_b : string;
142,49 → 143,176
 
--! Cola interna de producto punto, ubicada entre el pipe line aritm&eacute;co.
q0q1 : scfifo --! Debe ir registrada la salida.
generic map ("ON",8,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",16,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
generic map (
add_ram_output_register => "OFF",
allow_wrcycle_when_full => "OFF",
intended_device_family => "CycloneIII",
lpm_hint => "RAM_BLOCK_TYPE=M9K",
almost_full_value => 8,
lpm_numwords => 8,
lpm_showahead => "ON",
lpm_type => "SCIFIFO",
lpm_width => 64,
lpm_widthu => 3,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
rdreq => dpfifo_rd,
aclr => '0',
empty => open,
clock => clk,
q => dpfifo_q,
wrreq => dpfifo_wr,
data => dpfifo_d
);
--! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute
qxqyqz : scfifo
generic map ("ON",23,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",32,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
generic map (
add_ram_output_register => "OFF",
allow_wrcycle_when_full => "OFF",
intended_device_family => "Cyclone III",
lpm_hint => "RAM_BLOCK_TYPE=M9K",
almost_full_value => 32,
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_type => "SCFIFO",
lpm_width => 96,
lpm_widthu => 5,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
rdreq => normfifo_rd,
aclr => '0',
empty => open,
clock => clk,
q => normfifo_q,
wrreq => normfifo_wr,
data => normfifo_d,
almost_full => open,
full => open
);
--! Cola de instrucciones
qi : scfifo
generic map ("ON",31,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",32,"OFF","SCIFIFO",32,5,"ON","OFF","ON")
port map (instrfifo_rd,instrfifo_flush,instrfifo_empty,clk,instrfifo_q,instrfifo_wr,instrfifo_d,instrfifo_full);
generic map (
add_ram_output_register => "OFF",
allow_wrcycle_when_full => "OFF",
intended_device_family => "Cyclone III",
lpm_hint => "RAM_BLOCK_TYPE=M9K",
almost_full_value => 32,
lpm_numwords => 32,
lpm_showahead => "OFF",
lpm_type => "SCIFIFO",
lpm_width => 32,
lpm_widthu => 5,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
rdreq => instrfifo_rd,
aclr => '0',
empty => instrfifo_empty,
clock => clk,
q => instrfifo_q,
wrreq => instrfifo_wr,
data => instrfifo_d,
almost_full => open
);
--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de c&oacute;digo, no influye en la sintesis del circuito.
sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
--! Instanciaci&oacute;n de la cola de resultados de salida.
operands_blocks:
for i in 11 downto 0 generate
int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
operandsblock : altsyncram
generic map (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthadmemblock,
numwords_b => 2**widthadmemblock,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
rdcontrol_reg_b => "CLOCK0",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => widthadmemblock,
widthad_b => widthadmemblock,
width_a => width,
width_b => width,
width_byteena_a => 1
)
port map (
wren_a => s0ext_wr_add_one_hot(i),
clock0 => clk,
address_a => s0ext_wr_add(widthadmemblock-1 downto 0),
address_b => sint_rd_add((i/3) mod 2),
rden_b => '1',
q_b => s1int_q(i),
data_a => s0ext_d
);
end generate operands_blocks;
--! Instanciaci&oacute;n de la cola de resultados.
results_blocks:
for i in 7 downto 0 generate
sint_d(i) <= int_d((i+1)*width-1 downto i*width);
resultsfifo : scfifo
generic map ("ON",511,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",512,"OFF","SCIFIFO",32,9,"ON","OFF","ON")
port map (s0ext_rd_ack(i),resultfifo_flush,resultfifo_empty(i),clk,s0ext_q(i),resultfifo_wr,sint_d(i),open,sresultfifo_full(i));
generic map (
add_ram_output_register => "OFF",
almost_full_value => 480,
allow_wrcycle_when_full => "OFF",
intended_device_family => "Cyclone III",
lpm_hint => "RAM_BLOCK_TYPE=M9K",
lpm_numwords => 512,
lpm_showahead => "ON",
lpm_type => "SCIFIFO",
lpm_width => 32,
lpm_widthu => 9,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map (
rdreq => s0ext_rd_ack(i),
aclr => '0',
empty => resultfifo_empty(i),
clock => clk,
q => s0ext_q(i),
wrreq => resultfifo_wr,
data => sint_d(i),
almost_full => resultfifo_full(i),
full => open
);
end generate results_blocks;
--! Instanciaci&oacute;n de la cola de resultados de salida.
operands_blocks:
for i in 11 downto 0 generate
int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
operandsblock : altsyncram
generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
port map (s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0),sint_rd_add((i/3) mod 2),'1',s1int_q(i),s0ext_d);
end generate operands_blocks;
--! Escritura en registros de operandos de entrada.
operands_block_proc: process (clk,ena)
operands_block_proc: process (clk,rst)
begin
if clk'event and clk='1' and ena='1' then
--! Registro de entrada
s0ext_wr_add <= ext_wr_add;
s0ext_wr <= ext_wr;
s0ext_d <= ext_d;
if rst=rstMasterValue then
s0ext_wr_add <= (others => '0');
s0ext_wr <= '0';
s0ext_d <= (others => '0');
elsif clk'event and clk='1' then
--! Registro de entrada
s0ext_wr_add <= ext_wr_add;
s0ext_wr <= ext_wr;
s0ext_d <= ext_d;
end if;
end process;
213,9 → 341,12
end process;
--! Decodificaci&oacute;n para seleccionar que cola de resultados se conectar&acute; a la salida del RayTrac.
results_block_proc: process(clk,ena)
results_block_proc: process(clk,rst)
begin
if clk'event and clk='1' and ena='1' then
if rst=rstMasterValue then
s0ext_rd_add <= (others => '0');
s0ext_rd <= '0';
elsif clk'event and clk='1' then
--!Registrar entrada
s0ext_rd_add <= ext_rd_add;
s0ext_rd <= ext_rd;
/customCounter.vhd
147,11 → 147,6
case set is
--! Si subwidth es cero, p.ej. cuando se quiere hacer un contador simple y no detectar el final de bloques de 4 bits de ancho, el compilador ignora el statement con la expresi&oacute;n por fuera del rango.
when '1' => scount_d(subwidth-1 downto 0) <= (others => '0');scount_d(width-1 downto subwidth) <= setValue;
--! Strange, but yet true. Esto se puede hacer, es practicamente una compilacion condicional pero posiblemente coste una cuantas celdas logicas.
-- if subwidth>0 then
-- scount_d(subwidth-1 downto 0) <= (others => '0');
-- end if;
when others => scount_d <= scount_q+sgo;
end case;
end process;

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