OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /raytrac/branches/fp
    from Rev 150 to Rev 151
    ↔ Reverse comparison
  •

Rev 150 → Rev 151

/sm.vhd
25,8 → 25,8
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
use work.arithpack.all;
 
 
entity sm is
generic (
width : integer := 32;
53,6 → 53,9
--! End Of Instruction Event
eoi : out std_logic;
--! State Exposed for testbench purposes.
state : out macState;
--! DataPath Control uca code.
dpc_uca : out std_logic_vector (2 downto 0)
62,32 → 65,15
 
architecture sm_arch of sm is
 
type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
--! LOAD_INSTRUCTION: Estado en el que se espera que en la cola de instrucciones haya una instrucción para ejecutar.
--! EXECUTE_INSTRUCTION: Estado en el que se ejecuta la instrucción de la cola de instrucciones.
--! FLUSH_ARITH_PIPELINE: Estado en el que se espera un número específico de ciclos de reloj, para que se desocupe el pipeline aritmético.
signal state : macState;
constant rstMasterValue : std_logic:='0';
signal s_state : macState;
component customCounter
generic (
EOBFLAG : string ;
ZEROFLAG : string ;
BACKWARDS : string ;
EQUALFLAG : string ;
subwidth : integer;
width : integer
);
port (
clk,rst,go,set : in std_logic;
setValue,cmpBlockValue : in std_Logic_vector(width-1 downto subwidth);
zero_flag,eob_flag,eq_flag : out std_logic;
count : out std_logic_vector(width-1 downto 0)
);
end component;
signal s_instr_uca: std_logic_vector(2 downto 0);
signal s_dpc_uca: std_logic_vector(2 downto 0);
signal s_block_start_a: std_logic_vector(4 downto 0);
107,6 → 93,9
signal s_eb_b,s_eb_a: std_logic; --! Indica que se está leyendo en memoria el último operando del bloque actual, b o a, respectivamente.
begin
state <= s_state;
 
--! Código UCA, pero en la etapa DPC: La diferencia es que UCA en la etapa DPC, decodifica el datapath dentro del pipeline aritmético.
dpc_uca <= s_dpc_uca;
 
140,7 → 129,7
sm_comb:
process (state, full_r,s_eb_b,s_combinatory,s_zeroFlag_delay,s_eq_b,s_eb_a,s_eq_a,instrQ_empty)
process (s_state, full_r,s_eb_b,s_combinatory,s_zeroFlag_delay,s_eq_b,s_eb_a,s_eq_a,instrQ_empty)
begin
--!Se&ntilde;al de play/pause del contador de direcciones para el par&aacute;metro B/D.
s_go_b <= not(full_r and s_eb_b);
157,13 → 146,13
s_go_delay <= not(s_zeroFlag_delay);
--! Si estamos en el final de la instrucción, "descargamos" esta de la máquina de estados con acknowledge read.
if s_eb_b='1' and s_eq_b='1' and s_eb_a='1' and s_eq_a='1' and state=EXECUTE_INSTRUCTION then
if s_eb_b='1' and s_eq_b='1' and s_eb_a='1' and s_eq_a='1' and s_state=EXECUTE_INSTRUCTION then
instrRdAckd <= '1';
else
instrRdAckd <= '0';
end if;
if (s_eb_a='1' and s_eq_a='1') or state=LOAD_INSTRUCTION or state=FLUSH_ARITH_PIPELINE then
if (s_eb_a='1' and s_eq_a='1') or s_state=LOAD_INSTRUCTION or s_state=FLUSH_ARITH_PIPELINE then
s_set_a <= '1';
else
s_set_a <= '0';
171,7 → 160,7
if (s_eb_b='1' and s_eq_b='1') or state=LOAD_INSTRUCTION or state=FLUSH_ARITH_PIPELINE then
if (s_eb_b='1' and s_eq_b='1') or s_state=LOAD_INSTRUCTION or s_state=FLUSH_ARITH_PIPELINE then
s_set_b <= '1';
else
s_set_b <= '0';
180,12 → 169,12
end process;
sm_proc:
process (clk,rst,state, full_r,s_eb_b,s_combinatory,s_zeroFlag_delay,s_eq_b,s_eb_a,s_eq_a,instrQ_empty)
process (clk,rst,s_state, full_r,s_eb_b,s_combinatory,s_zeroFlag_delay,s_eq_b,s_eb_a,s_eq_a,instrQ_empty)
begin
if rst=rstMasterValue then
state <= LOAD_INSTRUCTION;
s_state <= LOAD_INSTRUCTION;
s_set_dly <= '1';
sync_chain_0 <= '0';
eoi<='0';
194,7 → 183,7
elsif clk='1' and clk'event then
case state is
case s_state is
--! Cargar la siguiente instrucción.
when LOAD_INSTRUCTION =>
204,7 → 193,7
if instrQ_empty='0' and full_r='0' then
--! Siguiente estado: Ejecutar la instrucción.
state <= EXECUTE_INSTRUCTION;
s_state <= EXECUTE_INSTRUCTION;
--! Asignar el código UCA para que comience la decodificación.
s_dpc_uca <= s_instr_uca;
233,13 → 222,13
--! Notificar fin de procesamiento de la instruccion (End Of Instruction)
eoi <= '1';
state <= LOAD_INSTRUCTION;
s_state <= LOAD_INSTRUCTION;
s_set_dly <= '1';
else
state <= FLUSH_ARITH_PIPELINE;
s_state <= FLUSH_ARITH_PIPELINE;
s_set_dly <= '0';
end if;
259,7 → 248,7
--! Notificar fin de procesamiento de la instruccion (End Of Instruction)
eoi <= '1';
state <= LOAD_INSTRUCTION;
s_state <= LOAD_INSTRUCTION;
s_set_dly <= '1';
end if;
/fsqrt32.vhd
25,6 → 25,7
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity sqrt32 is
port (
/im.vhd
25,7 → 25,7
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
use work.arithpack.all;
entity im is
generic (
num_events : integer :=4;
36,7 → 36,8
rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
rfull_int: out std_logic_vector(num_events-1downto 0) --! full results queue related interruptions
rfull_int: out std_logic_vector(num_events-1downto 0); --! full results queue related interruptions
state: out iCtrlState
);
end entity;
43,15 → 44,15
 
architecture im_arch of im is
 
type macState is (WAITING_FOR_AN_EVENT,FIRING_INTERRUPTIONS,SUSPEND);
signal state : macState;
constant rstMasterValue : std_logic:='0';
signal s_state : iCtrlState;
signal s_event_polling_chain : std_logic_vector(num_events-1 downto 0);
signal s_eoi_events : std_logic_vector(num_events-1 downto 0);
begin
 
 
state <= s_state;
sm_proc:
process (clk,rst,s_event_polling_chain,rfull_events,eoi_events)
variable tempo : integer range 0 to cycles_to_wait:=cycles_to_wait;
58,7 → 59,7
begin
if rst=rstMasterValue then
tempo := cycles_to_wait;
state <= WAITING_FOR_AN_EVENT;
s_state <= WAITING_FOR_AN_EVENT;
s_event_polling_chain <= (others => '0');
s_eoi_events <= (others => '0');
rfull_int <= (others => '0');
75,17 → 76,17
eoi_int(i) <= s_event_polling_chain(i) and s_eoi_events(i);
end loop;
case state is
case s_state is
when WAITING_FOR_AN_EVENT =>
for i in num_events-1 downto 0 loop
if rfull_events(i)='1' then
state <= FIRING_INTERRUPTIONS;
s_state <= FIRING_INTERRUPTIONS;
s_event_polling_chain(0) <= '1';
end if;
end loop;
when FIRING_INTERRUPTIONS =>
if s_event_polling_chain(num_events-1)='1' then
state <= SUSPEND;
s_state <= SUSPEND;
tempo := cycles_to_wait;
end if;
for i in num_events-1 downto 1 loop
94,7 → 95,7
s_event_polling_chain(0) <= '0';
when SUSPEND =>
if tempo=0 then
state <= WAITING_FOR_AN_EVENT;
s_state <= WAITING_FOR_AN_EVENT;
else
tempo:=tempo-1;
end if;
/raytrac.vhd
5,7 → 5,7
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- memblock.vhd
-- Rytrac.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
24,6 → 24,7
 
library ieee;
use ieee.std_logic_1164.all;
use work.arithpack.all;
 
entity raytrac is
port (
47,8 → 48,13
int : out std_logic_vector (7 downto 0);
--! Salidas
q : out std_logic_vector (31 downto 0)
q : out std_logic_vector (31 downto 0);
--! Estado Controlador de Interrupciones
intCtrlState : out iCtrlState;
--! Estado Maquina de Estados
smState : out macState
);
end entity;
55,204 → 61,45
 
architecture raytrac_arch of raytrac is
 
--! Definicion de Tipos y de Constantes
constant rstMasterValue : std_logic := '0';
--! Definición de componentes del sistema.
 
--! Bloque de memorias
component memblock
generic (
width : integer;
blocksize : integer;
widthadmemblock : integer;
external_writeable_blocks : integer;
external_readable_blocks : integer;
external_readable_widthad : integer;
external_writeable_widthad : integer
);
port (
clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
instrfifo_rd : in std_logic;
resultfifo_wr: in std_logic_vector(external_readable_blocks-1 downto 0);
instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
ext_d: in std_logic_vector(width-1 downto 0);
int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
resultfifo_full : out std_logic_vector(3 downto 0);
ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);
int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
dpfifo_d : in std_logic_vector(width*2-1 downto 0);
normfifo_d : in std_logic_vector(width*3-1 downto 0);
dpfifo_q : out std_logic_vector(width*2-1 downto 0);
normfifo_q : out std_logic_vector(width*3-1 downto 0)
);
end component;
--! Bloque decodificacion DataPath Control.
component dpc
generic (
width : integer
);
port (
clk,rst : in std_logic;
paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
fifo32x23_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
eoi_int : in std_logic; --! Sennal de interrupción de final de instrucción.
eoi_demuxed_int : out std_logic_vector (3 downto 0); --! Señal de interrupción de final de instrucción pero esta vez va asociada a la instruccón UCA.
sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalizaci&oacute;n.
fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicaci&oacute;n respectivamente.
add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
resw : out std_logic_vector (4 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
fifo32x09_w : out std_logic;
fifo32x23_w,fifo32x09_r : out std_logic;
fifo32x23_r : out std_logic;
resf_vector : in std_logic_vector(3 downto 0); --! Entradas de la se&ntilde;al de full de las colas de resultados.
resf_event : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operaci&oacute;n que est&aacute; en curso.
resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 8 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
);
end component;
--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
component arithblock
port (
clk : in std_logic;
rst : in std_logic;
dpc : in std_logic;
f : in std_logic_vector (12*32-1 downto 0);
a : in std_logic_vector (8*32-1 downto 0);
s : out std_logic_vector (4*32-1 downto 0);
p : out std_logic_vector (6*32-1 downto 0)
);
end component;
--! Bloque de Raiz Cuadrada
component sqrt32
port (
clk : in std_logic;
rd32: in std_logic_vector(31 downto 0);
sq32: out std_logic_vector(31 downto 0)
);
end component;
--! Bloque de Inversores.
component invr32
port (
clk : in std_logic;
dvd32 : in std_logic_vector(31 downto 0);
qout32 : out std_logic_vector(31 downto 0)
);
end component;
--! Maquina de Estados.
component sm
generic (
width : integer ;
widthadmemblock : integer
--!external_readable_widthad :
);
port (
--! Se&ntilde;ales normales de secuencia.
clk,rst: in std_logic;
--! Vector con las instrucción codficada
instrQq:in std_logic_vector(width-1 downto 0);
--! Señal de cola vacia.
instrQ_empty:in std_logic;
adda,addb:out std_logic_vector (widthadmemblock-1 downto 0);
sync_chain_0,instrRdAckd:out std_logic;
full_r: in std_logic; --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.
--! End Of Instruction Event
eoi : out std_logic;
--! DataPath Control uca code.
dpc_uca : out std_logic_vector (2 downto 0)
);
end component;
--! Maquina de Interrupciones
component im
generic (
num_events : integer ;
cycles_to_wait : integer
);
port (
clk,rst: in std_logic;
rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
rfull_int: out std_logic_vector(num_events-1downto 0) --! full results queue related interruptions
);
end component;
--! Se&ntilde;ales de State Machine -> Memblock
--!TBXSTART:SM
signal s_adda : std_logic_vector (8 downto 0);
signal s_addb : std_logic_vector (8 downto 0);
signal s_iq_rd_ack : std_logic;
--! Se&ntilde;ales de State Machine -> DataPathControl
signal s_sync_chain_0 : std_logic;
signal s_dpc_uca : std_logic_vector(2 downto 0);
signal s_eoi : std_logic;
--! Se&ntilde;ales de State Machine -> Testbench
signal s_smState : macState;
--!TBXEND
--!TBXSTART:MBLK
--! Se&ntilde;ales de Memblock -> State Machine
signal s_iq_empty : std_logic;
signal s_iq : std_logic_vector (31 downto 0);
 
--! Se&ntilde;ales de Memblock -> Interruption Machine
signal s_rfull_events : std_logic_vector (3 downto 0); --Estas se&ntilde;ales tambien entran a DPC.
--! Se&ntilde;ales de Memblock -> DPC.
signal s_q : std_logic_vector (12*32-1 downto 0);
signal s_normfifo_q : std_logic_vector (3*32-1 downto 0);
signal s_dpfifo_q : std_logic_vector (2*32-1 downto 0);
--! Se&ntilde;ales de State Machine -> Memblock
signal s_adda : std_logic_vector (8 downto 0);
signal s_addb : std_logic_vector (8 downto 0);
signal s_iq_rd_ack : std_logic;
--! Se&ntilde;ales de State Machine -> DataPathControl
signal s_sync_chain_0 : std_logic;
signal s_dpc_uca : std_logic_vector(2 downto 0);
signal s_eoi : std_logic;
--!TBXEND
--!TBXSTART:SQR32
--!Se&ntilde;ales de Bloque de Ra&iacute;z Cuadrada a DPC
signal s_sq32 : std_logic_vector (31 downto 0);
--!TBXEND
--!TBXSTART:INV32
--!Se&ntilde;ales del bloque inversor a DPC.
signal s_qout32 : std_logic_vector (31 downto 0);
--!TBXEND
--!TBXSTART:DPC
--! Se&ntilde;ales de DataPathControl -> State Machine
signal s_full_r : std_logic;
 
--! Se&ntilde;ales de State Machin a Interruption Machine.
signal s_eoi_events : std_logic_vector (3 downto 0);
--! Se&ntilde;ales de DPC a ArithBlock
signal s_f : std_logic_vector (12*32-1 downto 0);
signal s_a : std_logic_vector (8*32-1 downto 0);
--! Parcialmente las se&ntilde;ales de salida de los sumadores van al data path control.
signal s_s : std_logic_vector (4*32-1 downto 0);
signal s_p : std_logic_vector (6*32-1 downto 0);
 
--! Se&ntilde;ales de DPC a sqrt32.
signal s_rd32 : std_logic_vector (31 downto 0);
signal s_sq32 : std_logic_vector (31 downto 0);
 
--! Se&ntilde;ales de DPC a inv32.
signal s_dvd32 : std_logic_vector (31 downto 0);
--! Se&ntilde;ales de DPC a invr32.
signal s_dvd32 : std_logic_vector (31 downto 0);
signal s_qout32 : std_logic_vector (31 downto 0);
--! Se&ntilde que va desde DPC -> Memblock
signal s_resultsfifo_w : std_logic_vector (4 downto 0);
signal s_dpfifo_w : std_logic;
262,8 → 109,25
signal s_normfifo_r : std_logic;
signal s_results_d : std_logic_vector (8*32-1 downto 0);
signal s_normfifo_d : std_logic_vector (3*32-1 downto 0);
--!Se&ntilde;ales de DPC a Interruption Machine
signal s_eoi_events : std_logic_vector (3 downto 0);
--! Se&ntilde;ales de DPC a ArithBlock
signal s_f : std_logic_vector (12*32-1 downto 0);
signal s_a : std_logic_vector (8*32-1 downto 0);
--! Parcialmente las se&ntilde;ales de salida de los sumadores van al data path control.
signal s_s : std_logic_vector (4*32-1 downto 0);
signal s_p : std_logic_vector (6*32-1 downto 0);
--!TBXEND
--!TBXSTART:IM
--! Se&ntilde;ales de Interruption Machine al testbench
signal s_iCtrlState : iCtrlState;
--!TBXEND
begin
 
 
--! Instanciar el bloque de memorias MEMBLOCK
MemoryBlock : memblock
generic map (
349,7 → 213,7
qout32 => s_qout32
);
 
--! Instanciar el bloque de raíz cuadrada.
--! Instanciar el bloque de ra&iacute;z cuadrada.
square_root : sqrt32
port map (
clk => clk,
358,7 → 222,7
);
--! Instanciar el bloque aritmético.
--! Instanciar el bloque aritm&eacute;tico.
arithmetic_block : arithblock
port map (
clk => clk,
382,7 → 246,8
rfull_events => s_rfull_events,
eoi_events => s_eoi_events,
eoi_int => int(3 downto 0),
rfull_int => int(7 downto 4)
rfull_int => int(7 downto 4),
state => s_iCtrlState
);
--!Instanciar la maquina de estados
402,7 → 267,9
instrRdAckd => s_iq_rd_ack,
full_r => s_full_r,
eoi => s_eoi,
dpc_uca => s_dpc_uca
dpc_uca => s_dpc_uca,
state => s_smState
);
 
/dpc.vhd
22,6 → 22,7
 
library ieee;
use ieee.std_logic_1164.all;
use work.arithpack.all;
 
entity dpc is
generic (
95,8 → 96,8
signal sres24f,sres0f : std_logic;
constant rstMasterValue : std_logic := '0';
begin
--! Cadena de sincronizaci&oacute;n: 29 posiciones.
/arithpack.vhd
0,0 → 1,248
library ieee;
use ieee.std_logic_1164.all;
 
--! Memory Compiler Library
library lpm;
use lpm.all;
 
 
 
package arithpack is
--! Estados para la maquina de estados.
type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
--! Estados para el controlador de interrupciones.
type iCtrlState is (WAITING_FOR_AN_EVENT,FIRING_INTERRUPTIONS,SUSPEND);
--! Constante de reseteo
constant rstMasterValue : std_logic :='0';
--! Constantes periodicas.
constant tclk : time := 20 ns;
constant tclk_2 : time := tclk/2;
constant tclk_4 : time := tclk/4;
--! Contadores para la m&aacute:quina de estados.
component customCounter
generic (
EOBFLAG : string ;
ZEROFLAG : string ;
BACKWARDS : string ;
EQUALFLAG : string ;
subwidth : integer;
width : integer
);
port (
clk,rst,go,set : in std_logic;
setValue,cmpBlockValue : in std_Logic_vector(width-1 downto subwidth);
zero_flag,eob_flag,eq_flag : out std_logic;
count : out std_logic_vector(width-1 downto 0)
);
end component;
--! LPM Memory Compiler.
component scfifo
generic (
add_ram_output_register :string;
almost_full_value :natural;
allow_wrcycle_when_full :string;
intended_device_family :string;
lpm_hint :string;
lpm_numwords :natural;
lpm_showahead :string;
lpm_type :string;
lpm_width :natural;
lpm_widthu :natural;
overflow_checking :string;
underflow_checking :string;
use_eab :string
);
port(
rdreq : in std_logic;
aclr : in std_logic;
empty : out std_logic;
clock : in std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector(lpm_width-1 downto 0);
almost_full : out std_logic;
full : out std_logic
);
end component;
component altsyncram
generic (
address_aclr_b : string;
address_reg_b : string;
clock_enable_input_a : string;
clock_enable_input_b : string;
clock_enable_output_b : string;
intended_device_family : string;
lpm_type : string;
numwords_a : natural;
numwords_b : natural;
operation_mode : string;
outdata_aclr_b : string;
outdata_reg_b : string;
power_up_uninitialized : string;
ram_block_type : string;
rdcontrol_reg_b : string;
read_during_write_mode_mixed_ports : string;
widthad_a : natural;
widthad_b : natural;
width_a : natural;
width_b : natural;
width_byteena_a : natural
);
port (
wren_a : in std_logic;
clock0 : in std_logic;
address_a : in std_logic_vector(8 downto 0);
address_b : in std_logic_vector(8 downto 0);
rden_b : in std_logic;
q_b : out std_logic_vector(31 downto 0);
data_a : in std_logic_vector(31 downto 0)
);
end component;
--! Maquina de Estados.
component sm
generic (
width : integer ;
widthadmemblock : integer
--!external_readable_widthad :
);
port (
--! Se&ntilde;ales normales de secuencia.
clk,rst: in std_logic;
--! Vector con las instrucción codficada
instrQq:in std_logic_vector(31 downto 0);
--! Señal de cola vacia.
instrQ_empty:in std_logic;
adda,addb:out std_logic_vector (8 downto 0);
sync_chain_0,instrRdAckd:out std_logic;
full_r: in std_logic; --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.
--! End Of Instruction Event
eoi : out std_logic;
--! DataPath Control uca code.
dpc_uca : out std_logic_vector (2 downto 0);
state : out macState
);
end component;
--! Maquina de Interrupciones
component im
generic (
num_events : integer ;
cycles_to_wait : integer
);
port (
clk,rst: in std_logic;
rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
rfull_int: out std_logic_vector(num_events-1downto 0); --! full results queue related interruptions
state: out iCtrlState
);
end component;
--! Bloque de memorias
component memblock
generic (
width : integer;
blocksize : integer;
widthadmemblock : integer;
external_writeable_blocks : integer;
external_readable_blocks : integer;
external_readable_widthad : integer;
external_writeable_widthad : integer
);
port (
clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
instrfifo_rd : in std_logic;
resultfifo_wr: in std_logic_vector(external_readable_blocks-1 downto 0);
instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
ext_d: in std_logic_vector(width-1 downto 0);
int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
resultfifo_full : out std_logic_vector(3 downto 0);
ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);
int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
dpfifo_d : in std_logic_vector(width*2-1 downto 0);
normfifo_d : in std_logic_vector(width*3-1 downto 0);
dpfifo_q : out std_logic_vector(width*2-1 downto 0);
normfifo_q : out std_logic_vector(width*3-1 downto 0)
);
end component;
--! Bloque decodificacion DataPath Control.
component dpc
generic (
width : integer
);
port (
clk,rst : in std_logic;
paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
fifo32x23_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
eoi_int : in std_logic; --! Sennal de interrupción de final de instrucción.
eoi_demuxed_int : out std_logic_vector (3 downto 0); --! Señal de interrupción de final de instrucción pero esta vez va asociada a la instruccón UCA.
sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalizaci&oacute;n.
fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicaci&oacute;n respectivamente.
add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
resw : out std_logic_vector (4 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
fifo32x09_w : out std_logic;
fifo32x23_w,fifo32x09_r : out std_logic;
fifo32x23_r : out std_logic;
resf_vector : in std_logic_vector(3 downto 0); --! Entradas de la se&ntilde;al de full de las colas de resultados.
resf_event : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operaci&oacute;n que est&aacute; en curso.
resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 8 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
);
end component;
--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
component arithblock
port (
clk : in std_logic;
rst : in std_logic;
dpc : in std_logic;
f : in std_logic_vector (12*32-1 downto 0);
a : in std_logic_vector (8*32-1 downto 0);
s : out std_logic_vector (4*32-1 downto 0);
p : out std_logic_vector (6*32-1 downto 0)
);
end component;
--! Bloque de Raiz Cuadrada
component sqrt32
port (
clk : in std_logic;
rd32: in std_logic_vector(31 downto 0);
sq32: out std_logic_vector(31 downto 0)
);
end component;
--! Bloque de Inversores.
component invr32
port (
clk : in std_logic;
dvd32 : in std_logic_vector(31 downto 0);
qout32 : out std_logic_vector(31 downto 0)
);
end component;
end package;
/finvr32.vhd
25,6 → 25,8
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
 
entity invr32 is
port (
/memblock.vhd
22,6 → 22,7
 
library ieee;
use ieee.std_logic_1164.all;
use work.arithpack.all;
 
entity memblock is
generic (
61,73 → 62,10
type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
type vectorblock08 is array (07 downto 0) of std_logic_vector(width-1 downto 0);
type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
constant rstMasterValue : std_logic := '0';
component scfifo
generic (
add_ram_output_register :string;
almost_full_value :natural;
allow_wrcycle_when_full :string;
intended_device_family :string;
lpm_hint :string;
lpm_numwords :natural;
lpm_showahead :string;
lpm_type :string;
lpm_width :natural;
lpm_widthu :natural;
overflow_checking :string;
underflow_checking :string;
use_eab :string
);
port(
rdreq : in std_logic;
aclr : in std_logic;
empty : out std_logic;
clock : in std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector(lpm_width-1 downto 0);
almost_full : out std_logic;
full : out std_logic
);
end component;
component altsyncram
generic (
address_aclr_b : string;
address_reg_b : string;
clock_enable_input_a : string;
clock_enable_input_b : string;
clock_enable_output_b : string;
intended_device_family : string;
lpm_type : string;
numwords_a : natural;
numwords_b : natural;
operation_mode : string;
outdata_aclr_b : string;
outdata_reg_b : string;
power_up_uninitialized : string;
ram_block_type : string;
rdcontrol_reg_b : string;
read_during_write_mode_mixed_ports : string;
widthad_a : natural;
widthad_b : natural;
width_a : natural;
width_b : natural;
width_byteena_a : natural
);
port (
wren_a : in std_logic;
clock0 : in std_logic;
address_a : in std_logic_vector(widthad_a-1 downto 0);
address_b : in std_logic_vector(widthad_b-1 downto 0);
rden_b : in std_logic;
q_b : out std_logic_vector(width-1 downto 0);
data_a : in std_logic_vector(width-1 downto 0)
);
end component;
signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se &ntilde;al extra es para la escritura de la cola de instrucciones.
signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
/customCounter.vhd
24,8 → 24,8
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.arithpack.all;
 
 
entity customCounter is
generic (
EOBFLAG : string := "NO";
47,7 → 47,7
 
architecture customCounter_arch of customCounter is
 
constant rstMasterValue : std_logic := '0';
signal scount_d, scount_q, sgo : std_logic_vector(width-1 downto 0);
signal seob_flag : std_logic;
 

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